root / target-mips / op_helper.c @ 29b358f9
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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h> |
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#include "cpu.h" |
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#include "qemu/host-utils.h" |
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#include "helper.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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#ifndef CONFIG_USER_ONLY
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static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); |
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#endif
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/*****************************************************************************/
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/* Exceptions processing helpers */
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static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, |
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uint32_t exception, |
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int error_code,
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uintptr_t pc) |
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{ |
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if (exception < EXCP_SC) {
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qemu_log("%s: %d %d\n", __func__, exception, error_code);
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} |
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env->exception_index = exception; |
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env->error_code = error_code; |
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if (pc) {
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/* now we have a real cpu fault */
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cpu_restore_state(env, pc); |
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} |
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cpu_loop_exit(env); |
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} |
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static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, |
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uint32_t exception, |
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uintptr_t pc) |
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{ |
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do_raise_exception_err(env, exception, 0, pc);
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} |
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void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
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int error_code)
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{ |
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do_raise_exception_err(env, exception, error_code, 0);
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} |
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void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
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{ |
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do_raise_exception(env, exception, 0);
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} |
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#if defined(CONFIG_USER_ONLY)
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#define HELPER_LD(name, insn, type) \
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static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
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int mem_idx) \
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{ \ |
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return (type) insn##_raw(addr); \ |
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} |
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#else
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#define HELPER_LD(name, insn, type) \
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static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
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int mem_idx) \
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{ \ |
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switch (mem_idx) \
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{ \ |
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case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ |
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case 1: return (type) cpu_##insn##_super(env, addr); break; \ |
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default: \
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case 2: return (type) cpu_##insn##_user(env, addr); break; \ |
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} \ |
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} |
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#endif
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HELPER_LD(lbu, ldub, uint8_t) |
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HELPER_LD(lw, ldl, int32_t) |
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#ifdef TARGET_MIPS64
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HELPER_LD(ld, ldq, int64_t) |
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#endif
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#undef HELPER_LD
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#if defined(CONFIG_USER_ONLY)
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#define HELPER_ST(name, insn, type) \
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static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
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type val, int mem_idx) \
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{ \ |
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insn##_raw(addr, val); \ |
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} |
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#else
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#define HELPER_ST(name, insn, type) \
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static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
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type val, int mem_idx) \
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{ \ |
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switch (mem_idx) \
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{ \ |
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case 0: cpu_##insn##_kernel(env, addr, val); break; \ |
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case 1: cpu_##insn##_super(env, addr, val); break; \ |
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default: \
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case 2: cpu_##insn##_user(env, addr, val); break; \ |
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} \ |
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} |
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#endif
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HELPER_ST(sb, stb, uint8_t) |
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HELPER_ST(sw, stl, uint32_t) |
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#ifdef TARGET_MIPS64
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HELPER_ST(sd, stq, uint64_t) |
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#endif
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#undef HELPER_ST
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target_ulong helper_clo (target_ulong arg1) |
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{ |
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return clo32(arg1);
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} |
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target_ulong helper_clz (target_ulong arg1) |
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{ |
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return clz32(arg1);
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} |
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#if defined(TARGET_MIPS64)
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target_ulong helper_dclo (target_ulong arg1) |
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{ |
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return clo64(arg1);
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} |
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target_ulong helper_dclz (target_ulong arg1) |
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{ |
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return clz64(arg1);
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} |
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#endif /* TARGET_MIPS64 */ |
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/* 64 bits arithmetic for 32 bits hosts */
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static inline uint64_t get_HILO(CPUMIPSState *env) |
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{ |
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return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
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} |
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static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) |
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{ |
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target_ulong tmp; |
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env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
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tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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return tmp;
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} |
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static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) |
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{ |
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target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
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env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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return tmp;
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} |
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/* Multiplication variants of the vr54xx. */
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target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * |
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(int64_t)(int32_t)arg2)); |
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} |
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target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * |
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(uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
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(uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
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} |
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target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
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(uint64_t)(uint32_t)arg2); |
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} |
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target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * |
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(int64_t)(int32_t)arg2); |
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} |
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target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, |
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target_ulong arg2) |
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{ |
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return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * |
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(uint64_t)(uint32_t)arg2); |
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} |
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#ifndef CONFIG_USER_ONLY
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static inline hwaddr do_translate_address(CPUMIPSState *env, |
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target_ulong address, |
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int rw)
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{ |
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hwaddr lladdr; |
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lladdr = cpu_mips_translate_address(env, address, rw); |
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if (lladdr == -1LL) { |
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cpu_loop_exit(env); |
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} else {
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return lladdr;
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} |
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} |
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#define HELPER_LD_ATOMIC(name, insn) \
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target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ |
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{ \ |
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env->lladdr = do_translate_address(env, arg, 0); \
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env->llval = do_##insn(env, arg, mem_idx); \ |
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return env->llval; \
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} |
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HELPER_LD_ATOMIC(ll, lw) |
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#ifdef TARGET_MIPS64
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HELPER_LD_ATOMIC(lld, ld) |
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#endif
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#undef HELPER_LD_ATOMIC
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#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
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target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ |
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target_ulong arg2, int mem_idx) \
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{ \ |
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target_long tmp; \ |
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\ |
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if (arg2 & almask) { \
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env->CP0_BadVAddr = arg2; \ |
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helper_raise_exception(env, EXCP_AdES); \ |
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} \ |
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if (do_translate_address(env, arg2, 1) == env->lladdr) { \ |
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tmp = do_##ld_insn(env, arg2, mem_idx); \ |
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if (tmp == env->llval) { \
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do_##st_insn(env, arg2, arg1, mem_idx); \ |
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return 1; \ |
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} \ |
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} \ |
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return 0; \ |
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} |
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HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
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#ifdef TARGET_MIPS64
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HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
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#endif
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#undef HELPER_ST_ATOMIC
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK(v) ((v) & 3) |
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#define GET_OFFSET(addr, offset) (addr + (offset))
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#else
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#define GET_LMASK(v) (((v) & 3) ^ 3) |
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#define GET_OFFSET(addr, offset) (addr - (offset))
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#endif
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void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{ |
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do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
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if (GET_LMASK(arg2) <= 2) |
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do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
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if (GET_LMASK(arg2) <= 1) |
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do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
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if (GET_LMASK(arg2) == 0) |
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do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
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} |
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void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{ |
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do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
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if (GET_LMASK(arg2) >= 1) |
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do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
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if (GET_LMASK(arg2) >= 2) |
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do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
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if (GET_LMASK(arg2) == 3) |
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do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
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} |
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#if defined(TARGET_MIPS64)
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/* "half" load and stores. We must do the memory access inline,
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or fault handling won't work. */
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK64(v) ((v) & 7) |
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#else
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#define GET_LMASK64(v) (((v) & 7) ^ 7) |
372 |
#endif
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void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
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int mem_idx)
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{ |
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do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
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|
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if (GET_LMASK64(arg2) <= 6) |
380 |
do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
381 |
|
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if (GET_LMASK64(arg2) <= 5) |
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do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
384 |
|
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if (GET_LMASK64(arg2) <= 4) |
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do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
387 |
|
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if (GET_LMASK64(arg2) <= 3) |
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do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
390 |
|
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if (GET_LMASK64(arg2) <= 2) |
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do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
393 |
|
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if (GET_LMASK64(arg2) <= 1) |
395 |
do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
396 |
|
397 |
if (GET_LMASK64(arg2) <= 0) |
398 |
do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
|
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} |
400 |
|
401 |
void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
|
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int mem_idx)
|
403 |
{ |
404 |
do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
405 |
|
406 |
if (GET_LMASK64(arg2) >= 1) |
407 |
do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
408 |
|
409 |
if (GET_LMASK64(arg2) >= 2) |
410 |
do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
411 |
|
412 |
if (GET_LMASK64(arg2) >= 3) |
413 |
do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
414 |
|
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if (GET_LMASK64(arg2) >= 4) |
416 |
do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
417 |
|
418 |
if (GET_LMASK64(arg2) >= 5) |
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do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
420 |
|
421 |
if (GET_LMASK64(arg2) >= 6) |
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do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
423 |
|
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if (GET_LMASK64(arg2) == 7) |
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do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
426 |
} |
427 |
#endif /* TARGET_MIPS64 */ |
428 |
|
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static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
430 |
|
431 |
void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
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uint32_t mem_idx) |
433 |
{ |
434 |
target_ulong base_reglist = reglist & 0xf;
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435 |
target_ulong do_r31 = reglist & 0x10;
|
436 |
|
437 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
438 |
target_ulong i; |
439 |
|
440 |
for (i = 0; i < base_reglist; i++) { |
441 |
env->active_tc.gpr[multiple_regs[i]] = |
442 |
(target_long)do_lw(env, addr, mem_idx); |
443 |
addr += 4;
|
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} |
445 |
} |
446 |
|
447 |
if (do_r31) {
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448 |
env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
|
449 |
} |
450 |
} |
451 |
|
452 |
void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
453 |
uint32_t mem_idx) |
454 |
{ |
455 |
target_ulong base_reglist = reglist & 0xf;
|
456 |
target_ulong do_r31 = reglist & 0x10;
|
457 |
|
458 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
459 |
target_ulong i; |
460 |
|
461 |
for (i = 0; i < base_reglist; i++) { |
462 |
do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
463 |
addr += 4;
|
464 |
} |
465 |
} |
466 |
|
467 |
if (do_r31) {
|
468 |
do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
|
469 |
} |
470 |
} |
471 |
|
472 |
#if defined(TARGET_MIPS64)
|
473 |
void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
474 |
uint32_t mem_idx) |
475 |
{ |
476 |
target_ulong base_reglist = reglist & 0xf;
|
477 |
target_ulong do_r31 = reglist & 0x10;
|
478 |
|
479 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
480 |
target_ulong i; |
481 |
|
482 |
for (i = 0; i < base_reglist; i++) { |
483 |
env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx); |
484 |
addr += 8;
|
485 |
} |
486 |
} |
487 |
|
488 |
if (do_r31) {
|
489 |
env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
|
490 |
} |
491 |
} |
492 |
|
493 |
void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
|
494 |
uint32_t mem_idx) |
495 |
{ |
496 |
target_ulong base_reglist = reglist & 0xf;
|
497 |
target_ulong do_r31 = reglist & 0x10;
|
498 |
|
499 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
500 |
target_ulong i; |
501 |
|
502 |
for (i = 0; i < base_reglist; i++) { |
503 |
do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
504 |
addr += 8;
|
505 |
} |
506 |
} |
507 |
|
508 |
if (do_r31) {
|
509 |
do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
|
510 |
} |
511 |
} |
512 |
#endif
|
513 |
|
514 |
#ifndef CONFIG_USER_ONLY
|
515 |
/* SMP helpers. */
|
516 |
static bool mips_vpe_is_wfi(MIPSCPU *c) |
517 |
{ |
518 |
CPUState *cpu = CPU(c); |
519 |
CPUMIPSState *env = &c->env; |
520 |
|
521 |
/* If the VPE is halted but otherwise active, it means it's waiting for
|
522 |
an interrupt. */
|
523 |
return cpu->halted && mips_vpe_active(env);
|
524 |
} |
525 |
|
526 |
static inline void mips_vpe_wake(MIPSCPU *c) |
527 |
{ |
528 |
/* Dont set ->halted = 0 directly, let it be done via cpu_has_work
|
529 |
because there might be other conditions that state that c should
|
530 |
be sleeping. */
|
531 |
cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); |
532 |
} |
533 |
|
534 |
static inline void mips_vpe_sleep(MIPSCPU *cpu) |
535 |
{ |
536 |
CPUState *cs = CPU(cpu); |
537 |
|
538 |
/* The VPE was shut off, really go to bed.
|
539 |
Reset any old _WAKE requests. */
|
540 |
cs->halted = 1;
|
541 |
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); |
542 |
} |
543 |
|
544 |
static inline void mips_tc_wake(MIPSCPU *cpu, int tc) |
545 |
{ |
546 |
CPUMIPSState *c = &cpu->env; |
547 |
|
548 |
/* FIXME: TC reschedule. */
|
549 |
if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
|
550 |
mips_vpe_wake(cpu); |
551 |
} |
552 |
} |
553 |
|
554 |
static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) |
555 |
{ |
556 |
CPUMIPSState *c = &cpu->env; |
557 |
|
558 |
/* FIXME: TC reschedule. */
|
559 |
if (!mips_vpe_active(c)) {
|
560 |
mips_vpe_sleep(cpu); |
561 |
} |
562 |
} |
563 |
|
564 |
/**
|
565 |
* mips_cpu_map_tc:
|
566 |
* @env: CPU from which mapping is performed.
|
567 |
* @tc: Should point to an int with the value of the global TC index.
|
568 |
*
|
569 |
* This function will transform @tc into a local index within the
|
570 |
* returned #CPUMIPSState.
|
571 |
*/
|
572 |
/* FIXME: This code assumes that all VPEs have the same number of TCs,
|
573 |
which depends on runtime setup. Can probably be fixed by
|
574 |
walking the list of CPUMIPSStates. */
|
575 |
static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) |
576 |
{ |
577 |
MIPSCPU *cpu; |
578 |
CPUState *cs; |
579 |
CPUState *other_cs; |
580 |
int vpe_idx;
|
581 |
int tc_idx = *tc;
|
582 |
|
583 |
if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { |
584 |
/* Not allowed to address other CPUs. */
|
585 |
*tc = env->current_tc; |
586 |
return env;
|
587 |
} |
588 |
|
589 |
cs = CPU(mips_env_get_cpu(env)); |
590 |
vpe_idx = tc_idx / cs->nr_threads; |
591 |
*tc = tc_idx % cs->nr_threads; |
592 |
other_cs = qemu_get_cpu(vpe_idx); |
593 |
if (other_cs == NULL) { |
594 |
return env;
|
595 |
} |
596 |
cpu = MIPS_CPU(other_cs); |
597 |
return &cpu->env;
|
598 |
} |
599 |
|
600 |
/* The per VPE CP0_Status register shares some fields with the per TC
|
601 |
CP0_TCStatus registers. These fields are wired to the same registers,
|
602 |
so changes to either of them should be reflected on both registers.
|
603 |
|
604 |
Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
|
605 |
|
606 |
These helper call synchronizes the regs for a given cpu. */
|
607 |
|
608 |
/* Called for updates to CP0_Status. */
|
609 |
static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) |
610 |
{ |
611 |
int32_t tcstatus, *tcst; |
612 |
uint32_t v = cpu->CP0_Status; |
613 |
uint32_t cu, mx, asid, ksu; |
614 |
uint32_t mask = ((1 << CP0TCSt_TCU3)
|
615 |
| (1 << CP0TCSt_TCU2)
|
616 |
| (1 << CP0TCSt_TCU1)
|
617 |
| (1 << CP0TCSt_TCU0)
|
618 |
| (1 << CP0TCSt_TMX)
|
619 |
| (3 << CP0TCSt_TKSU)
|
620 |
| (0xff << CP0TCSt_TASID));
|
621 |
|
622 |
cu = (v >> CP0St_CU0) & 0xf;
|
623 |
mx = (v >> CP0St_MX) & 0x1;
|
624 |
ksu = (v >> CP0St_KSU) & 0x3;
|
625 |
asid = env->CP0_EntryHi & 0xff;
|
626 |
|
627 |
tcstatus = cu << CP0TCSt_TCU0; |
628 |
tcstatus |= mx << CP0TCSt_TMX; |
629 |
tcstatus |= ksu << CP0TCSt_TKSU; |
630 |
tcstatus |= asid; |
631 |
|
632 |
if (tc == cpu->current_tc) {
|
633 |
tcst = &cpu->active_tc.CP0_TCStatus; |
634 |
} else {
|
635 |
tcst = &cpu->tcs[tc].CP0_TCStatus; |
636 |
} |
637 |
|
638 |
*tcst &= ~mask; |
639 |
*tcst |= tcstatus; |
640 |
compute_hflags(cpu); |
641 |
} |
642 |
|
643 |
/* Called for updates to CP0_TCStatus. */
|
644 |
static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, |
645 |
target_ulong v) |
646 |
{ |
647 |
uint32_t status; |
648 |
uint32_t tcu, tmx, tasid, tksu; |
649 |
uint32_t mask = ((1 << CP0St_CU3)
|
650 |
| (1 << CP0St_CU2)
|
651 |
| (1 << CP0St_CU1)
|
652 |
| (1 << CP0St_CU0)
|
653 |
| (1 << CP0St_MX)
|
654 |
| (3 << CP0St_KSU));
|
655 |
|
656 |
tcu = (v >> CP0TCSt_TCU0) & 0xf;
|
657 |
tmx = (v >> CP0TCSt_TMX) & 0x1;
|
658 |
tasid = v & 0xff;
|
659 |
tksu = (v >> CP0TCSt_TKSU) & 0x3;
|
660 |
|
661 |
status = tcu << CP0St_CU0; |
662 |
status |= tmx << CP0St_MX; |
663 |
status |= tksu << CP0St_KSU; |
664 |
|
665 |
cpu->CP0_Status &= ~mask; |
666 |
cpu->CP0_Status |= status; |
667 |
|
668 |
/* Sync the TASID with EntryHi. */
|
669 |
cpu->CP0_EntryHi &= ~0xff;
|
670 |
cpu->CP0_EntryHi = tasid; |
671 |
|
672 |
compute_hflags(cpu); |
673 |
} |
674 |
|
675 |
/* Called for updates to CP0_EntryHi. */
|
676 |
static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) |
677 |
{ |
678 |
int32_t *tcst; |
679 |
uint32_t asid, v = cpu->CP0_EntryHi; |
680 |
|
681 |
asid = v & 0xff;
|
682 |
|
683 |
if (tc == cpu->current_tc) {
|
684 |
tcst = &cpu->active_tc.CP0_TCStatus; |
685 |
} else {
|
686 |
tcst = &cpu->tcs[tc].CP0_TCStatus; |
687 |
} |
688 |
|
689 |
*tcst &= ~0xff;
|
690 |
*tcst |= asid; |
691 |
} |
692 |
|
693 |
/* CP0 helpers */
|
694 |
target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) |
695 |
{ |
696 |
return env->mvp->CP0_MVPControl;
|
697 |
} |
698 |
|
699 |
target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) |
700 |
{ |
701 |
return env->mvp->CP0_MVPConf0;
|
702 |
} |
703 |
|
704 |
target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) |
705 |
{ |
706 |
return env->mvp->CP0_MVPConf1;
|
707 |
} |
708 |
|
709 |
target_ulong helper_mfc0_random(CPUMIPSState *env) |
710 |
{ |
711 |
return (int32_t)cpu_mips_get_random(env);
|
712 |
} |
713 |
|
714 |
target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) |
715 |
{ |
716 |
return env->active_tc.CP0_TCStatus;
|
717 |
} |
718 |
|
719 |
target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) |
720 |
{ |
721 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
722 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
723 |
|
724 |
if (other_tc == other->current_tc)
|
725 |
return other->active_tc.CP0_TCStatus;
|
726 |
else
|
727 |
return other->tcs[other_tc].CP0_TCStatus;
|
728 |
} |
729 |
|
730 |
target_ulong helper_mfc0_tcbind(CPUMIPSState *env) |
731 |
{ |
732 |
return env->active_tc.CP0_TCBind;
|
733 |
} |
734 |
|
735 |
target_ulong helper_mftc0_tcbind(CPUMIPSState *env) |
736 |
{ |
737 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
738 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
739 |
|
740 |
if (other_tc == other->current_tc)
|
741 |
return other->active_tc.CP0_TCBind;
|
742 |
else
|
743 |
return other->tcs[other_tc].CP0_TCBind;
|
744 |
} |
745 |
|
746 |
target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) |
747 |
{ |
748 |
return env->active_tc.PC;
|
749 |
} |
750 |
|
751 |
target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) |
752 |
{ |
753 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
754 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
755 |
|
756 |
if (other_tc == other->current_tc)
|
757 |
return other->active_tc.PC;
|
758 |
else
|
759 |
return other->tcs[other_tc].PC;
|
760 |
} |
761 |
|
762 |
target_ulong helper_mfc0_tchalt(CPUMIPSState *env) |
763 |
{ |
764 |
return env->active_tc.CP0_TCHalt;
|
765 |
} |
766 |
|
767 |
target_ulong helper_mftc0_tchalt(CPUMIPSState *env) |
768 |
{ |
769 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
770 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
771 |
|
772 |
if (other_tc == other->current_tc)
|
773 |
return other->active_tc.CP0_TCHalt;
|
774 |
else
|
775 |
return other->tcs[other_tc].CP0_TCHalt;
|
776 |
} |
777 |
|
778 |
target_ulong helper_mfc0_tccontext(CPUMIPSState *env) |
779 |
{ |
780 |
return env->active_tc.CP0_TCContext;
|
781 |
} |
782 |
|
783 |
target_ulong helper_mftc0_tccontext(CPUMIPSState *env) |
784 |
{ |
785 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
786 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
787 |
|
788 |
if (other_tc == other->current_tc)
|
789 |
return other->active_tc.CP0_TCContext;
|
790 |
else
|
791 |
return other->tcs[other_tc].CP0_TCContext;
|
792 |
} |
793 |
|
794 |
target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) |
795 |
{ |
796 |
return env->active_tc.CP0_TCSchedule;
|
797 |
} |
798 |
|
799 |
target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) |
800 |
{ |
801 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
802 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
803 |
|
804 |
if (other_tc == other->current_tc)
|
805 |
return other->active_tc.CP0_TCSchedule;
|
806 |
else
|
807 |
return other->tcs[other_tc].CP0_TCSchedule;
|
808 |
} |
809 |
|
810 |
target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) |
811 |
{ |
812 |
return env->active_tc.CP0_TCScheFBack;
|
813 |
} |
814 |
|
815 |
target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) |
816 |
{ |
817 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
818 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
819 |
|
820 |
if (other_tc == other->current_tc)
|
821 |
return other->active_tc.CP0_TCScheFBack;
|
822 |
else
|
823 |
return other->tcs[other_tc].CP0_TCScheFBack;
|
824 |
} |
825 |
|
826 |
target_ulong helper_mfc0_count(CPUMIPSState *env) |
827 |
{ |
828 |
return (int32_t)cpu_mips_get_count(env);
|
829 |
} |
830 |
|
831 |
target_ulong helper_mftc0_entryhi(CPUMIPSState *env) |
832 |
{ |
833 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
834 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
835 |
|
836 |
return other->CP0_EntryHi;
|
837 |
} |
838 |
|
839 |
target_ulong helper_mftc0_cause(CPUMIPSState *env) |
840 |
{ |
841 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
842 |
int32_t tccause; |
843 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
844 |
|
845 |
if (other_tc == other->current_tc) {
|
846 |
tccause = other->CP0_Cause; |
847 |
} else {
|
848 |
tccause = other->CP0_Cause; |
849 |
} |
850 |
|
851 |
return tccause;
|
852 |
} |
853 |
|
854 |
target_ulong helper_mftc0_status(CPUMIPSState *env) |
855 |
{ |
856 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
857 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
858 |
|
859 |
return other->CP0_Status;
|
860 |
} |
861 |
|
862 |
target_ulong helper_mfc0_lladdr(CPUMIPSState *env) |
863 |
{ |
864 |
return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
|
865 |
} |
866 |
|
867 |
target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
868 |
{ |
869 |
return (int32_t)env->CP0_WatchLo[sel];
|
870 |
} |
871 |
|
872 |
target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) |
873 |
{ |
874 |
return env->CP0_WatchHi[sel];
|
875 |
} |
876 |
|
877 |
target_ulong helper_mfc0_debug(CPUMIPSState *env) |
878 |
{ |
879 |
target_ulong t0 = env->CP0_Debug; |
880 |
if (env->hflags & MIPS_HFLAG_DM)
|
881 |
t0 |= 1 << CP0DB_DM;
|
882 |
|
883 |
return t0;
|
884 |
} |
885 |
|
886 |
target_ulong helper_mftc0_debug(CPUMIPSState *env) |
887 |
{ |
888 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
889 |
int32_t tcstatus; |
890 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
891 |
|
892 |
if (other_tc == other->current_tc)
|
893 |
tcstatus = other->active_tc.CP0_Debug_tcstatus; |
894 |
else
|
895 |
tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; |
896 |
|
897 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
898 |
return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
899 |
(tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
900 |
} |
901 |
|
902 |
#if defined(TARGET_MIPS64)
|
903 |
target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) |
904 |
{ |
905 |
return env->active_tc.PC;
|
906 |
} |
907 |
|
908 |
target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) |
909 |
{ |
910 |
return env->active_tc.CP0_TCHalt;
|
911 |
} |
912 |
|
913 |
target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) |
914 |
{ |
915 |
return env->active_tc.CP0_TCContext;
|
916 |
} |
917 |
|
918 |
target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) |
919 |
{ |
920 |
return env->active_tc.CP0_TCSchedule;
|
921 |
} |
922 |
|
923 |
target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) |
924 |
{ |
925 |
return env->active_tc.CP0_TCScheFBack;
|
926 |
} |
927 |
|
928 |
target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) |
929 |
{ |
930 |
return env->lladdr >> env->CP0_LLAddr_shift;
|
931 |
} |
932 |
|
933 |
target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
934 |
{ |
935 |
return env->CP0_WatchLo[sel];
|
936 |
} |
937 |
#endif /* TARGET_MIPS64 */ |
938 |
|
939 |
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
|
940 |
{ |
941 |
int num = 1; |
942 |
unsigned int tmp = env->tlb->nb_tlb; |
943 |
|
944 |
do {
|
945 |
tmp >>= 1;
|
946 |
num <<= 1;
|
947 |
} while (tmp);
|
948 |
env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
949 |
} |
950 |
|
951 |
void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
|
952 |
{ |
953 |
uint32_t mask = 0;
|
954 |
uint32_t newval; |
955 |
|
956 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
957 |
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
958 |
(1 << CP0MVPCo_EVP);
|
959 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
960 |
mask |= (1 << CP0MVPCo_STLB);
|
961 |
newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
962 |
|
963 |
// TODO: Enable/disable shared TLB, enable/disable VPEs.
|
964 |
|
965 |
env->mvp->CP0_MVPControl = newval; |
966 |
} |
967 |
|
968 |
void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
|
969 |
{ |
970 |
uint32_t mask; |
971 |
uint32_t newval; |
972 |
|
973 |
mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
974 |
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
975 |
newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
976 |
|
977 |
/* Yield scheduler intercept not implemented. */
|
978 |
/* Gating storage scheduler intercept not implemented. */
|
979 |
|
980 |
// TODO: Enable/disable TCs.
|
981 |
|
982 |
env->CP0_VPEControl = newval; |
983 |
} |
984 |
|
985 |
void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
|
986 |
{ |
987 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
988 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
989 |
uint32_t mask; |
990 |
uint32_t newval; |
991 |
|
992 |
mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
993 |
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
994 |
newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); |
995 |
|
996 |
/* TODO: Enable/disable TCs. */
|
997 |
|
998 |
other->CP0_VPEControl = newval; |
999 |
} |
1000 |
|
1001 |
target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) |
1002 |
{ |
1003 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1004 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1005 |
/* FIXME: Mask away return zero on read bits. */
|
1006 |
return other->CP0_VPEControl;
|
1007 |
} |
1008 |
|
1009 |
target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) |
1010 |
{ |
1011 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1012 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1013 |
|
1014 |
return other->CP0_VPEConf0;
|
1015 |
} |
1016 |
|
1017 |
void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
|
1018 |
{ |
1019 |
uint32_t mask = 0;
|
1020 |
uint32_t newval; |
1021 |
|
1022 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
1023 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
1024 |
mask |= (0xff << CP0VPEC0_XTC);
|
1025 |
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
1026 |
} |
1027 |
newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
1028 |
|
1029 |
// TODO: TC exclusive handling due to ERL/EXL.
|
1030 |
|
1031 |
env->CP0_VPEConf0 = newval; |
1032 |
} |
1033 |
|
1034 |
void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
|
1035 |
{ |
1036 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1037 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1038 |
uint32_t mask = 0;
|
1039 |
uint32_t newval; |
1040 |
|
1041 |
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
1042 |
newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
1043 |
|
1044 |
/* TODO: TC exclusive handling due to ERL/EXL. */
|
1045 |
other->CP0_VPEConf0 = newval; |
1046 |
} |
1047 |
|
1048 |
void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
|
1049 |
{ |
1050 |
uint32_t mask = 0;
|
1051 |
uint32_t newval; |
1052 |
|
1053 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1054 |
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
1055 |
(0xff << CP0VPEC1_NCP1);
|
1056 |
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
1057 |
|
1058 |
/* UDI not implemented. */
|
1059 |
/* CP2 not implemented. */
|
1060 |
|
1061 |
// TODO: Handle FPU (CP1) binding.
|
1062 |
|
1063 |
env->CP0_VPEConf1 = newval; |
1064 |
} |
1065 |
|
1066 |
void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
|
1067 |
{ |
1068 |
/* Yield qualifier inputs not implemented. */
|
1069 |
env->CP0_YQMask = 0x00000000;
|
1070 |
} |
1071 |
|
1072 |
void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
|
1073 |
{ |
1074 |
env->CP0_VPEOpt = arg1 & 0x0000ffff;
|
1075 |
} |
1076 |
|
1077 |
void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
|
1078 |
{ |
1079 |
/* Large physaddr (PABITS) not implemented */
|
1080 |
/* 1k pages not implemented */
|
1081 |
env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
|
1082 |
} |
1083 |
|
1084 |
void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
|
1085 |
{ |
1086 |
uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
1087 |
uint32_t newval; |
1088 |
|
1089 |
newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
1090 |
|
1091 |
env->active_tc.CP0_TCStatus = newval; |
1092 |
sync_c0_tcstatus(env, env->current_tc, newval); |
1093 |
} |
1094 |
|
1095 |
void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
|
1096 |
{ |
1097 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1098 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1099 |
|
1100 |
if (other_tc == other->current_tc)
|
1101 |
other->active_tc.CP0_TCStatus = arg1; |
1102 |
else
|
1103 |
other->tcs[other_tc].CP0_TCStatus = arg1; |
1104 |
sync_c0_tcstatus(other, other_tc, arg1); |
1105 |
} |
1106 |
|
1107 |
void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
|
1108 |
{ |
1109 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
1110 |
uint32_t newval; |
1111 |
|
1112 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1113 |
mask |= (1 << CP0TCBd_CurVPE);
|
1114 |
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
1115 |
env->active_tc.CP0_TCBind = newval; |
1116 |
} |
1117 |
|
1118 |
void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
|
1119 |
{ |
1120 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1121 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
1122 |
uint32_t newval; |
1123 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1124 |
|
1125 |
if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1126 |
mask |= (1 << CP0TCBd_CurVPE);
|
1127 |
if (other_tc == other->current_tc) {
|
1128 |
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
1129 |
other->active_tc.CP0_TCBind = newval; |
1130 |
} else {
|
1131 |
newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
1132 |
other->tcs[other_tc].CP0_TCBind = newval; |
1133 |
} |
1134 |
} |
1135 |
|
1136 |
void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
|
1137 |
{ |
1138 |
env->active_tc.PC = arg1; |
1139 |
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
1140 |
env->lladdr = 0ULL;
|
1141 |
/* MIPS16 not implemented. */
|
1142 |
} |
1143 |
|
1144 |
void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
|
1145 |
{ |
1146 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1147 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1148 |
|
1149 |
if (other_tc == other->current_tc) {
|
1150 |
other->active_tc.PC = arg1; |
1151 |
other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
1152 |
other->lladdr = 0ULL;
|
1153 |
/* MIPS16 not implemented. */
|
1154 |
} else {
|
1155 |
other->tcs[other_tc].PC = arg1; |
1156 |
other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
1157 |
other->lladdr = 0ULL;
|
1158 |
/* MIPS16 not implemented. */
|
1159 |
} |
1160 |
} |
1161 |
|
1162 |
void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
|
1163 |
{ |
1164 |
MIPSCPU *cpu = mips_env_get_cpu(env); |
1165 |
|
1166 |
env->active_tc.CP0_TCHalt = arg1 & 0x1;
|
1167 |
|
1168 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
1169 |
if (env->active_tc.CP0_TCHalt & 1) { |
1170 |
mips_tc_sleep(cpu, env->current_tc); |
1171 |
} else {
|
1172 |
mips_tc_wake(cpu, env->current_tc); |
1173 |
} |
1174 |
} |
1175 |
|
1176 |
void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
|
1177 |
{ |
1178 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1179 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1180 |
MIPSCPU *other_cpu = mips_env_get_cpu(other); |
1181 |
|
1182 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
1183 |
|
1184 |
if (other_tc == other->current_tc)
|
1185 |
other->active_tc.CP0_TCHalt = arg1; |
1186 |
else
|
1187 |
other->tcs[other_tc].CP0_TCHalt = arg1; |
1188 |
|
1189 |
if (arg1 & 1) { |
1190 |
mips_tc_sleep(other_cpu, other_tc); |
1191 |
} else {
|
1192 |
mips_tc_wake(other_cpu, other_tc); |
1193 |
} |
1194 |
} |
1195 |
|
1196 |
void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
|
1197 |
{ |
1198 |
env->active_tc.CP0_TCContext = arg1; |
1199 |
} |
1200 |
|
1201 |
void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
|
1202 |
{ |
1203 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1204 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1205 |
|
1206 |
if (other_tc == other->current_tc)
|
1207 |
other->active_tc.CP0_TCContext = arg1; |
1208 |
else
|
1209 |
other->tcs[other_tc].CP0_TCContext = arg1; |
1210 |
} |
1211 |
|
1212 |
void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
|
1213 |
{ |
1214 |
env->active_tc.CP0_TCSchedule = arg1; |
1215 |
} |
1216 |
|
1217 |
void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
|
1218 |
{ |
1219 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1220 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1221 |
|
1222 |
if (other_tc == other->current_tc)
|
1223 |
other->active_tc.CP0_TCSchedule = arg1; |
1224 |
else
|
1225 |
other->tcs[other_tc].CP0_TCSchedule = arg1; |
1226 |
} |
1227 |
|
1228 |
void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
|
1229 |
{ |
1230 |
env->active_tc.CP0_TCScheFBack = arg1; |
1231 |
} |
1232 |
|
1233 |
void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
|
1234 |
{ |
1235 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1236 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1237 |
|
1238 |
if (other_tc == other->current_tc)
|
1239 |
other->active_tc.CP0_TCScheFBack = arg1; |
1240 |
else
|
1241 |
other->tcs[other_tc].CP0_TCScheFBack = arg1; |
1242 |
} |
1243 |
|
1244 |
void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
|
1245 |
{ |
1246 |
/* Large physaddr (PABITS) not implemented */
|
1247 |
/* 1k pages not implemented */
|
1248 |
env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
|
1249 |
} |
1250 |
|
1251 |
void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
|
1252 |
{ |
1253 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
1254 |
} |
1255 |
|
1256 |
void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
|
1257 |
{ |
1258 |
/* 1k pages not implemented */
|
1259 |
env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
1260 |
} |
1261 |
|
1262 |
void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
|
1263 |
{ |
1264 |
/* SmartMIPS not implemented */
|
1265 |
/* Large physaddr (PABITS) not implemented */
|
1266 |
/* 1k pages not implemented */
|
1267 |
env->CP0_PageGrain = 0;
|
1268 |
} |
1269 |
|
1270 |
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
|
1271 |
{ |
1272 |
env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
1273 |
} |
1274 |
|
1275 |
void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
|
1276 |
{ |
1277 |
env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
1278 |
} |
1279 |
|
1280 |
void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
|
1281 |
{ |
1282 |
env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
1283 |
} |
1284 |
|
1285 |
void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
|
1286 |
{ |
1287 |
env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
1288 |
} |
1289 |
|
1290 |
void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
|
1291 |
{ |
1292 |
env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
1293 |
} |
1294 |
|
1295 |
void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
|
1296 |
{ |
1297 |
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
1298 |
} |
1299 |
|
1300 |
void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
|
1301 |
{ |
1302 |
env->CP0_HWREna = arg1 & 0x0000000F;
|
1303 |
} |
1304 |
|
1305 |
void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
|
1306 |
{ |
1307 |
cpu_mips_store_count(env, arg1); |
1308 |
} |
1309 |
|
1310 |
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
|
1311 |
{ |
1312 |
target_ulong old, val; |
1313 |
|
1314 |
/* 1k pages not implemented */
|
1315 |
val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
1316 |
#if defined(TARGET_MIPS64)
|
1317 |
val &= env->SEGMask; |
1318 |
#endif
|
1319 |
old = env->CP0_EntryHi; |
1320 |
env->CP0_EntryHi = val; |
1321 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
1322 |
sync_c0_entryhi(env, env->current_tc); |
1323 |
} |
1324 |
/* If the ASID changes, flush qemu's TLB. */
|
1325 |
if ((old & 0xFF) != (val & 0xFF)) |
1326 |
cpu_mips_tlb_flush(env, 1);
|
1327 |
} |
1328 |
|
1329 |
void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
|
1330 |
{ |
1331 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1332 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1333 |
|
1334 |
other->CP0_EntryHi = arg1; |
1335 |
sync_c0_entryhi(other, other_tc); |
1336 |
} |
1337 |
|
1338 |
void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
|
1339 |
{ |
1340 |
cpu_mips_store_compare(env, arg1); |
1341 |
} |
1342 |
|
1343 |
void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
|
1344 |
{ |
1345 |
uint32_t val, old; |
1346 |
uint32_t mask = env->CP0_Status_rw_bitmask; |
1347 |
|
1348 |
val = arg1 & mask; |
1349 |
old = env->CP0_Status; |
1350 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1351 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
1352 |
sync_c0_status(env, env, env->current_tc); |
1353 |
} else {
|
1354 |
compute_hflags(env); |
1355 |
} |
1356 |
|
1357 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
1358 |
qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
|
1359 |
old, old & env->CP0_Cause & CP0Ca_IP_mask, |
1360 |
val, val & env->CP0_Cause & CP0Ca_IP_mask, |
1361 |
env->CP0_Cause); |
1362 |
switch (env->hflags & MIPS_HFLAG_KSU) {
|
1363 |
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
1364 |
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
1365 |
case MIPS_HFLAG_KM: qemu_log("\n"); break; |
1366 |
default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
1367 |
} |
1368 |
} |
1369 |
} |
1370 |
|
1371 |
void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
|
1372 |
{ |
1373 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1374 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1375 |
|
1376 |
other->CP0_Status = arg1 & ~0xf1000018;
|
1377 |
sync_c0_status(env, other, other_tc); |
1378 |
} |
1379 |
|
1380 |
void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
|
1381 |
{ |
1382 |
/* vectored interrupts not implemented, no performance counters. */
|
1383 |
env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); |
1384 |
} |
1385 |
|
1386 |
void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
|
1387 |
{ |
1388 |
uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
1389 |
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
1390 |
} |
1391 |
|
1392 |
static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) |
1393 |
{ |
1394 |
uint32_t mask = 0x00C00300;
|
1395 |
uint32_t old = cpu->CP0_Cause; |
1396 |
int i;
|
1397 |
|
1398 |
if (cpu->insn_flags & ISA_MIPS32R2) {
|
1399 |
mask |= 1 << CP0Ca_DC;
|
1400 |
} |
1401 |
|
1402 |
cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask); |
1403 |
|
1404 |
if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) { |
1405 |
if (cpu->CP0_Cause & (1 << CP0Ca_DC)) { |
1406 |
cpu_mips_stop_count(cpu); |
1407 |
} else {
|
1408 |
cpu_mips_start_count(cpu); |
1409 |
} |
1410 |
} |
1411 |
|
1412 |
/* Set/reset software interrupts */
|
1413 |
for (i = 0 ; i < 2 ; i++) { |
1414 |
if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) { |
1415 |
cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
|
1416 |
} |
1417 |
} |
1418 |
} |
1419 |
|
1420 |
void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
|
1421 |
{ |
1422 |
mtc0_cause(env, arg1); |
1423 |
} |
1424 |
|
1425 |
void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
|
1426 |
{ |
1427 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1428 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1429 |
|
1430 |
mtc0_cause(other, arg1); |
1431 |
} |
1432 |
|
1433 |
target_ulong helper_mftc0_epc(CPUMIPSState *env) |
1434 |
{ |
1435 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1436 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1437 |
|
1438 |
return other->CP0_EPC;
|
1439 |
} |
1440 |
|
1441 |
target_ulong helper_mftc0_ebase(CPUMIPSState *env) |
1442 |
{ |
1443 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1444 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1445 |
|
1446 |
return other->CP0_EBase;
|
1447 |
} |
1448 |
|
1449 |
void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
|
1450 |
{ |
1451 |
/* vectored interrupts not implemented */
|
1452 |
env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
1453 |
} |
1454 |
|
1455 |
void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
|
1456 |
{ |
1457 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1458 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1459 |
other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
1460 |
} |
1461 |
|
1462 |
target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) |
1463 |
{ |
1464 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1465 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1466 |
|
1467 |
switch (idx) {
|
1468 |
case 0: return other->CP0_Config0; |
1469 |
case 1: return other->CP0_Config1; |
1470 |
case 2: return other->CP0_Config2; |
1471 |
case 3: return other->CP0_Config3; |
1472 |
/* 4 and 5 are reserved. */
|
1473 |
case 6: return other->CP0_Config6; |
1474 |
case 7: return other->CP0_Config7; |
1475 |
default:
|
1476 |
break;
|
1477 |
} |
1478 |
return 0; |
1479 |
} |
1480 |
|
1481 |
void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
|
1482 |
{ |
1483 |
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
1484 |
} |
1485 |
|
1486 |
void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
|
1487 |
{ |
1488 |
/* tertiary/secondary caches not implemented */
|
1489 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
1490 |
} |
1491 |
|
1492 |
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
|
1493 |
{ |
1494 |
target_long mask = env->CP0_LLAddr_rw_bitmask; |
1495 |
arg1 = arg1 << env->CP0_LLAddr_shift; |
1496 |
env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); |
1497 |
} |
1498 |
|
1499 |
void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
1500 |
{ |
1501 |
/* Watch exceptions for instructions, data loads, data stores
|
1502 |
not implemented. */
|
1503 |
env->CP0_WatchLo[sel] = (arg1 & ~0x7);
|
1504 |
} |
1505 |
|
1506 |
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
1507 |
{ |
1508 |
env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
|
1509 |
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
|
1510 |
} |
1511 |
|
1512 |
void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
|
1513 |
{ |
1514 |
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
1515 |
env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
1516 |
} |
1517 |
|
1518 |
void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
|
1519 |
{ |
1520 |
env->CP0_Framemask = arg1; /* XXX */
|
1521 |
} |
1522 |
|
1523 |
void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
|
1524 |
{ |
1525 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
1526 |
if (arg1 & (1 << CP0DB_DM)) |
1527 |
env->hflags |= MIPS_HFLAG_DM; |
1528 |
else
|
1529 |
env->hflags &= ~MIPS_HFLAG_DM; |
1530 |
} |
1531 |
|
1532 |
void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
|
1533 |
{ |
1534 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1535 |
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
1536 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1537 |
|
1538 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
1539 |
if (other_tc == other->current_tc)
|
1540 |
other->active_tc.CP0_Debug_tcstatus = val; |
1541 |
else
|
1542 |
other->tcs[other_tc].CP0_Debug_tcstatus = val; |
1543 |
other->CP0_Debug = (other->CP0_Debug & |
1544 |
((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
1545 |
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
1546 |
} |
1547 |
|
1548 |
void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
|
1549 |
{ |
1550 |
env->CP0_Performance0 = arg1 & 0x000007ff;
|
1551 |
} |
1552 |
|
1553 |
void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
|
1554 |
{ |
1555 |
env->CP0_TagLo = arg1 & 0xFFFFFCF6;
|
1556 |
} |
1557 |
|
1558 |
void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
|
1559 |
{ |
1560 |
env->CP0_DataLo = arg1; /* XXX */
|
1561 |
} |
1562 |
|
1563 |
void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
|
1564 |
{ |
1565 |
env->CP0_TagHi = arg1; /* XXX */
|
1566 |
} |
1567 |
|
1568 |
void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
|
1569 |
{ |
1570 |
env->CP0_DataHi = arg1; /* XXX */
|
1571 |
} |
1572 |
|
1573 |
/* MIPS MT functions */
|
1574 |
target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) |
1575 |
{ |
1576 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1577 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1578 |
|
1579 |
if (other_tc == other->current_tc)
|
1580 |
return other->active_tc.gpr[sel];
|
1581 |
else
|
1582 |
return other->tcs[other_tc].gpr[sel];
|
1583 |
} |
1584 |
|
1585 |
target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) |
1586 |
{ |
1587 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1588 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1589 |
|
1590 |
if (other_tc == other->current_tc)
|
1591 |
return other->active_tc.LO[sel];
|
1592 |
else
|
1593 |
return other->tcs[other_tc].LO[sel];
|
1594 |
} |
1595 |
|
1596 |
target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) |
1597 |
{ |
1598 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1599 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1600 |
|
1601 |
if (other_tc == other->current_tc)
|
1602 |
return other->active_tc.HI[sel];
|
1603 |
else
|
1604 |
return other->tcs[other_tc].HI[sel];
|
1605 |
} |
1606 |
|
1607 |
target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) |
1608 |
{ |
1609 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1610 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1611 |
|
1612 |
if (other_tc == other->current_tc)
|
1613 |
return other->active_tc.ACX[sel];
|
1614 |
else
|
1615 |
return other->tcs[other_tc].ACX[sel];
|
1616 |
} |
1617 |
|
1618 |
target_ulong helper_mftdsp(CPUMIPSState *env) |
1619 |
{ |
1620 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1621 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1622 |
|
1623 |
if (other_tc == other->current_tc)
|
1624 |
return other->active_tc.DSPControl;
|
1625 |
else
|
1626 |
return other->tcs[other_tc].DSPControl;
|
1627 |
} |
1628 |
|
1629 |
void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
1630 |
{ |
1631 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1632 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1633 |
|
1634 |
if (other_tc == other->current_tc)
|
1635 |
other->active_tc.gpr[sel] = arg1; |
1636 |
else
|
1637 |
other->tcs[other_tc].gpr[sel] = arg1; |
1638 |
} |
1639 |
|
1640 |
void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
1641 |
{ |
1642 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1643 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1644 |
|
1645 |
if (other_tc == other->current_tc)
|
1646 |
other->active_tc.LO[sel] = arg1; |
1647 |
else
|
1648 |
other->tcs[other_tc].LO[sel] = arg1; |
1649 |
} |
1650 |
|
1651 |
void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
1652 |
{ |
1653 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1654 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1655 |
|
1656 |
if (other_tc == other->current_tc)
|
1657 |
other->active_tc.HI[sel] = arg1; |
1658 |
else
|
1659 |
other->tcs[other_tc].HI[sel] = arg1; |
1660 |
} |
1661 |
|
1662 |
void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
|
1663 |
{ |
1664 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1665 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1666 |
|
1667 |
if (other_tc == other->current_tc)
|
1668 |
other->active_tc.ACX[sel] = arg1; |
1669 |
else
|
1670 |
other->tcs[other_tc].ACX[sel] = arg1; |
1671 |
} |
1672 |
|
1673 |
void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
|
1674 |
{ |
1675 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1676 |
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
1677 |
|
1678 |
if (other_tc == other->current_tc)
|
1679 |
other->active_tc.DSPControl = arg1; |
1680 |
else
|
1681 |
other->tcs[other_tc].DSPControl = arg1; |
1682 |
} |
1683 |
|
1684 |
/* MIPS MT functions */
|
1685 |
target_ulong helper_dmt(void)
|
1686 |
{ |
1687 |
// TODO
|
1688 |
return 0; |
1689 |
} |
1690 |
|
1691 |
target_ulong helper_emt(void)
|
1692 |
{ |
1693 |
// TODO
|
1694 |
return 0; |
1695 |
} |
1696 |
|
1697 |
target_ulong helper_dvpe(CPUMIPSState *env) |
1698 |
{ |
1699 |
CPUMIPSState *other_cpu_env = first_cpu; |
1700 |
target_ulong prev = env->mvp->CP0_MVPControl; |
1701 |
|
1702 |
do {
|
1703 |
/* Turn off all VPEs except the one executing the dvpe. */
|
1704 |
if (other_cpu_env != env) {
|
1705 |
MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
1706 |
|
1707 |
other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
|
1708 |
mips_vpe_sleep(other_cpu); |
1709 |
} |
1710 |
other_cpu_env = other_cpu_env->next_cpu; |
1711 |
} while (other_cpu_env);
|
1712 |
return prev;
|
1713 |
} |
1714 |
|
1715 |
target_ulong helper_evpe(CPUMIPSState *env) |
1716 |
{ |
1717 |
CPUMIPSState *other_cpu_env = first_cpu; |
1718 |
target_ulong prev = env->mvp->CP0_MVPControl; |
1719 |
|
1720 |
do {
|
1721 |
MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
1722 |
|
1723 |
if (other_cpu_env != env
|
1724 |
/* If the VPE is WFI, don't disturb its sleep. */
|
1725 |
&& !mips_vpe_is_wfi(other_cpu)) { |
1726 |
/* Enable the VPE. */
|
1727 |
other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
|
1728 |
mips_vpe_wake(other_cpu); /* And wake it up. */
|
1729 |
} |
1730 |
other_cpu_env = other_cpu_env->next_cpu; |
1731 |
} while (other_cpu_env);
|
1732 |
return prev;
|
1733 |
} |
1734 |
#endif /* !CONFIG_USER_ONLY */ |
1735 |
|
1736 |
void helper_fork(target_ulong arg1, target_ulong arg2)
|
1737 |
{ |
1738 |
// arg1 = rt, arg2 = rs
|
1739 |
arg1 = 0;
|
1740 |
// TODO: store to TC register
|
1741 |
} |
1742 |
|
1743 |
target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) |
1744 |
{ |
1745 |
target_long arg1 = arg; |
1746 |
|
1747 |
if (arg1 < 0) { |
1748 |
/* No scheduling policy implemented. */
|
1749 |
if (arg1 != -2) { |
1750 |
if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
1751 |
env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
|
1752 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
1753 |
env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
1754 |
helper_raise_exception(env, EXCP_THREAD); |
1755 |
} |
1756 |
} |
1757 |
} else if (arg1 == 0) { |
1758 |
if (0 /* TODO: TC underflow */) { |
1759 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
1760 |
helper_raise_exception(env, EXCP_THREAD); |
1761 |
} else {
|
1762 |
// TODO: Deallocate TC
|
1763 |
} |
1764 |
} else if (arg1 > 0) { |
1765 |
/* Yield qualifier inputs not implemented. */
|
1766 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
1767 |
env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
1768 |
helper_raise_exception(env, EXCP_THREAD); |
1769 |
} |
1770 |
return env->CP0_YQMask;
|
1771 |
} |
1772 |
|
1773 |
#ifndef CONFIG_USER_ONLY
|
1774 |
/* TLB management */
|
1775 |
static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) |
1776 |
{ |
1777 |
/* Flush qemu's TLB and discard all shadowed entries. */
|
1778 |
tlb_flush (env, flush_global); |
1779 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
1780 |
} |
1781 |
|
1782 |
static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) |
1783 |
{ |
1784 |
/* Discard entries from env->tlb[first] onwards. */
|
1785 |
while (env->tlb->tlb_in_use > first) {
|
1786 |
r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
1787 |
} |
1788 |
} |
1789 |
|
1790 |
static void r4k_fill_tlb(CPUMIPSState *env, int idx) |
1791 |
{ |
1792 |
r4k_tlb_t *tlb; |
1793 |
|
1794 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
1795 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1796 |
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
1797 |
#if defined(TARGET_MIPS64)
|
1798 |
tlb->VPN &= env->SEGMask; |
1799 |
#endif
|
1800 |
tlb->ASID = env->CP0_EntryHi & 0xFF;
|
1801 |
tlb->PageMask = env->CP0_PageMask; |
1802 |
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
1803 |
tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
1804 |
tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
1805 |
tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
1806 |
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
1807 |
tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
1808 |
tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
1809 |
tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
1810 |
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
1811 |
} |
1812 |
|
1813 |
void r4k_helper_tlbwi(CPUMIPSState *env)
|
1814 |
{ |
1815 |
r4k_tlb_t *tlb; |
1816 |
int idx;
|
1817 |
target_ulong VPN; |
1818 |
uint8_t ASID; |
1819 |
bool G, V0, D0, V1, D1;
|
1820 |
|
1821 |
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
1822 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1823 |
VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
1824 |
#if defined(TARGET_MIPS64)
|
1825 |
VPN &= env->SEGMask; |
1826 |
#endif
|
1827 |
ASID = env->CP0_EntryHi & 0xff;
|
1828 |
G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
1829 |
V0 = (env->CP0_EntryLo0 & 2) != 0; |
1830 |
D0 = (env->CP0_EntryLo0 & 4) != 0; |
1831 |
V1 = (env->CP0_EntryLo1 & 2) != 0; |
1832 |
D1 = (env->CP0_EntryLo1 & 4) != 0; |
1833 |
|
1834 |
/* Discard cached TLB entries, unless tlbwi is just upgrading access
|
1835 |
permissions on the current entry. */
|
1836 |
if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
|
1837 |
(tlb->V0 && !V0) || (tlb->D0 && !D0) || |
1838 |
(tlb->V1 && !V1) || (tlb->D1 && !D1)) { |
1839 |
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
1840 |
} |
1841 |
|
1842 |
r4k_invalidate_tlb(env, idx, 0);
|
1843 |
r4k_fill_tlb(env, idx); |
1844 |
} |
1845 |
|
1846 |
void r4k_helper_tlbwr(CPUMIPSState *env)
|
1847 |
{ |
1848 |
int r = cpu_mips_get_random(env);
|
1849 |
|
1850 |
r4k_invalidate_tlb(env, r, 1);
|
1851 |
r4k_fill_tlb(env, r); |
1852 |
} |
1853 |
|
1854 |
void r4k_helper_tlbp(CPUMIPSState *env)
|
1855 |
{ |
1856 |
r4k_tlb_t *tlb; |
1857 |
target_ulong mask; |
1858 |
target_ulong tag; |
1859 |
target_ulong VPN; |
1860 |
uint8_t ASID; |
1861 |
int i;
|
1862 |
|
1863 |
ASID = env->CP0_EntryHi & 0xFF;
|
1864 |
for (i = 0; i < env->tlb->nb_tlb; i++) { |
1865 |
tlb = &env->tlb->mmu.r4k.tlb[i]; |
1866 |
/* 1k pages are not supported. */
|
1867 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
1868 |
tag = env->CP0_EntryHi & ~mask; |
1869 |
VPN = tlb->VPN & ~mask; |
1870 |
#if defined(TARGET_MIPS64)
|
1871 |
tag &= env->SEGMask; |
1872 |
#endif
|
1873 |
/* Check ASID, virtual page number & size */
|
1874 |
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
1875 |
/* TLB match */
|
1876 |
env->CP0_Index = i; |
1877 |
break;
|
1878 |
} |
1879 |
} |
1880 |
if (i == env->tlb->nb_tlb) {
|
1881 |
/* No match. Discard any shadow entries, if any of them match. */
|
1882 |
for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
1883 |
tlb = &env->tlb->mmu.r4k.tlb[i]; |
1884 |
/* 1k pages are not supported. */
|
1885 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
1886 |
tag = env->CP0_EntryHi & ~mask; |
1887 |
VPN = tlb->VPN & ~mask; |
1888 |
#if defined(TARGET_MIPS64)
|
1889 |
tag &= env->SEGMask; |
1890 |
#endif
|
1891 |
/* Check ASID, virtual page number & size */
|
1892 |
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
1893 |
r4k_mips_tlb_flush_extra (env, i); |
1894 |
break;
|
1895 |
} |
1896 |
} |
1897 |
|
1898 |
env->CP0_Index |= 0x80000000;
|
1899 |
} |
1900 |
} |
1901 |
|
1902 |
void r4k_helper_tlbr(CPUMIPSState *env)
|
1903 |
{ |
1904 |
r4k_tlb_t *tlb; |
1905 |
uint8_t ASID; |
1906 |
int idx;
|
1907 |
|
1908 |
ASID = env->CP0_EntryHi & 0xFF;
|
1909 |
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
1910 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1911 |
|
1912 |
/* If this will change the current ASID, flush qemu's TLB. */
|
1913 |
if (ASID != tlb->ASID)
|
1914 |
cpu_mips_tlb_flush (env, 1);
|
1915 |
|
1916 |
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
1917 |
|
1918 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
1919 |
env->CP0_PageMask = tlb->PageMask; |
1920 |
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
1921 |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
1922 |
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
1923 |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
1924 |
} |
1925 |
|
1926 |
void helper_tlbwi(CPUMIPSState *env)
|
1927 |
{ |
1928 |
env->tlb->helper_tlbwi(env); |
1929 |
} |
1930 |
|
1931 |
void helper_tlbwr(CPUMIPSState *env)
|
1932 |
{ |
1933 |
env->tlb->helper_tlbwr(env); |
1934 |
} |
1935 |
|
1936 |
void helper_tlbp(CPUMIPSState *env)
|
1937 |
{ |
1938 |
env->tlb->helper_tlbp(env); |
1939 |
} |
1940 |
|
1941 |
void helper_tlbr(CPUMIPSState *env)
|
1942 |
{ |
1943 |
env->tlb->helper_tlbr(env); |
1944 |
} |
1945 |
|
1946 |
/* Specials */
|
1947 |
target_ulong helper_di(CPUMIPSState *env) |
1948 |
{ |
1949 |
target_ulong t0 = env->CP0_Status; |
1950 |
|
1951 |
env->CP0_Status = t0 & ~(1 << CP0St_IE);
|
1952 |
return t0;
|
1953 |
} |
1954 |
|
1955 |
target_ulong helper_ei(CPUMIPSState *env) |
1956 |
{ |
1957 |
target_ulong t0 = env->CP0_Status; |
1958 |
|
1959 |
env->CP0_Status = t0 | (1 << CP0St_IE);
|
1960 |
return t0;
|
1961 |
} |
1962 |
|
1963 |
static void debug_pre_eret(CPUMIPSState *env) |
1964 |
{ |
1965 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
1966 |
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1967 |
env->active_tc.PC, env->CP0_EPC); |
1968 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
1969 |
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
1970 |
if (env->hflags & MIPS_HFLAG_DM)
|
1971 |
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
1972 |
qemu_log("\n");
|
1973 |
} |
1974 |
} |
1975 |
|
1976 |
static void debug_post_eret(CPUMIPSState *env) |
1977 |
{ |
1978 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
1979 |
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1980 |
env->active_tc.PC, env->CP0_EPC); |
1981 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
1982 |
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
1983 |
if (env->hflags & MIPS_HFLAG_DM)
|
1984 |
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
1985 |
switch (env->hflags & MIPS_HFLAG_KSU) {
|
1986 |
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
1987 |
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
1988 |
case MIPS_HFLAG_KM: qemu_log("\n"); break; |
1989 |
default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
1990 |
} |
1991 |
} |
1992 |
} |
1993 |
|
1994 |
static void set_pc(CPUMIPSState *env, target_ulong error_pc) |
1995 |
{ |
1996 |
env->active_tc.PC = error_pc & ~(target_ulong)1;
|
1997 |
if (error_pc & 1) { |
1998 |
env->hflags |= MIPS_HFLAG_M16; |
1999 |
} else {
|
2000 |
env->hflags &= ~(MIPS_HFLAG_M16); |
2001 |
} |
2002 |
} |
2003 |
|
2004 |
void helper_eret(CPUMIPSState *env)
|
2005 |
{ |
2006 |
debug_pre_eret(env); |
2007 |
if (env->CP0_Status & (1 << CP0St_ERL)) { |
2008 |
set_pc(env, env->CP0_ErrorEPC); |
2009 |
env->CP0_Status &= ~(1 << CP0St_ERL);
|
2010 |
} else {
|
2011 |
set_pc(env, env->CP0_EPC); |
2012 |
env->CP0_Status &= ~(1 << CP0St_EXL);
|
2013 |
} |
2014 |
compute_hflags(env); |
2015 |
debug_post_eret(env); |
2016 |
env->lladdr = 1;
|
2017 |
} |
2018 |
|
2019 |
void helper_deret(CPUMIPSState *env)
|
2020 |
{ |
2021 |
debug_pre_eret(env); |
2022 |
set_pc(env, env->CP0_DEPC); |
2023 |
|
2024 |
env->hflags &= MIPS_HFLAG_DM; |
2025 |
compute_hflags(env); |
2026 |
debug_post_eret(env); |
2027 |
env->lladdr = 1;
|
2028 |
} |
2029 |
#endif /* !CONFIG_USER_ONLY */ |
2030 |
|
2031 |
target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) |
2032 |
{ |
2033 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
2034 |
(env->CP0_HWREna & (1 << 0))) |
2035 |
return env->CP0_EBase & 0x3ff; |
2036 |
else
|
2037 |
helper_raise_exception(env, EXCP_RI); |
2038 |
|
2039 |
return 0; |
2040 |
} |
2041 |
|
2042 |
target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) |
2043 |
{ |
2044 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
2045 |
(env->CP0_HWREna & (1 << 1))) |
2046 |
return env->SYNCI_Step;
|
2047 |
else
|
2048 |
helper_raise_exception(env, EXCP_RI); |
2049 |
|
2050 |
return 0; |
2051 |
} |
2052 |
|
2053 |
target_ulong helper_rdhwr_cc(CPUMIPSState *env) |
2054 |
{ |
2055 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
2056 |
(env->CP0_HWREna & (1 << 2))) |
2057 |
return env->CP0_Count;
|
2058 |
else
|
2059 |
helper_raise_exception(env, EXCP_RI); |
2060 |
|
2061 |
return 0; |
2062 |
} |
2063 |
|
2064 |
target_ulong helper_rdhwr_ccres(CPUMIPSState *env) |
2065 |
{ |
2066 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
2067 |
(env->CP0_HWREna & (1 << 3))) |
2068 |
return env->CCRes;
|
2069 |
else
|
2070 |
helper_raise_exception(env, EXCP_RI); |
2071 |
|
2072 |
return 0; |
2073 |
} |
2074 |
|
2075 |
void helper_pmon(CPUMIPSState *env, int function) |
2076 |
{ |
2077 |
function /= 2;
|
2078 |
switch (function) {
|
2079 |
case 2: /* TODO: char inbyte(int waitflag); */ |
2080 |
if (env->active_tc.gpr[4] == 0) |
2081 |
env->active_tc.gpr[2] = -1; |
2082 |
/* Fall through */
|
2083 |
case 11: /* TODO: char inbyte (void); */ |
2084 |
env->active_tc.gpr[2] = -1; |
2085 |
break;
|
2086 |
case 3: |
2087 |
case 12: |
2088 |
printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
2089 |
break;
|
2090 |
case 17: |
2091 |
break;
|
2092 |
case 158: |
2093 |
{ |
2094 |
unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; |
2095 |
printf("%s", fmt);
|
2096 |
} |
2097 |
break;
|
2098 |
} |
2099 |
} |
2100 |
|
2101 |
void helper_wait(CPUMIPSState *env)
|
2102 |
{ |
2103 |
CPUState *cs = CPU(mips_env_get_cpu(env)); |
2104 |
|
2105 |
cs->halted = 1;
|
2106 |
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); |
2107 |
helper_raise_exception(env, EXCP_HLT); |
2108 |
} |
2109 |
|
2110 |
#if !defined(CONFIG_USER_ONLY)
|
2111 |
|
2112 |
static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, |
2113 |
target_ulong addr, int is_write,
|
2114 |
int is_user, uintptr_t retaddr);
|
2115 |
|
2116 |
#define MMUSUFFIX _mmu
|
2117 |
#define ALIGNED_ONLY
|
2118 |
|
2119 |
#define SHIFT 0 |
2120 |
#include "exec/softmmu_template.h" |
2121 |
|
2122 |
#define SHIFT 1 |
2123 |
#include "exec/softmmu_template.h" |
2124 |
|
2125 |
#define SHIFT 2 |
2126 |
#include "exec/softmmu_template.h" |
2127 |
|
2128 |
#define SHIFT 3 |
2129 |
#include "exec/softmmu_template.h" |
2130 |
|
2131 |
static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, |
2132 |
int is_write, int is_user, uintptr_t retaddr) |
2133 |
{ |
2134 |
env->CP0_BadVAddr = addr; |
2135 |
do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
|
2136 |
} |
2137 |
|
2138 |
void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, |
2139 |
uintptr_t retaddr) |
2140 |
{ |
2141 |
int ret;
|
2142 |
|
2143 |
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); |
2144 |
if (ret) {
|
2145 |
do_raise_exception_err(env, env->exception_index, |
2146 |
env->error_code, retaddr); |
2147 |
} |
2148 |
} |
2149 |
|
2150 |
void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
|
2151 |
bool is_write, bool is_exec, int unused, |
2152 |
unsigned size)
|
2153 |
{ |
2154 |
MIPSCPU *cpu = MIPS_CPU(cs); |
2155 |
CPUMIPSState *env = &cpu->env; |
2156 |
|
2157 |
if (is_exec) {
|
2158 |
helper_raise_exception(env, EXCP_IBE); |
2159 |
} else {
|
2160 |
helper_raise_exception(env, EXCP_DBE); |
2161 |
} |
2162 |
} |
2163 |
#endif /* !CONFIG_USER_ONLY */ |
2164 |
|
2165 |
/* Complex FPU operations which may need stack space. */
|
2166 |
|
2167 |
#define FLOAT_TWO32 make_float32(1 << 30) |
2168 |
#define FLOAT_TWO64 make_float64(1ULL << 62) |
2169 |
#define FP_TO_INT32_OVERFLOW 0x7fffffff |
2170 |
#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL |
2171 |
|
2172 |
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
2173 |
static unsigned int ieee_rm[] = { |
2174 |
float_round_nearest_even, |
2175 |
float_round_to_zero, |
2176 |
float_round_up, |
2177 |
float_round_down |
2178 |
}; |
2179 |
|
2180 |
static inline void restore_rounding_mode(CPUMIPSState *env) |
2181 |
{ |
2182 |
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
|
2183 |
&env->active_fpu.fp_status); |
2184 |
} |
2185 |
|
2186 |
static inline void restore_flush_mode(CPUMIPSState *env) |
2187 |
{ |
2188 |
set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, |
2189 |
&env->active_fpu.fp_status); |
2190 |
} |
2191 |
|
2192 |
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) |
2193 |
{ |
2194 |
target_ulong arg1; |
2195 |
|
2196 |
switch (reg) {
|
2197 |
case 0: |
2198 |
arg1 = (int32_t)env->active_fpu.fcr0; |
2199 |
break;
|
2200 |
case 25: |
2201 |
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
2202 |
break;
|
2203 |
case 26: |
2204 |
arg1 = env->active_fpu.fcr31 & 0x0003f07c;
|
2205 |
break;
|
2206 |
case 28: |
2207 |
arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
2208 |
break;
|
2209 |
default:
|
2210 |
arg1 = (int32_t)env->active_fpu.fcr31; |
2211 |
break;
|
2212 |
} |
2213 |
|
2214 |
return arg1;
|
2215 |
} |
2216 |
|
2217 |
void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
|
2218 |
{ |
2219 |
switch(reg) {
|
2220 |
case 25: |
2221 |
if (arg1 & 0xffffff00) |
2222 |
return;
|
2223 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
2224 |
((arg1 & 0x1) << 23); |
2225 |
break;
|
2226 |
case 26: |
2227 |
if (arg1 & 0x007c0000) |
2228 |
return;
|
2229 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
2230 |
break;
|
2231 |
case 28: |
2232 |
if (arg1 & 0x007c0000) |
2233 |
return;
|
2234 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
2235 |
((arg1 & 0x4) << 22); |
2236 |
break;
|
2237 |
case 31: |
2238 |
if (arg1 & 0x007c0000) |
2239 |
return;
|
2240 |
env->active_fpu.fcr31 = arg1; |
2241 |
break;
|
2242 |
default:
|
2243 |
return;
|
2244 |
} |
2245 |
/* set rounding mode */
|
2246 |
restore_rounding_mode(env); |
2247 |
/* set flush-to-zero mode */
|
2248 |
restore_flush_mode(env); |
2249 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2250 |
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) |
2251 |
do_raise_exception(env, EXCP_FPE, GETPC()); |
2252 |
} |
2253 |
|
2254 |
static inline int ieee_ex_to_mips(int xcpt) |
2255 |
{ |
2256 |
int ret = 0; |
2257 |
if (xcpt) {
|
2258 |
if (xcpt & float_flag_invalid) {
|
2259 |
ret |= FP_INVALID; |
2260 |
} |
2261 |
if (xcpt & float_flag_overflow) {
|
2262 |
ret |= FP_OVERFLOW; |
2263 |
} |
2264 |
if (xcpt & float_flag_underflow) {
|
2265 |
ret |= FP_UNDERFLOW; |
2266 |
} |
2267 |
if (xcpt & float_flag_divbyzero) {
|
2268 |
ret |= FP_DIV0; |
2269 |
} |
2270 |
if (xcpt & float_flag_inexact) {
|
2271 |
ret |= FP_INEXACT; |
2272 |
} |
2273 |
} |
2274 |
return ret;
|
2275 |
} |
2276 |
|
2277 |
static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) |
2278 |
{ |
2279 |
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
|
2280 |
|
2281 |
SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
2282 |
|
2283 |
if (tmp) {
|
2284 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2285 |
|
2286 |
if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
|
2287 |
do_raise_exception(env, EXCP_FPE, pc); |
2288 |
} else {
|
2289 |
UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
2290 |
} |
2291 |
} |
2292 |
} |
2293 |
|
2294 |
/* Float support.
|
2295 |
Single precition routines have a "s" suffix, double precision a
|
2296 |
"d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
|
2297 |
paired single lower "pl", paired single upper "pu". */
|
2298 |
|
2299 |
/* unary operations, modifying fp status */
|
2300 |
uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) |
2301 |
{ |
2302 |
fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
2303 |
update_fcr31(env, GETPC()); |
2304 |
return fdt0;
|
2305 |
} |
2306 |
|
2307 |
uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) |
2308 |
{ |
2309 |
fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
2310 |
update_fcr31(env, GETPC()); |
2311 |
return fst0;
|
2312 |
} |
2313 |
|
2314 |
uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) |
2315 |
{ |
2316 |
uint64_t fdt2; |
2317 |
|
2318 |
fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
2319 |
update_fcr31(env, GETPC()); |
2320 |
return fdt2;
|
2321 |
} |
2322 |
|
2323 |
uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) |
2324 |
{ |
2325 |
uint64_t fdt2; |
2326 |
|
2327 |
fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
2328 |
update_fcr31(env, GETPC()); |
2329 |
return fdt2;
|
2330 |
} |
2331 |
|
2332 |
uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) |
2333 |
{ |
2334 |
uint64_t fdt2; |
2335 |
|
2336 |
fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
2337 |
update_fcr31(env, GETPC()); |
2338 |
return fdt2;
|
2339 |
} |
2340 |
|
2341 |
uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) |
2342 |
{ |
2343 |
uint64_t dt2; |
2344 |
|
2345 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2346 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2347 |
& (float_flag_invalid | float_flag_overflow)) { |
2348 |
dt2 = FP_TO_INT64_OVERFLOW; |
2349 |
} |
2350 |
update_fcr31(env, GETPC()); |
2351 |
return dt2;
|
2352 |
} |
2353 |
|
2354 |
uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) |
2355 |
{ |
2356 |
uint64_t dt2; |
2357 |
|
2358 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2359 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2360 |
& (float_flag_invalid | float_flag_overflow)) { |
2361 |
dt2 = FP_TO_INT64_OVERFLOW; |
2362 |
} |
2363 |
update_fcr31(env, GETPC()); |
2364 |
return dt2;
|
2365 |
} |
2366 |
|
2367 |
uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) |
2368 |
{ |
2369 |
uint32_t fst2; |
2370 |
uint32_t fsth2; |
2371 |
|
2372 |
fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2373 |
fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
|
2374 |
update_fcr31(env, GETPC()); |
2375 |
return ((uint64_t)fsth2 << 32) | fst2; |
2376 |
} |
2377 |
|
2378 |
uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) |
2379 |
{ |
2380 |
uint32_t wt2; |
2381 |
uint32_t wth2; |
2382 |
int excp, excph;
|
2383 |
|
2384 |
wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2385 |
excp = get_float_exception_flags(&env->active_fpu.fp_status); |
2386 |
if (excp & (float_flag_overflow | float_flag_invalid)) {
|
2387 |
wt2 = FP_TO_INT32_OVERFLOW; |
2388 |
} |
2389 |
|
2390 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2391 |
wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
|
2392 |
excph = get_float_exception_flags(&env->active_fpu.fp_status); |
2393 |
if (excph & (float_flag_overflow | float_flag_invalid)) {
|
2394 |
wth2 = FP_TO_INT32_OVERFLOW; |
2395 |
} |
2396 |
|
2397 |
set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); |
2398 |
update_fcr31(env, GETPC()); |
2399 |
|
2400 |
return ((uint64_t)wth2 << 32) | wt2; |
2401 |
} |
2402 |
|
2403 |
uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) |
2404 |
{ |
2405 |
uint32_t fst2; |
2406 |
|
2407 |
fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
2408 |
update_fcr31(env, GETPC()); |
2409 |
return fst2;
|
2410 |
} |
2411 |
|
2412 |
uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) |
2413 |
{ |
2414 |
uint32_t fst2; |
2415 |
|
2416 |
fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
2417 |
update_fcr31(env, GETPC()); |
2418 |
return fst2;
|
2419 |
} |
2420 |
|
2421 |
uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) |
2422 |
{ |
2423 |
uint32_t fst2; |
2424 |
|
2425 |
fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
2426 |
update_fcr31(env, GETPC()); |
2427 |
return fst2;
|
2428 |
} |
2429 |
|
2430 |
uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) |
2431 |
{ |
2432 |
uint32_t wt2; |
2433 |
|
2434 |
wt2 = wt0; |
2435 |
update_fcr31(env, GETPC()); |
2436 |
return wt2;
|
2437 |
} |
2438 |
|
2439 |
uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) |
2440 |
{ |
2441 |
uint32_t wt2; |
2442 |
|
2443 |
wt2 = wth0; |
2444 |
update_fcr31(env, GETPC()); |
2445 |
return wt2;
|
2446 |
} |
2447 |
|
2448 |
uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) |
2449 |
{ |
2450 |
uint32_t wt2; |
2451 |
|
2452 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2453 |
update_fcr31(env, GETPC()); |
2454 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2455 |
& (float_flag_invalid | float_flag_overflow)) { |
2456 |
wt2 = FP_TO_INT32_OVERFLOW; |
2457 |
} |
2458 |
return wt2;
|
2459 |
} |
2460 |
|
2461 |
uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) |
2462 |
{ |
2463 |
uint32_t wt2; |
2464 |
|
2465 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2466 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2467 |
& (float_flag_invalid | float_flag_overflow)) { |
2468 |
wt2 = FP_TO_INT32_OVERFLOW; |
2469 |
} |
2470 |
update_fcr31(env, GETPC()); |
2471 |
return wt2;
|
2472 |
} |
2473 |
|
2474 |
uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) |
2475 |
{ |
2476 |
uint64_t dt2; |
2477 |
|
2478 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2479 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2480 |
restore_rounding_mode(env); |
2481 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2482 |
& (float_flag_invalid | float_flag_overflow)) { |
2483 |
dt2 = FP_TO_INT64_OVERFLOW; |
2484 |
} |
2485 |
update_fcr31(env, GETPC()); |
2486 |
return dt2;
|
2487 |
} |
2488 |
|
2489 |
uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) |
2490 |
{ |
2491 |
uint64_t dt2; |
2492 |
|
2493 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2494 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2495 |
restore_rounding_mode(env); |
2496 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2497 |
& (float_flag_invalid | float_flag_overflow)) { |
2498 |
dt2 = FP_TO_INT64_OVERFLOW; |
2499 |
} |
2500 |
update_fcr31(env, GETPC()); |
2501 |
return dt2;
|
2502 |
} |
2503 |
|
2504 |
uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) |
2505 |
{ |
2506 |
uint32_t wt2; |
2507 |
|
2508 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2509 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2510 |
restore_rounding_mode(env); |
2511 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2512 |
& (float_flag_invalid | float_flag_overflow)) { |
2513 |
wt2 = FP_TO_INT32_OVERFLOW; |
2514 |
} |
2515 |
update_fcr31(env, GETPC()); |
2516 |
return wt2;
|
2517 |
} |
2518 |
|
2519 |
uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) |
2520 |
{ |
2521 |
uint32_t wt2; |
2522 |
|
2523 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2524 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2525 |
restore_rounding_mode(env); |
2526 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2527 |
& (float_flag_invalid | float_flag_overflow)) { |
2528 |
wt2 = FP_TO_INT32_OVERFLOW; |
2529 |
} |
2530 |
update_fcr31(env, GETPC()); |
2531 |
return wt2;
|
2532 |
} |
2533 |
|
2534 |
uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) |
2535 |
{ |
2536 |
uint64_t dt2; |
2537 |
|
2538 |
dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
2539 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2540 |
& (float_flag_invalid | float_flag_overflow)) { |
2541 |
dt2 = FP_TO_INT64_OVERFLOW; |
2542 |
} |
2543 |
update_fcr31(env, GETPC()); |
2544 |
return dt2;
|
2545 |
} |
2546 |
|
2547 |
uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) |
2548 |
{ |
2549 |
uint64_t dt2; |
2550 |
|
2551 |
dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
2552 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2553 |
& (float_flag_invalid | float_flag_overflow)) { |
2554 |
dt2 = FP_TO_INT64_OVERFLOW; |
2555 |
} |
2556 |
update_fcr31(env, GETPC()); |
2557 |
return dt2;
|
2558 |
} |
2559 |
|
2560 |
uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) |
2561 |
{ |
2562 |
uint32_t wt2; |
2563 |
|
2564 |
wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
2565 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2566 |
& (float_flag_invalid | float_flag_overflow)) { |
2567 |
wt2 = FP_TO_INT32_OVERFLOW; |
2568 |
} |
2569 |
update_fcr31(env, GETPC()); |
2570 |
return wt2;
|
2571 |
} |
2572 |
|
2573 |
uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) |
2574 |
{ |
2575 |
uint32_t wt2; |
2576 |
|
2577 |
wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
2578 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2579 |
& (float_flag_invalid | float_flag_overflow)) { |
2580 |
wt2 = FP_TO_INT32_OVERFLOW; |
2581 |
} |
2582 |
update_fcr31(env, GETPC()); |
2583 |
return wt2;
|
2584 |
} |
2585 |
|
2586 |
uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) |
2587 |
{ |
2588 |
uint64_t dt2; |
2589 |
|
2590 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2591 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2592 |
restore_rounding_mode(env); |
2593 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2594 |
& (float_flag_invalid | float_flag_overflow)) { |
2595 |
dt2 = FP_TO_INT64_OVERFLOW; |
2596 |
} |
2597 |
update_fcr31(env, GETPC()); |
2598 |
return dt2;
|
2599 |
} |
2600 |
|
2601 |
uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) |
2602 |
{ |
2603 |
uint64_t dt2; |
2604 |
|
2605 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2606 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2607 |
restore_rounding_mode(env); |
2608 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2609 |
& (float_flag_invalid | float_flag_overflow)) { |
2610 |
dt2 = FP_TO_INT64_OVERFLOW; |
2611 |
} |
2612 |
update_fcr31(env, GETPC()); |
2613 |
return dt2;
|
2614 |
} |
2615 |
|
2616 |
uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) |
2617 |
{ |
2618 |
uint32_t wt2; |
2619 |
|
2620 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2621 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2622 |
restore_rounding_mode(env); |
2623 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2624 |
& (float_flag_invalid | float_flag_overflow)) { |
2625 |
wt2 = FP_TO_INT32_OVERFLOW; |
2626 |
} |
2627 |
update_fcr31(env, GETPC()); |
2628 |
return wt2;
|
2629 |
} |
2630 |
|
2631 |
uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) |
2632 |
{ |
2633 |
uint32_t wt2; |
2634 |
|
2635 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2636 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2637 |
restore_rounding_mode(env); |
2638 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2639 |
& (float_flag_invalid | float_flag_overflow)) { |
2640 |
wt2 = FP_TO_INT32_OVERFLOW; |
2641 |
} |
2642 |
update_fcr31(env, GETPC()); |
2643 |
return wt2;
|
2644 |
} |
2645 |
|
2646 |
uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) |
2647 |
{ |
2648 |
uint64_t dt2; |
2649 |
|
2650 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2651 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2652 |
restore_rounding_mode(env); |
2653 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2654 |
& (float_flag_invalid | float_flag_overflow)) { |
2655 |
dt2 = FP_TO_INT64_OVERFLOW; |
2656 |
} |
2657 |
update_fcr31(env, GETPC()); |
2658 |
return dt2;
|
2659 |
} |
2660 |
|
2661 |
uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) |
2662 |
{ |
2663 |
uint64_t dt2; |
2664 |
|
2665 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2666 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2667 |
restore_rounding_mode(env); |
2668 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2669 |
& (float_flag_invalid | float_flag_overflow)) { |
2670 |
dt2 = FP_TO_INT64_OVERFLOW; |
2671 |
} |
2672 |
update_fcr31(env, GETPC()); |
2673 |
return dt2;
|
2674 |
} |
2675 |
|
2676 |
uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) |
2677 |
{ |
2678 |
uint32_t wt2; |
2679 |
|
2680 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2681 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2682 |
restore_rounding_mode(env); |
2683 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2684 |
& (float_flag_invalid | float_flag_overflow)) { |
2685 |
wt2 = FP_TO_INT32_OVERFLOW; |
2686 |
} |
2687 |
update_fcr31(env, GETPC()); |
2688 |
return wt2;
|
2689 |
} |
2690 |
|
2691 |
uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) |
2692 |
{ |
2693 |
uint32_t wt2; |
2694 |
|
2695 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2696 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2697 |
restore_rounding_mode(env); |
2698 |
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
2699 |
& (float_flag_invalid | float_flag_overflow)) { |
2700 |
wt2 = FP_TO_INT32_OVERFLOW; |
2701 |
} |
2702 |
update_fcr31(env, GETPC()); |
2703 |
return wt2;
|
2704 |
} |
2705 |
|
2706 |
/* unary operations, not modifying fp status */
|
2707 |
#define FLOAT_UNOP(name) \
|
2708 |
uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
2709 |
{ \ |
2710 |
return float64_ ## name(fdt0); \ |
2711 |
} \ |
2712 |
uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
2713 |
{ \ |
2714 |
return float32_ ## name(fst0); \ |
2715 |
} \ |
2716 |
uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
2717 |
{ \ |
2718 |
uint32_t wt0; \ |
2719 |
uint32_t wth0; \ |
2720 |
\ |
2721 |
wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ |
2722 |
wth0 = float32_ ## name(fdt0 >> 32); \ |
2723 |
return ((uint64_t)wth0 << 32) | wt0; \ |
2724 |
} |
2725 |
FLOAT_UNOP(abs) |
2726 |
FLOAT_UNOP(chs) |
2727 |
#undef FLOAT_UNOP
|
2728 |
|
2729 |
/* MIPS specific unary operations */
|
2730 |
uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) |
2731 |
{ |
2732 |
uint64_t fdt2; |
2733 |
|
2734 |
fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
2735 |
update_fcr31(env, GETPC()); |
2736 |
return fdt2;
|
2737 |
} |
2738 |
|
2739 |
uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) |
2740 |
{ |
2741 |
uint32_t fst2; |
2742 |
|
2743 |
fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
2744 |
update_fcr31(env, GETPC()); |
2745 |
return fst2;
|
2746 |
} |
2747 |
|
2748 |
uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) |
2749 |
{ |
2750 |
uint64_t fdt2; |
2751 |
|
2752 |
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
2753 |
fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
2754 |
update_fcr31(env, GETPC()); |
2755 |
return fdt2;
|
2756 |
} |
2757 |
|
2758 |
uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) |
2759 |
{ |
2760 |
uint32_t fst2; |
2761 |
|
2762 |
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
2763 |
fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
2764 |
update_fcr31(env, GETPC()); |
2765 |
return fst2;
|
2766 |
} |
2767 |
|
2768 |
uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) |
2769 |
{ |
2770 |
uint64_t fdt2; |
2771 |
|
2772 |
fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
2773 |
update_fcr31(env, GETPC()); |
2774 |
return fdt2;
|
2775 |
} |
2776 |
|
2777 |
uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) |
2778 |
{ |
2779 |
uint32_t fst2; |
2780 |
|
2781 |
fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
2782 |
update_fcr31(env, GETPC()); |
2783 |
return fst2;
|
2784 |
} |
2785 |
|
2786 |
uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) |
2787 |
{ |
2788 |
uint32_t fst2; |
2789 |
uint32_t fsth2; |
2790 |
|
2791 |
fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2792 |
fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
|
2793 |
update_fcr31(env, GETPC()); |
2794 |
return ((uint64_t)fsth2 << 32) | fst2; |
2795 |
} |
2796 |
|
2797 |
uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) |
2798 |
{ |
2799 |
uint64_t fdt2; |
2800 |
|
2801 |
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
2802 |
fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
2803 |
update_fcr31(env, GETPC()); |
2804 |
return fdt2;
|
2805 |
} |
2806 |
|
2807 |
uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) |
2808 |
{ |
2809 |
uint32_t fst2; |
2810 |
|
2811 |
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
2812 |
fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
2813 |
update_fcr31(env, GETPC()); |
2814 |
return fst2;
|
2815 |
} |
2816 |
|
2817 |
uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) |
2818 |
{ |
2819 |
uint32_t fst2; |
2820 |
uint32_t fsth2; |
2821 |
|
2822 |
fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2823 |
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
|
2824 |
fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
2825 |
fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); |
2826 |
update_fcr31(env, GETPC()); |
2827 |
return ((uint64_t)fsth2 << 32) | fst2; |
2828 |
} |
2829 |
|
2830 |
#define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env) |
2831 |
|
2832 |
/* binary operations */
|
2833 |
#define FLOAT_BINOP(name) \
|
2834 |
uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
2835 |
uint64_t fdt0, uint64_t fdt1) \ |
2836 |
{ \ |
2837 |
uint64_t dt2; \ |
2838 |
\ |
2839 |
dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2840 |
update_fcr31(env, GETPC()); \ |
2841 |
return dt2; \
|
2842 |
} \ |
2843 |
\ |
2844 |
uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
2845 |
uint32_t fst0, uint32_t fst1) \ |
2846 |
{ \ |
2847 |
uint32_t wt2; \ |
2848 |
\ |
2849 |
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
2850 |
update_fcr31(env, GETPC()); \ |
2851 |
return wt2; \
|
2852 |
} \ |
2853 |
\ |
2854 |
uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
2855 |
uint64_t fdt0, \ |
2856 |
uint64_t fdt1) \ |
2857 |
{ \ |
2858 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
2859 |
uint32_t fsth0 = fdt0 >> 32; \
|
2860 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
2861 |
uint32_t fsth1 = fdt1 >> 32; \
|
2862 |
uint32_t wt2; \ |
2863 |
uint32_t wth2; \ |
2864 |
\ |
2865 |
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
2866 |
wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ |
2867 |
update_fcr31(env, GETPC()); \ |
2868 |
return ((uint64_t)wth2 << 32) | wt2; \ |
2869 |
} |
2870 |
|
2871 |
FLOAT_BINOP(add) |
2872 |
FLOAT_BINOP(sub) |
2873 |
FLOAT_BINOP(mul) |
2874 |
FLOAT_BINOP(div) |
2875 |
#undef FLOAT_BINOP
|
2876 |
|
2877 |
#define UNFUSED_FMA(prefix, a, b, c, flags) \
|
2878 |
{ \ |
2879 |
a = prefix##_mul(a, b, &env->active_fpu.fp_status); \ |
2880 |
if ((flags) & float_muladd_negate_c) { \
|
2881 |
a = prefix##_sub(a, c, &env->active_fpu.fp_status); \ |
2882 |
} else { \
|
2883 |
a = prefix##_add(a, c, &env->active_fpu.fp_status); \ |
2884 |
} \ |
2885 |
if ((flags) & float_muladd_negate_result) { \
|
2886 |
a = prefix##_chs(a); \ |
2887 |
} \ |
2888 |
} |
2889 |
|
2890 |
/* FMA based operations */
|
2891 |
#define FLOAT_FMA(name, type) \
|
2892 |
uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
2893 |
uint64_t fdt0, uint64_t fdt1, \ |
2894 |
uint64_t fdt2) \ |
2895 |
{ \ |
2896 |
UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \ |
2897 |
update_fcr31(env, GETPC()); \ |
2898 |
return fdt0; \
|
2899 |
} \ |
2900 |
\ |
2901 |
uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
2902 |
uint32_t fst0, uint32_t fst1, \ |
2903 |
uint32_t fst2) \ |
2904 |
{ \ |
2905 |
UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ |
2906 |
update_fcr31(env, GETPC()); \ |
2907 |
return fst0; \
|
2908 |
} \ |
2909 |
\ |
2910 |
uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
2911 |
uint64_t fdt0, uint64_t fdt1, \ |
2912 |
uint64_t fdt2) \ |
2913 |
{ \ |
2914 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
2915 |
uint32_t fsth0 = fdt0 >> 32; \
|
2916 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
2917 |
uint32_t fsth1 = fdt1 >> 32; \
|
2918 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
|
2919 |
uint32_t fsth2 = fdt2 >> 32; \
|
2920 |
\ |
2921 |
UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ |
2922 |
UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \ |
2923 |
update_fcr31(env, GETPC()); \ |
2924 |
return ((uint64_t)fsth0 << 32) | fst0; \ |
2925 |
} |
2926 |
FLOAT_FMA(madd, 0)
|
2927 |
FLOAT_FMA(msub, float_muladd_negate_c) |
2928 |
FLOAT_FMA(nmadd, float_muladd_negate_result) |
2929 |
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) |
2930 |
#undef FLOAT_FMA
|
2931 |
|
2932 |
/* MIPS specific binary operations */
|
2933 |
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
2934 |
{ |
2935 |
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
2936 |
fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); |
2937 |
update_fcr31(env, GETPC()); |
2938 |
return fdt2;
|
2939 |
} |
2940 |
|
2941 |
uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
2942 |
{ |
2943 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2944 |
fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
2945 |
update_fcr31(env, GETPC()); |
2946 |
return fst2;
|
2947 |
} |
2948 |
|
2949 |
uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
2950 |
{ |
2951 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
2952 |
uint32_t fsth0 = fdt0 >> 32;
|
2953 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF;
|
2954 |
uint32_t fsth2 = fdt2 >> 32;
|
2955 |
|
2956 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2957 |
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
2958 |
fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
2959 |
fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); |
2960 |
update_fcr31(env, GETPC()); |
2961 |
return ((uint64_t)fsth2 << 32) | fst2; |
2962 |
} |
2963 |
|
2964 |
uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
2965 |
{ |
2966 |
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
2967 |
fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); |
2968 |
fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
2969 |
update_fcr31(env, GETPC()); |
2970 |
return fdt2;
|
2971 |
} |
2972 |
|
2973 |
uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
2974 |
{ |
2975 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2976 |
fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
2977 |
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2978 |
update_fcr31(env, GETPC()); |
2979 |
return fst2;
|
2980 |
} |
2981 |
|
2982 |
uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
2983 |
{ |
2984 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
2985 |
uint32_t fsth0 = fdt0 >> 32;
|
2986 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF;
|
2987 |
uint32_t fsth2 = fdt2 >> 32;
|
2988 |
|
2989 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2990 |
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
2991 |
fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
2992 |
fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); |
2993 |
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2994 |
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2995 |
update_fcr31(env, GETPC()); |
2996 |
return ((uint64_t)fsth2 << 32) | fst2; |
2997 |
} |
2998 |
|
2999 |
uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
3000 |
{ |
3001 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
3002 |
uint32_t fsth0 = fdt0 >> 32;
|
3003 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF;
|
3004 |
uint32_t fsth1 = fdt1 >> 32;
|
3005 |
uint32_t fst2; |
3006 |
uint32_t fsth2; |
3007 |
|
3008 |
fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
3009 |
fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); |
3010 |
update_fcr31(env, GETPC()); |
3011 |
return ((uint64_t)fsth2 << 32) | fst2; |
3012 |
} |
3013 |
|
3014 |
uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
3015 |
{ |
3016 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
3017 |
uint32_t fsth0 = fdt0 >> 32;
|
3018 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF;
|
3019 |
uint32_t fsth1 = fdt1 >> 32;
|
3020 |
uint32_t fst2; |
3021 |
uint32_t fsth2; |
3022 |
|
3023 |
fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
3024 |
fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); |
3025 |
update_fcr31(env, GETPC()); |
3026 |
return ((uint64_t)fsth2 << 32) | fst2; |
3027 |
} |
3028 |
|
3029 |
/* compare operations */
|
3030 |
#define FOP_COND_D(op, cond) \
|
3031 |
void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3032 |
uint64_t fdt1, int cc) \
|
3033 |
{ \ |
3034 |
int c; \
|
3035 |
c = cond; \ |
3036 |
update_fcr31(env, GETPC()); \ |
3037 |
if (c) \
|
3038 |
SET_FP_COND(cc, env->active_fpu); \ |
3039 |
else \
|
3040 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3041 |
} \ |
3042 |
void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3043 |
uint64_t fdt1, int cc) \
|
3044 |
{ \ |
3045 |
int c; \
|
3046 |
fdt0 = float64_abs(fdt0); \ |
3047 |
fdt1 = float64_abs(fdt1); \ |
3048 |
c = cond; \ |
3049 |
update_fcr31(env, GETPC()); \ |
3050 |
if (c) \
|
3051 |
SET_FP_COND(cc, env->active_fpu); \ |
3052 |
else \
|
3053 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3054 |
} |
3055 |
|
3056 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3057 |
* but float64_unordered_quiet() is still called. */
|
3058 |
FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
|
3059 |
FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) |
3060 |
FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3061 |
FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3062 |
FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3063 |
FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3064 |
FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3065 |
FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3066 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3067 |
* but float64_unordered() is still called. */
|
3068 |
FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
|
3069 |
FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) |
3070 |
FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
3071 |
FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
3072 |
FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
3073 |
FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
3074 |
FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
3075 |
FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
3076 |
|
3077 |
#define FOP_COND_S(op, cond) \
|
3078 |
void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
3079 |
uint32_t fst1, int cc) \
|
3080 |
{ \ |
3081 |
int c; \
|
3082 |
c = cond; \ |
3083 |
update_fcr31(env, GETPC()); \ |
3084 |
if (c) \
|
3085 |
SET_FP_COND(cc, env->active_fpu); \ |
3086 |
else \
|
3087 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3088 |
} \ |
3089 |
void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
3090 |
uint32_t fst1, int cc) \
|
3091 |
{ \ |
3092 |
int c; \
|
3093 |
fst0 = float32_abs(fst0); \ |
3094 |
fst1 = float32_abs(fst1); \ |
3095 |
c = cond; \ |
3096 |
update_fcr31(env, GETPC()); \ |
3097 |
if (c) \
|
3098 |
SET_FP_COND(cc, env->active_fpu); \ |
3099 |
else \
|
3100 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3101 |
} |
3102 |
|
3103 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3104 |
* but float32_unordered_quiet() is still called. */
|
3105 |
FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
|
3106 |
FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) |
3107 |
FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3108 |
FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3109 |
FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3110 |
FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3111 |
FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3112 |
FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3113 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3114 |
* but float32_unordered() is still called. */
|
3115 |
FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
|
3116 |
FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) |
3117 |
FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
3118 |
FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
3119 |
FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
3120 |
FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
3121 |
FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
3122 |
FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
3123 |
|
3124 |
#define FOP_COND_PS(op, condl, condh) \
|
3125 |
void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3126 |
uint64_t fdt1, int cc) \
|
3127 |
{ \ |
3128 |
uint32_t fst0, fsth0, fst1, fsth1; \ |
3129 |
int ch, cl; \
|
3130 |
fst0 = fdt0 & 0XFFFFFFFF; \
|
3131 |
fsth0 = fdt0 >> 32; \
|
3132 |
fst1 = fdt1 & 0XFFFFFFFF; \
|
3133 |
fsth1 = fdt1 >> 32; \
|
3134 |
cl = condl; \ |
3135 |
ch = condh; \ |
3136 |
update_fcr31(env, GETPC()); \ |
3137 |
if (cl) \
|
3138 |
SET_FP_COND(cc, env->active_fpu); \ |
3139 |
else \
|
3140 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3141 |
if (ch) \
|
3142 |
SET_FP_COND(cc + 1, env->active_fpu); \
|
3143 |
else \
|
3144 |
CLEAR_FP_COND(cc + 1, env->active_fpu); \
|
3145 |
} \ |
3146 |
void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3147 |
uint64_t fdt1, int cc) \
|
3148 |
{ \ |
3149 |
uint32_t fst0, fsth0, fst1, fsth1; \ |
3150 |
int ch, cl; \
|
3151 |
fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
|
3152 |
fsth0 = float32_abs(fdt0 >> 32); \
|
3153 |
fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
|
3154 |
fsth1 = float32_abs(fdt1 >> 32); \
|
3155 |
cl = condl; \ |
3156 |
ch = condh; \ |
3157 |
update_fcr31(env, GETPC()); \ |
3158 |
if (cl) \
|
3159 |
SET_FP_COND(cc, env->active_fpu); \ |
3160 |
else \
|
3161 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3162 |
if (ch) \
|
3163 |
SET_FP_COND(cc + 1, env->active_fpu); \
|
3164 |
else \
|
3165 |
CLEAR_FP_COND(cc + 1, env->active_fpu); \
|
3166 |
} |
3167 |
|
3168 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3169 |
* but float32_unordered_quiet() is still called. */
|
3170 |
FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
|
3171 |
(float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
|
3172 |
FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), |
3173 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) |
3174 |
FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3175 |
float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3176 |
FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3177 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3178 |
FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3179 |
float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3180 |
FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3181 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3182 |
FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3183 |
float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3184 |
FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3185 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3186 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3187 |
* but float32_unordered() is still called. */
|
3188 |
FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
|
3189 |
(float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
|
3190 |
FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), |
3191 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) |
3192 |
FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
3193 |
float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
3194 |
FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
3195 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
3196 |
FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
3197 |
float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
3198 |
FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
3199 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
3200 |
FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3201 |
float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
3202 |
FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3203 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |