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/*
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 *  SH4 emulation
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 *
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 *  Copyright (c) 2005 Samuel Tardieu
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec.h"
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static inline void set_t(void)
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{
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    env->sr |= SR_T;
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}
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static inline void clr_t(void)
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{
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    env->sr &= ~SR_T;
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}
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static inline void cond_t(int cond)
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{
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    if (cond)
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        set_t();
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    else
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        clr_t();
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}
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void OPPROTO op_movl_imm_T0(void)
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{
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    T0 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_movl_imm_T1(void)
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{
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    T1 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_cmp_eq_imm_T0(void)
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{
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    cond_t((int32_t) T0 == (int32_t) PARAM1);
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    RETURN();
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}
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void OPPROTO op_cmd_eq_T0_T1(void)
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{
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    cond_t(T0 == T1);
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    RETURN();
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}
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void OPPROTO op_cmd_hs_T0_T1(void)
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{
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    cond_t((uint32_t) T0 <= (uint32_t) T1);
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    RETURN();
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}
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void OPPROTO op_cmd_ge_T0_T1(void)
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{
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    cond_t((int32_t) T0 <= (int32_t) T1);
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    RETURN();
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}
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void OPPROTO op_cmd_hi_T0_T1(void)
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{
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    cond_t((uint32_t) T0 < (uint32_t) T1);
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    RETURN();
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}
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void OPPROTO op_cmd_gt_T0_T1(void)
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{
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    cond_t((int32_t) T0 < (int32_t) T1);
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    RETURN();
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}
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void OPPROTO op_not_T0(void)
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{
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    T0 = ~T0;
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    RETURN();
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}
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void OPPROTO op_bf_s(void)
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{
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    env->delayed_pc = PARAM1;
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    if (!(env->sr & SR_T)) {
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        env->flags |= DELAY_SLOT_TRUE;
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    }
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    RETURN();
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}
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void OPPROTO op_bt_s(void)
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{
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    env->delayed_pc = PARAM1;
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    if (env->sr & SR_T) {
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        env->flags |= DELAY_SLOT_TRUE;
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    }
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    RETURN();
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}
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void OPPROTO op_store_flags(void)
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{
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    env->flags &= DELAY_SLOT_TRUE;
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    env->flags |= PARAM1;
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    RETURN();
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}
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void OPPROTO op_bra(void)
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{
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    env->delayed_pc = PARAM1;
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    RETURN();
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}
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void OPPROTO op_braf_T0(void)
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{
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    env->delayed_pc = PARAM1 + T0;
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    RETURN();
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}
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void OPPROTO op_bsr(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = PARAM2;
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    RETURN();
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}
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void OPPROTO op_bsrf_T0(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = PARAM1 + T0;
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    RETURN();
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}
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void OPPROTO op_jsr_T0(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = T0;
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    RETURN();
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}
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void OPPROTO op_rts(void)
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{
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    env->delayed_pc = env->pr;
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    RETURN();
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}
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void OPPROTO op_addl_imm_T0(void)
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{
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    T0 += PARAM1;
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    RETURN();
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}
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void OPPROTO op_addl_imm_T1(void)
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{
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    T1 += PARAM1;
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    RETURN();
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}
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void OPPROTO op_clrmac(void)
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{
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    env->mach = env->macl = 0;
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    RETURN();
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}
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void OPPROTO op_clrs(void)
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{
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    env->sr &= ~SR_S;
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    RETURN();
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}
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void OPPROTO op_clrt(void)
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{
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    env->sr &= ~SR_T;
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    RETURN();
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}
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void OPPROTO op_ldtlb(void)
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{
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    helper_ldtlb();
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    RETURN();
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}
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void OPPROTO op_sets(void)
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{
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    env->sr |= SR_S;
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    RETURN();
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}
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void OPPROTO op_sett(void)
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{
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    env->sr |= SR_T;
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    RETURN();
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}
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void OPPROTO op_frchg(void)
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{
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    env->fpscr ^= FPSCR_FR;
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    RETURN();
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}
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void OPPROTO op_fschg(void)
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{
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    env->fpscr ^= FPSCR_SZ;
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    RETURN();
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}
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void OPPROTO op_rte(void)
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{
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    env->sr = env->ssr;
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    env->delayed_pc = env->spc;
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    RETURN();
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}
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void OPPROTO op_swapb_T0(void)
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{
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    T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff);
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    RETURN();
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}
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void OPPROTO op_swapw_T0(void)
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{
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    T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff);
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    RETURN();
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}
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void OPPROTO op_xtrct_T0_T1(void)
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{
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    T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff);
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    RETURN();
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}
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void OPPROTO op_add_T0_T1(void)
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{
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    T1 += T0;
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    RETURN();
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}
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void OPPROTO op_addc_T0_T1(void)
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{
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    helper_addc_T0_T1();
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    RETURN();
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}
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void OPPROTO op_addv_T0_T1(void)
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{
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    helper_addv_T0_T1();
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    RETURN();
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}
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void OPPROTO op_cmp_eq_T0_T1(void)
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{
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    cond_t(T1 == T0);
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    RETURN();
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}
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void OPPROTO op_cmp_ge_T0_T1(void)
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{
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    cond_t((int32_t) T1 >= (int32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_gt_T0_T1(void)
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{
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    cond_t((int32_t) T1 > (int32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_hi_T0_T1(void)
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{
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    cond_t((uint32_t) T1 > (uint32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_hs_T0_T1(void)
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{
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    cond_t((uint32_t) T1 >= (uint32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_str_T0_T1(void)
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{
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    cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
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           (T0 & 0x0000ff00) == (T1 & 0x0000ff00) ||
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           (T0 & 0x00ff0000) == (T1 & 0x00ff0000) ||
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           (T0 & 0xff000000) == (T1 & 0xff000000));
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    RETURN();
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}
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void OPPROTO op_tst_T0_T1(void)
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{
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    cond_t((T1 & T0) == 0);
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    RETURN();
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}
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void OPPROTO op_div0s_T0_T1(void)
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{
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    if (T1 & 0x80000000)
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        env->sr |= SR_Q;
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    else
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        env->sr &= ~SR_Q;
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    if (T0 & 0x80000000)
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        env->sr |= SR_M;
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    else
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        env->sr &= ~SR_M;
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    cond_t((T1 ^ T0) & 0x80000000);
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    RETURN();
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}
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void OPPROTO op_div0u(void)
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{
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    env->sr &= ~(SR_M | SR_Q | SR_T);
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    RETURN();
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}
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void OPPROTO op_div1_T0_T1(void)
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{
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    helper_div1_T0_T1();
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    RETURN();
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}
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void OPPROTO op_dmulsl_T0_T1(void)
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{
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    helper_dmulsl_T0_T1();
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    RETURN();
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}
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void OPPROTO op_dmulul_T0_T1(void)
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{
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    helper_dmulul_T0_T1();
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    RETURN();
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}
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void OPPROTO op_macl_T0_T1(void)
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{
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    helper_macl_T0_T1();
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    RETURN();
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}
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void OPPROTO op_macw_T0_T1(void)
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{
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    helper_macw_T0_T1();
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    RETURN();
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}
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void OPPROTO op_mull_T0_T1(void)
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{
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    env->macl = (T0 * T1) & 0xffffffff;
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    RETURN();
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}
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void OPPROTO op_mulsw_T0_T1(void)
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{
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    env->macl = (int32_t)(int16_t) T0 *(int32_t)(int16_t) T1;
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    RETURN();
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}
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void OPPROTO op_muluw_T0_T1(void)
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{
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    env->macl = (uint32_t)(uint16_t) T0 *(uint32_t)(uint16_t) T1;
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    RETURN();
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}
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void OPPROTO op_neg_T0(void)
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{
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    T0 = -T0;
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    RETURN();
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}
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void OPPROTO op_negc_T0(void)
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{
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    helper_negc_T0();
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    RETURN();
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}
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void OPPROTO op_shad_T0_T1(void)
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{
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    if ((T0 & 0x80000000) == 0)
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        T1 <<= (T0 & 0x1f);
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    else if ((T0 & 0x1f) == 0)
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        T1 = (T1 & 0x80000000)? 0xffffffff : 0;
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    else
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        T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1);
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    RETURN();
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}
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void OPPROTO op_shld_T0_T1(void)
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{
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    if ((T0 & 0x80000000) == 0)
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        T1 <<= (T0 & 0x1f);
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    else if ((T0 & 0x1f) == 0)
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        T1 = 0;
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    else
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        T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1);
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    RETURN();
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}
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void OPPROTO op_subc_T0_T1(void)
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{
410 fdf9b3e8 bellard
    helper_subc_T0_T1();
411 fdf9b3e8 bellard
    RETURN();
412 fdf9b3e8 bellard
}
413 fdf9b3e8 bellard
414 fdf9b3e8 bellard
void OPPROTO op_subv_T0_T1(void)
415 fdf9b3e8 bellard
{
416 fdf9b3e8 bellard
    helper_subv_T0_T1();
417 fdf9b3e8 bellard
    RETURN();
418 fdf9b3e8 bellard
}
419 fdf9b3e8 bellard
420 fdf9b3e8 bellard
void OPPROTO op_trapa(void)
421 fdf9b3e8 bellard
{
422 e96e2044 ths
    env->tra = PARAM1 << 2;
423 fdf9b3e8 bellard
    env->exception_index = 0x160;
424 fdf9b3e8 bellard
    do_raise_exception();
425 fdf9b3e8 bellard
    RETURN();
426 fdf9b3e8 bellard
}
427 fdf9b3e8 bellard
428 fdf9b3e8 bellard
void OPPROTO op_cmp_pl_T0(void)
429 fdf9b3e8 bellard
{
430 fdf9b3e8 bellard
    cond_t((int32_t) T0 > 0);
431 fdf9b3e8 bellard
    RETURN();
432 fdf9b3e8 bellard
}
433 fdf9b3e8 bellard
434 fdf9b3e8 bellard
void OPPROTO op_cmp_pz_T0(void)
435 fdf9b3e8 bellard
{
436 fdf9b3e8 bellard
    cond_t((int32_t) T0 >= 0);
437 fdf9b3e8 bellard
    RETURN();
438 fdf9b3e8 bellard
}
439 fdf9b3e8 bellard
440 fdf9b3e8 bellard
void OPPROTO op_jmp_T0(void)
441 fdf9b3e8 bellard
{
442 fdf9b3e8 bellard
    env->delayed_pc = T0;
443 fdf9b3e8 bellard
    RETURN();
444 fdf9b3e8 bellard
}
445 fdf9b3e8 bellard
446 fdf9b3e8 bellard
void OPPROTO op_movl_rN_rN(void)
447 fdf9b3e8 bellard
{
448 fdf9b3e8 bellard
    env->gregs[PARAM2] = env->gregs[PARAM1];
449 fdf9b3e8 bellard
    RETURN();
450 fdf9b3e8 bellard
}
451 fdf9b3e8 bellard
452 fdf9b3e8 bellard
void OPPROTO op_ldcl_rMplus_rN_bank(void)
453 fdf9b3e8 bellard
{
454 fdf9b3e8 bellard
    env->gregs[PARAM2] = env->gregs[PARAM1];
455 fdf9b3e8 bellard
    env->gregs[PARAM1] += 4;
456 fdf9b3e8 bellard
    RETURN();
457 fdf9b3e8 bellard
}
458 fdf9b3e8 bellard
459 eda9b09b bellard
void OPPROTO op_ldc_T0_sr(void)
460 eda9b09b bellard
{
461 eda9b09b bellard
    env->sr = T0 & 0x700083f3;
462 eda9b09b bellard
    RETURN();
463 eda9b09b bellard
}
464 eda9b09b bellard
465 eda9b09b bellard
void OPPROTO op_stc_sr_T0(void)
466 eda9b09b bellard
{
467 eda9b09b bellard
    T0 = env->sr;
468 eda9b09b bellard
    RETURN();
469 eda9b09b bellard
}
470 eda9b09b bellard
471 fdf9b3e8 bellard
#define LDSTOPS(target,load,store) \
472 fdf9b3e8 bellard
void OPPROTO op_##load##_T0_##target (void) \
473 fdf9b3e8 bellard
{ env ->target = T0;   RETURN(); \
474 fdf9b3e8 bellard
} \
475 fdf9b3e8 bellard
void OPPROTO op_##store##_##target##_T0 (void) \
476 fdf9b3e8 bellard
{ T0 = env->target;   RETURN(); \
477 fdf9b3e8 bellard
} \
478 fdf9b3e8 bellard
479 fdf9b3e8 bellard
    LDSTOPS(gbr, ldc, stc)
480 fdf9b3e8 bellard
    LDSTOPS(vbr, ldc, stc)
481 fdf9b3e8 bellard
    LDSTOPS(ssr, ldc, stc)
482 fdf9b3e8 bellard
    LDSTOPS(spc, ldc, stc)
483 fdf9b3e8 bellard
    LDSTOPS(sgr, ldc, stc)
484 fdf9b3e8 bellard
    LDSTOPS(dbr, ldc, stc)
485 fdf9b3e8 bellard
    LDSTOPS(mach, lds, sts)
486 fdf9b3e8 bellard
    LDSTOPS(macl, lds, sts)
487 fdf9b3e8 bellard
    LDSTOPS(pr, lds, sts)
488 eda9b09b bellard
    LDSTOPS(fpul, lds, sts)
489 eda9b09b bellard
490 eda9b09b bellard
void OPPROTO op_lds_T0_fpscr(void)
491 eda9b09b bellard
{
492 eda9b09b bellard
    env->fpscr = T0 & 0x003fffff;
493 ea6cf6be ths
    env->fp_status.float_rounding_mode = T0 & 0x01 ?
494 ea6cf6be ths
      float_round_to_zero : float_round_nearest_even;
495 ea6cf6be ths
496 eda9b09b bellard
    RETURN();
497 eda9b09b bellard
}
498 eda9b09b bellard
499 eda9b09b bellard
void OPPROTO op_sts_fpscr_T0(void)
500 eda9b09b bellard
{
501 eda9b09b bellard
    T0 = env->fpscr & 0x003fffff;
502 eda9b09b bellard
    RETURN();
503 eda9b09b bellard
}
504 fdf9b3e8 bellard
505 fdf9b3e8 bellard
void OPPROTO op_movt_rN(void)
506 fdf9b3e8 bellard
{
507 fdf9b3e8 bellard
    env->gregs[PARAM1] = env->sr & SR_T;
508 fdf9b3e8 bellard
    RETURN();
509 fdf9b3e8 bellard
}
510 fdf9b3e8 bellard
511 fdf9b3e8 bellard
void OPPROTO op_rotcl_Rn(void)
512 fdf9b3e8 bellard
{
513 fdf9b3e8 bellard
    helper_rotcl(&env->gregs[PARAM1]);
514 fdf9b3e8 bellard
    RETURN();
515 fdf9b3e8 bellard
}
516 fdf9b3e8 bellard
517 fdf9b3e8 bellard
void OPPROTO op_rotcr_Rn(void)
518 fdf9b3e8 bellard
{
519 fdf9b3e8 bellard
    helper_rotcr(&env->gregs[PARAM1]);
520 fdf9b3e8 bellard
    RETURN();
521 fdf9b3e8 bellard
}
522 fdf9b3e8 bellard
523 fdf9b3e8 bellard
void OPPROTO op_rotl_Rn(void)
524 fdf9b3e8 bellard
{
525 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 0x80000000);
526 fdf9b3e8 bellard
    env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
527 fdf9b3e8 bellard
    RETURN();
528 fdf9b3e8 bellard
}
529 fdf9b3e8 bellard
530 fdf9b3e8 bellard
void OPPROTO op_rotr_Rn(void)
531 fdf9b3e8 bellard
{
532 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
533 fdf9b3e8 bellard
    env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
534 fdf9b3e8 bellard
        ((env->sr & SR_T) ? 0x80000000 : 0);
535 fdf9b3e8 bellard
    RETURN();
536 fdf9b3e8 bellard
}
537 fdf9b3e8 bellard
538 fdf9b3e8 bellard
void OPPROTO op_shal_Rn(void)
539 fdf9b3e8 bellard
{
540 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 0x80000000);
541 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 1;
542 fdf9b3e8 bellard
    RETURN();
543 fdf9b3e8 bellard
}
544 fdf9b3e8 bellard
545 fdf9b3e8 bellard
void OPPROTO op_shar_Rn(void)
546 fdf9b3e8 bellard
{
547 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
548 24988dc2 aurel32
    *(int32_t *)&env->gregs[PARAM1] >>= 1;
549 fdf9b3e8 bellard
    RETURN();
550 fdf9b3e8 bellard
}
551 fdf9b3e8 bellard
552 fdf9b3e8 bellard
void OPPROTO op_shlr_Rn(void)
553 fdf9b3e8 bellard
{
554 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
555 a5d251bd ths
    env->gregs[PARAM1] >>= 1;
556 fdf9b3e8 bellard
    RETURN();
557 fdf9b3e8 bellard
}
558 fdf9b3e8 bellard
559 fdf9b3e8 bellard
void OPPROTO op_shll2_Rn(void)
560 fdf9b3e8 bellard
{
561 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 2;
562 fdf9b3e8 bellard
    RETURN();
563 fdf9b3e8 bellard
}
564 fdf9b3e8 bellard
565 fdf9b3e8 bellard
void OPPROTO op_shll8_Rn(void)
566 fdf9b3e8 bellard
{
567 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 8;
568 fdf9b3e8 bellard
    RETURN();
569 fdf9b3e8 bellard
}
570 fdf9b3e8 bellard
571 fdf9b3e8 bellard
void OPPROTO op_shll16_Rn(void)
572 fdf9b3e8 bellard
{
573 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 16;
574 fdf9b3e8 bellard
    RETURN();
575 fdf9b3e8 bellard
}
576 fdf9b3e8 bellard
577 fdf9b3e8 bellard
void OPPROTO op_shlr2_Rn(void)
578 fdf9b3e8 bellard
{
579 a5d251bd ths
    env->gregs[PARAM1] >>= 2;
580 fdf9b3e8 bellard
    RETURN();
581 fdf9b3e8 bellard
}
582 fdf9b3e8 bellard
583 fdf9b3e8 bellard
void OPPROTO op_shlr8_Rn(void)
584 fdf9b3e8 bellard
{
585 a5d251bd ths
    env->gregs[PARAM1] >>= 8;
586 fdf9b3e8 bellard
    RETURN();
587 fdf9b3e8 bellard
}
588 fdf9b3e8 bellard
589 fdf9b3e8 bellard
void OPPROTO op_shlr16_Rn(void)
590 fdf9b3e8 bellard
{
591 a5d251bd ths
    env->gregs[PARAM1] >>= 16;
592 fdf9b3e8 bellard
    RETURN();
593 fdf9b3e8 bellard
}
594 fdf9b3e8 bellard
595 fdf9b3e8 bellard
void OPPROTO op_tasb_rN(void)
596 fdf9b3e8 bellard
{
597 526ccb7a balrog
    cond_t((env->gregs[PARAM1] & 0xff) == 0);
598 59aa3bbf balrog
    *(int8_t *) &env->gregs[PARAM1] |= 0x80;
599 fdf9b3e8 bellard
    RETURN();
600 fdf9b3e8 bellard
}
601 fdf9b3e8 bellard
602 fdf9b3e8 bellard
void OPPROTO op_movl_T0_rN(void)
603 fdf9b3e8 bellard
{
604 fdf9b3e8 bellard
    env->gregs[PARAM1] = T0;
605 fdf9b3e8 bellard
    RETURN();
606 fdf9b3e8 bellard
}
607 fdf9b3e8 bellard
608 fdf9b3e8 bellard
void OPPROTO op_movl_T1_rN(void)
609 fdf9b3e8 bellard
{
610 fdf9b3e8 bellard
    env->gregs[PARAM1] = T1;
611 fdf9b3e8 bellard
    RETURN();
612 fdf9b3e8 bellard
}
613 fdf9b3e8 bellard
614 fdf9b3e8 bellard
void OPPROTO op_movb_rN_T0(void)
615 fdf9b3e8 bellard
{
616 fdf9b3e8 bellard
    T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
617 fdf9b3e8 bellard
    RETURN();
618 fdf9b3e8 bellard
}
619 fdf9b3e8 bellard
620 fdf9b3e8 bellard
void OPPROTO op_movub_rN_T0(void)
621 fdf9b3e8 bellard
{
622 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1] & 0xff;
623 fdf9b3e8 bellard
    RETURN();
624 fdf9b3e8 bellard
}
625 fdf9b3e8 bellard
626 fdf9b3e8 bellard
void OPPROTO op_movw_rN_T0(void)
627 fdf9b3e8 bellard
{
628 fdf9b3e8 bellard
    T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
629 fdf9b3e8 bellard
    RETURN();
630 fdf9b3e8 bellard
}
631 fdf9b3e8 bellard
632 fdf9b3e8 bellard
void OPPROTO op_movuw_rN_T0(void)
633 fdf9b3e8 bellard
{
634 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1] & 0xffff;
635 fdf9b3e8 bellard
    RETURN();
636 fdf9b3e8 bellard
}
637 fdf9b3e8 bellard
638 fdf9b3e8 bellard
void OPPROTO op_movl_rN_T0(void)
639 fdf9b3e8 bellard
{
640 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1];
641 fdf9b3e8 bellard
    RETURN();
642 fdf9b3e8 bellard
}
643 fdf9b3e8 bellard
644 fdf9b3e8 bellard
void OPPROTO op_movb_rN_T1(void)
645 fdf9b3e8 bellard
{
646 fdf9b3e8 bellard
    T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
647 fdf9b3e8 bellard
    RETURN();
648 fdf9b3e8 bellard
}
649 fdf9b3e8 bellard
650 fdf9b3e8 bellard
void OPPROTO op_movub_rN_T1(void)
651 fdf9b3e8 bellard
{
652 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1] & 0xff;
653 fdf9b3e8 bellard
    RETURN();
654 fdf9b3e8 bellard
}
655 fdf9b3e8 bellard
656 fdf9b3e8 bellard
void OPPROTO op_movw_rN_T1(void)
657 fdf9b3e8 bellard
{
658 fdf9b3e8 bellard
    T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
659 fdf9b3e8 bellard
    RETURN();
660 fdf9b3e8 bellard
}
661 fdf9b3e8 bellard
662 fdf9b3e8 bellard
void OPPROTO op_movuw_rN_T1(void)
663 fdf9b3e8 bellard
{
664 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1] & 0xffff;
665 fdf9b3e8 bellard
    RETURN();
666 fdf9b3e8 bellard
}
667 fdf9b3e8 bellard
668 fdf9b3e8 bellard
void OPPROTO op_movl_rN_T1(void)
669 fdf9b3e8 bellard
{
670 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1];
671 fdf9b3e8 bellard
    RETURN();
672 fdf9b3e8 bellard
}
673 fdf9b3e8 bellard
674 fdf9b3e8 bellard
void OPPROTO op_movl_imm_rN(void)
675 fdf9b3e8 bellard
{
676 fdf9b3e8 bellard
    env->gregs[PARAM2] = PARAM1;
677 fdf9b3e8 bellard
    RETURN();
678 fdf9b3e8 bellard
}
679 fdf9b3e8 bellard
680 eda9b09b bellard
void OPPROTO op_fmov_frN_FT0(void)
681 eda9b09b bellard
{
682 e04ea3dc ths
    FT0 = env->fregs[PARAM1];
683 eda9b09b bellard
    RETURN();
684 eda9b09b bellard
}
685 eda9b09b bellard
686 eda9b09b bellard
void OPPROTO op_fmov_drN_DT0(void)
687 eda9b09b bellard
{
688 e04ea3dc ths
    CPU_DoubleU d;
689 e04ea3dc ths
690 e04ea3dc ths
    d.l.upper = *(uint32_t *)&env->fregs[PARAM1];
691 e04ea3dc ths
    d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
692 e04ea3dc ths
    DT0 = d.d;
693 eda9b09b bellard
    RETURN();
694 eda9b09b bellard
}
695 eda9b09b bellard
696 ea6cf6be ths
void OPPROTO op_fmov_frN_FT1(void)
697 ea6cf6be ths
{
698 e04ea3dc ths
    FT1 = env->fregs[PARAM1];
699 ea6cf6be ths
    RETURN();
700 ea6cf6be ths
}
701 ea6cf6be ths
702 ea6cf6be ths
void OPPROTO op_fmov_drN_DT1(void)
703 ea6cf6be ths
{
704 e04ea3dc ths
    CPU_DoubleU d;
705 e04ea3dc ths
706 e04ea3dc ths
    d.l.upper = *(uint32_t *)&env->fregs[PARAM1];
707 e04ea3dc ths
    d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
708 e04ea3dc ths
    DT1 = d.d;
709 ea6cf6be ths
    RETURN();
710 ea6cf6be ths
}
711 ea6cf6be ths
712 eda9b09b bellard
void OPPROTO op_fmov_FT0_frN(void)
713 eda9b09b bellard
{
714 e04ea3dc ths
    env->fregs[PARAM1] = FT0;
715 eda9b09b bellard
    RETURN();
716 eda9b09b bellard
}
717 eda9b09b bellard
718 eda9b09b bellard
void OPPROTO op_fmov_DT0_drN(void)
719 eda9b09b bellard
{
720 e04ea3dc ths
    CPU_DoubleU d;
721 e04ea3dc ths
722 e04ea3dc ths
    d.d = DT0;
723 e04ea3dc ths
    *(uint32_t *)&env->fregs[PARAM1] = d.l.upper;
724 e04ea3dc ths
    *(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
725 eda9b09b bellard
    RETURN();
726 eda9b09b bellard
}
727 eda9b09b bellard
728 ea6cf6be ths
void OPPROTO op_fadd_FT(void)
729 ea6cf6be ths
{
730 ea6cf6be ths
    FT0 = float32_add(FT0, FT1, &env->fp_status);
731 ea6cf6be ths
    RETURN();
732 ea6cf6be ths
}
733 ea6cf6be ths
734 ea6cf6be ths
void OPPROTO op_fadd_DT(void)
735 ea6cf6be ths
{
736 ea6cf6be ths
    DT0 = float64_add(DT0, DT1, &env->fp_status);
737 ea6cf6be ths
    RETURN();
738 ea6cf6be ths
}
739 ea6cf6be ths
740 ea6cf6be ths
void OPPROTO op_fsub_FT(void)
741 ea6cf6be ths
{
742 ea6cf6be ths
    FT0 = float32_sub(FT0, FT1, &env->fp_status);
743 ea6cf6be ths
    RETURN();
744 ea6cf6be ths
}
745 ea6cf6be ths
746 ea6cf6be ths
void OPPROTO op_fsub_DT(void)
747 ea6cf6be ths
{
748 ea6cf6be ths
    DT0 = float64_sub(DT0, DT1, &env->fp_status);
749 ea6cf6be ths
    RETURN();
750 ea6cf6be ths
}
751 ea6cf6be ths
752 ea6cf6be ths
void OPPROTO op_fmul_FT(void)
753 ea6cf6be ths
{
754 ea6cf6be ths
    FT0 = float32_mul(FT0, FT1, &env->fp_status);
755 ea6cf6be ths
    RETURN();
756 ea6cf6be ths
}
757 ea6cf6be ths
758 ea6cf6be ths
void OPPROTO op_fmul_DT(void)
759 ea6cf6be ths
{
760 ea6cf6be ths
    DT0 = float64_mul(DT0, DT1, &env->fp_status);
761 ea6cf6be ths
    RETURN();
762 ea6cf6be ths
}
763 ea6cf6be ths
764 ea6cf6be ths
void OPPROTO op_fdiv_FT(void)
765 ea6cf6be ths
{
766 ea6cf6be ths
    FT0 = float32_div(FT0, FT1, &env->fp_status);
767 ea6cf6be ths
    RETURN();
768 ea6cf6be ths
}
769 ea6cf6be ths
770 ea6cf6be ths
void OPPROTO op_fdiv_DT(void)
771 ea6cf6be ths
{
772 ea6cf6be ths
    DT0 = float64_div(DT0, DT1, &env->fp_status);
773 ea6cf6be ths
    RETURN();
774 ea6cf6be ths
}
775 ea6cf6be ths
776 24988dc2 aurel32
void OPPROTO op_fcmp_eq_FT(void)
777 24988dc2 aurel32
{
778 24988dc2 aurel32
    cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);
779 24988dc2 aurel32
    RETURN();
780 24988dc2 aurel32
}
781 24988dc2 aurel32
782 24988dc2 aurel32
void OPPROTO op_fcmp_eq_DT(void)
783 24988dc2 aurel32
{
784 24988dc2 aurel32
    cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);
785 24988dc2 aurel32
    RETURN();
786 24988dc2 aurel32
}
787 24988dc2 aurel32
788 24988dc2 aurel32
void OPPROTO op_fcmp_gt_FT(void)
789 24988dc2 aurel32
{
790 24988dc2 aurel32
    cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);
791 24988dc2 aurel32
    RETURN();
792 24988dc2 aurel32
}
793 24988dc2 aurel32
794 24988dc2 aurel32
void OPPROTO op_fcmp_gt_DT(void)
795 24988dc2 aurel32
{
796 24988dc2 aurel32
    cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);
797 24988dc2 aurel32
    RETURN();
798 24988dc2 aurel32
}
799 24988dc2 aurel32
800 ea6cf6be ths
void OPPROTO op_float_FT(void)
801 ea6cf6be ths
{
802 ea6cf6be ths
    FT0 = int32_to_float32(env->fpul, &env->fp_status);
803 ea6cf6be ths
    RETURN();
804 ea6cf6be ths
}
805 ea6cf6be ths
806 ea6cf6be ths
void OPPROTO op_float_DT(void)
807 ea6cf6be ths
{
808 ea6cf6be ths
    DT0 = int32_to_float64(env->fpul, &env->fp_status);
809 ea6cf6be ths
    RETURN();
810 ea6cf6be ths
}
811 ea6cf6be ths
812 ea6cf6be ths
void OPPROTO op_ftrc_FT(void)
813 ea6cf6be ths
{
814 ea6cf6be ths
    env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status);
815 ea6cf6be ths
    RETURN();
816 ea6cf6be ths
}
817 ea6cf6be ths
818 ea6cf6be ths
void OPPROTO op_ftrc_DT(void)
819 ea6cf6be ths
{
820 ea6cf6be ths
    env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status);
821 ea6cf6be ths
    RETURN();
822 ea6cf6be ths
}
823 ea6cf6be ths
824 24988dc2 aurel32
void OPPROTO op_fneg_frN(void)
825 24988dc2 aurel32
{
826 24988dc2 aurel32
    env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]);
827 24988dc2 aurel32
    RETURN();
828 24988dc2 aurel32
}
829 24988dc2 aurel32
830 24988dc2 aurel32
void OPPROTO op_fabs_FT(void)
831 24988dc2 aurel32
{
832 24988dc2 aurel32
    FT0 = float32_abs(FT0);
833 24988dc2 aurel32
    RETURN();
834 24988dc2 aurel32
}
835 24988dc2 aurel32
836 24988dc2 aurel32
void OPPROTO op_fabs_DT(void)
837 24988dc2 aurel32
{
838 24988dc2 aurel32
    DT0 = float64_abs(DT0);
839 24988dc2 aurel32
    RETURN();
840 24988dc2 aurel32
}
841 24988dc2 aurel32
842 24988dc2 aurel32
void OPPROTO op_fcnvsd_FT_DT(void)
843 24988dc2 aurel32
{
844 24988dc2 aurel32
    DT0 = float32_to_float64(FT0, &env->fp_status);
845 24988dc2 aurel32
    RETURN();
846 24988dc2 aurel32
}
847 24988dc2 aurel32
848 24988dc2 aurel32
void OPPROTO op_fcnvds_DT_FT(void)
849 24988dc2 aurel32
{
850 24988dc2 aurel32
    FT0 = float64_to_float32(DT0, &env->fp_status);
851 24988dc2 aurel32
    RETURN();
852 24988dc2 aurel32
}
853 24988dc2 aurel32
854 24988dc2 aurel32
void OPPROTO op_fsqrt_FT(void)
855 24988dc2 aurel32
{
856 24988dc2 aurel32
    FT0 = float32_sqrt(FT0, &env->fp_status);
857 24988dc2 aurel32
    RETURN();
858 24988dc2 aurel32
}
859 24988dc2 aurel32
860 24988dc2 aurel32
void OPPROTO op_fsqrt_DT(void)
861 24988dc2 aurel32
{
862 24988dc2 aurel32
    DT0 = float64_sqrt(DT0, &env->fp_status);
863 24988dc2 aurel32
    RETURN();
864 24988dc2 aurel32
}
865 24988dc2 aurel32
866 ea6cf6be ths
void OPPROTO op_fmov_T0_frN(void)
867 ea6cf6be ths
{
868 24988dc2 aurel32
    *(uint32_t *)&env->fregs[PARAM1] = T0;
869 ea6cf6be ths
    RETURN();
870 ea6cf6be ths
}
871 ea6cf6be ths
872 fdf9b3e8 bellard
void OPPROTO op_dec1_rN(void)
873 fdf9b3e8 bellard
{
874 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 1;
875 fdf9b3e8 bellard
    RETURN();
876 fdf9b3e8 bellard
}
877 fdf9b3e8 bellard
878 fdf9b3e8 bellard
void OPPROTO op_dec2_rN(void)
879 fdf9b3e8 bellard
{
880 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 2;
881 fdf9b3e8 bellard
    RETURN();
882 fdf9b3e8 bellard
}
883 fdf9b3e8 bellard
884 fdf9b3e8 bellard
void OPPROTO op_dec4_rN(void)
885 fdf9b3e8 bellard
{
886 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 4;
887 fdf9b3e8 bellard
    RETURN();
888 fdf9b3e8 bellard
}
889 fdf9b3e8 bellard
890 eda9b09b bellard
void OPPROTO op_dec8_rN(void)
891 eda9b09b bellard
{
892 0a618140 ths
    env->gregs[PARAM1] -= 8;
893 eda9b09b bellard
    RETURN();
894 eda9b09b bellard
}
895 eda9b09b bellard
896 fdf9b3e8 bellard
void OPPROTO op_inc1_rN(void)
897 fdf9b3e8 bellard
{
898 fdf9b3e8 bellard
    env->gregs[PARAM1] += 1;
899 fdf9b3e8 bellard
    RETURN();
900 fdf9b3e8 bellard
}
901 fdf9b3e8 bellard
902 fdf9b3e8 bellard
void OPPROTO op_inc2_rN(void)
903 fdf9b3e8 bellard
{
904 fdf9b3e8 bellard
    env->gregs[PARAM1] += 2;
905 fdf9b3e8 bellard
    RETURN();
906 fdf9b3e8 bellard
}
907 fdf9b3e8 bellard
908 fdf9b3e8 bellard
void OPPROTO op_inc4_rN(void)
909 fdf9b3e8 bellard
{
910 fdf9b3e8 bellard
    env->gregs[PARAM1] += 4;
911 fdf9b3e8 bellard
    RETURN();
912 fdf9b3e8 bellard
}
913 fdf9b3e8 bellard
914 eda9b09b bellard
void OPPROTO op_inc8_rN(void)
915 eda9b09b bellard
{
916 0a618140 ths
    env->gregs[PARAM1] += 8;
917 eda9b09b bellard
    RETURN();
918 eda9b09b bellard
}
919 eda9b09b bellard
920 fdf9b3e8 bellard
void OPPROTO op_add_T0_rN(void)
921 fdf9b3e8 bellard
{
922 fdf9b3e8 bellard
    env->gregs[PARAM1] += T0;
923 fdf9b3e8 bellard
    RETURN();
924 fdf9b3e8 bellard
}
925 fdf9b3e8 bellard
926 fdf9b3e8 bellard
void OPPROTO op_sub_T0_rN(void)
927 fdf9b3e8 bellard
{
928 fdf9b3e8 bellard
    env->gregs[PARAM1] -= T0;
929 fdf9b3e8 bellard
    RETURN();
930 fdf9b3e8 bellard
}
931 fdf9b3e8 bellard
932 fdf9b3e8 bellard
void OPPROTO op_and_T0_rN(void)
933 fdf9b3e8 bellard
{
934 fdf9b3e8 bellard
    env->gregs[PARAM1] &= T0;
935 fdf9b3e8 bellard
    RETURN();
936 fdf9b3e8 bellard
}
937 fdf9b3e8 bellard
938 fdf9b3e8 bellard
void OPPROTO op_or_T0_rN(void)
939 fdf9b3e8 bellard
{
940 fdf9b3e8 bellard
    env->gregs[PARAM1] |= T0;
941 fdf9b3e8 bellard
    RETURN();
942 fdf9b3e8 bellard
}
943 fdf9b3e8 bellard
944 fdf9b3e8 bellard
void OPPROTO op_xor_T0_rN(void)
945 fdf9b3e8 bellard
{
946 fdf9b3e8 bellard
    env->gregs[PARAM1] ^= T0;
947 fdf9b3e8 bellard
    RETURN();
948 fdf9b3e8 bellard
}
949 fdf9b3e8 bellard
950 fdf9b3e8 bellard
void OPPROTO op_add_rN_T0(void)
951 fdf9b3e8 bellard
{
952 fdf9b3e8 bellard
    T0 += env->gregs[PARAM1];
953 fdf9b3e8 bellard
    RETURN();
954 fdf9b3e8 bellard
}
955 fdf9b3e8 bellard
956 fdf9b3e8 bellard
void OPPROTO op_add_rN_T1(void)
957 fdf9b3e8 bellard
{
958 fdf9b3e8 bellard
    T1 += env->gregs[PARAM1];
959 fdf9b3e8 bellard
    RETURN();
960 fdf9b3e8 bellard
}
961 fdf9b3e8 bellard
962 fdf9b3e8 bellard
void OPPROTO op_add_imm_rN(void)
963 fdf9b3e8 bellard
{
964 fdf9b3e8 bellard
    env->gregs[PARAM2] += PARAM1;
965 fdf9b3e8 bellard
    RETURN();
966 fdf9b3e8 bellard
}
967 fdf9b3e8 bellard
968 fdf9b3e8 bellard
void OPPROTO op_and_imm_rN(void)
969 fdf9b3e8 bellard
{
970 fdf9b3e8 bellard
    env->gregs[PARAM2] &= PARAM1;
971 fdf9b3e8 bellard
    RETURN();
972 fdf9b3e8 bellard
}
973 fdf9b3e8 bellard
974 fdf9b3e8 bellard
void OPPROTO op_or_imm_rN(void)
975 fdf9b3e8 bellard
{
976 fdf9b3e8 bellard
    env->gregs[PARAM2] |= PARAM1;
977 fdf9b3e8 bellard
    RETURN();
978 fdf9b3e8 bellard
}
979 fdf9b3e8 bellard
980 fdf9b3e8 bellard
void OPPROTO op_xor_imm_rN(void)
981 fdf9b3e8 bellard
{
982 fdf9b3e8 bellard
    env->gregs[PARAM2] ^= PARAM1;
983 fdf9b3e8 bellard
    RETURN();
984 fdf9b3e8 bellard
}
985 fdf9b3e8 bellard
986 fdf9b3e8 bellard
void OPPROTO op_dt_rN(void)
987 fdf9b3e8 bellard
{
988 fdf9b3e8 bellard
    cond_t((--env->gregs[PARAM1]) == 0);
989 fdf9b3e8 bellard
    RETURN();
990 fdf9b3e8 bellard
}
991 fdf9b3e8 bellard
992 fdf9b3e8 bellard
void OPPROTO op_tst_imm_rN(void)
993 fdf9b3e8 bellard
{
994 fdf9b3e8 bellard
    cond_t((env->gregs[PARAM2] & PARAM1) == 0);
995 fdf9b3e8 bellard
    RETURN();
996 fdf9b3e8 bellard
}
997 fdf9b3e8 bellard
998 fdf9b3e8 bellard
void OPPROTO op_movl_T0_T1(void)
999 fdf9b3e8 bellard
{
1000 fdf9b3e8 bellard
    T1 = T0;
1001 fdf9b3e8 bellard
    RETURN();
1002 fdf9b3e8 bellard
}
1003 fdf9b3e8 bellard
1004 eda9b09b bellard
void OPPROTO op_movl_fpul_FT0(void)
1005 eda9b09b bellard
{
1006 eda9b09b bellard
    FT0 = *(float32 *)&env->fpul;
1007 eda9b09b bellard
    RETURN();
1008 eda9b09b bellard
}
1009 eda9b09b bellard
1010 eda9b09b bellard
void OPPROTO op_movl_FT0_fpul(void)
1011 eda9b09b bellard
{
1012 eda9b09b bellard
    *(float32 *)&env->fpul = FT0;
1013 eda9b09b bellard
    RETURN();
1014 eda9b09b bellard
}
1015 eda9b09b bellard
1016 fdf9b3e8 bellard
void OPPROTO op_movl_imm_PC(void)
1017 fdf9b3e8 bellard
{
1018 fdf9b3e8 bellard
    env->pc = PARAM1;
1019 fdf9b3e8 bellard
    RETURN();
1020 fdf9b3e8 bellard
}
1021 fdf9b3e8 bellard
1022 fdf9b3e8 bellard
void OPPROTO op_jT(void)
1023 fdf9b3e8 bellard
{
1024 fdf9b3e8 bellard
    if (env->sr & SR_T)
1025 fdf9b3e8 bellard
        GOTO_LABEL_PARAM(1);
1026 fdf9b3e8 bellard
    RETURN();
1027 fdf9b3e8 bellard
}
1028 fdf9b3e8 bellard
1029 9c2a9ea1 pbrook
void OPPROTO op_jdelayed(void)
1030 fdf9b3e8 bellard
{
1031 823029f9 ths
    if (env->flags & DELAY_SLOT_TRUE) {
1032 823029f9 ths
        env->flags &= ~DELAY_SLOT_TRUE;
1033 823029f9 ths
        GOTO_LABEL_PARAM(1);
1034 823029f9 ths
    }
1035 fdf9b3e8 bellard
    RETURN();
1036 fdf9b3e8 bellard
}
1037 fdf9b3e8 bellard
1038 fdf9b3e8 bellard
void OPPROTO op_movl_delayed_pc_PC(void)
1039 fdf9b3e8 bellard
{
1040 fdf9b3e8 bellard
    env->pc = env->delayed_pc;
1041 fdf9b3e8 bellard
    RETURN();
1042 fdf9b3e8 bellard
}
1043 fdf9b3e8 bellard
1044 fdf9b3e8 bellard
void OPPROTO op_addl_GBR_T0(void)
1045 fdf9b3e8 bellard
{
1046 fdf9b3e8 bellard
    T0 += env->gbr;
1047 fdf9b3e8 bellard
    RETURN();
1048 fdf9b3e8 bellard
}
1049 fdf9b3e8 bellard
1050 fdf9b3e8 bellard
void OPPROTO op_and_imm_T0(void)
1051 fdf9b3e8 bellard
{
1052 fdf9b3e8 bellard
    T0 &= PARAM1;
1053 fdf9b3e8 bellard
    RETURN();
1054 fdf9b3e8 bellard
}
1055 fdf9b3e8 bellard
1056 fdf9b3e8 bellard
void OPPROTO op_or_imm_T0(void)
1057 fdf9b3e8 bellard
{
1058 fdf9b3e8 bellard
    T0 |= PARAM1;
1059 fdf9b3e8 bellard
    RETURN();
1060 fdf9b3e8 bellard
}
1061 fdf9b3e8 bellard
1062 fdf9b3e8 bellard
void OPPROTO op_xor_imm_T0(void)
1063 fdf9b3e8 bellard
{
1064 fdf9b3e8 bellard
    T0 ^= PARAM1;
1065 fdf9b3e8 bellard
    RETURN();
1066 fdf9b3e8 bellard
}
1067 fdf9b3e8 bellard
1068 fdf9b3e8 bellard
void OPPROTO op_tst_imm_T0(void)
1069 fdf9b3e8 bellard
{
1070 fdf9b3e8 bellard
    cond_t((T0 & PARAM1) == 0);
1071 fdf9b3e8 bellard
    RETURN();
1072 fdf9b3e8 bellard
}
1073 fdf9b3e8 bellard
1074 fdf9b3e8 bellard
void OPPROTO op_raise_illegal_instruction(void)
1075 fdf9b3e8 bellard
{
1076 fdf9b3e8 bellard
    env->exception_index = 0x180;
1077 fdf9b3e8 bellard
    do_raise_exception();
1078 fdf9b3e8 bellard
    RETURN();
1079 fdf9b3e8 bellard
}
1080 fdf9b3e8 bellard
1081 fdf9b3e8 bellard
void OPPROTO op_raise_slot_illegal_instruction(void)
1082 fdf9b3e8 bellard
{
1083 fdf9b3e8 bellard
    env->exception_index = 0x1a0;
1084 fdf9b3e8 bellard
    do_raise_exception();
1085 fdf9b3e8 bellard
    RETURN();
1086 fdf9b3e8 bellard
}
1087 fdf9b3e8 bellard
1088 fdf9b3e8 bellard
void OPPROTO op_debug(void)
1089 fdf9b3e8 bellard
{
1090 fdf9b3e8 bellard
    env->exception_index = EXCP_DEBUG;
1091 fdf9b3e8 bellard
    cpu_loop_exit();
1092 fdf9b3e8 bellard
}
1093 fdf9b3e8 bellard
1094 833ed386 aurel32
void OPPROTO op_sleep(void)
1095 833ed386 aurel32
{
1096 833ed386 aurel32
    env->halted = 1;
1097 833ed386 aurel32
    env->exception_index = EXCP_HLT;
1098 833ed386 aurel32
    cpu_loop_exit();
1099 833ed386 aurel32
}
1100 833ed386 aurel32
1101 fdf9b3e8 bellard
/* Load and store */
1102 fdf9b3e8 bellard
#define MEMSUFFIX _raw
1103 fdf9b3e8 bellard
#include "op_mem.c"
1104 fdf9b3e8 bellard
#undef MEMSUFFIX
1105 fdf9b3e8 bellard
#if !defined(CONFIG_USER_ONLY)
1106 fdf9b3e8 bellard
#define MEMSUFFIX _user
1107 fdf9b3e8 bellard
#include "op_mem.c"
1108 fdf9b3e8 bellard
#undef MEMSUFFIX
1109 fdf9b3e8 bellard
1110 fdf9b3e8 bellard
#define MEMSUFFIX _kernel
1111 fdf9b3e8 bellard
#include "op_mem.c"
1112 fdf9b3e8 bellard
#undef MEMSUFFIX
1113 fdf9b3e8 bellard
#endif