root / target-cris / cpu.h @ 2a1704a7
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/*
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* CRIS virtual CPU header
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*
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* Copyright (c) 2007 AXIS Communications AB
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* Written by Edgar E. Iglesias
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_CRIS_H
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#define CPU_CRIS_H
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#define TARGET_LONG_BITS 32 |
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#define CPUState struct CPUCRISState |
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#include "cpu-defs.h" |
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#define TARGET_HAS_ICE 1 |
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#define ELF_MACHINE EM_CRIS
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#define EXCP_NMI 1 |
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#define EXCP_GURU 2 |
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#define EXCP_BUSFAULT 3 |
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#define EXCP_IRQ 4 |
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#define EXCP_BREAK 5 |
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/* Register aliases. R0 - R15 */
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#define R_FP 8 |
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#define R_SP 14 |
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#define R_ACR 15 |
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/* Support regs, P0 - P15 */
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#define PR_BZ 0 |
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#define PR_VR 1 |
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#define PR_PID 2 |
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#define PR_SRS 3 |
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#define PR_WZ 4 |
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#define PR_EXS 5 |
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#define PR_EDA 6 |
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#define PR_MOF 7 |
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#define PR_DZ 8 |
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#define PR_EBP 9 |
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#define PR_ERP 10 |
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#define PR_SRP 11 |
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#define PR_NRP 12 |
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#define PR_CCS 13 |
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#define PR_USP 14 |
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#define PR_SPC 15 |
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/* CPU flags. */
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#define Q_FLAG 0x80000000 |
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#define M_FLAG 0x40000000 |
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#define S_FLAG 0x200 |
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#define R_FLAG 0x100 |
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#define P_FLAG 0x80 |
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#define U_FLAG 0x40 |
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#define I_FLAG 0x20 |
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#define X_FLAG 0x10 |
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#define N_FLAG 0x08 |
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#define Z_FLAG 0x04 |
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#define V_FLAG 0x02 |
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#define C_FLAG 0x01 |
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#define ALU_FLAGS 0x1F |
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/* Condition codes. */
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#define CC_CC 0 |
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#define CC_CS 1 |
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#define CC_NE 2 |
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#define CC_EQ 3 |
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#define CC_VC 4 |
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#define CC_VS 5 |
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#define CC_PL 6 |
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#define CC_MI 7 |
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#define CC_LS 8 |
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#define CC_HI 9 |
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#define CC_GE 10 |
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#define CC_LT 11 |
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#define CC_GT 12 |
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#define CC_LE 13 |
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#define CC_A 14 |
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#define CC_P 15 |
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#define NB_MMU_MODES 2 |
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typedef struct CPUCRISState { |
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uint32_t regs[16];
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/* P0 - P15 are referred to as special registers in the docs. */
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uint32_t pregs[16];
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/* Pseudo register for the PC. Not directly accessable on CRIS. */
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uint32_t pc; |
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/* Pseudo register for the kernel stack. */
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uint32_t ksp; |
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/* Branch. */
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int dslot;
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int btaken;
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uint32_t btarget; |
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/* Condition flag tracking. */
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uint32_t cc_op; |
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uint32_t cc_mask; |
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uint32_t cc_dest; |
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uint32_t cc_src; |
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uint32_t cc_result; |
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/* size of the operation, 1 = byte, 2 = word, 4 = dword. */
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int cc_size;
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/* X flag at the time of cc snapshot. */
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int cc_x;
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int interrupt_vector;
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int fault_vector;
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int trap_vector;
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/* FIXME: add a check in the translator to avoid writing to support
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register sets beyond the 4th. The ISA allows up to 256! but in
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practice there is no core that implements more than 4.
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Support function registers are used to control units close to the
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core. Accesses do not pass down the normal hierarchy.
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*/
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uint32_t sregs[4][16]; |
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/* Linear feedback shift reg in the mmu. Used to provide pseudo
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randomness for the 'hint' the mmu gives to sw for chosing valid
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sets on TLB refills. */
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uint32_t mmu_rand_lfsr; |
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/*
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* We just store the stores to the tlbset here for later evaluation
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* when the hw needs access to them.
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*
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* One for I and another for D.
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*/
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struct
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{ |
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uint32_t hi; |
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uint32_t lo; |
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} tlbsets[2][4][16]; |
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CPU_COMMON |
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} CPUCRISState; |
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CPUCRISState *cpu_cris_init(const char *cpu_model); |
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int cpu_cris_exec(CPUCRISState *s);
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void cpu_cris_close(CPUCRISState *s);
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void do_interrupt(CPUCRISState *env);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_cris_signal_handler(int host_signum, void *pinfo, |
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void *puc);
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enum {
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CC_OP_DYNAMIC, /* Use env->cc_op */
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CC_OP_FLAGS, |
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CC_OP_CMP, |
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CC_OP_MOVE, |
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CC_OP_ADD, |
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CC_OP_ADDC, |
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CC_OP_MCP, |
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CC_OP_ADDU, |
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CC_OP_SUB, |
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CC_OP_SUBU, |
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CC_OP_NEG, |
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CC_OP_BTST, |
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CC_OP_MULS, |
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CC_OP_MULU, |
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CC_OP_DSTEP, |
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CC_OP_BOUND, |
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CC_OP_OR, |
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CC_OP_AND, |
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CC_OP_XOR, |
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CC_OP_LSL, |
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CC_OP_LSR, |
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CC_OP_ASR, |
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CC_OP_LZ |
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}; |
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/* CRIS uses 8k pages. */
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#define TARGET_PAGE_BITS 13 |
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#define MMAP_SHIFT TARGET_PAGE_BITS
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#define cpu_init cpu_cris_init
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#define cpu_exec cpu_cris_exec
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#define cpu_gen_code cpu_cris_gen_code
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#define cpu_signal_handler cpu_cris_signal_handler
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#define CPU_SAVE_VERSION 1 |
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1 |
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static inline int cpu_mmu_index (CPUState *env) |
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{ |
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return !!(env->pregs[PR_CCS] & U_FLAG);
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} |
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int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu); |
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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{ |
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if (newsp)
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env->regs[14] = newsp;
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env->regs[10] = 0; |
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} |
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#endif
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static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls) |
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{ |
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env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
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} |
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/* Support function regs. */
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#define SFR_RW_GC_CFG 0][0 |
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#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 |
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#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1 |
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#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2 |
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#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3 |
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#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4 |
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#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 |
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#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 |
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#include "cpu-all.h" |
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#include "exec-all.h" |
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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{ |
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env->pc = tb->pc; |
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} |
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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target_ulong *cs_base, int *flags)
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{ |
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*pc = env->pc; |
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*cs_base = 0;
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*flags = env->dslot | |
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(env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG)); |
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} |
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#endif
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