root / target-microblaze / mmu.c @ 2a2af967
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1 | afeeceb0 | Edgar E. Iglesias | /*
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2 | afeeceb0 | Edgar E. Iglesias | * Microblaze MMU emulation for qemu.
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3 | afeeceb0 | Edgar E. Iglesias | *
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4 | afeeceb0 | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias
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5 | afeeceb0 | Edgar E. Iglesias | *
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6 | afeeceb0 | Edgar E. Iglesias | * This library is free software; you can redistribute it and/or
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7 | afeeceb0 | Edgar E. Iglesias | * modify it under the terms of the GNU Lesser General Public
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8 | afeeceb0 | Edgar E. Iglesias | * License as published by the Free Software Foundation; either
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9 | afeeceb0 | Edgar E. Iglesias | * version 2 of the License, or (at your option) any later version.
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10 | afeeceb0 | Edgar E. Iglesias | *
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11 | afeeceb0 | Edgar E. Iglesias | * This library is distributed in the hope that it will be useful,
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12 | afeeceb0 | Edgar E. Iglesias | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | afeeceb0 | Edgar E. Iglesias | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | afeeceb0 | Edgar E. Iglesias | * Lesser General Public License for more details.
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15 | afeeceb0 | Edgar E. Iglesias | *
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16 | afeeceb0 | Edgar E. Iglesias | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | afeeceb0 | Edgar E. Iglesias | */
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19 | afeeceb0 | Edgar E. Iglesias | #include <stdio.h> |
20 | afeeceb0 | Edgar E. Iglesias | #include <stdlib.h> |
21 | afeeceb0 | Edgar E. Iglesias | #include <assert.h> |
22 | afeeceb0 | Edgar E. Iglesias | |
23 | afeeceb0 | Edgar E. Iglesias | #include "config.h" |
24 | afeeceb0 | Edgar E. Iglesias | #include "cpu.h" |
25 | afeeceb0 | Edgar E. Iglesias | |
26 | afeeceb0 | Edgar E. Iglesias | #define D(x)
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27 | afeeceb0 | Edgar E. Iglesias | |
28 | afeeceb0 | Edgar E. Iglesias | static unsigned int tlb_decode_size(unsigned int f) |
29 | afeeceb0 | Edgar E. Iglesias | { |
30 | afeeceb0 | Edgar E. Iglesias | static const unsigned int sizes[] = { |
31 | afeeceb0 | Edgar E. Iglesias | 1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024, |
32 | afeeceb0 | Edgar E. Iglesias | 1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024 |
33 | afeeceb0 | Edgar E. Iglesias | }; |
34 | afeeceb0 | Edgar E. Iglesias | assert(f < ARRAY_SIZE(sizes)); |
35 | afeeceb0 | Edgar E. Iglesias | return sizes[f];
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36 | afeeceb0 | Edgar E. Iglesias | } |
37 | afeeceb0 | Edgar E. Iglesias | |
38 | 6b2fce90 | Edgar E. Iglesias | static void mmu_flush_idx(CPUState *env, unsigned int idx) |
39 | afeeceb0 | Edgar E. Iglesias | { |
40 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu *mmu = &env->mmu;
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41 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_size; |
42 | afeeceb0 | Edgar E. Iglesias | uint32_t tlb_tag, end, t; |
43 | afeeceb0 | Edgar E. Iglesias | |
44 | afeeceb0 | Edgar E. Iglesias | t = mmu->rams[RAM_TAG][idx]; |
45 | afeeceb0 | Edgar E. Iglesias | if (!(t & TLB_VALID))
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46 | afeeceb0 | Edgar E. Iglesias | return;
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47 | afeeceb0 | Edgar E. Iglesias | |
48 | afeeceb0 | Edgar E. Iglesias | tlb_tag = t & TLB_EPN_MASK; |
49 | afeeceb0 | Edgar E. Iglesias | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
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50 | afeeceb0 | Edgar E. Iglesias | end = tlb_tag + tlb_size; |
51 | afeeceb0 | Edgar E. Iglesias | |
52 | afeeceb0 | Edgar E. Iglesias | while (tlb_tag < end) {
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53 | afeeceb0 | Edgar E. Iglesias | tlb_flush_page(env, tlb_tag); |
54 | afeeceb0 | Edgar E. Iglesias | tlb_tag += TARGET_PAGE_SIZE; |
55 | afeeceb0 | Edgar E. Iglesias | } |
56 | afeeceb0 | Edgar E. Iglesias | } |
57 | afeeceb0 | Edgar E. Iglesias | |
58 | afeeceb0 | Edgar E. Iglesias | static void mmu_change_pid(CPUState *env, unsigned int newpid) |
59 | afeeceb0 | Edgar E. Iglesias | { |
60 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu *mmu = &env->mmu;
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61 | afeeceb0 | Edgar E. Iglesias | unsigned int i; |
62 | 183aa454 | Blue Swirl | uint32_t t; |
63 | afeeceb0 | Edgar E. Iglesias | |
64 | afeeceb0 | Edgar E. Iglesias | if (newpid & ~0xff) |
65 | afeeceb0 | Edgar E. Iglesias | qemu_log("Illegal rpid=%x\n", newpid);
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66 | afeeceb0 | Edgar E. Iglesias | |
67 | afeeceb0 | Edgar E. Iglesias | for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { |
68 | afeeceb0 | Edgar E. Iglesias | /* Lookup and decode. */
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69 | afeeceb0 | Edgar E. Iglesias | t = mmu->rams[RAM_TAG][i]; |
70 | afeeceb0 | Edgar E. Iglesias | if (t & TLB_VALID) {
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71 | afeeceb0 | Edgar E. Iglesias | if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i])) |
72 | afeeceb0 | Edgar E. Iglesias | mmu_flush_idx(env, i); |
73 | afeeceb0 | Edgar E. Iglesias | } |
74 | afeeceb0 | Edgar E. Iglesias | } |
75 | afeeceb0 | Edgar E. Iglesias | } |
76 | afeeceb0 | Edgar E. Iglesias | |
77 | afeeceb0 | Edgar E. Iglesias | /* rw - 0 = read, 1 = write, 2 = fetch. */
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78 | afeeceb0 | Edgar E. Iglesias | unsigned int mmu_translate(struct microblaze_mmu *mmu, |
79 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu_lookup *lu,
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80 | afeeceb0 | Edgar E. Iglesias | target_ulong vaddr, int rw, int mmu_idx) |
81 | afeeceb0 | Edgar E. Iglesias | { |
82 | afeeceb0 | Edgar E. Iglesias | unsigned int i, hit = 0; |
83 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel; |
84 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_size; |
85 | afeeceb0 | Edgar E. Iglesias | uint32_t tlb_tag, tlb_rpn, mask, t0; |
86 | afeeceb0 | Edgar E. Iglesias | |
87 | afeeceb0 | Edgar E. Iglesias | lu->err = ERR_MISS; |
88 | afeeceb0 | Edgar E. Iglesias | for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { |
89 | afeeceb0 | Edgar E. Iglesias | uint32_t t, d; |
90 | afeeceb0 | Edgar E. Iglesias | |
91 | afeeceb0 | Edgar E. Iglesias | /* Lookup and decode. */
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92 | afeeceb0 | Edgar E. Iglesias | t = mmu->rams[RAM_TAG][i]; |
93 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
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94 | afeeceb0 | Edgar E. Iglesias | if (t & TLB_VALID) {
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95 | afeeceb0 | Edgar E. Iglesias | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
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96 | afeeceb0 | Edgar E. Iglesias | if (tlb_size < TARGET_PAGE_SIZE) {
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97 | afeeceb0 | Edgar E. Iglesias | qemu_log("%d pages not supported\n", tlb_size);
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98 | afeeceb0 | Edgar E. Iglesias | abort(); |
99 | afeeceb0 | Edgar E. Iglesias | } |
100 | afeeceb0 | Edgar E. Iglesias | |
101 | afeeceb0 | Edgar E. Iglesias | mask = ~(tlb_size - 1);
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102 | afeeceb0 | Edgar E. Iglesias | tlb_tag = t & TLB_EPN_MASK; |
103 | afeeceb0 | Edgar E. Iglesias | if ((vaddr & mask) != (tlb_tag & mask)) {
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104 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
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105 | afeeceb0 | Edgar E. Iglesias | i, vaddr & mask, tlb_tag & mask)); |
106 | afeeceb0 | Edgar E. Iglesias | continue;
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107 | afeeceb0 | Edgar E. Iglesias | } |
108 | afeeceb0 | Edgar E. Iglesias | if (mmu->tids[i]
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109 | afeeceb0 | Edgar E. Iglesias | && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
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110 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("TLB %d pid=%x != tid=%x\n",
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111 | afeeceb0 | Edgar E. Iglesias | i, mmu->regs[MMU_R_PID], mmu->tids[i])); |
112 | afeeceb0 | Edgar E. Iglesias | continue;
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113 | afeeceb0 | Edgar E. Iglesias | } |
114 | afeeceb0 | Edgar E. Iglesias | |
115 | afeeceb0 | Edgar E. Iglesias | /* Bring in the data part. */
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116 | afeeceb0 | Edgar E. Iglesias | d = mmu->rams[RAM_DATA][i]; |
117 | afeeceb0 | Edgar E. Iglesias | tlb_ex = d & TLB_EX; |
118 | afeeceb0 | Edgar E. Iglesias | tlb_wr = d & TLB_WR; |
119 | afeeceb0 | Edgar E. Iglesias | |
120 | afeeceb0 | Edgar E. Iglesias | /* Now lets see if there is a zone that overrides the protbits. */
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121 | afeeceb0 | Edgar E. Iglesias | tlb_zsel = (d >> 4) & 0xf; |
122 | afeeceb0 | Edgar E. Iglesias | t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2)); |
123 | afeeceb0 | Edgar E. Iglesias | t0 &= 0x3;
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124 | 3c50a71f | Edgar E. Iglesias | |
125 | 3c50a71f | Edgar E. Iglesias | if (tlb_zsel > mmu->c_mmu_zones) {
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126 | 3c50a71f | Edgar E. Iglesias | qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
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127 | 3c50a71f | Edgar E. Iglesias | t0 = 1; /* Ignore. */ |
128 | 3c50a71f | Edgar E. Iglesias | } |
129 | 3c50a71f | Edgar E. Iglesias | |
130 | 3c50a71f | Edgar E. Iglesias | if (mmu->c_mmu == 1) { |
131 | 3c50a71f | Edgar E. Iglesias | t0 = 1; /* Zones are disabled. */ |
132 | 3c50a71f | Edgar E. Iglesias | } |
133 | 3c50a71f | Edgar E. Iglesias | |
134 | afeeceb0 | Edgar E. Iglesias | switch (t0) {
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135 | afeeceb0 | Edgar E. Iglesias | case 0: |
136 | afeeceb0 | Edgar E. Iglesias | if (mmu_idx == MMU_USER_IDX)
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137 | afeeceb0 | Edgar E. Iglesias | continue;
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138 | afeeceb0 | Edgar E. Iglesias | break;
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139 | afeeceb0 | Edgar E. Iglesias | case 2: |
140 | afeeceb0 | Edgar E. Iglesias | if (mmu_idx != MMU_USER_IDX) {
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141 | afeeceb0 | Edgar E. Iglesias | tlb_ex = 1;
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142 | afeeceb0 | Edgar E. Iglesias | tlb_wr = 1;
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143 | afeeceb0 | Edgar E. Iglesias | } |
144 | afeeceb0 | Edgar E. Iglesias | break;
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145 | afeeceb0 | Edgar E. Iglesias | case 3: |
146 | afeeceb0 | Edgar E. Iglesias | tlb_ex = 1;
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147 | afeeceb0 | Edgar E. Iglesias | tlb_wr = 1;
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148 | afeeceb0 | Edgar E. Iglesias | break;
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149 | 3c50a71f | Edgar E. Iglesias | default: break; |
150 | afeeceb0 | Edgar E. Iglesias | } |
151 | afeeceb0 | Edgar E. Iglesias | |
152 | afeeceb0 | Edgar E. Iglesias | lu->err = ERR_PROT; |
153 | afeeceb0 | Edgar E. Iglesias | lu->prot = PAGE_READ; |
154 | afeeceb0 | Edgar E. Iglesias | if (tlb_wr)
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155 | afeeceb0 | Edgar E. Iglesias | lu->prot |= PAGE_WRITE; |
156 | afeeceb0 | Edgar E. Iglesias | else if (rw == 1) |
157 | afeeceb0 | Edgar E. Iglesias | goto done;
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158 | afeeceb0 | Edgar E. Iglesias | if (tlb_ex)
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159 | afeeceb0 | Edgar E. Iglesias | lu->prot |=PAGE_EXEC; |
160 | afeeceb0 | Edgar E. Iglesias | else if (rw == 2) { |
161 | afeeceb0 | Edgar E. Iglesias | goto done;
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162 | afeeceb0 | Edgar E. Iglesias | } |
163 | afeeceb0 | Edgar E. Iglesias | |
164 | afeeceb0 | Edgar E. Iglesias | tlb_rpn = d & TLB_RPN_MASK; |
165 | afeeceb0 | Edgar E. Iglesias | |
166 | afeeceb0 | Edgar E. Iglesias | lu->vaddr = tlb_tag; |
167 | afeeceb0 | Edgar E. Iglesias | lu->paddr = tlb_rpn; |
168 | afeeceb0 | Edgar E. Iglesias | lu->size = tlb_size; |
169 | afeeceb0 | Edgar E. Iglesias | lu->err = ERR_HIT; |
170 | afeeceb0 | Edgar E. Iglesias | lu->idx = i; |
171 | afeeceb0 | Edgar E. Iglesias | hit = 1;
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172 | afeeceb0 | Edgar E. Iglesias | goto done;
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173 | afeeceb0 | Edgar E. Iglesias | } |
174 | afeeceb0 | Edgar E. Iglesias | } |
175 | afeeceb0 | Edgar E. Iglesias | done:
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176 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
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177 | afeeceb0 | Edgar E. Iglesias | vaddr, rw, tlb_wr, tlb_ex, hit)); |
178 | afeeceb0 | Edgar E. Iglesias | return hit;
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179 | afeeceb0 | Edgar E. Iglesias | } |
180 | afeeceb0 | Edgar E. Iglesias | |
181 | afeeceb0 | Edgar E. Iglesias | /* Writes/reads to the MMU's special regs end up here. */
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182 | afeeceb0 | Edgar E. Iglesias | uint32_t mmu_read(CPUState *env, uint32_t rn) |
183 | afeeceb0 | Edgar E. Iglesias | { |
184 | afeeceb0 | Edgar E. Iglesias | unsigned int i; |
185 | afeeceb0 | Edgar E. Iglesias | uint32_t r; |
186 | afeeceb0 | Edgar E. Iglesias | |
187 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { |
188 | 3c50a71f | Edgar E. Iglesias | qemu_log("MMU access on MMU-less system\n");
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189 | 3c50a71f | Edgar E. Iglesias | return 0; |
190 | 3c50a71f | Edgar E. Iglesias | } |
191 | 3c50a71f | Edgar E. Iglesias | |
192 | afeeceb0 | Edgar E. Iglesias | switch (rn) {
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193 | afeeceb0 | Edgar E. Iglesias | /* Reads to HI/LO trig reads from the mmu rams. */
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194 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBLO:
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195 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBHI:
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196 | 3c50a71f | Edgar E. Iglesias | if (!(env->mmu.c_mmu_tlb_access & 1)) { |
197 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
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198 | 3c50a71f | Edgar E. Iglesias | return 0; |
199 | 3c50a71f | Edgar E. Iglesias | } |
200 | 3c50a71f | Edgar E. Iglesias | |
201 | afeeceb0 | Edgar E. Iglesias | i = env->mmu.regs[MMU_R_TLBX] & 0xff;
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202 | afeeceb0 | Edgar E. Iglesias | r = env->mmu.rams[rn & 1][i];
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203 | afeeceb0 | Edgar E. Iglesias | if (rn == MMU_R_TLBHI)
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204 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[MMU_R_PID] = env->mmu.tids[i]; |
205 | afeeceb0 | Edgar E. Iglesias | break;
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206 | 3c50a71f | Edgar E. Iglesias | case MMU_R_PID:
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207 | 3c50a71f | Edgar E. Iglesias | case MMU_R_ZPR:
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208 | 3c50a71f | Edgar E. Iglesias | if (!(env->mmu.c_mmu_tlb_access & 1)) { |
209 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
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210 | 3c50a71f | Edgar E. Iglesias | return 0; |
211 | 3c50a71f | Edgar E. Iglesias | } |
212 | 3c50a71f | Edgar E. Iglesias | r = env->mmu.regs[rn]; |
213 | 3c50a71f | Edgar E. Iglesias | break;
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214 | afeeceb0 | Edgar E. Iglesias | default:
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215 | afeeceb0 | Edgar E. Iglesias | r = env->mmu.regs[rn]; |
216 | afeeceb0 | Edgar E. Iglesias | break;
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217 | afeeceb0 | Edgar E. Iglesias | } |
218 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
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219 | afeeceb0 | Edgar E. Iglesias | return r;
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220 | afeeceb0 | Edgar E. Iglesias | } |
221 | afeeceb0 | Edgar E. Iglesias | |
222 | afeeceb0 | Edgar E. Iglesias | void mmu_write(CPUState *env, uint32_t rn, uint32_t v)
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223 | afeeceb0 | Edgar E. Iglesias | { |
224 | afeeceb0 | Edgar E. Iglesias | unsigned int i; |
225 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
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226 | afeeceb0 | Edgar E. Iglesias | |
227 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { |
228 | 3c50a71f | Edgar E. Iglesias | qemu_log("MMU access on MMU-less system\n");
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229 | 3c50a71f | Edgar E. Iglesias | return;
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230 | 3c50a71f | Edgar E. Iglesias | } |
231 | 3c50a71f | Edgar E. Iglesias | |
232 | afeeceb0 | Edgar E. Iglesias | switch (rn) {
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233 | afeeceb0 | Edgar E. Iglesias | /* Writes to HI/LO trig writes to the mmu rams. */
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234 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBLO:
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235 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBHI:
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236 | afeeceb0 | Edgar E. Iglesias | i = env->mmu.regs[MMU_R_TLBX] & 0xff;
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237 | afeeceb0 | Edgar E. Iglesias | if (rn == MMU_R_TLBHI) {
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238 | afeeceb0 | Edgar E. Iglesias | if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) |
239 | afeeceb0 | Edgar E. Iglesias | qemu_log("invalidating index %x at pc=%x\n",
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240 | afeeceb0 | Edgar E. Iglesias | i, env->sregs[SR_PC]); |
241 | afeeceb0 | Edgar E. Iglesias | env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
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242 | afeeceb0 | Edgar E. Iglesias | mmu_flush_idx(env, i); |
243 | afeeceb0 | Edgar E. Iglesias | } |
244 | afeeceb0 | Edgar E. Iglesias | env->mmu.rams[rn & 1][i] = v;
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245 | afeeceb0 | Edgar E. Iglesias | |
246 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v)); |
247 | afeeceb0 | Edgar E. Iglesias | break;
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248 | afeeceb0 | Edgar E. Iglesias | case MMU_R_ZPR:
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249 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu_tlb_access <= 1) { |
250 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
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251 | 3c50a71f | Edgar E. Iglesias | return;
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252 | 3c50a71f | Edgar E. Iglesias | } |
253 | 3c50a71f | Edgar E. Iglesias | |
254 | d0f3654f | Edgar E. Iglesias | /* Changes to the zone protection reg flush the QEMU TLB.
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255 | d0f3654f | Edgar E. Iglesias | Fortunately, these are very uncommon. */
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256 | d0f3654f | Edgar E. Iglesias | if (v != env->mmu.regs[rn]) {
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257 | d0f3654f | Edgar E. Iglesias | tlb_flush(env, 1);
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258 | d0f3654f | Edgar E. Iglesias | } |
259 | d0f3654f | Edgar E. Iglesias | env->mmu.regs[rn] = v; |
260 | d0f3654f | Edgar E. Iglesias | break;
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261 | afeeceb0 | Edgar E. Iglesias | case MMU_R_PID:
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262 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu_tlb_access <= 1) { |
263 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
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264 | 3c50a71f | Edgar E. Iglesias | return;
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265 | 3c50a71f | Edgar E. Iglesias | } |
266 | 3c50a71f | Edgar E. Iglesias | |
267 | afeeceb0 | Edgar E. Iglesias | if (v != env->mmu.regs[rn]) {
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268 | afeeceb0 | Edgar E. Iglesias | mmu_change_pid(env, v); |
269 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[rn] = v; |
270 | afeeceb0 | Edgar E. Iglesias | } |
271 | afeeceb0 | Edgar E. Iglesias | break;
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272 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBSX:
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273 | afeeceb0 | Edgar E. Iglesias | { |
274 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu_lookup lu;
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275 | afeeceb0 | Edgar E. Iglesias | int hit;
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276 | 3c50a71f | Edgar E. Iglesias | |
277 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu_tlb_access <= 1) { |
278 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
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279 | 3c50a71f | Edgar E. Iglesias | return;
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280 | 3c50a71f | Edgar E. Iglesias | } |
281 | 3c50a71f | Edgar E. Iglesias | |
282 | afeeceb0 | Edgar E. Iglesias | hit = mmu_translate(&env->mmu, &lu, |
283 | afeeceb0 | Edgar E. Iglesias | v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
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284 | afeeceb0 | Edgar E. Iglesias | if (hit) {
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285 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[MMU_R_TLBX] = lu.idx; |
286 | afeeceb0 | Edgar E. Iglesias | } else
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287 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
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288 | afeeceb0 | Edgar E. Iglesias | break;
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289 | afeeceb0 | Edgar E. Iglesias | } |
290 | afeeceb0 | Edgar E. Iglesias | default:
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291 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[rn] = v; |
292 | afeeceb0 | Edgar E. Iglesias | break;
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293 | afeeceb0 | Edgar E. Iglesias | } |
294 | afeeceb0 | Edgar E. Iglesias | } |
295 | afeeceb0 | Edgar E. Iglesias | |
296 | afeeceb0 | Edgar E. Iglesias | void mmu_init(struct microblaze_mmu *mmu) |
297 | afeeceb0 | Edgar E. Iglesias | { |
298 | 3c50a71f | Edgar E. Iglesias | int i;
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299 | 3c50a71f | Edgar E. Iglesias | for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { |
300 | 3c50a71f | Edgar E. Iglesias | mmu->regs[i] = 0;
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301 | 3c50a71f | Edgar E. Iglesias | } |
302 | afeeceb0 | Edgar E. Iglesias | } |