Revision 2a98c198 hw/lance.c
b/hw/lance.c | ||
---|---|---|
48 | 48 |
#define LE_RDP 0 |
49 | 49 |
#define LE_RAP 1 |
50 | 50 |
|
51 |
#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
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52 |
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53 |
#define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
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54 |
#define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
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55 |
#define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
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56 |
#define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
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57 |
#define LE_C0_MERR 0x0800 /* ME: Memory error */
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58 |
#define LE_C0_RINT 0x0400 /* Received interrupt */
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59 |
#define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
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60 |
#define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
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61 |
#define LE_C0_INTR 0x0080 /* Interrupt or error */
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62 |
#define LE_C0_INEA 0x0040 /* Interrupt enable */
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63 |
#define LE_C0_RXON 0x0020 /* Receiver on */
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64 |
#define LE_C0_TXON 0x0010 /* Transmitter on */
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65 |
#define LE_C0_TDMD 0x0008 /* Transmitter demand */
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66 |
#define LE_C0_STOP 0x0004 /* Stop the card */
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67 |
#define LE_C0_STRT 0x0002 /* Start the card */
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68 |
#define LE_C0_INIT 0x0001 /* Init the card */
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69 |
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70 |
#define LE_C3_BSWP 0x4 /* SWAP */
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71 |
#define LE_C3_ACON 0x2 /* ALE Control */
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72 |
#define LE_C3_BCON 0x1 /* Byte control */
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51 |
#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
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52 |
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53 |
#define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
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54 |
#define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
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55 |
#define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
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56 |
#define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
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57 |
#define LE_C0_MERR 0x0800 /* ME: Memory error */
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58 |
#define LE_C0_RINT 0x0400 /* Received interrupt */
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59 |
#define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
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60 |
#define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
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61 |
#define LE_C0_INTR 0x0080 /* Interrupt or error */
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62 |
#define LE_C0_INEA 0x0040 /* Interrupt enable */
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63 |
#define LE_C0_RXON 0x0020 /* Receiver on */
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64 |
#define LE_C0_TXON 0x0010 /* Transmitter on */
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65 |
#define LE_C0_TDMD 0x0008 /* Transmitter demand */
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66 |
#define LE_C0_STOP 0x0004 /* Stop the card */
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67 |
#define LE_C0_STRT 0x0002 /* Start the card */
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68 |
#define LE_C0_INIT 0x0001 /* Init the card */
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69 |
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70 |
#define LE_C3_BSWP 0x4 /* SWAP */
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71 |
#define LE_C3_ACON 0x2 /* ALE Control */
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72 |
#define LE_C3_BCON 0x1 /* Byte control */
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73 | 73 |
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74 | 74 |
/* Receive message descriptor 1 */ |
75 |
#define LE_R1_OWN 0x80 /* Who owns the entry */
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76 |
#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
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77 |
#define LE_R1_FRA 0x20 /* FRA: Frame error */
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78 |
#define LE_R1_OFL 0x10 /* OFL: Frame overflow */
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79 |
#define LE_R1_CRC 0x08 /* CRC error */
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80 |
#define LE_R1_BUF 0x04 /* BUF: Buffer error */
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81 |
#define LE_R1_SOP 0x02 /* Start of packet */
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82 |
#define LE_R1_EOP 0x01 /* End of packet */
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83 |
#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
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84 |
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85 |
#define LE_T1_OWN 0x80 /* Lance owns the packet */
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86 |
#define LE_T1_ERR 0x40 /* Error summary */
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87 |
#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
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88 |
#define LE_T1_EONE 0x08 /* Error: one retry needed */
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89 |
#define LE_T1_EDEF 0x04 /* Error: deferred */
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90 |
#define LE_T1_SOP 0x02 /* Start of packet */
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91 |
#define LE_T1_EOP 0x01 /* End of packet */
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92 |
#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
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93 |
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94 |
#define LE_T3_BUF 0x8000 /* Buffer error */
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95 |
#define LE_T3_UFL 0x4000 /* Error underflow */
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96 |
#define LE_T3_LCOL 0x1000 /* Error late collision */
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97 |
#define LE_T3_CLOS 0x0800 /* Error carrier loss */
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98 |
#define LE_T3_RTY 0x0400 /* Error retry */
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99 |
#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
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75 |
#define LE_R1_OWN 0x80 /* Who owns the entry */
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76 |
#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
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77 |
#define LE_R1_FRA 0x20 /* FRA: Frame error */
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78 |
#define LE_R1_OFL 0x10 /* OFL: Frame overflow */
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79 |
#define LE_R1_CRC 0x08 /* CRC error */
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80 |
#define LE_R1_BUF 0x04 /* BUF: Buffer error */
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81 |
#define LE_R1_SOP 0x02 /* Start of packet */
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82 |
#define LE_R1_EOP 0x01 /* End of packet */
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83 |
#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
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84 |
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85 |
#define LE_T1_OWN 0x80 /* Lance owns the packet */
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86 |
#define LE_T1_ERR 0x40 /* Error summary */
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87 |
#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
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88 |
#define LE_T1_EONE 0x08 /* Error: one retry needed */
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89 |
#define LE_T1_EDEF 0x04 /* Error: deferred */
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90 |
#define LE_T1_SOP 0x02 /* Start of packet */
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91 |
#define LE_T1_EOP 0x01 /* End of packet */
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92 |
#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
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93 |
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94 |
#define LE_T3_BUF 0x8000 /* Buffer error */
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95 |
#define LE_T3_UFL 0x4000 /* Error underflow */
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96 |
#define LE_T3_LCOL 0x1000 /* Error late collision */
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97 |
#define LE_T3_CLOS 0x0800 /* Error carrier loss */
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98 |
#define LE_T3_RTY 0x0400 /* Error retry */
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99 |
#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
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100 | 100 |
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101 | 101 |
#define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS)) |
102 | 102 |
#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
... | ... | |
111 | 111 |
#define TX_BUFF_SIZE PKT_BUF_SZ |
112 | 112 |
|
113 | 113 |
struct lance_rx_desc { |
114 |
unsigned short rmd0; /* low address of packet */
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115 |
unsigned char rmd1_bits; /* descriptor bits */
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116 |
unsigned char rmd1_hadr; /* high address of packet */
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117 |
short length; /* This length is 2s complement (negative)!
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118 |
* Buffer length
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119 |
*/
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120 |
unsigned short mblength; /* This is the actual number of bytes received */
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114 |
unsigned short rmd0; /* low address of packet */
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115 |
unsigned char rmd1_bits; /* descriptor bits */
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116 |
unsigned char rmd1_hadr; /* high address of packet */
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117 |
short length; /* This length is 2s complement (negative)!
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118 |
* Buffer length
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119 |
*/
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120 |
unsigned short mblength; /* This is the actual number of bytes received */
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121 | 121 |
}; |
122 | 122 |
|
123 | 123 |
struct lance_tx_desc { |
124 |
unsigned short tmd0; /* low address of packet */
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125 |
unsigned char tmd1_bits; /* descriptor bits */
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126 |
unsigned char tmd1_hadr; /* high address of packet */
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127 |
short length; /* Length is 2s complement (negative)! */
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124 |
unsigned short tmd0; /* low address of packet */
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125 |
unsigned char tmd1_bits; /* descriptor bits */
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126 |
unsigned char tmd1_hadr; /* high address of packet */
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127 |
short length; /* Length is 2s complement (negative)! */
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128 | 128 |
unsigned short misc; |
129 | 129 |
}; |
130 | 130 |
|
131 | 131 |
/* The LANCE initialization block, described in databook. */ |
132 | 132 |
/* On the Sparc, this block should be on a DMA region */ |
133 | 133 |
struct lance_init_block { |
134 |
unsigned short mode; /* Pre-set mode (reg. 15) */
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135 |
unsigned char phys_addr[6]; /* Physical ethernet address */
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136 |
unsigned filter[2]; /* Multicast filter. */
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134 |
unsigned short mode; /* Pre-set mode (reg. 15) */
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135 |
unsigned char phys_addr[6]; /* Physical ethernet address */
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136 |
unsigned filter[2]; /* Multicast filter. */
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137 | 137 |
|
138 | 138 |
/* Receive and transmit ring base, along with extra bits. */ |
139 |
unsigned short rx_ptr; /* receive descriptor addr */
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140 |
unsigned short rx_len; /* receive len and high addr */
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141 |
unsigned short tx_ptr; /* transmit descriptor addr */
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142 |
unsigned short tx_len; /* transmit len and high addr */
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139 |
unsigned short rx_ptr; /* receive descriptor addr */
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140 |
unsigned short rx_len; /* receive len and high addr */
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141 |
unsigned short tx_ptr; /* transmit descriptor addr */
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142 |
unsigned short tx_len; /* transmit len and high addr */
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143 | 143 |
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144 | 144 |
/* The Tx and Rx ring entries must aligned on 8-byte boundaries. */ |
145 | 145 |
struct lance_rx_desc brx_ring[RX_RING_SIZE]; |
146 | 146 |
struct lance_tx_desc btx_ring[TX_RING_SIZE]; |
147 | 147 |
|
148 | 148 |
char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE]; |
149 |
char pad[2]; /* align rx_buf for copy_and_sum(). */
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149 |
char pad[2]; /* align rx_buf for copy_and_sum(). */
|
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150 | 150 |
char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE]; |
151 | 151 |
}; |
152 | 152 |
|
... | ... | |
155 | 155 |
|
156 | 156 |
typedef struct LANCEState { |
157 | 157 |
VLANClientState *vc; |
158 |
uint8_t macaddr[6]; /* init mac address */
|
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158 |
uint8_t macaddr[6]; /* init mac address */
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159 | 159 |
uint32_t leptr; |
160 | 160 |
uint16_t addr; |
161 | 161 |
uint16_t regs[LE_NREGS]; |
162 |
uint8_t phys[6]; /* mac address */
|
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162 |
uint8_t phys[6]; /* mac address */
|
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163 | 163 |
int irq; |
164 | 164 |
unsigned int rxptr, txptr; |
165 | 165 |
uint32_t ledmaregs[LEDMA_REGS]; |
... | ... | |
186 | 186 |
saddr = addr & LE_MAXREG; |
187 | 187 |
switch (saddr >> 1) { |
188 | 188 |
case LE_RDP: |
189 |
DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
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190 |
return s->regs[s->addr];
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189 |
DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
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190 |
return s->regs[s->addr];
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191 | 191 |
case LE_RAP: |
192 |
DPRINTF("read areg = %4.4x\n", s->addr);
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193 |
return s->addr;
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192 |
DPRINTF("read areg = %4.4x\n", s->addr);
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193 |
return s->addr;
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194 | 194 |
default: |
195 |
DPRINTF("read unknown(%d)\n", saddr >> 1);
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196 |
break;
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195 |
DPRINTF("read unknown(%d)\n", saddr >> 1);
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196 |
break;
|
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197 | 197 |
} |
198 | 198 |
return 0; |
199 | 199 |
} |
200 | 200 |
|
201 | 201 |
static void lance_mem_writew(void *opaque, target_phys_addr_t addr, |
202 |
uint32_t val)
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202 |
uint32_t val)
|
|
203 | 203 |
{ |
204 | 204 |
LANCEState *s = opaque; |
205 | 205 |
uint32_t saddr; |
... | ... | |
208 | 208 |
saddr = addr & LE_MAXREG; |
209 | 209 |
switch (saddr >> 1) { |
210 | 210 |
case LE_RDP: |
211 |
DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
|
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212 |
switch (s->addr) {
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213 |
case LE_CSR0:
|
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214 |
if (val & LE_C0_STOP) {
|
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215 |
s->regs[LE_CSR0] = LE_C0_STOP;
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216 |
break;
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217 |
}
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218 |
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219 |
reg = s->regs[LE_CSR0];
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220 |
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|
221 |
// 1 = clear for some bits
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222 |
reg &= ~(val & 0x7f00);
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223 |
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|
224 |
// generated bits
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|
225 |
reg &= ~(LE_C0_ERR | LE_C0_INTR);
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226 |
if (reg & 0x7100)
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227 |
reg |= LE_C0_ERR;
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228 |
if (reg & 0x7f00)
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229 |
reg |= LE_C0_INTR;
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230 |
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231 |
// direct bit
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232 |
reg &= ~LE_C0_INEA;
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233 |
reg |= val & LE_C0_INEA;
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234 |
|
|
235 |
// exclusive bits
|
|
236 |
if (val & LE_C0_INIT) {
|
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237 |
reg |= LE_C0_IDON | LE_C0_INIT;
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238 |
reg &= ~LE_C0_STOP;
|
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239 |
} else if (val & LE_C0_STRT) {
|
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240 |
reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
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241 |
reg &= ~LE_C0_STOP;
|
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242 |
}
|
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243 |
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|
244 |
s->regs[LE_CSR0] = reg;
|
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245 |
break;
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246 |
case LE_CSR1:
|
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247 |
s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
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248 |
s->regs[s->addr] = val;
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249 |
break;
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250 |
case LE_CSR2:
|
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251 |
s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16);
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252 |
s->regs[s->addr] = val;
|
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253 |
break;
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254 |
case LE_CSR3:
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255 |
s->regs[s->addr] = val;
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256 |
break;
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257 |
}
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258 |
break;
|
|
211 |
DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
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212 |
switch (s->addr) {
|
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213 |
case LE_CSR0:
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214 |
if (val & LE_C0_STOP) {
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215 |
s->regs[LE_CSR0] = LE_C0_STOP;
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216 |
break;
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|
217 |
}
|
|
218 |
|
|
219 |
reg = s->regs[LE_CSR0];
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220 |
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|
221 |
// 1 = clear for some bits
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222 |
reg &= ~(val & 0x7f00);
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223 |
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|
224 |
// generated bits
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225 |
reg &= ~(LE_C0_ERR | LE_C0_INTR);
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226 |
if (reg & 0x7100)
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227 |
reg |= LE_C0_ERR;
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228 |
if (reg & 0x7f00)
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229 |
reg |= LE_C0_INTR;
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230 |
|
|
231 |
// direct bit
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|
232 |
reg &= ~LE_C0_INEA;
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233 |
reg |= val & LE_C0_INEA;
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234 |
|
|
235 |
// exclusive bits
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|
236 |
if (val & LE_C0_INIT) {
|
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237 |
reg |= LE_C0_IDON | LE_C0_INIT;
|
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238 |
reg &= ~LE_C0_STOP;
|
|
239 |
} else if (val & LE_C0_STRT) {
|
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240 |
reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
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241 |
reg &= ~LE_C0_STOP;
|
|
242 |
}
|
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243 |
|
|
244 |
s->regs[LE_CSR0] = reg;
|
|
245 |
break;
|
|
246 |
case LE_CSR1:
|
|
247 |
s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
|
|
248 |
s->regs[s->addr] = val;
|
|
249 |
break;
|
|
250 |
case LE_CSR2:
|
|
251 |
s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16);
|
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252 |
s->regs[s->addr] = val;
|
|
253 |
break;
|
|
254 |
case LE_CSR3:
|
|
255 |
s->regs[s->addr] = val;
|
|
256 |
break;
|
|
257 |
}
|
|
258 |
break;
|
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259 | 259 |
case LE_RAP: |
260 |
DPRINTF("write areg = %4.4x\n", val);
|
|
261 |
if (val < LE_NREGS)
|
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262 |
s->addr = val;
|
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263 |
break;
|
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260 |
DPRINTF("write areg = %4.4x\n", val);
|
|
261 |
if (val < LE_NREGS)
|
|
262 |
s->addr = val;
|
|
263 |
break;
|
|
264 | 264 |
default: |
265 |
DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val);
|
|
266 |
break;
|
|
265 |
DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val);
|
|
266 |
break;
|
|
267 | 267 |
} |
268 | 268 |
lance_send(s); |
269 | 269 |
} |
... | ... | |
299 | 299 |
|
300 | 300 |
DPRINTF("receive size %d\n", size); |
301 | 301 |
if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP) |
302 |
return;
|
|
302 |
return;
|
|
303 | 303 |
|
304 | 304 |
ib = (void *) iommu_translate(dmaptr); |
305 | 305 |
|
306 | 306 |
old_rxptr = s->rxptr; |
307 | 307 |
for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); |
308 |
i = (i + 1) & RX_RING_MOD_MASK) {
|
|
309 |
cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits,
|
|
310 |
(void *) &temp8, 1);
|
|
311 |
if (temp8 == (LE_R1_OWN)) {
|
|
312 |
s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
|
|
313 |
temp16 = size + 4;
|
|
314 |
bswap16s(&temp16);
|
|
315 |
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
|
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316 |
mblength, (void *) &temp16, 2);
|
|
317 |
cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf,
|
|
318 |
size);
|
|
319 |
temp8 = LE_R1_POK;
|
|
320 |
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
|
|
321 |
rmd1_bits, (void *) &temp8, 1);
|
|
322 |
s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
|
|
323 |
if (s->regs[LE_CSR0] & LE_C0_INEA)
|
|
324 |
pic_set_irq(s->irq, 1);
|
|
325 |
DPRINTF("got packet, len %d\n", size);
|
|
326 |
return;
|
|
327 |
}
|
|
308 |
i = (i + 1) & RX_RING_MOD_MASK) {
|
|
309 |
cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits,
|
|
310 |
(void *) &temp8, 1);
|
|
311 |
if (temp8 == (LE_R1_OWN)) {
|
|
312 |
s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
|
|
313 |
temp16 = size + 4;
|
|
314 |
bswap16s(&temp16);
|
|
315 |
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
|
|
316 |
mblength, (void *) &temp16, 2);
|
|
317 |
cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf,
|
|
318 |
size);
|
|
319 |
temp8 = LE_R1_POK;
|
|
320 |
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
|
|
321 |
rmd1_bits, (void *) &temp8, 1);
|
|
322 |
s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
|
|
323 |
if (s->regs[LE_CSR0] & LE_C0_INEA)
|
|
324 |
pic_set_irq(s->irq, 1);
|
|
325 |
DPRINTF("got packet, len %d\n", size);
|
|
326 |
return;
|
|
327 |
}
|
|
328 | 328 |
} |
329 | 329 |
} |
330 | 330 |
|
... | ... | |
340 | 340 |
|
341 | 341 |
DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]); |
342 | 342 |
if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP) |
343 |
return;
|
|
343 |
return;
|
|
344 | 344 |
|
345 | 345 |
ib = (void *) iommu_translate(dmaptr); |
346 | 346 |
|
347 | 347 |
DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", |
348 |
dmaptr, ib, &ib->btx_ring);
|
|
348 |
dmaptr, ib, &ib->btx_ring);
|
|
349 | 349 |
old_txptr = s->txptr; |
350 | 350 |
for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); |
351 |
i = (i + 1) & TX_RING_MOD_MASK) {
|
|
352 |
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits,
|
|
353 |
(void *) &temp8, 1);
|
|
354 |
if (temp8 == (LE_T1_POK | LE_T1_OWN)) {
|
|
355 |
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length,
|
|
356 |
(void *) &temp16, 2);
|
|
357 |
bswap16s(&temp16);
|
|
358 |
temp16 = (~temp16) + 1;
|
|
359 |
cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf,
|
|
360 |
temp16);
|
|
361 |
DPRINTF("sending packet, len %d\n", temp16);
|
|
362 |
qemu_send_packet(s->vc, pkt_buf, temp16);
|
|
363 |
temp8 = LE_T1_POK;
|
|
364 |
cpu_physical_memory_write((uint32_t) & ib->btx_ring[i].
|
|
365 |
tmd1_bits, (void *) &temp8, 1);
|
|
366 |
s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
|
|
367 |
s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
|
|
368 |
}
|
|
351 |
i = (i + 1) & TX_RING_MOD_MASK) {
|
|
352 |
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits,
|
|
353 |
(void *) &temp8, 1);
|
|
354 |
if (temp8 == (LE_T1_POK | LE_T1_OWN)) {
|
|
355 |
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length,
|
|
356 |
(void *) &temp16, 2);
|
|
357 |
bswap16s(&temp16);
|
|
358 |
temp16 = (~temp16) + 1;
|
|
359 |
cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf,
|
|
360 |
temp16);
|
|
361 |
DPRINTF("sending packet, len %d\n", temp16);
|
|
362 |
qemu_send_packet(s->vc, pkt_buf, temp16);
|
|
363 |
temp8 = LE_T1_POK;
|
|
364 |
cpu_physical_memory_write((uint32_t) & ib->btx_ring[i].
|
|
365 |
tmd1_bits, (void *) &temp8, 1);
|
|
366 |
s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
|
|
367 |
s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
|
|
368 |
}
|
|
369 | 369 |
} |
370 | 370 |
if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA)) |
371 |
pic_set_irq(s->irq, 1);
|
|
371 |
pic_set_irq(s->irq, 1);
|
|
372 | 372 |
} |
373 | 373 |
|
374 | 374 |
static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr) |
... | ... | |
381 | 381 |
} |
382 | 382 |
|
383 | 383 |
static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, |
384 |
uint32_t val)
|
|
384 |
uint32_t val)
|
|
385 | 385 |
{ |
386 | 386 |
LANCEState *s = opaque; |
387 | 387 |
uint32_t saddr; |
... | ... | |
410 | 410 |
qemu_put_be32s(f, &s->leptr); |
411 | 411 |
qemu_put_be16s(f, &s->addr); |
412 | 412 |
for (i = 0; i < LE_NREGS; i++) |
413 |
qemu_put_be16s(f, &s->regs[i]);
|
|
413 |
qemu_put_be16s(f, &s->regs[i]);
|
|
414 | 414 |
qemu_put_buffer(f, s->phys, 6); |
415 | 415 |
qemu_put_be32s(f, &s->irq); |
416 | 416 |
for (i = 0; i < LEDMA_REGS; i++) |
417 |
qemu_put_be32s(f, &s->ledmaregs[i]);
|
|
417 |
qemu_put_be32s(f, &s->ledmaregs[i]);
|
|
418 | 418 |
} |
419 | 419 |
|
420 | 420 |
static int lance_load(QEMUFile * f, void *opaque, int version_id) |
... | ... | |
423 | 423 |
int i; |
424 | 424 |
|
425 | 425 |
if (version_id != 1) |
426 |
return -EINVAL;
|
|
426 |
return -EINVAL;
|
|
427 | 427 |
|
428 | 428 |
qemu_get_be32s(f, &s->leptr); |
429 | 429 |
qemu_get_be16s(f, &s->addr); |
430 | 430 |
for (i = 0; i < LE_NREGS; i++) |
431 |
qemu_get_be16s(f, &s->regs[i]);
|
|
431 |
qemu_get_be16s(f, &s->regs[i]);
|
|
432 | 432 |
qemu_get_buffer(f, s->phys, 6); |
433 | 433 |
qemu_get_be32s(f, &s->irq); |
434 | 434 |
for (i = 0; i < LEDMA_REGS; i++) |
435 |
qemu_get_be32s(f, &s->ledmaregs[i]);
|
|
435 |
qemu_get_be32s(f, &s->ledmaregs[i]);
|
|
436 | 436 |
return 0; |
437 | 437 |
} |
438 | 438 |
|
... | ... | |
443 | 443 |
|
444 | 444 |
s = qemu_mallocz(sizeof(LANCEState)); |
445 | 445 |
if (!s) |
446 |
return;
|
|
446 |
return;
|
|
447 | 447 |
|
448 | 448 |
s->irq = irq; |
449 | 449 |
|
450 | 450 |
lance_io_memory = |
451 |
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
|
|
451 |
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
|
|
452 | 452 |
cpu_register_physical_memory(leaddr, 4, lance_io_memory); |
453 | 453 |
|
454 | 454 |
ledma_io_memory = |
455 |
cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
|
|
455 |
cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
|
|
456 | 456 |
cpu_register_physical_memory(ledaddr, 16, ledma_io_memory); |
457 | 457 |
|
458 | 458 |
memcpy(s->macaddr, nd->macaddr, 6); |
... | ... | |
460 | 460 |
lance_reset(s); |
461 | 461 |
|
462 | 462 |
s->vc = |
463 |
qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive,
|
|
464 |
s);
|
|
463 |
qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive,
|
|
464 |
s);
|
|
465 | 465 |
|
466 | 466 |
snprintf(s->vc->info_str, sizeof(s->vc->info_str), |
467 |
"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
|
468 |
s->macaddr[0],
|
|
469 |
s->macaddr[1],
|
|
470 |
s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
|
|
467 |
"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
|
468 |
s->macaddr[0],
|
|
469 |
s->macaddr[1],
|
|
470 |
s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
|
|
471 | 471 |
|
472 | 472 |
register_savevm("lance", leaddr, 1, lance_save, lance_load, s); |
473 | 473 |
qemu_register_reset(lance_reset, s); |
Also available in: Unified diff