Revision 2aae2b8e
| b/target-sparc/cpu.h | ||
|---|---|---|
| 92 | 92 |
#define PSR_CARRY_SHIFT 20 |
| 93 | 93 |
#define PSR_CARRY (1 << PSR_CARRY_SHIFT) |
| 94 | 94 |
#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
| 95 |
#if !defined(TARGET_SPARC64) |
|
| 95 | 96 |
#define PSR_EF (1<<12) |
| 96 | 97 |
#define PSR_PIL 0xf00 |
| 97 | 98 |
#define PSR_S (1<<7) |
| 98 | 99 |
#define PSR_PS (1<<6) |
| 99 | 100 |
#define PSR_ET (1<<5) |
| 100 | 101 |
#define PSR_CWP 0x1f |
| 102 |
#endif |
|
| 101 | 103 |
|
| 102 | 104 |
#define CC_SRC (env->cc_src) |
| 103 | 105 |
#define CC_SRC2 (env->cc_src2) |
| ... | ... | |
| 341 | 343 |
uint32_t wim; /* window invalid mask */ |
| 342 | 344 |
#endif |
| 343 | 345 |
target_ulong tbr; /* trap base register */ |
| 346 |
#if !defined(TARGET_SPARC64) |
|
| 344 | 347 |
int psrs; /* supervisor mode (extracted from PSR) */ |
| 345 | 348 |
int psrps; /* previous supervisor mode */ |
| 346 |
#if !defined(TARGET_SPARC64) |
|
| 347 | 349 |
int psret; /* enable traps */ |
| 348 | 350 |
#endif |
| 349 | 351 |
uint32_t psrpil; /* interrupt blocking level */ |
| 350 | 352 |
uint32_t pil_in; /* incoming interrupt level bitmap */ |
| 353 |
#if !defined(TARGET_SPARC64) |
|
| 351 | 354 |
int psref; /* enable fpu */ |
| 355 |
#endif |
|
| 352 | 356 |
target_ulong version; |
| 353 | 357 |
int interrupt_index; |
| 354 | 358 |
uint32_t nwindows; |
| ... | ... | |
| 508 | 512 |
#define CPU_SAVE_VERSION 6 |
| 509 | 513 |
|
| 510 | 514 |
/* MMU modes definitions */ |
| 515 |
#if defined (TARGET_SPARC64) |
|
| 516 |
#define MMU_USER_IDX 0 |
|
| 511 | 517 |
#define MMU_MODE0_SUFFIX _user |
| 512 |
#define MMU_MODE1_SUFFIX _kernel |
|
| 513 |
#ifdef TARGET_SPARC64 |
|
| 514 |
#define MMU_MODE2_SUFFIX _hypv |
|
| 515 |
#define MMU_MODE3_SUFFIX _nucleus |
|
| 516 |
#define MMU_MODE4_SUFFIX _user_secondary |
|
| 517 |
#define MMU_MODE5_SUFFIX _kernel_secondary |
|
| 518 |
#endif |
|
| 518 |
#define MMU_USER_SECONDARY_IDX 1 |
|
| 519 |
#define MMU_MODE1_SUFFIX _user_secondary |
|
| 520 |
#define MMU_KERNEL_IDX 2 |
|
| 521 |
#define MMU_MODE2_SUFFIX _kernel |
|
| 522 |
#define MMU_KERNEL_SECONDARY_IDX 3 |
|
| 523 |
#define MMU_MODE3_SUFFIX _kernel_secondary |
|
| 524 |
#define MMU_NUCLEUS_IDX 4 |
|
| 525 |
#define MMU_MODE4_SUFFIX _nucleus |
|
| 526 |
#define MMU_HYPV_IDX 5 |
|
| 527 |
#define MMU_MODE5_SUFFIX _hypv |
|
| 528 |
#else |
|
| 519 | 529 |
#define MMU_USER_IDX 0 |
| 530 |
#define MMU_MODE0_SUFFIX _user |
|
| 520 | 531 |
#define MMU_KERNEL_IDX 1 |
| 521 |
#define MMU_HYPV_IDX 2 |
|
| 522 |
#ifdef TARGET_SPARC64 |
|
| 523 |
#define MMU_NUCLEUS_IDX 3 |
|
| 524 |
#define MMU_USER_SECONDARY_IDX 4 |
|
| 525 |
#define MMU_KERNEL_SECONDARY_IDX 5 |
|
| 532 |
#define MMU_MODE1_SUFFIX _kernel |
|
| 533 |
#endif |
|
| 534 |
|
|
| 535 |
#if defined (TARGET_SPARC64) |
|
| 536 |
static inline int cpu_has_hypervisor(CPUState *env1) |
|
| 537 |
{
|
|
| 538 |
return env1->def->features & CPU_FEATURE_HYPV; |
|
| 539 |
} |
|
| 540 |
|
|
| 541 |
static inline int cpu_hypervisor_mode(CPUState *env1) |
|
| 542 |
{
|
|
| 543 |
return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); |
|
| 544 |
} |
|
| 545 |
|
|
| 546 |
static inline int cpu_supervisor_mode(CPUState *env1) |
|
| 547 |
{
|
|
| 548 |
return env1->pstate & PS_PRIV; |
|
| 549 |
} |
|
| 526 | 550 |
#endif |
| 527 | 551 |
|
| 528 | 552 |
static inline int cpu_mmu_index(CPUState *env1) |
| ... | ... | |
| 532 | 556 |
#elif !defined(TARGET_SPARC64) |
| 533 | 557 |
return env1->psrs; |
| 534 | 558 |
#else |
| 535 |
if (!env1->psrs) |
|
| 536 |
return MMU_USER_IDX; |
|
| 537 |
else if ((env1->hpstate & HS_PRIV) == 0) |
|
| 538 |
return MMU_KERNEL_IDX; |
|
| 539 |
else |
|
| 559 |
if (cpu_hypervisor_mode(env1)) {
|
|
| 540 | 560 |
return MMU_HYPV_IDX; |
| 561 |
} else if (cpu_supervisor_mode(env1)) {
|
|
| 562 |
return MMU_KERNEL_IDX; |
|
| 563 |
} else {
|
|
| 564 |
return MMU_USER_IDX; |
|
| 565 |
} |
|
| 541 | 566 |
#endif |
| 542 | 567 |
} |
| 543 | 568 |
|
| b/target-sparc/helper.c | ||
|---|---|---|
| 746 | 746 |
#else |
| 747 | 747 |
#if !defined(TARGET_SPARC64) |
| 748 | 748 |
env->psret = 0; |
| 749 |
#endif |
|
| 750 | 749 |
env->psrs = 1; |
| 751 | 750 |
env->psrps = 1; |
| 751 |
#endif |
|
| 752 | 752 |
#ifdef TARGET_SPARC64 |
| 753 | 753 |
env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG; |
| 754 |
env->hpstate = HS_PRIV;
|
|
| 754 |
env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
|
|
| 755 | 755 |
env->tl = env->maxtl; |
| 756 | 756 |
cpu_tsptr(env)->tt = TT_POWER_ON_RESET; |
| 757 | 757 |
env->lsu = 0; |
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 1404 | 1404 |
(env->psrps? PSR_PS : 0) | |
| 1405 | 1405 |
(env->psret? PSR_ET : 0) | env->cwp; |
| 1406 | 1406 |
#else |
| 1407 |
return env->version | (env->psr & PSR_ICC) | |
|
| 1408 |
(env->psref? PSR_EF : 0) | |
|
| 1409 |
(env->psrpil << 8) | |
|
| 1410 |
(env->psrs? PSR_S : 0) | |
|
| 1411 |
(env->psrps? PSR_PS : 0) | env->cwp; |
|
| 1407 |
return env->psr & PSR_ICC; |
|
| 1412 | 1408 |
#endif |
| 1413 | 1409 |
} |
| 1414 | 1410 |
|
| ... | ... | |
| 1427 | 1423 |
static void put_psr(target_ulong val) |
| 1428 | 1424 |
{
|
| 1429 | 1425 |
env->psr = val & PSR_ICC; |
| 1426 |
#if !defined (TARGET_SPARC64) |
|
| 1430 | 1427 |
env->psref = (val & PSR_EF)? 1 : 0; |
| 1431 | 1428 |
env->psrpil = (val & PSR_PIL) >> 8; |
| 1429 |
#endif |
|
| 1432 | 1430 |
#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) |
| 1433 | 1431 |
cpu_check_irqs(env); |
| 1434 | 1432 |
#endif |
| 1433 |
#if !defined (TARGET_SPARC64) |
|
| 1435 | 1434 |
env->psrs = (val & PSR_S)? 1 : 0; |
| 1436 | 1435 |
env->psrps = (val & PSR_PS)? 1 : 0; |
| 1437 |
#if !defined (TARGET_SPARC64) |
|
| 1438 | 1436 |
env->psret = (val & PSR_ET)? 1 : 0; |
| 1439 |
#endif |
|
| 1440 | 1437 |
set_cwp(val & PSR_CWP); |
| 1438 |
#endif |
|
| 1441 | 1439 |
env->cc_op = CC_OP_FLAGS; |
| 1442 | 1440 |
} |
| 1443 | 1441 |
|
| ... | ... | |
| 2326 | 2324 |
asi &= 0xff; |
| 2327 | 2325 |
|
| 2328 | 2326 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 2329 |
|| ((env->def->features & CPU_FEATURE_HYPV)
|
|
| 2327 |
|| (cpu_has_hypervisor(env)
|
|
| 2330 | 2328 |
&& asi >= 0x30 && asi < 0x80 |
| 2331 | 2329 |
&& !(env->hpstate & HS_PRIV))) |
| 2332 | 2330 |
raise_exception(TT_PRIV_ACT); |
| ... | ... | |
| 2361 | 2359 |
case 0xe2: // UA2007 Primary block init |
| 2362 | 2360 |
case 0xe3: // UA2007 Secondary block init |
| 2363 | 2361 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
|
| 2364 |
if ((env->def->features & CPU_FEATURE_HYPV) |
|
| 2365 |
&& env->hpstate & HS_PRIV) {
|
|
| 2362 |
if (cpu_hypervisor_mode(env)) {
|
|
| 2366 | 2363 |
switch(size) {
|
| 2367 | 2364 |
case 1: |
| 2368 | 2365 |
ret = ldub_hypv(addr); |
| ... | ... | |
| 2678 | 2675 |
asi &= 0xff; |
| 2679 | 2676 |
|
| 2680 | 2677 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 2681 |
|| ((env->def->features & CPU_FEATURE_HYPV)
|
|
| 2678 |
|| (cpu_has_hypervisor(env)
|
|
| 2682 | 2679 |
&& asi >= 0x30 && asi < 0x80 |
| 2683 | 2680 |
&& !(env->hpstate & HS_PRIV))) |
| 2684 | 2681 |
raise_exception(TT_PRIV_ACT); |
| ... | ... | |
| 2722 | 2719 |
case 0xe2: // UA2007 Primary block init |
| 2723 | 2720 |
case 0xe3: // UA2007 Secondary block init |
| 2724 | 2721 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
|
| 2725 |
if ((env->def->features & CPU_FEATURE_HYPV) |
|
| 2726 |
&& env->hpstate & HS_PRIV) {
|
|
| 2722 |
if (cpu_hypervisor_mode(env)) {
|
|
| 2727 | 2723 |
switch(size) {
|
| 2728 | 2724 |
case 1: |
| 2729 | 2725 |
stb_hypv(addr, val); |
| ... | ... | |
| 3048 | 3044 |
void helper_ldda_asi(target_ulong addr, int asi, int rd) |
| 3049 | 3045 |
{
|
| 3050 | 3046 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 3051 |
|| ((env->def->features & CPU_FEATURE_HYPV)
|
|
| 3047 |
|| (cpu_has_hypervisor(env)
|
|
| 3052 | 3048 |
&& asi >= 0x30 && asi < 0x80 |
| 3053 | 3049 |
&& !(env->hpstate & HS_PRIV))) |
| 3054 | 3050 |
raise_exception(TT_PRIV_ACT); |
| b/target-sparc/translate.c | ||
|---|---|---|
| 183 | 183 |
#define hypervisor(dc) 0 |
| 184 | 184 |
#endif |
| 185 | 185 |
#else |
| 186 |
#define supervisor(dc) (dc->mem_idx >= 1)
|
|
| 186 |
#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
|
|
| 187 | 187 |
#ifdef TARGET_SPARC64 |
| 188 |
#define hypervisor(dc) (dc->mem_idx == 2)
|
|
| 188 |
#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
|
|
| 189 | 189 |
#else |
| 190 | 190 |
#endif |
| 191 | 191 |
#endif |
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