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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 8253/8254 interval timer emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 80cabfad | bellard | |
29 | b0a21b53 | bellard | //#define DEBUG_PIT
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30 | b0a21b53 | bellard | |
31 | ec844b96 | bellard | #define RW_STATE_LSB 1 |
32 | ec844b96 | bellard | #define RW_STATE_MSB 2 |
33 | ec844b96 | bellard | #define RW_STATE_WORD0 3 |
34 | ec844b96 | bellard | #define RW_STATE_WORD1 4 |
35 | 80cabfad | bellard | |
36 | ec844b96 | bellard | typedef struct PITChannelState { |
37 | ec844b96 | bellard | int count; /* can be 65536 */ |
38 | ec844b96 | bellard | uint16_t latched_count; |
39 | ec844b96 | bellard | uint8_t count_latched; |
40 | ec844b96 | bellard | uint8_t status_latched; |
41 | ec844b96 | bellard | uint8_t status; |
42 | ec844b96 | bellard | uint8_t read_state; |
43 | ec844b96 | bellard | uint8_t write_state; |
44 | ec844b96 | bellard | uint8_t write_latch; |
45 | ec844b96 | bellard | uint8_t rw_mode; |
46 | ec844b96 | bellard | uint8_t mode; |
47 | ec844b96 | bellard | uint8_t bcd; /* not supported */
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48 | ec844b96 | bellard | uint8_t gate; /* timer start */
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49 | ec844b96 | bellard | int64_t count_load_time; |
50 | ec844b96 | bellard | /* irq handling */
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51 | ec844b96 | bellard | int64_t next_transition_time; |
52 | ec844b96 | bellard | QEMUTimer *irq_timer; |
53 | d537cf6c | pbrook | qemu_irq irq; |
54 | ec844b96 | bellard | } PITChannelState; |
55 | ec844b96 | bellard | |
56 | 64d7e9a4 | Blue Swirl | typedef struct PITState { |
57 | 64d7e9a4 | Blue Swirl | ISADevice dev; |
58 | 60ea6aa8 | Richard Henderson | MemoryRegion ioports; |
59 | 64d7e9a4 | Blue Swirl | uint32_t irq; |
60 | 64d7e9a4 | Blue Swirl | uint32_t iobase; |
61 | ec844b96 | bellard | PITChannelState channels[3];
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62 | 64d7e9a4 | Blue Swirl | } PITState; |
63 | ec844b96 | bellard | |
64 | ec844b96 | bellard | static PITState pit_state;
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65 | 80cabfad | bellard | |
66 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
67 | b0a21b53 | bellard | |
68 | 80cabfad | bellard | static int pit_get_count(PITChannelState *s) |
69 | 80cabfad | bellard | { |
70 | 80cabfad | bellard | uint64_t d; |
71 | 80cabfad | bellard | int counter;
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72 | 80cabfad | bellard | |
73 | 74475455 | Paolo Bonzini | d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ, |
74 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
75 | 80cabfad | bellard | switch(s->mode) {
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76 | 80cabfad | bellard | case 0: |
77 | 80cabfad | bellard | case 1: |
78 | 80cabfad | bellard | case 4: |
79 | 80cabfad | bellard | case 5: |
80 | 80cabfad | bellard | counter = (s->count - d) & 0xffff;
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81 | 80cabfad | bellard | break;
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82 | 80cabfad | bellard | case 3: |
83 | 80cabfad | bellard | /* XXX: may be incorrect for odd counts */
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84 | 80cabfad | bellard | counter = s->count - ((2 * d) % s->count);
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85 | 80cabfad | bellard | break;
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86 | 80cabfad | bellard | default:
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87 | 80cabfad | bellard | counter = s->count - (d % s->count); |
88 | 80cabfad | bellard | break;
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89 | 80cabfad | bellard | } |
90 | 80cabfad | bellard | return counter;
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91 | 80cabfad | bellard | } |
92 | 80cabfad | bellard | |
93 | 80cabfad | bellard | /* get pit output bit */
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94 | ec844b96 | bellard | static int pit_get_out1(PITChannelState *s, int64_t current_time) |
95 | 80cabfad | bellard | { |
96 | 80cabfad | bellard | uint64_t d; |
97 | 80cabfad | bellard | int out;
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98 | 80cabfad | bellard | |
99 | 6ee093c9 | Juan Quintela | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
100 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
101 | 80cabfad | bellard | switch(s->mode) {
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102 | 80cabfad | bellard | default:
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103 | 80cabfad | bellard | case 0: |
104 | 80cabfad | bellard | out = (d >= s->count); |
105 | 80cabfad | bellard | break;
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106 | 80cabfad | bellard | case 1: |
107 | 80cabfad | bellard | out = (d < s->count); |
108 | 80cabfad | bellard | break;
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109 | 80cabfad | bellard | case 2: |
110 | 80cabfad | bellard | if ((d % s->count) == 0 && d != 0) |
111 | 80cabfad | bellard | out = 1;
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112 | 80cabfad | bellard | else
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113 | 80cabfad | bellard | out = 0;
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114 | 80cabfad | bellard | break;
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115 | 80cabfad | bellard | case 3: |
116 | 80cabfad | bellard | out = (d % s->count) < ((s->count + 1) >> 1); |
117 | 80cabfad | bellard | break;
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118 | 80cabfad | bellard | case 4: |
119 | 80cabfad | bellard | case 5: |
120 | 80cabfad | bellard | out = (d == s->count); |
121 | 80cabfad | bellard | break;
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122 | 80cabfad | bellard | } |
123 | 80cabfad | bellard | return out;
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124 | 80cabfad | bellard | } |
125 | 80cabfad | bellard | |
126 | 64d7e9a4 | Blue Swirl | int pit_get_out(ISADevice *dev, int channel, int64_t current_time) |
127 | ec844b96 | bellard | { |
128 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
129 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
130 | ec844b96 | bellard | return pit_get_out1(s, current_time);
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131 | ec844b96 | bellard | } |
132 | ec844b96 | bellard | |
133 | b0a21b53 | bellard | /* return -1 if no transition will occur. */
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134 | 5fafdf24 | ths | static int64_t pit_get_next_transition_time(PITChannelState *s,
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135 | b0a21b53 | bellard | int64_t current_time) |
136 | 80cabfad | bellard | { |
137 | b0a21b53 | bellard | uint64_t d, next_time, base; |
138 | b0a21b53 | bellard | int period2;
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139 | 80cabfad | bellard | |
140 | 6ee093c9 | Juan Quintela | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
141 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
142 | 80cabfad | bellard | switch(s->mode) {
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143 | 80cabfad | bellard | default:
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144 | 80cabfad | bellard | case 0: |
145 | 80cabfad | bellard | case 1: |
146 | b0a21b53 | bellard | if (d < s->count)
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147 | b0a21b53 | bellard | next_time = s->count; |
148 | b0a21b53 | bellard | else
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149 | b0a21b53 | bellard | return -1; |
150 | 80cabfad | bellard | break;
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151 | 80cabfad | bellard | case 2: |
152 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
153 | b0a21b53 | bellard | if ((d - base) == 0 && d != 0) |
154 | b0a21b53 | bellard | next_time = base + s->count; |
155 | b0a21b53 | bellard | else
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156 | b0a21b53 | bellard | next_time = base + s->count + 1;
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157 | 80cabfad | bellard | break;
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158 | 80cabfad | bellard | case 3: |
159 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
160 | b0a21b53 | bellard | period2 = ((s->count + 1) >> 1); |
161 | 5fafdf24 | ths | if ((d - base) < period2)
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162 | b0a21b53 | bellard | next_time = base + period2; |
163 | b0a21b53 | bellard | else
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164 | b0a21b53 | bellard | next_time = base + s->count; |
165 | 80cabfad | bellard | break;
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166 | 80cabfad | bellard | case 4: |
167 | 80cabfad | bellard | case 5: |
168 | b0a21b53 | bellard | if (d < s->count)
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169 | b0a21b53 | bellard | next_time = s->count; |
170 | b0a21b53 | bellard | else if (d == s->count) |
171 | b0a21b53 | bellard | next_time = s->count + 1;
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172 | 80cabfad | bellard | else
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173 | b0a21b53 | bellard | return -1; |
174 | 80cabfad | bellard | break;
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175 | 80cabfad | bellard | } |
176 | b0a21b53 | bellard | /* convert to timer units */
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177 | 6ee093c9 | Juan Quintela | next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(), |
178 | 6ee093c9 | Juan Quintela | PIT_FREQ); |
179 | 1154e441 | bellard | /* fix potential rounding problems */
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180 | 1154e441 | bellard | /* XXX: better solution: use a clock at PIT_FREQ Hz */
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181 | 1154e441 | bellard | if (next_time <= current_time)
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182 | 1154e441 | bellard | next_time = current_time + 1;
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183 | b0a21b53 | bellard | return next_time;
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184 | 80cabfad | bellard | } |
185 | 80cabfad | bellard | |
186 | 80cabfad | bellard | /* val must be 0 or 1 */
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187 | 64d7e9a4 | Blue Swirl | void pit_set_gate(ISADevice *dev, int channel, int val) |
188 | 80cabfad | bellard | { |
189 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
190 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
191 | ec844b96 | bellard | |
192 | 80cabfad | bellard | switch(s->mode) {
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193 | 80cabfad | bellard | default:
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194 | 80cabfad | bellard | case 0: |
195 | 80cabfad | bellard | case 4: |
196 | 80cabfad | bellard | /* XXX: just disable/enable counting */
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197 | 80cabfad | bellard | break;
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198 | 80cabfad | bellard | case 1: |
199 | 80cabfad | bellard | case 5: |
200 | 80cabfad | bellard | if (s->gate < val) {
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201 | 80cabfad | bellard | /* restart counting on rising edge */
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202 | 74475455 | Paolo Bonzini | s->count_load_time = qemu_get_clock_ns(vm_clock); |
203 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
204 | 80cabfad | bellard | } |
205 | 80cabfad | bellard | break;
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206 | 80cabfad | bellard | case 2: |
207 | 80cabfad | bellard | case 3: |
208 | 80cabfad | bellard | if (s->gate < val) {
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209 | 80cabfad | bellard | /* restart counting on rising edge */
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210 | 74475455 | Paolo Bonzini | s->count_load_time = qemu_get_clock_ns(vm_clock); |
211 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
212 | 80cabfad | bellard | } |
213 | 80cabfad | bellard | /* XXX: disable/enable counting */
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214 | 80cabfad | bellard | break;
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215 | 80cabfad | bellard | } |
216 | 80cabfad | bellard | s->gate = val; |
217 | 80cabfad | bellard | } |
218 | 80cabfad | bellard | |
219 | 64d7e9a4 | Blue Swirl | int pit_get_gate(ISADevice *dev, int channel) |
220 | ec844b96 | bellard | { |
221 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
222 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
223 | ec844b96 | bellard | return s->gate;
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224 | ec844b96 | bellard | } |
225 | ec844b96 | bellard | |
226 | 64d7e9a4 | Blue Swirl | int pit_get_initial_count(ISADevice *dev, int channel) |
227 | fd06c375 | bellard | { |
228 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
229 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
230 | fd06c375 | bellard | return s->count;
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231 | fd06c375 | bellard | } |
232 | fd06c375 | bellard | |
233 | 64d7e9a4 | Blue Swirl | int pit_get_mode(ISADevice *dev, int channel) |
234 | fd06c375 | bellard | { |
235 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
236 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
237 | fd06c375 | bellard | return s->mode;
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238 | fd06c375 | bellard | } |
239 | fd06c375 | bellard | |
240 | 80cabfad | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
241 | 80cabfad | bellard | { |
242 | 80cabfad | bellard | if (val == 0) |
243 | 80cabfad | bellard | val = 0x10000;
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244 | 74475455 | Paolo Bonzini | s->count_load_time = qemu_get_clock_ns(vm_clock); |
245 | 80cabfad | bellard | s->count = val; |
246 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
247 | 80cabfad | bellard | } |
248 | 80cabfad | bellard | |
249 | ec844b96 | bellard | /* if already latched, do not latch again */
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250 | ec844b96 | bellard | static void pit_latch_count(PITChannelState *s) |
251 | ec844b96 | bellard | { |
252 | ec844b96 | bellard | if (!s->count_latched) {
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253 | ec844b96 | bellard | s->latched_count = pit_get_count(s); |
254 | ec844b96 | bellard | s->count_latched = s->rw_mode; |
255 | ec844b96 | bellard | } |
256 | ec844b96 | bellard | } |
257 | ec844b96 | bellard | |
258 | b41a2cd1 | bellard | static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
259 | 80cabfad | bellard | { |
260 | ec844b96 | bellard | PITState *pit = opaque; |
261 | 80cabfad | bellard | int channel, access;
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262 | 80cabfad | bellard | PITChannelState *s; |
263 | 80cabfad | bellard | |
264 | 80cabfad | bellard | addr &= 3;
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265 | 80cabfad | bellard | if (addr == 3) { |
266 | 80cabfad | bellard | channel = val >> 6;
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267 | ec844b96 | bellard | if (channel == 3) { |
268 | ec844b96 | bellard | /* read back command */
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269 | ec844b96 | bellard | for(channel = 0; channel < 3; channel++) { |
270 | ec844b96 | bellard | s = &pit->channels[channel]; |
271 | ec844b96 | bellard | if (val & (2 << channel)) { |
272 | ec844b96 | bellard | if (!(val & 0x20)) { |
273 | ec844b96 | bellard | pit_latch_count(s); |
274 | ec844b96 | bellard | } |
275 | ec844b96 | bellard | if (!(val & 0x10) && !s->status_latched) { |
276 | ec844b96 | bellard | /* status latch */
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277 | ec844b96 | bellard | /* XXX: add BCD and null count */
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278 | 74475455 | Paolo Bonzini | s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) |
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279 | ec844b96 | bellard | (s->rw_mode << 4) |
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280 | ec844b96 | bellard | (s->mode << 1) |
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281 | ec844b96 | bellard | s->bcd; |
282 | ec844b96 | bellard | s->status_latched = 1;
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283 | ec844b96 | bellard | } |
284 | ec844b96 | bellard | } |
285 | ec844b96 | bellard | } |
286 | ec844b96 | bellard | } else {
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287 | ec844b96 | bellard | s = &pit->channels[channel]; |
288 | ec844b96 | bellard | access = (val >> 4) & 3; |
289 | ec844b96 | bellard | if (access == 0) { |
290 | ec844b96 | bellard | pit_latch_count(s); |
291 | ec844b96 | bellard | } else {
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292 | ec844b96 | bellard | s->rw_mode = access; |
293 | ec844b96 | bellard | s->read_state = access; |
294 | ec844b96 | bellard | s->write_state = access; |
295 | ec844b96 | bellard | |
296 | ec844b96 | bellard | s->mode = (val >> 1) & 7; |
297 | ec844b96 | bellard | s->bcd = val & 1;
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298 | ec844b96 | bellard | /* XXX: update irq timer ? */
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299 | ec844b96 | bellard | } |
300 | 80cabfad | bellard | } |
301 | 80cabfad | bellard | } else {
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302 | ec844b96 | bellard | s = &pit->channels[addr]; |
303 | ec844b96 | bellard | switch(s->write_state) {
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304 | ec844b96 | bellard | default:
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305 | 80cabfad | bellard | case RW_STATE_LSB:
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306 | 80cabfad | bellard | pit_load_count(s, val); |
307 | 80cabfad | bellard | break;
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308 | 80cabfad | bellard | case RW_STATE_MSB:
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309 | 80cabfad | bellard | pit_load_count(s, val << 8);
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310 | 80cabfad | bellard | break;
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311 | 80cabfad | bellard | case RW_STATE_WORD0:
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312 | ec844b96 | bellard | s->write_latch = val; |
313 | ec844b96 | bellard | s->write_state = RW_STATE_WORD1; |
314 | ec844b96 | bellard | break;
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315 | 80cabfad | bellard | case RW_STATE_WORD1:
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316 | ec844b96 | bellard | pit_load_count(s, s->write_latch | (val << 8));
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317 | ec844b96 | bellard | s->write_state = RW_STATE_WORD0; |
318 | 80cabfad | bellard | break;
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319 | 80cabfad | bellard | } |
320 | 80cabfad | bellard | } |
321 | 80cabfad | bellard | } |
322 | 80cabfad | bellard | |
323 | b41a2cd1 | bellard | static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
324 | 80cabfad | bellard | { |
325 | ec844b96 | bellard | PITState *pit = opaque; |
326 | 80cabfad | bellard | int ret, count;
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327 | 80cabfad | bellard | PITChannelState *s; |
328 | 3b46e624 | ths | |
329 | 80cabfad | bellard | addr &= 3;
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330 | ec844b96 | bellard | s = &pit->channels[addr]; |
331 | ec844b96 | bellard | if (s->status_latched) {
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332 | ec844b96 | bellard | s->status_latched = 0;
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333 | ec844b96 | bellard | ret = s->status; |
334 | ec844b96 | bellard | } else if (s->count_latched) { |
335 | ec844b96 | bellard | switch(s->count_latched) {
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336 | ec844b96 | bellard | default:
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337 | ec844b96 | bellard | case RW_STATE_LSB:
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338 | ec844b96 | bellard | ret = s->latched_count & 0xff;
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339 | ec844b96 | bellard | s->count_latched = 0;
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340 | ec844b96 | bellard | break;
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341 | ec844b96 | bellard | case RW_STATE_MSB:
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342 | 80cabfad | bellard | ret = s->latched_count >> 8;
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343 | ec844b96 | bellard | s->count_latched = 0;
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344 | ec844b96 | bellard | break;
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345 | ec844b96 | bellard | case RW_STATE_WORD0:
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346 | 80cabfad | bellard | ret = s->latched_count & 0xff;
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347 | ec844b96 | bellard | s->count_latched = RW_STATE_MSB; |
348 | ec844b96 | bellard | break;
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349 | ec844b96 | bellard | } |
350 | ec844b96 | bellard | } else {
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351 | ec844b96 | bellard | switch(s->read_state) {
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352 | ec844b96 | bellard | default:
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353 | ec844b96 | bellard | case RW_STATE_LSB:
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354 | ec844b96 | bellard | count = pit_get_count(s); |
355 | ec844b96 | bellard | ret = count & 0xff;
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356 | ec844b96 | bellard | break;
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357 | ec844b96 | bellard | case RW_STATE_MSB:
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358 | ec844b96 | bellard | count = pit_get_count(s); |
359 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
360 | ec844b96 | bellard | break;
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361 | ec844b96 | bellard | case RW_STATE_WORD0:
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362 | ec844b96 | bellard | count = pit_get_count(s); |
363 | ec844b96 | bellard | ret = count & 0xff;
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364 | ec844b96 | bellard | s->read_state = RW_STATE_WORD1; |
365 | ec844b96 | bellard | break;
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366 | ec844b96 | bellard | case RW_STATE_WORD1:
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367 | ec844b96 | bellard | count = pit_get_count(s); |
368 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
369 | ec844b96 | bellard | s->read_state = RW_STATE_WORD0; |
370 | ec844b96 | bellard | break;
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371 | ec844b96 | bellard | } |
372 | 80cabfad | bellard | } |
373 | 80cabfad | bellard | return ret;
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374 | 80cabfad | bellard | } |
375 | 80cabfad | bellard | |
376 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
377 | b0a21b53 | bellard | { |
378 | b0a21b53 | bellard | int64_t expire_time; |
379 | b0a21b53 | bellard | int irq_level;
|
380 | b0a21b53 | bellard | |
381 | b0a21b53 | bellard | if (!s->irq_timer)
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382 | b0a21b53 | bellard | return;
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383 | b0a21b53 | bellard | expire_time = pit_get_next_transition_time(s, current_time); |
384 | ec844b96 | bellard | irq_level = pit_get_out1(s, current_time); |
385 | d537cf6c | pbrook | qemu_set_irq(s->irq, irq_level); |
386 | b0a21b53 | bellard | #ifdef DEBUG_PIT
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387 | b0a21b53 | bellard | printf("irq_level=%d next_delay=%f\n",
|
388 | 5fafdf24 | ths | irq_level, |
389 | 6ee093c9 | Juan Quintela | (double)(expire_time - current_time) / get_ticks_per_sec());
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390 | b0a21b53 | bellard | #endif
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391 | b0a21b53 | bellard | s->next_transition_time = expire_time; |
392 | b0a21b53 | bellard | if (expire_time != -1) |
393 | b0a21b53 | bellard | qemu_mod_timer(s->irq_timer, expire_time); |
394 | b0a21b53 | bellard | else
|
395 | b0a21b53 | bellard | qemu_del_timer(s->irq_timer); |
396 | b0a21b53 | bellard | } |
397 | b0a21b53 | bellard | |
398 | b0a21b53 | bellard | static void pit_irq_timer(void *opaque) |
399 | b0a21b53 | bellard | { |
400 | b0a21b53 | bellard | PITChannelState *s = opaque; |
401 | b0a21b53 | bellard | |
402 | b0a21b53 | bellard | pit_irq_timer_update(s, s->next_transition_time); |
403 | b0a21b53 | bellard | } |
404 | b0a21b53 | bellard | |
405 | 5122b431 | Juan Quintela | static const VMStateDescription vmstate_pit_channel = { |
406 | 5122b431 | Juan Quintela | .name = "pit channel",
|
407 | 5122b431 | Juan Quintela | .version_id = 2,
|
408 | 5122b431 | Juan Quintela | .minimum_version_id = 2,
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409 | 5122b431 | Juan Quintela | .minimum_version_id_old = 2,
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410 | 5122b431 | Juan Quintela | .fields = (VMStateField []) { |
411 | 5122b431 | Juan Quintela | VMSTATE_INT32(count, PITChannelState), |
412 | 5122b431 | Juan Quintela | VMSTATE_UINT16(latched_count, PITChannelState), |
413 | 5122b431 | Juan Quintela | VMSTATE_UINT8(count_latched, PITChannelState), |
414 | 5122b431 | Juan Quintela | VMSTATE_UINT8(status_latched, PITChannelState), |
415 | 5122b431 | Juan Quintela | VMSTATE_UINT8(status, PITChannelState), |
416 | 5122b431 | Juan Quintela | VMSTATE_UINT8(read_state, PITChannelState), |
417 | 5122b431 | Juan Quintela | VMSTATE_UINT8(write_state, PITChannelState), |
418 | 5122b431 | Juan Quintela | VMSTATE_UINT8(write_latch, PITChannelState), |
419 | 5122b431 | Juan Quintela | VMSTATE_UINT8(rw_mode, PITChannelState), |
420 | 5122b431 | Juan Quintela | VMSTATE_UINT8(mode, PITChannelState), |
421 | 5122b431 | Juan Quintela | VMSTATE_UINT8(bcd, PITChannelState), |
422 | 5122b431 | Juan Quintela | VMSTATE_UINT8(gate, PITChannelState), |
423 | 5122b431 | Juan Quintela | VMSTATE_INT64(count_load_time, PITChannelState), |
424 | 5122b431 | Juan Quintela | VMSTATE_INT64(next_transition_time, PITChannelState), |
425 | 5122b431 | Juan Quintela | VMSTATE_END_OF_LIST() |
426 | b0a21b53 | bellard | } |
427 | 5122b431 | Juan Quintela | }; |
428 | b0a21b53 | bellard | |
429 | 5122b431 | Juan Quintela | static int pit_load_old(QEMUFile *f, void *opaque, int version_id) |
430 | b0a21b53 | bellard | { |
431 | ec844b96 | bellard | PITState *pit = opaque; |
432 | b0a21b53 | bellard | PITChannelState *s; |
433 | b0a21b53 | bellard | int i;
|
434 | 3b46e624 | ths | |
435 | b0a21b53 | bellard | if (version_id != 1) |
436 | b0a21b53 | bellard | return -EINVAL;
|
437 | b0a21b53 | bellard | |
438 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
439 | ec844b96 | bellard | s = &pit->channels[i]; |
440 | bee8d684 | ths | s->count=qemu_get_be32(f); |
441 | b0a21b53 | bellard | qemu_get_be16s(f, &s->latched_count); |
442 | ec844b96 | bellard | qemu_get_8s(f, &s->count_latched); |
443 | ec844b96 | bellard | qemu_get_8s(f, &s->status_latched); |
444 | ec844b96 | bellard | qemu_get_8s(f, &s->status); |
445 | ec844b96 | bellard | qemu_get_8s(f, &s->read_state); |
446 | ec844b96 | bellard | qemu_get_8s(f, &s->write_state); |
447 | ec844b96 | bellard | qemu_get_8s(f, &s->write_latch); |
448 | ec844b96 | bellard | qemu_get_8s(f, &s->rw_mode); |
449 | b0a21b53 | bellard | qemu_get_8s(f, &s->mode); |
450 | b0a21b53 | bellard | qemu_get_8s(f, &s->bcd); |
451 | b0a21b53 | bellard | qemu_get_8s(f, &s->gate); |
452 | bee8d684 | ths | s->count_load_time=qemu_get_be64(f); |
453 | b0a21b53 | bellard | if (s->irq_timer) {
|
454 | bee8d684 | ths | s->next_transition_time=qemu_get_be64(f); |
455 | b0a21b53 | bellard | qemu_get_timer(f, s->irq_timer); |
456 | b0a21b53 | bellard | } |
457 | b0a21b53 | bellard | } |
458 | b0a21b53 | bellard | return 0; |
459 | b0a21b53 | bellard | } |
460 | b0a21b53 | bellard | |
461 | 5122b431 | Juan Quintela | static const VMStateDescription vmstate_pit = { |
462 | 5122b431 | Juan Quintela | .name = "i8254",
|
463 | 5122b431 | Juan Quintela | .version_id = 2,
|
464 | 5122b431 | Juan Quintela | .minimum_version_id = 2,
|
465 | 5122b431 | Juan Quintela | .minimum_version_id_old = 1,
|
466 | 5122b431 | Juan Quintela | .load_state_old = pit_load_old, |
467 | 5122b431 | Juan Quintela | .fields = (VMStateField []) { |
468 | 5122b431 | Juan Quintela | VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState), |
469 | 5122b431 | Juan Quintela | VMSTATE_TIMER(channels[0].irq_timer, PITState),
|
470 | 5122b431 | Juan Quintela | VMSTATE_END_OF_LIST() |
471 | 5122b431 | Juan Quintela | } |
472 | 5122b431 | Juan Quintela | }; |
473 | 5122b431 | Juan Quintela | |
474 | 64d7e9a4 | Blue Swirl | static void pit_reset(DeviceState *dev) |
475 | 80cabfad | bellard | { |
476 | 64d7e9a4 | Blue Swirl | PITState *pit = container_of(dev, PITState, dev.qdev); |
477 | 80cabfad | bellard | PITChannelState *s; |
478 | 80cabfad | bellard | int i;
|
479 | 80cabfad | bellard | |
480 | 80cabfad | bellard | for(i = 0;i < 3; i++) { |
481 | ec844b96 | bellard | s = &pit->channels[i]; |
482 | 80cabfad | bellard | s->mode = 3;
|
483 | 80cabfad | bellard | s->gate = (i != 2);
|
484 | 80cabfad | bellard | pit_load_count(s, 0);
|
485 | 80cabfad | bellard | } |
486 | d7d02e3c | bellard | } |
487 | d7d02e3c | bellard | |
488 | 16b29ae1 | aliguori | /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
|
489 | 16b29ae1 | aliguori | void hpet_pit_disable(void) { |
490 | 16b29ae1 | aliguori | PITChannelState *s; |
491 | 16b29ae1 | aliguori | s = &pit_state.channels[0];
|
492 | e0dd114c | aliguori | if (s->irq_timer)
|
493 | e0dd114c | aliguori | qemu_del_timer(s->irq_timer); |
494 | 16b29ae1 | aliguori | } |
495 | 16b29ae1 | aliguori | |
496 | c50c2d68 | aurel32 | /* When HPET is reset or leaving legacy mode, it must reenable i8254
|
497 | 16b29ae1 | aliguori | * timer 0
|
498 | 16b29ae1 | aliguori | */
|
499 | 16b29ae1 | aliguori | |
500 | 16b29ae1 | aliguori | void hpet_pit_enable(void) |
501 | 16b29ae1 | aliguori | { |
502 | 16b29ae1 | aliguori | PITState *pit = &pit_state; |
503 | 16b29ae1 | aliguori | PITChannelState *s; |
504 | 16b29ae1 | aliguori | s = &pit->channels[0];
|
505 | 16b29ae1 | aliguori | s->mode = 3;
|
506 | 16b29ae1 | aliguori | s->gate = 1;
|
507 | 16b29ae1 | aliguori | pit_load_count(s, 0);
|
508 | 16b29ae1 | aliguori | } |
509 | 16b29ae1 | aliguori | |
510 | 60ea6aa8 | Richard Henderson | static const MemoryRegionPortio pit_portio[] = { |
511 | 60ea6aa8 | Richard Henderson | { 0, 4, 1, .write = pit_ioport_write }, |
512 | 60ea6aa8 | Richard Henderson | { 0, 3, 1, .read = pit_ioport_read }, |
513 | 60ea6aa8 | Richard Henderson | PORTIO_END_OF_LIST() |
514 | 60ea6aa8 | Richard Henderson | }; |
515 | 60ea6aa8 | Richard Henderson | |
516 | 60ea6aa8 | Richard Henderson | static const MemoryRegionOps pit_ioport_ops = { |
517 | 60ea6aa8 | Richard Henderson | .old_portio = pit_portio |
518 | 60ea6aa8 | Richard Henderson | }; |
519 | 60ea6aa8 | Richard Henderson | |
520 | 64d7e9a4 | Blue Swirl | static int pit_initfn(ISADevice *dev) |
521 | d7d02e3c | bellard | { |
522 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
523 | d7d02e3c | bellard | PITChannelState *s; |
524 | d7d02e3c | bellard | |
525 | d7d02e3c | bellard | s = &pit->channels[0];
|
526 | d7d02e3c | bellard | /* the timer 0 is connected to an IRQ */
|
527 | 74475455 | Paolo Bonzini | s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s); |
528 | 48a18b3c | Hervé Poussineau | s->irq = isa_get_irq(dev, pit->irq); |
529 | 80cabfad | bellard | |
530 | 60ea6aa8 | Richard Henderson | memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4); |
531 | 60ea6aa8 | Richard Henderson | isa_register_ioport(dev, &pit->ioports, pit->iobase); |
532 | d7d02e3c | bellard | |
533 | ca22a3a3 | Jan Kiszka | qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
|
534 | ca22a3a3 | Jan Kiszka | |
535 | 64d7e9a4 | Blue Swirl | return 0; |
536 | 64d7e9a4 | Blue Swirl | } |
537 | 64d7e9a4 | Blue Swirl | |
538 | 64d7e9a4 | Blue Swirl | static ISADeviceInfo pit_info = {
|
539 | 64d7e9a4 | Blue Swirl | .qdev.name = "isa-pit",
|
540 | 64d7e9a4 | Blue Swirl | .qdev.size = sizeof(PITState),
|
541 | 64d7e9a4 | Blue Swirl | .qdev.vmsd = &vmstate_pit, |
542 | 64d7e9a4 | Blue Swirl | .qdev.reset = pit_reset, |
543 | 64d7e9a4 | Blue Swirl | .qdev.no_user = 1,
|
544 | 64d7e9a4 | Blue Swirl | .init = pit_initfn, |
545 | 64d7e9a4 | Blue Swirl | .qdev.props = (Property[]) { |
546 | 64d7e9a4 | Blue Swirl | DEFINE_PROP_UINT32("irq", PITState, irq, -1), |
547 | 64d7e9a4 | Blue Swirl | DEFINE_PROP_HEX32("iobase", PITState, iobase, -1), |
548 | 64d7e9a4 | Blue Swirl | DEFINE_PROP_END_OF_LIST(), |
549 | 64d7e9a4 | Blue Swirl | }, |
550 | 64d7e9a4 | Blue Swirl | }; |
551 | 64d7e9a4 | Blue Swirl | |
552 | 64d7e9a4 | Blue Swirl | static void pit_register(void) |
553 | 64d7e9a4 | Blue Swirl | { |
554 | 64d7e9a4 | Blue Swirl | isa_qdev_register(&pit_info); |
555 | 80cabfad | bellard | } |
556 | 64d7e9a4 | Blue Swirl | device_init(pit_register) |