root / target-sparc / translate.c @ 2b29924f
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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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19 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 7a3f1944 | bellard | */
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21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | /*
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23 | 7a3f1944 | bellard | TODO-list:
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24 | 7a3f1944 | bellard | |
25 | 3475187d | bellard | Rest of V9 instructions, VIS instructions
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26 | bd497938 | bellard | NPC/PC static optimisations (use JUMP_TB when possible)
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27 | 7a3f1944 | bellard | Optimize synthetic instructions
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28 | bd497938 | bellard | */
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29 | 7a3f1944 | bellard | |
30 | 7a3f1944 | bellard | #include <stdarg.h> |
31 | 7a3f1944 | bellard | #include <stdlib.h> |
32 | 7a3f1944 | bellard | #include <stdio.h> |
33 | 7a3f1944 | bellard | #include <string.h> |
34 | 7a3f1944 | bellard | #include <inttypes.h> |
35 | 7a3f1944 | bellard | |
36 | 7a3f1944 | bellard | #include "cpu.h" |
37 | 7a3f1944 | bellard | #include "exec-all.h" |
38 | 7a3f1944 | bellard | #include "disas.h" |
39 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
40 | 57fec1fe | bellard | #include "tcg-op.h" |
41 | 7a3f1944 | bellard | |
42 | 7a3f1944 | bellard | #define DEBUG_DISAS
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43 | 7a3f1944 | bellard | |
44 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
45 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
46 | 72cbca10 | bellard | according to jump_pc[T2] */
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47 | 72cbca10 | bellard | |
48 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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49 | d9bdab86 | blueswir1 | static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
50 | 48d5c82b | blueswir1 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
51 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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52 | dc99a3f2 | blueswir1 | static TCGv cpu_xcc;
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53 | dc99a3f2 | blueswir1 | #endif
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54 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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55 | 1a2fb1c0 | blueswir1 | static TCGv cpu_tmp0;
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56 | 1a2fb1c0 | blueswir1 | |
57 | 7a3f1944 | bellard | typedef struct DisasContext { |
58 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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59 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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60 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
61 | cf495bcf | bellard | int is_br;
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62 | e8af50a3 | bellard | int mem_idx;
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63 | a80dde08 | bellard | int fpu_enabled;
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64 | cf495bcf | bellard | struct TranslationBlock *tb;
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65 | 7a3f1944 | bellard | } DisasContext; |
66 | 7a3f1944 | bellard | |
67 | aaed909a | bellard | typedef struct sparc_def_t sparc_def_t; |
68 | aaed909a | bellard | |
69 | 62724a37 | blueswir1 | struct sparc_def_t {
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70 | 62724a37 | blueswir1 | const unsigned char *name; |
71 | 62724a37 | blueswir1 | target_ulong iu_version; |
72 | 62724a37 | blueswir1 | uint32_t fpu_version; |
73 | 62724a37 | blueswir1 | uint32_t mmu_version; |
74 | 6d5f237a | blueswir1 | uint32_t mmu_bm; |
75 | 3deaeab7 | blueswir1 | uint32_t mmu_ctpr_mask; |
76 | 3deaeab7 | blueswir1 | uint32_t mmu_cxr_mask; |
77 | 3deaeab7 | blueswir1 | uint32_t mmu_sfsr_mask; |
78 | 3deaeab7 | blueswir1 | uint32_t mmu_trcr_mask; |
79 | 62724a37 | blueswir1 | }; |
80 | 62724a37 | blueswir1 | |
81 | aaed909a | bellard | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
82 | aaed909a | bellard | |
83 | 7a3f1944 | bellard | extern FILE *logfile;
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84 | 7a3f1944 | bellard | extern int loglevel; |
85 | 7a3f1944 | bellard | |
86 | 3475187d | bellard | // This function uses non-native bit order
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87 | 7a3f1944 | bellard | #define GET_FIELD(X, FROM, TO) \
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88 | 7a3f1944 | bellard | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
89 | 7a3f1944 | bellard | |
90 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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91 | 3475187d | bellard | #define GET_FIELD_SP(X, FROM, TO) \
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92 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
93 | 3475187d | bellard | |
94 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
95 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
96 | 3475187d | bellard | |
97 | 3475187d | bellard | #ifdef TARGET_SPARC64
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98 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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99 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
100 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
101 | 3475187d | bellard | #else
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102 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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103 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
104 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
105 | 3475187d | bellard | #endif
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106 | 3475187d | bellard | |
107 | 3475187d | bellard | static int sign_extend(int x, int len) |
108 | 3475187d | bellard | { |
109 | 3475187d | bellard | len = 32 - len;
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110 | 3475187d | bellard | return (x << len) >> len;
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111 | 3475187d | bellard | } |
112 | 3475187d | bellard | |
113 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
114 | 7a3f1944 | bellard | |
115 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc); |
116 | 7a3f1944 | bellard | |
117 | ff07ec83 | blueswir1 | /* floating point registers moves */
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118 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_FT0(unsigned int src) |
119 | ff07ec83 | blueswir1 | { |
120 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
121 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0)); |
122 | 3475187d | bellard | } |
123 | ff07ec83 | blueswir1 | |
124 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_FT1(unsigned int src) |
125 | ff07ec83 | blueswir1 | { |
126 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
127 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1)); |
128 | e8af50a3 | bellard | } |
129 | e8af50a3 | bellard | |
130 | ff07ec83 | blueswir1 | static void gen_op_store_FT0_fpr(unsigned int dst) |
131 | ff07ec83 | blueswir1 | { |
132 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0)); |
133 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
134 | ff07ec83 | blueswir1 | } |
135 | ff07ec83 | blueswir1 | |
136 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
137 | ff07ec83 | blueswir1 | { |
138 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
139 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); |
140 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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141 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); |
142 | ff07ec83 | blueswir1 | } |
143 | ff07ec83 | blueswir1 | |
144 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
145 | ff07ec83 | blueswir1 | { |
146 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
147 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper)); |
148 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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149 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower)); |
150 | ff07ec83 | blueswir1 | } |
151 | ff07ec83 | blueswir1 | |
152 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
153 | ff07ec83 | blueswir1 | { |
154 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); |
155 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
156 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); |
157 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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158 | ff07ec83 | blueswir1 | } |
159 | ff07ec83 | blueswir1 | |
160 | ff07ec83 | blueswir1 | #ifdef CONFIG_USER_ONLY
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161 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
162 | ff07ec83 | blueswir1 | { |
163 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
164 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); |
165 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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166 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); |
167 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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168 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); |
169 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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170 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); |
171 | ff07ec83 | blueswir1 | } |
172 | ff07ec83 | blueswir1 | |
173 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
174 | ff07ec83 | blueswir1 | { |
175 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
176 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost)); |
177 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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178 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper)); |
179 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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180 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower)); |
181 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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182 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest)); |
183 | ff07ec83 | blueswir1 | } |
184 | ff07ec83 | blueswir1 | |
185 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
186 | ff07ec83 | blueswir1 | { |
187 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); |
188 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
189 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); |
190 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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191 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); |
192 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
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193 | ff07ec83 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); |
194 | ff07ec83 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
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195 | ff07ec83 | blueswir1 | } |
196 | 1f587329 | blueswir1 | #endif
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197 | 1f587329 | blueswir1 | |
198 | 81ad8ba2 | blueswir1 | /* moves */
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199 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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200 | 3475187d | bellard | #define supervisor(dc) 0 |
201 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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202 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
203 | 81ad8ba2 | blueswir1 | #endif
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204 | 3475187d | bellard | #define gen_op_ldst(name) gen_op_##name##_raw() |
205 | 3475187d | bellard | #else
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206 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
207 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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208 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
209 | 6f27aba6 | blueswir1 | #define OP_LD_TABLE(width) \
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210 | 6f27aba6 | blueswir1 | static GenOpFunc * const gen_op_##width[] = { \ |
211 | 6f27aba6 | blueswir1 | &gen_op_##width##_user, \ |
212 | 6f27aba6 | blueswir1 | &gen_op_##width##_kernel, \ |
213 | 6f27aba6 | blueswir1 | &gen_op_##width##_hypv, \ |
214 | 6f27aba6 | blueswir1 | }; |
215 | 6f27aba6 | blueswir1 | #else
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216 | 0f8a249a | blueswir1 | #define OP_LD_TABLE(width) \
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217 | a68156d0 | blueswir1 | static GenOpFunc * const gen_op_##width[] = { \ |
218 | 0f8a249a | blueswir1 | &gen_op_##width##_user, \ |
219 | 0f8a249a | blueswir1 | &gen_op_##width##_kernel, \ |
220 | 81ad8ba2 | blueswir1 | }; |
221 | 3475187d | bellard | #endif
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222 | 6f27aba6 | blueswir1 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
223 | 6f27aba6 | blueswir1 | #endif
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224 | e8af50a3 | bellard | |
225 | 81ad8ba2 | blueswir1 | #ifndef CONFIG_USER_ONLY
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226 | b25deda7 | blueswir1 | #ifdef __i386__
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227 | b25deda7 | blueswir1 | OP_LD_TABLE(std); |
228 | b25deda7 | blueswir1 | #endif /* __i386__ */ |
229 | e8af50a3 | bellard | OP_LD_TABLE(stf); |
230 | e8af50a3 | bellard | OP_LD_TABLE(stdf); |
231 | e8af50a3 | bellard | OP_LD_TABLE(ldf); |
232 | e8af50a3 | bellard | OP_LD_TABLE(lddf); |
233 | 81ad8ba2 | blueswir1 | #endif
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234 | 81ad8ba2 | blueswir1 | |
235 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_ABI32
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236 | 1a2fb1c0 | blueswir1 | #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL); |
237 | 1a2fb1c0 | blueswir1 | #else
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238 | 1a2fb1c0 | blueswir1 | #define ABI32_MASK(addr)
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239 | 1a2fb1c0 | blueswir1 | #endif
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240 | 3391c818 | blueswir1 | |
241 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_simm_T1(int32_t val) |
242 | 81ad8ba2 | blueswir1 | { |
243 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[1], val);
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244 | 81ad8ba2 | blueswir1 | } |
245 | 81ad8ba2 | blueswir1 | |
246 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
247 | 81ad8ba2 | blueswir1 | { |
248 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
249 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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250 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
251 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
252 | 1a2fb1c0 | blueswir1 | else {
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253 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
254 | 81ad8ba2 | blueswir1 | } |
255 | 81ad8ba2 | blueswir1 | } |
256 | 81ad8ba2 | blueswir1 | |
257 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_T0(int reg) |
258 | 81ad8ba2 | blueswir1 | { |
259 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(reg, cpu_T[0]);
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260 | 81ad8ba2 | blueswir1 | } |
261 | 81ad8ba2 | blueswir1 | |
262 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_T1(int reg) |
263 | 81ad8ba2 | blueswir1 | { |
264 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(reg, cpu_T[1]);
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265 | 81ad8ba2 | blueswir1 | } |
266 | 81ad8ba2 | blueswir1 | |
267 | b25deda7 | blueswir1 | #ifdef __i386__
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268 | b25deda7 | blueswir1 | static inline void gen_movl_reg_T2(int reg) |
269 | b25deda7 | blueswir1 | { |
270 | b25deda7 | blueswir1 | gen_movl_reg_TN(reg, cpu_T[2]);
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271 | b25deda7 | blueswir1 | } |
272 | b25deda7 | blueswir1 | |
273 | b25deda7 | blueswir1 | #endif /* __i386__ */ |
274 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
275 | 81ad8ba2 | blueswir1 | { |
276 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
277 | 1a2fb1c0 | blueswir1 | return;
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278 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
279 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
280 | 1a2fb1c0 | blueswir1 | else {
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281 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
282 | 81ad8ba2 | blueswir1 | } |
283 | 81ad8ba2 | blueswir1 | } |
284 | 81ad8ba2 | blueswir1 | |
285 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_T0_reg(int reg) |
286 | 3475187d | bellard | { |
287 | 1a2fb1c0 | blueswir1 | gen_movl_TN_reg(reg, cpu_T[0]);
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288 | 3475187d | bellard | } |
289 | 3475187d | bellard | |
290 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_T1_reg(int reg) |
291 | 3475187d | bellard | { |
292 | 1a2fb1c0 | blueswir1 | gen_movl_TN_reg(reg, cpu_T[1]);
|
293 | 3475187d | bellard | } |
294 | 3475187d | bellard | |
295 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movl_T0_env(size_t offset) |
296 | 7a3f1944 | bellard | { |
297 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
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298 | 7a3f1944 | bellard | } |
299 | 7a3f1944 | bellard | |
300 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movl_env_T0(size_t offset) |
301 | 7a3f1944 | bellard | { |
302 | 1a2fb1c0 | blueswir1 | tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
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303 | 7a3f1944 | bellard | } |
304 | 7a3f1944 | bellard | |
305 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movtl_T0_env(size_t offset) |
306 | 7a3f1944 | bellard | { |
307 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
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308 | 7a3f1944 | bellard | } |
309 | 7a3f1944 | bellard | |
310 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movtl_env_T0(size_t offset) |
311 | 7a3f1944 | bellard | { |
312 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
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313 | 7a3f1944 | bellard | } |
314 | 7a3f1944 | bellard | |
315 | 1a2fb1c0 | blueswir1 | static inline void gen_op_add_T1_T0(void) |
316 | 7a3f1944 | bellard | { |
317 | 1a2fb1c0 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
318 | 7a3f1944 | bellard | } |
319 | 7a3f1944 | bellard | |
320 | 1a2fb1c0 | blueswir1 | static inline void gen_op_or_T1_T0(void) |
321 | 7a3f1944 | bellard | { |
322 | 1a2fb1c0 | blueswir1 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
323 | 7a3f1944 | bellard | } |
324 | 7a3f1944 | bellard | |
325 | 1a2fb1c0 | blueswir1 | static inline void gen_op_xor_T1_T0(void) |
326 | 7a3f1944 | bellard | { |
327 | 1a2fb1c0 | blueswir1 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
328 | 7a3f1944 | bellard | } |
329 | 7a3f1944 | bellard | |
330 | 3475187d | bellard | static inline void gen_jmp_im(target_ulong pc) |
331 | 3475187d | bellard | { |
332 | 48d5c82b | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
333 | 3475187d | bellard | } |
334 | 3475187d | bellard | |
335 | 3475187d | bellard | static inline void gen_movl_npc_im(target_ulong npc) |
336 | 3475187d | bellard | { |
337 | 48d5c82b | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
338 | 3475187d | bellard | } |
339 | 3475187d | bellard | |
340 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
341 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
342 | 6e256c93 | bellard | { |
343 | 6e256c93 | bellard | TranslationBlock *tb; |
344 | 6e256c93 | bellard | |
345 | 6e256c93 | bellard | tb = s->tb; |
346 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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347 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
348 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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349 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
350 | 6e256c93 | bellard | gen_jmp_im(pc); |
351 | 6e256c93 | bellard | gen_movl_npc_im(npc); |
352 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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353 | 6e256c93 | bellard | } else {
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354 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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355 | 6e256c93 | bellard | gen_jmp_im(pc); |
356 | 6e256c93 | bellard | gen_movl_npc_im(npc); |
357 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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358 | 6e256c93 | bellard | } |
359 | 6e256c93 | bellard | } |
360 | 6e256c93 | bellard | |
361 | 19f329ad | blueswir1 | // XXX suboptimal
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362 | 19f329ad | blueswir1 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) |
363 | 19f329ad | blueswir1 | { |
364 | 19f329ad | blueswir1 | tcg_gen_shri_i32(reg, src, 23);
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365 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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366 | 19f329ad | blueswir1 | } |
367 | 19f329ad | blueswir1 | |
368 | 19f329ad | blueswir1 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) |
369 | 19f329ad | blueswir1 | { |
370 | 19f329ad | blueswir1 | tcg_gen_shri_i32(reg, src, 22);
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371 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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372 | 19f329ad | blueswir1 | } |
373 | 19f329ad | blueswir1 | |
374 | 19f329ad | blueswir1 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) |
375 | 19f329ad | blueswir1 | { |
376 | 19f329ad | blueswir1 | tcg_gen_shri_i32(reg, src, 21);
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377 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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378 | 19f329ad | blueswir1 | } |
379 | 19f329ad | blueswir1 | |
380 | 19f329ad | blueswir1 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
381 | 19f329ad | blueswir1 | { |
382 | 19f329ad | blueswir1 | tcg_gen_shri_i32(reg, src, 20);
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383 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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384 | 19f329ad | blueswir1 | } |
385 | 19f329ad | blueswir1 | |
386 | dc99a3f2 | blueswir1 | static inline void gen_op_exception(int exception) |
387 | dc99a3f2 | blueswir1 | { |
388 | 0425bee5 | blueswir1 | tcg_gen_movi_i32(cpu_tmp0, exception); |
389 | 0425bee5 | blueswir1 | tcg_gen_helper_0_1(raise_exception, cpu_tmp0); |
390 | dc99a3f2 | blueswir1 | } |
391 | dc99a3f2 | blueswir1 | |
392 | dc99a3f2 | blueswir1 | static inline void gen_cc_clear(void) |
393 | dc99a3f2 | blueswir1 | { |
394 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_psr, 0);
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395 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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396 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_xcc, 0);
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397 | dc99a3f2 | blueswir1 | #endif
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398 | dc99a3f2 | blueswir1 | } |
399 | dc99a3f2 | blueswir1 | |
400 | dc99a3f2 | blueswir1 | /* old op:
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401 | dc99a3f2 | blueswir1 | if (!T0)
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402 | dc99a3f2 | blueswir1 | env->psr |= PSR_ZERO;
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403 | dc99a3f2 | blueswir1 | if ((int32_t) T0 < 0)
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404 | dc99a3f2 | blueswir1 | env->psr |= PSR_NEG;
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405 | dc99a3f2 | blueswir1 | */
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406 | dc99a3f2 | blueswir1 | static inline void gen_cc_NZ(TCGv dst) |
407 | dc99a3f2 | blueswir1 | { |
408 | dc99a3f2 | blueswir1 | int l1, l2;
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409 | dc99a3f2 | blueswir1 | |
410 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
411 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
412 | 0425bee5 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_NE, dst, tcg_const_i32(0), l1);
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413 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
414 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
415 | 0425bee5 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_GE, dst, tcg_const_i32(0), l2);
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416 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
417 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
418 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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419 | dc99a3f2 | blueswir1 | { |
420 | dc99a3f2 | blueswir1 | int l3, l4;
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421 | dc99a3f2 | blueswir1 | |
422 | dc99a3f2 | blueswir1 | l3 = gen_new_label(); |
423 | dc99a3f2 | blueswir1 | l4 = gen_new_label(); |
424 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3);
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425 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
426 | dc99a3f2 | blueswir1 | gen_set_label(l3); |
427 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4);
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428 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
429 | dc99a3f2 | blueswir1 | gen_set_label(l4); |
430 | dc99a3f2 | blueswir1 | } |
431 | dc99a3f2 | blueswir1 | #endif
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432 | dc99a3f2 | blueswir1 | } |
433 | dc99a3f2 | blueswir1 | |
434 | dc99a3f2 | blueswir1 | /* old op:
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435 | dc99a3f2 | blueswir1 | if (T0 < src1)
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436 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
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437 | dc99a3f2 | blueswir1 | */
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438 | dc99a3f2 | blueswir1 | static inline void gen_cc_C_add(TCGv dst, TCGv src1) |
439 | dc99a3f2 | blueswir1 | { |
440 | dc99a3f2 | blueswir1 | int l1;
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441 | dc99a3f2 | blueswir1 | |
442 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
443 | dc99a3f2 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1); |
444 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
445 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
446 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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447 | dc99a3f2 | blueswir1 | { |
448 | dc99a3f2 | blueswir1 | int l2;
|
449 | dc99a3f2 | blueswir1 | |
450 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
451 | dc99a3f2 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2); |
452 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
453 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
454 | dc99a3f2 | blueswir1 | } |
455 | dc99a3f2 | blueswir1 | #endif
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456 | dc99a3f2 | blueswir1 | } |
457 | dc99a3f2 | blueswir1 | |
458 | dc99a3f2 | blueswir1 | /* old op:
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459 | dc99a3f2 | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
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460 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
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461 | dc99a3f2 | blueswir1 | */
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462 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) |
463 | dc99a3f2 | blueswir1 | { |
464 | 0425bee5 | blueswir1 | TCGv r_temp; |
465 | dc99a3f2 | blueswir1 | int l1;
|
466 | dc99a3f2 | blueswir1 | |
467 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
468 | dc99a3f2 | blueswir1 | |
469 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
470 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
471 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
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472 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
473 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
474 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
475 | 0425bee5 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
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476 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
477 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
478 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
479 | dc99a3f2 | blueswir1 | { |
480 | dc99a3f2 | blueswir1 | int l2;
|
481 | dc99a3f2 | blueswir1 | |
482 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
483 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
484 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
485 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
486 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
487 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
488 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
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489 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
490 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
491 | dc99a3f2 | blueswir1 | } |
492 | dc99a3f2 | blueswir1 | #endif
|
493 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
494 | dc99a3f2 | blueswir1 | } |
495 | dc99a3f2 | blueswir1 | |
496 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
497 | dc99a3f2 | blueswir1 | { |
498 | 0425bee5 | blueswir1 | TCGv r_temp; |
499 | dc99a3f2 | blueswir1 | int l1;
|
500 | dc99a3f2 | blueswir1 | |
501 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
502 | dc99a3f2 | blueswir1 | |
503 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
504 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
505 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
506 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
507 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
508 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
509 | 0425bee5 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
|
510 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
511 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
512 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
513 | dc99a3f2 | blueswir1 | { |
514 | dc99a3f2 | blueswir1 | int l2;
|
515 | dc99a3f2 | blueswir1 | |
516 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
517 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
518 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
519 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
520 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
521 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
522 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
523 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
524 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
525 | dc99a3f2 | blueswir1 | } |
526 | dc99a3f2 | blueswir1 | #endif
|
527 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
528 | dc99a3f2 | blueswir1 | } |
529 | dc99a3f2 | blueswir1 | |
530 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
531 | dc99a3f2 | blueswir1 | { |
532 | dc99a3f2 | blueswir1 | int l1;
|
533 | dc99a3f2 | blueswir1 | |
534 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
535 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
536 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
537 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
|
538 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
539 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
540 | dc99a3f2 | blueswir1 | } |
541 | dc99a3f2 | blueswir1 | |
542 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
543 | dc99a3f2 | blueswir1 | { |
544 | dc99a3f2 | blueswir1 | int l1;
|
545 | dc99a3f2 | blueswir1 | |
546 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
547 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
548 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
549 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
|
550 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
551 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
552 | dc99a3f2 | blueswir1 | } |
553 | dc99a3f2 | blueswir1 | |
554 | dc99a3f2 | blueswir1 | static inline void gen_op_add_T1_T0_cc(void) |
555 | dc99a3f2 | blueswir1 | { |
556 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
557 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
558 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
559 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
560 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
561 | dc99a3f2 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
562 | dc99a3f2 | blueswir1 | } |
563 | dc99a3f2 | blueswir1 | |
564 | dc99a3f2 | blueswir1 | static inline void gen_op_addx_T1_T0_cc(void) |
565 | dc99a3f2 | blueswir1 | { |
566 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
567 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
568 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
569 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
570 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
571 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
572 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
573 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
574 | dc99a3f2 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
575 | dc99a3f2 | blueswir1 | } |
576 | dc99a3f2 | blueswir1 | |
577 | dc99a3f2 | blueswir1 | static inline void gen_op_tadd_T1_T0_cc(void) |
578 | dc99a3f2 | blueswir1 | { |
579 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
580 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
581 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
582 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
583 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
584 | dc99a3f2 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
585 | dc99a3f2 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
|
586 | dc99a3f2 | blueswir1 | } |
587 | dc99a3f2 | blueswir1 | |
588 | dc99a3f2 | blueswir1 | static inline void gen_op_tadd_T1_T0_ccTV(void) |
589 | dc99a3f2 | blueswir1 | { |
590 | dc99a3f2 | blueswir1 | gen_tag_tv(cpu_T[0], cpu_T[1]); |
591 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
592 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
593 | dc99a3f2 | blueswir1 | gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
594 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
595 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
596 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
597 | dc99a3f2 | blueswir1 | } |
598 | dc99a3f2 | blueswir1 | |
599 | dc99a3f2 | blueswir1 | /* old op:
|
600 | dc99a3f2 | blueswir1 | if (src1 < T1)
|
601 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
602 | dc99a3f2 | blueswir1 | */
|
603 | dc99a3f2 | blueswir1 | static inline void gen_cc_C_sub(TCGv src1, TCGv src2) |
604 | dc99a3f2 | blueswir1 | { |
605 | dc99a3f2 | blueswir1 | int l1;
|
606 | dc99a3f2 | blueswir1 | |
607 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
608 | dc99a3f2 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1); |
609 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
610 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
611 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
612 | dc99a3f2 | blueswir1 | { |
613 | dc99a3f2 | blueswir1 | int l2;
|
614 | dc99a3f2 | blueswir1 | |
615 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
616 | dc99a3f2 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2); |
617 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
618 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
619 | dc99a3f2 | blueswir1 | } |
620 | dc99a3f2 | blueswir1 | #endif
|
621 | dc99a3f2 | blueswir1 | } |
622 | dc99a3f2 | blueswir1 | |
623 | dc99a3f2 | blueswir1 | /* old op:
|
624 | dc99a3f2 | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
|
625 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
626 | dc99a3f2 | blueswir1 | */
|
627 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) |
628 | dc99a3f2 | blueswir1 | { |
629 | 0425bee5 | blueswir1 | TCGv r_temp; |
630 | dc99a3f2 | blueswir1 | int l1;
|
631 | dc99a3f2 | blueswir1 | |
632 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
633 | dc99a3f2 | blueswir1 | |
634 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
635 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
636 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
637 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
638 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
639 | 0425bee5 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
|
640 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
641 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
642 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
643 | dc99a3f2 | blueswir1 | { |
644 | dc99a3f2 | blueswir1 | int l2;
|
645 | dc99a3f2 | blueswir1 | |
646 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
647 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
648 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
649 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
650 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
651 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
652 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
653 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
654 | dc99a3f2 | blueswir1 | } |
655 | dc99a3f2 | blueswir1 | #endif
|
656 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
657 | dc99a3f2 | blueswir1 | } |
658 | dc99a3f2 | blueswir1 | |
659 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
660 | dc99a3f2 | blueswir1 | { |
661 | 0425bee5 | blueswir1 | TCGv r_temp; |
662 | dc99a3f2 | blueswir1 | int l1;
|
663 | dc99a3f2 | blueswir1 | |
664 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
665 | dc99a3f2 | blueswir1 | |
666 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
667 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
668 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
669 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
670 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
671 | 0425bee5 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
|
672 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
673 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
674 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
675 | dc99a3f2 | blueswir1 | { |
676 | dc99a3f2 | blueswir1 | int l2;
|
677 | dc99a3f2 | blueswir1 | |
678 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
679 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
680 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
681 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
682 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
683 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
684 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
685 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
686 | dc99a3f2 | blueswir1 | } |
687 | dc99a3f2 | blueswir1 | #endif
|
688 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
689 | dc99a3f2 | blueswir1 | } |
690 | dc99a3f2 | blueswir1 | |
691 | dc99a3f2 | blueswir1 | static inline void gen_op_sub_T1_T0_cc(void) |
692 | dc99a3f2 | blueswir1 | { |
693 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
694 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
695 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
696 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
697 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
|
698 | dc99a3f2 | blueswir1 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
699 | dc99a3f2 | blueswir1 | } |
700 | dc99a3f2 | blueswir1 | |
701 | dc99a3f2 | blueswir1 | static inline void gen_op_subx_T1_T0_cc(void) |
702 | dc99a3f2 | blueswir1 | { |
703 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
704 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
705 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
706 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
707 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_T[0], cpu_cc_src);
|
708 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
709 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_T[0], cpu_cc_src);
|
710 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
711 | dc99a3f2 | blueswir1 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
712 | dc99a3f2 | blueswir1 | } |
713 | dc99a3f2 | blueswir1 | |
714 | dc99a3f2 | blueswir1 | static inline void gen_op_tsub_T1_T0_cc(void) |
715 | dc99a3f2 | blueswir1 | { |
716 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
717 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
718 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
719 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
720 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
|
721 | dc99a3f2 | blueswir1 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
722 | dc99a3f2 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
|
723 | dc99a3f2 | blueswir1 | } |
724 | dc99a3f2 | blueswir1 | |
725 | dc99a3f2 | blueswir1 | static inline void gen_op_tsub_T1_T0_ccTV(void) |
726 | dc99a3f2 | blueswir1 | { |
727 | dc99a3f2 | blueswir1 | gen_tag_tv(cpu_T[0], cpu_T[1]); |
728 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
729 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
730 | dc99a3f2 | blueswir1 | gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
731 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
732 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
733 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
|
734 | dc99a3f2 | blueswir1 | } |
735 | dc99a3f2 | blueswir1 | |
736 | d9bdab86 | blueswir1 | static inline void gen_op_mulscc_T1_T0(void) |
737 | d9bdab86 | blueswir1 | { |
738 | d9bdab86 | blueswir1 | TCGv r_temp; |
739 | d9bdab86 | blueswir1 | int l1, l2;
|
740 | d9bdab86 | blueswir1 | |
741 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
742 | d9bdab86 | blueswir1 | l2 = gen_new_label(); |
743 | d9bdab86 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
744 | d9bdab86 | blueswir1 | |
745 | d9bdab86 | blueswir1 | /* old op:
|
746 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
747 | d9bdab86 | blueswir1 | T1 = 0;
|
748 | d9bdab86 | blueswir1 | */
|
749 | d9bdab86 | blueswir1 | tcg_gen_ld_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
750 | d9bdab86 | blueswir1 | tcg_gen_andi_i32(r_temp, r_temp, 0x1);
|
751 | d9bdab86 | blueswir1 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
|
752 | d9bdab86 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
|
753 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
754 | d9bdab86 | blueswir1 | gen_set_label(l1); |
755 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
756 | d9bdab86 | blueswir1 | gen_set_label(l2); |
757 | d9bdab86 | blueswir1 | |
758 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
759 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
760 | d9bdab86 | blueswir1 | tcg_gen_shli_i32(r_temp, cpu_T[0], 31); |
761 | d9bdab86 | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
762 | d9bdab86 | blueswir1 | tcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 1);
|
763 | d9bdab86 | blueswir1 | tcg_gen_or_i32(cpu_tmp0, cpu_tmp0, r_temp); |
764 | d9bdab86 | blueswir1 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
765 | d9bdab86 | blueswir1 | |
766 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
767 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
768 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
769 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
770 | d9bdab86 | blueswir1 | |
771 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
772 | d9bdab86 | blueswir1 | // src1 = T0;
|
773 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
774 | d9bdab86 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1); |
775 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
776 | d9bdab86 | blueswir1 | |
777 | d9bdab86 | blueswir1 | /* do addition and update flags */
|
778 | d9bdab86 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2);
|
779 | d9bdab86 | blueswir1 | tcg_gen_discard_tl(r_temp); |
780 | d9bdab86 | blueswir1 | |
781 | d9bdab86 | blueswir1 | gen_cc_clear(); |
782 | d9bdab86 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
783 | d9bdab86 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2);
|
784 | d9bdab86 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
785 | d9bdab86 | blueswir1 | } |
786 | d9bdab86 | blueswir1 | |
787 | 8879d139 | blueswir1 | static inline void gen_op_umul_T1_T0(void) |
788 | 8879d139 | blueswir1 | { |
789 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
790 | 8879d139 | blueswir1 | |
791 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
792 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
793 | 8879d139 | blueswir1 | |
794 | 8879d139 | blueswir1 | tcg_gen_extu_i32_i64(r_temp, cpu_T[1]);
|
795 | 8879d139 | blueswir1 | tcg_gen_extu_i32_i64(r_temp2, cpu_T[0]);
|
796 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
797 | 8879d139 | blueswir1 | |
798 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
799 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(r_temp, r_temp); |
800 | 8879d139 | blueswir1 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
801 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
802 | 8879d139 | blueswir1 | tcg_gen_mov_i64(cpu_T[0], r_temp2);
|
803 | 8879d139 | blueswir1 | #else
|
804 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2);
|
805 | 8879d139 | blueswir1 | #endif
|
806 | 8879d139 | blueswir1 | |
807 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp); |
808 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp2); |
809 | 8879d139 | blueswir1 | } |
810 | 8879d139 | blueswir1 | |
811 | 8879d139 | blueswir1 | static inline void gen_op_smul_T1_T0(void) |
812 | 8879d139 | blueswir1 | { |
813 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
814 | 8879d139 | blueswir1 | |
815 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
816 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
817 | 8879d139 | blueswir1 | |
818 | 2483386a | blueswir1 | tcg_gen_ext_i32_i64(r_temp, cpu_T[1]);
|
819 | 2483386a | blueswir1 | tcg_gen_ext_i32_i64(r_temp2, cpu_T[0]);
|
820 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
821 | 8879d139 | blueswir1 | |
822 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
823 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(r_temp, r_temp); |
824 | 8879d139 | blueswir1 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
825 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
826 | 8879d139 | blueswir1 | tcg_gen_mov_i64(cpu_T[0], r_temp2);
|
827 | 8879d139 | blueswir1 | #else
|
828 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2);
|
829 | 8879d139 | blueswir1 | #endif
|
830 | 8879d139 | blueswir1 | |
831 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp); |
832 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp2); |
833 | 8879d139 | blueswir1 | } |
834 | 8879d139 | blueswir1 | |
835 | 3b89f26c | blueswir1 | static inline void gen_op_udiv_T1_T0(void) |
836 | 3b89f26c | blueswir1 | { |
837 | 3b89f26c | blueswir1 | tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]); |
838 | 3b89f26c | blueswir1 | } |
839 | 3b89f26c | blueswir1 | |
840 | 3b89f26c | blueswir1 | static inline void gen_op_sdiv_T1_T0(void) |
841 | 3b89f26c | blueswir1 | { |
842 | 3b89f26c | blueswir1 | tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]); |
843 | 3b89f26c | blueswir1 | } |
844 | 3b89f26c | blueswir1 | |
845 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
846 | 1a7b60e7 | blueswir1 | static inline void gen_trap_ifdivzero_i64(TCGv divisor) |
847 | 1a7b60e7 | blueswir1 | { |
848 | 1a7b60e7 | blueswir1 | int l1;
|
849 | 1a7b60e7 | blueswir1 | |
850 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
851 | 1a7b60e7 | blueswir1 | tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
|
852 | 1a7b60e7 | blueswir1 | gen_op_exception(TT_DIV_ZERO); |
853 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
854 | 1a7b60e7 | blueswir1 | } |
855 | 1a7b60e7 | blueswir1 | |
856 | 1a7b60e7 | blueswir1 | static inline void gen_op_sdivx_T1_T0(void) |
857 | 1a7b60e7 | blueswir1 | { |
858 | 1a7b60e7 | blueswir1 | int l1, l2;
|
859 | 1a7b60e7 | blueswir1 | |
860 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
861 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
862 | 1a7b60e7 | blueswir1 | gen_trap_ifdivzero_i64(cpu_T[1]);
|
863 | 1a7b60e7 | blueswir1 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1);
|
864 | 1a7b60e7 | blueswir1 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1); |
865 | 1a7b60e7 | blueswir1 | tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
|
866 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
867 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
868 | 1a7b60e7 | blueswir1 | tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
869 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
870 | 1a7b60e7 | blueswir1 | } |
871 | 1a7b60e7 | blueswir1 | #endif
|
872 | 1a7b60e7 | blueswir1 | |
873 | dc99a3f2 | blueswir1 | static inline void gen_op_div_cc(void) |
874 | dc99a3f2 | blueswir1 | { |
875 | dc99a3f2 | blueswir1 | int l1;
|
876 | dc99a3f2 | blueswir1 | |
877 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
878 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
879 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
880 | 3b89f26c | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
881 | 3b89f26c | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
|
882 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
883 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
884 | dc99a3f2 | blueswir1 | } |
885 | dc99a3f2 | blueswir1 | |
886 | dc99a3f2 | blueswir1 | static inline void gen_op_logic_T0_cc(void) |
887 | dc99a3f2 | blueswir1 | { |
888 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
889 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
890 | dc99a3f2 | blueswir1 | } |
891 | dc99a3f2 | blueswir1 | |
892 | 19f329ad | blueswir1 | // 1
|
893 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
894 | 19f329ad | blueswir1 | { |
895 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
896 | 19f329ad | blueswir1 | } |
897 | 19f329ad | blueswir1 | |
898 | 19f329ad | blueswir1 | // Z
|
899 | 19f329ad | blueswir1 | static inline void gen_op_eval_be(TCGv dst, TCGv src) |
900 | 19f329ad | blueswir1 | { |
901 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
902 | 19f329ad | blueswir1 | } |
903 | 19f329ad | blueswir1 | |
904 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
905 | 19f329ad | blueswir1 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) |
906 | 19f329ad | blueswir1 | { |
907 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
908 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
909 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
910 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
911 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
912 | 19f329ad | blueswir1 | } |
913 | 19f329ad | blueswir1 | |
914 | 19f329ad | blueswir1 | // N ^ V
|
915 | 19f329ad | blueswir1 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) |
916 | 19f329ad | blueswir1 | { |
917 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
918 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
919 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
920 | 19f329ad | blueswir1 | } |
921 | 19f329ad | blueswir1 | |
922 | 19f329ad | blueswir1 | // C | Z
|
923 | 19f329ad | blueswir1 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) |
924 | 19f329ad | blueswir1 | { |
925 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
926 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
927 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
928 | 19f329ad | blueswir1 | } |
929 | 19f329ad | blueswir1 | |
930 | 19f329ad | blueswir1 | // C
|
931 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) |
932 | 19f329ad | blueswir1 | { |
933 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
934 | 19f329ad | blueswir1 | } |
935 | 19f329ad | blueswir1 | |
936 | 19f329ad | blueswir1 | // V
|
937 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) |
938 | 19f329ad | blueswir1 | { |
939 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
940 | 19f329ad | blueswir1 | } |
941 | 19f329ad | blueswir1 | |
942 | 19f329ad | blueswir1 | // 0
|
943 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
944 | 19f329ad | blueswir1 | { |
945 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
946 | 19f329ad | blueswir1 | } |
947 | 19f329ad | blueswir1 | |
948 | 19f329ad | blueswir1 | // N
|
949 | 19f329ad | blueswir1 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) |
950 | 19f329ad | blueswir1 | { |
951 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
952 | 19f329ad | blueswir1 | } |
953 | 19f329ad | blueswir1 | |
954 | 19f329ad | blueswir1 | // !Z
|
955 | 19f329ad | blueswir1 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) |
956 | 19f329ad | blueswir1 | { |
957 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
958 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
959 | 19f329ad | blueswir1 | } |
960 | 19f329ad | blueswir1 | |
961 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
962 | 19f329ad | blueswir1 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) |
963 | 19f329ad | blueswir1 | { |
964 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
965 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
966 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
967 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
968 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
969 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
970 | 19f329ad | blueswir1 | } |
971 | 19f329ad | blueswir1 | |
972 | 19f329ad | blueswir1 | // !(N ^ V)
|
973 | 19f329ad | blueswir1 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) |
974 | 19f329ad | blueswir1 | { |
975 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
976 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
977 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
978 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
979 | 19f329ad | blueswir1 | } |
980 | 19f329ad | blueswir1 | |
981 | 19f329ad | blueswir1 | // !(C | Z)
|
982 | 19f329ad | blueswir1 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) |
983 | 19f329ad | blueswir1 | { |
984 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
985 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
986 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
987 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
988 | 19f329ad | blueswir1 | } |
989 | 19f329ad | blueswir1 | |
990 | 19f329ad | blueswir1 | // !C
|
991 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) |
992 | 19f329ad | blueswir1 | { |
993 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
994 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
995 | 19f329ad | blueswir1 | } |
996 | 19f329ad | blueswir1 | |
997 | 19f329ad | blueswir1 | // !N
|
998 | 19f329ad | blueswir1 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) |
999 | 19f329ad | blueswir1 | { |
1000 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
1001 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1002 | 19f329ad | blueswir1 | } |
1003 | 19f329ad | blueswir1 | |
1004 | 19f329ad | blueswir1 | // !V
|
1005 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) |
1006 | 19f329ad | blueswir1 | { |
1007 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
1008 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1009 | 19f329ad | blueswir1 | } |
1010 | 19f329ad | blueswir1 | |
1011 | 19f329ad | blueswir1 | /*
|
1012 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
1013 | 19f329ad | blueswir1 | 0 =
|
1014 | 19f329ad | blueswir1 | 1 <
|
1015 | 19f329ad | blueswir1 | 2 >
|
1016 | 19f329ad | blueswir1 | 3 unordered
|
1017 | 19f329ad | blueswir1 | */
|
1018 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
1019 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1020 | 19f329ad | blueswir1 | { |
1021 | 19f329ad | blueswir1 | tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
|
1022 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1023 | 19f329ad | blueswir1 | } |
1024 | 19f329ad | blueswir1 | |
1025 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
1026 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1027 | 19f329ad | blueswir1 | { |
1028 | 19f329ad | blueswir1 | tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
|
1029 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1030 | 19f329ad | blueswir1 | } |
1031 | 19f329ad | blueswir1 | |
1032 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
1033 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
1034 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1035 | 19f329ad | blueswir1 | { |
1036 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1037 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1038 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1039 | 19f329ad | blueswir1 | } |
1040 | 19f329ad | blueswir1 | |
1041 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
1042 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
1043 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1044 | 19f329ad | blueswir1 | { |
1045 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1046 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1047 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1048 | 19f329ad | blueswir1 | } |
1049 | 19f329ad | blueswir1 | |
1050 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
1051 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
1052 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1053 | 19f329ad | blueswir1 | { |
1054 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1055 | 19f329ad | blueswir1 | } |
1056 | 19f329ad | blueswir1 | |
1057 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
1058 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
1059 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1060 | 19f329ad | blueswir1 | { |
1061 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1062 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1063 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1064 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1065 | 19f329ad | blueswir1 | } |
1066 | 19f329ad | blueswir1 | |
1067 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
1068 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
1069 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1070 | 19f329ad | blueswir1 | { |
1071 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1072 | 19f329ad | blueswir1 | } |
1073 | 19f329ad | blueswir1 | |
1074 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
1075 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
1076 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1077 | 19f329ad | blueswir1 | { |
1078 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1079 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1080 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1081 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1082 | 19f329ad | blueswir1 | } |
1083 | 19f329ad | blueswir1 | |
1084 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
1085 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
1086 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1087 | 19f329ad | blueswir1 | { |
1088 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1089 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1090 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1091 | 19f329ad | blueswir1 | } |
1092 | 19f329ad | blueswir1 | |
1093 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
1094 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
1095 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1096 | 19f329ad | blueswir1 | { |
1097 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1098 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1099 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1100 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1101 | 19f329ad | blueswir1 | } |
1102 | 19f329ad | blueswir1 | |
1103 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
1104 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
1105 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1106 | 19f329ad | blueswir1 | { |
1107 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1108 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1109 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1110 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1111 | 19f329ad | blueswir1 | } |
1112 | 19f329ad | blueswir1 | |
1113 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
1114 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
1115 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1116 | 19f329ad | blueswir1 | { |
1117 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1118 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1119 | 19f329ad | blueswir1 | } |
1120 | 19f329ad | blueswir1 | |
1121 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
1122 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
1123 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1124 | 19f329ad | blueswir1 | { |
1125 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1126 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1127 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1128 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1129 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1130 | 19f329ad | blueswir1 | } |
1131 | 19f329ad | blueswir1 | |
1132 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
1133 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
1134 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1135 | 19f329ad | blueswir1 | { |
1136 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1137 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1138 | 19f329ad | blueswir1 | } |
1139 | 19f329ad | blueswir1 | |
1140 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
1141 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
1142 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1143 | 19f329ad | blueswir1 | { |
1144 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1145 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1146 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1147 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1148 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1149 | 19f329ad | blueswir1 | } |
1150 | 19f329ad | blueswir1 | |
1151 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
1152 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
1153 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1154 | 19f329ad | blueswir1 | { |
1155 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1156 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1157 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1158 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1159 | 19f329ad | blueswir1 | } |
1160 | 19f329ad | blueswir1 | |
1161 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
1162 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1163 | 83469015 | bellard | { |
1164 | 83469015 | bellard | int l1;
|
1165 | 83469015 | bellard | |
1166 | 83469015 | bellard | l1 = gen_new_label(); |
1167 | 83469015 | bellard | |
1168 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
|
1169 | 83469015 | bellard | |
1170 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
1171 | 83469015 | bellard | |
1172 | 83469015 | bellard | gen_set_label(l1); |
1173 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
1174 | 83469015 | bellard | } |
1175 | 83469015 | bellard | |
1176 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1177 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1178 | 83469015 | bellard | { |
1179 | 83469015 | bellard | int l1;
|
1180 | 83469015 | bellard | |
1181 | 83469015 | bellard | l1 = gen_new_label(); |
1182 | 83469015 | bellard | |
1183 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
|
1184 | 83469015 | bellard | |
1185 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1186 | 83469015 | bellard | |
1187 | 83469015 | bellard | gen_set_label(l1); |
1188 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1189 | 83469015 | bellard | } |
1190 | 83469015 | bellard | |
1191 | 46525e1f | blueswir1 | static inline void gen_branch(DisasContext *dc, target_ulong pc, |
1192 | 46525e1f | blueswir1 | target_ulong npc) |
1193 | 83469015 | bellard | { |
1194 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc, npc);
|
1195 | 83469015 | bellard | } |
1196 | 83469015 | bellard | |
1197 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1198 | 19f329ad | blueswir1 | TCGv r_cond) |
1199 | 83469015 | bellard | { |
1200 | 83469015 | bellard | int l1, l2;
|
1201 | 83469015 | bellard | |
1202 | 83469015 | bellard | l1 = gen_new_label(); |
1203 | 83469015 | bellard | l2 = gen_new_label(); |
1204 | 19f329ad | blueswir1 | |
1205 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
|
1206 | 83469015 | bellard | |
1207 | 83469015 | bellard | gen_movl_npc_im(npc1); |
1208 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
1209 | 83469015 | bellard | |
1210 | 83469015 | bellard | gen_set_label(l1); |
1211 | 83469015 | bellard | gen_movl_npc_im(npc2); |
1212 | 83469015 | bellard | gen_set_label(l2); |
1213 | 83469015 | bellard | } |
1214 | 83469015 | bellard | |
1215 | 83469015 | bellard | /* call this function before using T2 as it may have been set for a jump */
|
1216 | 83469015 | bellard | static inline void flush_T2(DisasContext * dc) |
1217 | 83469015 | bellard | { |
1218 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1219 | 19f329ad | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
1220 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1221 | 83469015 | bellard | } |
1222 | 83469015 | bellard | } |
1223 | 83469015 | bellard | |
1224 | 72cbca10 | bellard | static inline void save_npc(DisasContext * dc) |
1225 | 72cbca10 | bellard | { |
1226 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1227 | 19f329ad | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
1228 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1229 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1230 | 3475187d | bellard | gen_movl_npc_im(dc->npc); |
1231 | 72cbca10 | bellard | } |
1232 | 72cbca10 | bellard | } |
1233 | 72cbca10 | bellard | |
1234 | 72cbca10 | bellard | static inline void save_state(DisasContext * dc) |
1235 | 72cbca10 | bellard | { |
1236 | 3475187d | bellard | gen_jmp_im(dc->pc); |
1237 | 72cbca10 | bellard | save_npc(dc); |
1238 | 72cbca10 | bellard | } |
1239 | 72cbca10 | bellard | |
1240 | 0bee699e | bellard | static inline void gen_mov_pc_npc(DisasContext * dc) |
1241 | 0bee699e | bellard | { |
1242 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1243 | 19f329ad | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
1244 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1245 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1246 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1247 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1248 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1249 | 0bee699e | bellard | } else {
|
1250 | 0bee699e | bellard | dc->pc = dc->npc; |
1251 | 0bee699e | bellard | } |
1252 | 0bee699e | bellard | } |
1253 | 0bee699e | bellard | |
1254 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1255 | 38bc628b | blueswir1 | { |
1256 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1257 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1258 | 38bc628b | blueswir1 | } |
1259 | 38bc628b | blueswir1 | |
1260 | 19f329ad | blueswir1 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1261 | 19f329ad | blueswir1 | { |
1262 | 19f329ad | blueswir1 | TCGv r_src; |
1263 | 3475187d | bellard | |
1264 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1265 | 19f329ad | blueswir1 | if (cc)
|
1266 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1267 | 19f329ad | blueswir1 | else
|
1268 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1269 | 3475187d | bellard | #else
|
1270 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1271 | 3475187d | bellard | #endif
|
1272 | 19f329ad | blueswir1 | switch (cond) {
|
1273 | 19f329ad | blueswir1 | case 0x0: |
1274 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1275 | 19f329ad | blueswir1 | break;
|
1276 | 19f329ad | blueswir1 | case 0x1: |
1277 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
1278 | 19f329ad | blueswir1 | break;
|
1279 | 19f329ad | blueswir1 | case 0x2: |
1280 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
1281 | 19f329ad | blueswir1 | break;
|
1282 | 19f329ad | blueswir1 | case 0x3: |
1283 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
1284 | 19f329ad | blueswir1 | break;
|
1285 | 19f329ad | blueswir1 | case 0x4: |
1286 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
1287 | 19f329ad | blueswir1 | break;
|
1288 | 19f329ad | blueswir1 | case 0x5: |
1289 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
1290 | 19f329ad | blueswir1 | break;
|
1291 | 19f329ad | blueswir1 | case 0x6: |
1292 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
1293 | 19f329ad | blueswir1 | break;
|
1294 | 19f329ad | blueswir1 | case 0x7: |
1295 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
1296 | 19f329ad | blueswir1 | break;
|
1297 | 19f329ad | blueswir1 | case 0x8: |
1298 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1299 | 19f329ad | blueswir1 | break;
|
1300 | 19f329ad | blueswir1 | case 0x9: |
1301 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
1302 | 19f329ad | blueswir1 | break;
|
1303 | 19f329ad | blueswir1 | case 0xa: |
1304 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1305 | 19f329ad | blueswir1 | break;
|
1306 | 19f329ad | blueswir1 | case 0xb: |
1307 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1308 | 19f329ad | blueswir1 | break;
|
1309 | 19f329ad | blueswir1 | case 0xc: |
1310 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1311 | 19f329ad | blueswir1 | break;
|
1312 | 19f329ad | blueswir1 | case 0xd: |
1313 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1314 | 19f329ad | blueswir1 | break;
|
1315 | 19f329ad | blueswir1 | case 0xe: |
1316 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1317 | 19f329ad | blueswir1 | break;
|
1318 | 19f329ad | blueswir1 | case 0xf: |
1319 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1320 | 19f329ad | blueswir1 | break;
|
1321 | 19f329ad | blueswir1 | } |
1322 | 19f329ad | blueswir1 | } |
1323 | 7a3f1944 | bellard | |
1324 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1325 | e8af50a3 | bellard | { |
1326 | 19f329ad | blueswir1 | unsigned int offset; |
1327 | 19f329ad | blueswir1 | |
1328 | 19f329ad | blueswir1 | switch (cc) {
|
1329 | 19f329ad | blueswir1 | default:
|
1330 | 19f329ad | blueswir1 | case 0x0: |
1331 | 19f329ad | blueswir1 | offset = 0;
|
1332 | 19f329ad | blueswir1 | break;
|
1333 | 19f329ad | blueswir1 | case 0x1: |
1334 | 19f329ad | blueswir1 | offset = 32 - 10; |
1335 | 19f329ad | blueswir1 | break;
|
1336 | 19f329ad | blueswir1 | case 0x2: |
1337 | 19f329ad | blueswir1 | offset = 34 - 10; |
1338 | 19f329ad | blueswir1 | break;
|
1339 | 19f329ad | blueswir1 | case 0x3: |
1340 | 19f329ad | blueswir1 | offset = 36 - 10; |
1341 | 19f329ad | blueswir1 | break;
|
1342 | 19f329ad | blueswir1 | } |
1343 | 19f329ad | blueswir1 | |
1344 | 19f329ad | blueswir1 | switch (cond) {
|
1345 | 19f329ad | blueswir1 | case 0x0: |
1346 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1347 | 19f329ad | blueswir1 | break;
|
1348 | 19f329ad | blueswir1 | case 0x1: |
1349 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1350 | 19f329ad | blueswir1 | break;
|
1351 | 19f329ad | blueswir1 | case 0x2: |
1352 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1353 | 19f329ad | blueswir1 | break;
|
1354 | 19f329ad | blueswir1 | case 0x3: |
1355 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1356 | 19f329ad | blueswir1 | break;
|
1357 | 19f329ad | blueswir1 | case 0x4: |
1358 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1359 | 19f329ad | blueswir1 | break;
|
1360 | 19f329ad | blueswir1 | case 0x5: |
1361 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1362 | 19f329ad | blueswir1 | break;
|
1363 | 19f329ad | blueswir1 | case 0x6: |
1364 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1365 | 19f329ad | blueswir1 | break;
|
1366 | 19f329ad | blueswir1 | case 0x7: |
1367 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1368 | 19f329ad | blueswir1 | break;
|
1369 | 19f329ad | blueswir1 | case 0x8: |
1370 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1371 | 19f329ad | blueswir1 | break;
|
1372 | 19f329ad | blueswir1 | case 0x9: |
1373 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1374 | 19f329ad | blueswir1 | break;
|
1375 | 19f329ad | blueswir1 | case 0xa: |
1376 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1377 | 19f329ad | blueswir1 | break;
|
1378 | 19f329ad | blueswir1 | case 0xb: |
1379 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1380 | 19f329ad | blueswir1 | break;
|
1381 | 19f329ad | blueswir1 | case 0xc: |
1382 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1383 | 19f329ad | blueswir1 | break;
|
1384 | 19f329ad | blueswir1 | case 0xd: |
1385 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1386 | 19f329ad | blueswir1 | break;
|
1387 | 19f329ad | blueswir1 | case 0xe: |
1388 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1389 | 19f329ad | blueswir1 | break;
|
1390 | 19f329ad | blueswir1 | case 0xf: |
1391 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1392 | 19f329ad | blueswir1 | break;
|
1393 | 19f329ad | blueswir1 | } |
1394 | e8af50a3 | bellard | } |
1395 | 00f219bf | blueswir1 | |
1396 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1397 | 00f219bf | blueswir1 | // Inverted logic
|
1398 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1399 | 00f219bf | blueswir1 | -1,
|
1400 | 00f219bf | blueswir1 | TCG_COND_NE, |
1401 | 00f219bf | blueswir1 | TCG_COND_GT, |
1402 | 00f219bf | blueswir1 | TCG_COND_GE, |
1403 | 00f219bf | blueswir1 | -1,
|
1404 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1405 | 00f219bf | blueswir1 | TCG_COND_LE, |
1406 | 00f219bf | blueswir1 | TCG_COND_LT, |
1407 | 00f219bf | blueswir1 | }; |
1408 | 19f329ad | blueswir1 | |
1409 | 19f329ad | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond) |
1410 | 19f329ad | blueswir1 | { |
1411 | 19f329ad | blueswir1 | int l1;
|
1412 | 19f329ad | blueswir1 | |
1413 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1414 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1415 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1); |
1416 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1417 | 19f329ad | blueswir1 | gen_set_label(l1); |
1418 | 19f329ad | blueswir1 | } |
1419 | 3475187d | bellard | #endif
|
1420 | cf495bcf | bellard | |
1421 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1422 | 3475187d | bellard | static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
1423 | 7a3f1944 | bellard | { |
1424 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1425 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1426 | 5fafdf24 | ths | |
1427 | cf495bcf | bellard | if (cond == 0x0) { |
1428 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1429 | 0f8a249a | blueswir1 | if (a) {
|
1430 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1431 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1432 | 0f8a249a | blueswir1 | } else {
|
1433 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1434 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1435 | 0f8a249a | blueswir1 | } |
1436 | cf495bcf | bellard | } else if (cond == 0x8) { |
1437 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1438 | 0f8a249a | blueswir1 | if (a) {
|
1439 | 0f8a249a | blueswir1 | dc->pc = target; |
1440 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1441 | 0f8a249a | blueswir1 | } else {
|
1442 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1443 | 0f8a249a | blueswir1 | dc->npc = target; |
1444 | 0f8a249a | blueswir1 | } |
1445 | cf495bcf | bellard | } else {
|
1446 | 72cbca10 | bellard | flush_T2(dc); |
1447 | 19f329ad | blueswir1 | gen_cond(cpu_T[2], cc, cond);
|
1448 | 0f8a249a | blueswir1 | if (a) {
|
1449 | 19f329ad | blueswir1 | gen_branch_a(dc, target, dc->npc, cpu_T[2]);
|
1450 | cf495bcf | bellard | dc->is_br = 1;
|
1451 | 0f8a249a | blueswir1 | } else {
|
1452 | cf495bcf | bellard | dc->pc = dc->npc; |
1453 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1454 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1455 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1456 | 0f8a249a | blueswir1 | } |
1457 | cf495bcf | bellard | } |
1458 | 7a3f1944 | bellard | } |
1459 | 7a3f1944 | bellard | |
1460 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1461 | 3475187d | bellard | static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
1462 | e8af50a3 | bellard | { |
1463 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1464 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1465 | af7bf89b | bellard | |
1466 | e8af50a3 | bellard | if (cond == 0x0) { |
1467 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1468 | 0f8a249a | blueswir1 | if (a) {
|
1469 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1470 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1471 | 0f8a249a | blueswir1 | } else {
|
1472 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1473 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1474 | 0f8a249a | blueswir1 | } |
1475 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1476 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1477 | 0f8a249a | blueswir1 | if (a) {
|
1478 | 0f8a249a | blueswir1 | dc->pc = target; |
1479 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1480 | 0f8a249a | blueswir1 | } else {
|
1481 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1482 | 0f8a249a | blueswir1 | dc->npc = target; |
1483 | 0f8a249a | blueswir1 | } |
1484 | e8af50a3 | bellard | } else {
|
1485 | e8af50a3 | bellard | flush_T2(dc); |
1486 | 19f329ad | blueswir1 | gen_fcond(cpu_T[2], cc, cond);
|
1487 | 0f8a249a | blueswir1 | if (a) {
|
1488 | 19f329ad | blueswir1 | gen_branch_a(dc, target, dc->npc, cpu_T[2]);
|
1489 | e8af50a3 | bellard | dc->is_br = 1;
|
1490 | 0f8a249a | blueswir1 | } else {
|
1491 | e8af50a3 | bellard | dc->pc = dc->npc; |
1492 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1493 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1494 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1495 | 0f8a249a | blueswir1 | } |
1496 | e8af50a3 | bellard | } |
1497 | e8af50a3 | bellard | } |
1498 | e8af50a3 | bellard | |
1499 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1500 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1501 | 3475187d | bellard | static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) |
1502 | 7a3f1944 | bellard | { |
1503 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1504 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1505 | 3475187d | bellard | |
1506 | 3475187d | bellard | flush_T2(dc); |
1507 | 19f329ad | blueswir1 | gen_cond_reg(cpu_T[2], cond);
|
1508 | 3475187d | bellard | if (a) {
|
1509 | 19f329ad | blueswir1 | gen_branch_a(dc, target, dc->npc, cpu_T[2]);
|
1510 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1511 | 3475187d | bellard | } else {
|
1512 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1513 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1514 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1515 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1516 | 3475187d | bellard | } |
1517 | 7a3f1944 | bellard | } |
1518 | 7a3f1944 | bellard | |
1519 | 3475187d | bellard | static GenOpFunc * const gen_fcmps[4] = { |
1520 | 7e8c2b6c | blueswir1 | helper_fcmps, |
1521 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc1, |
1522 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc2, |
1523 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc3, |
1524 | 3475187d | bellard | }; |
1525 | 3475187d | bellard | |
1526 | 3475187d | bellard | static GenOpFunc * const gen_fcmpd[4] = { |
1527 | 7e8c2b6c | blueswir1 | helper_fcmpd, |
1528 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc1, |
1529 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc2, |
1530 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc3, |
1531 | 3475187d | bellard | }; |
1532 | 417454b0 | blueswir1 | |
1533 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1534 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpq[4] = { |
1535 | 7e8c2b6c | blueswir1 | helper_fcmpq, |
1536 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc1, |
1537 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc2, |
1538 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc3, |
1539 | 1f587329 | blueswir1 | }; |
1540 | 1f587329 | blueswir1 | #endif
|
1541 | 1f587329 | blueswir1 | |
1542 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmpes[4] = { |
1543 | 7e8c2b6c | blueswir1 | helper_fcmpes, |
1544 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc1, |
1545 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc2, |
1546 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc3, |
1547 | 417454b0 | blueswir1 | }; |
1548 | 417454b0 | blueswir1 | |
1549 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmped[4] = { |
1550 | 7e8c2b6c | blueswir1 | helper_fcmped, |
1551 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc1, |
1552 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc2, |
1553 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc3, |
1554 | 417454b0 | blueswir1 | }; |
1555 | 417454b0 | blueswir1 | |
1556 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1557 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpeq[4] = { |
1558 | 7e8c2b6c | blueswir1 | helper_fcmpeq, |
1559 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc1, |
1560 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc2, |
1561 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc3, |
1562 | 1f587329 | blueswir1 | }; |
1563 | 1f587329 | blueswir1 | #endif
|
1564 | 7e8c2b6c | blueswir1 | |
1565 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmps(int fccno) |
1566 | 7e8c2b6c | blueswir1 | { |
1567 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmps[fccno]); |
1568 | 7e8c2b6c | blueswir1 | } |
1569 | 7e8c2b6c | blueswir1 | |
1570 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1571 | 7e8c2b6c | blueswir1 | { |
1572 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); |
1573 | 7e8c2b6c | blueswir1 | } |
1574 | 7e8c2b6c | blueswir1 | |
1575 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1576 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1577 | 7e8c2b6c | blueswir1 | { |
1578 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); |
1579 | 7e8c2b6c | blueswir1 | } |
1580 | 7e8c2b6c | blueswir1 | #endif
|
1581 | 7e8c2b6c | blueswir1 | |
1582 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpes(int fccno) |
1583 | 7e8c2b6c | blueswir1 | { |
1584 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); |
1585 | 7e8c2b6c | blueswir1 | } |
1586 | 7e8c2b6c | blueswir1 | |
1587 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1588 | 7e8c2b6c | blueswir1 | { |
1589 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmped[fccno]); |
1590 | 7e8c2b6c | blueswir1 | } |
1591 | 7e8c2b6c | blueswir1 | |
1592 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1593 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1594 | 7e8c2b6c | blueswir1 | { |
1595 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); |
1596 | 7e8c2b6c | blueswir1 | } |
1597 | 7e8c2b6c | blueswir1 | #endif
|
1598 | 7e8c2b6c | blueswir1 | |
1599 | 7e8c2b6c | blueswir1 | #else
|
1600 | 7e8c2b6c | blueswir1 | |
1601 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmps(int fccno) |
1602 | 7e8c2b6c | blueswir1 | { |
1603 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmps); |
1604 | 7e8c2b6c | blueswir1 | } |
1605 | 7e8c2b6c | blueswir1 | |
1606 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1607 | 7e8c2b6c | blueswir1 | { |
1608 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpd); |
1609 | 7e8c2b6c | blueswir1 | } |
1610 | 7e8c2b6c | blueswir1 | |
1611 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1612 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1613 | 7e8c2b6c | blueswir1 | { |
1614 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpq); |
1615 | 7e8c2b6c | blueswir1 | } |
1616 | 7e8c2b6c | blueswir1 | #endif
|
1617 | 7e8c2b6c | blueswir1 | |
1618 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpes(int fccno) |
1619 | 7e8c2b6c | blueswir1 | { |
1620 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpes); |
1621 | 7e8c2b6c | blueswir1 | } |
1622 | 7e8c2b6c | blueswir1 | |
1623 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1624 | 7e8c2b6c | blueswir1 | { |
1625 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmped); |
1626 | 7e8c2b6c | blueswir1 | } |
1627 | 7e8c2b6c | blueswir1 | |
1628 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1629 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1630 | 7e8c2b6c | blueswir1 | { |
1631 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq); |
1632 | 7e8c2b6c | blueswir1 | } |
1633 | 7e8c2b6c | blueswir1 | #endif
|
1634 | 7e8c2b6c | blueswir1 | |
1635 | 3475187d | bellard | #endif
|
1636 | 3475187d | bellard | |
1637 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1638 | 134d77a1 | blueswir1 | { |
1639 | 87e92502 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
1640 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1641 | 134d77a1 | blueswir1 | gen_op_exception(TT_FP_EXCP); |
1642 | 134d77a1 | blueswir1 | } |
1643 | 134d77a1 | blueswir1 | |
1644 | a80dde08 | bellard | static int gen_trap_ifnofpu(DisasContext * dc) |
1645 | a80dde08 | bellard | { |
1646 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1647 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1648 | a80dde08 | bellard | save_state(dc); |
1649 | a80dde08 | bellard | gen_op_exception(TT_NFPU_INSN); |
1650 | a80dde08 | bellard | dc->is_br = 1;
|
1651 | a80dde08 | bellard | return 1; |
1652 | a80dde08 | bellard | } |
1653 | a80dde08 | bellard | #endif
|
1654 | a80dde08 | bellard | return 0; |
1655 | a80dde08 | bellard | } |
1656 | a80dde08 | bellard | |
1657 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1658 | 7e8c2b6c | blueswir1 | { |
1659 | 87e92502 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
1660 | 7e8c2b6c | blueswir1 | } |
1661 | 7e8c2b6c | blueswir1 | |
1662 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1663 | 7e8c2b6c | blueswir1 | { |
1664 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_clear_float_exceptions); |
1665 | 7e8c2b6c | blueswir1 | } |
1666 | 7e8c2b6c | blueswir1 | |
1667 | 2b29924f | blueswir1 | static inline void gen_check_align(TCGv r_addr, int align) |
1668 | 2b29924f | blueswir1 | { |
1669 | 2b29924f | blueswir1 | tcg_gen_helper_0_2(helper_check_align, r_addr, tcg_const_i32(align)); |
1670 | 2b29924f | blueswir1 | } |
1671 | 2b29924f | blueswir1 | |
1672 | 2b29924f | blueswir1 | static inline void gen_op_check_align_T0_1(void) |
1673 | 2b29924f | blueswir1 | { |
1674 | 2b29924f | blueswir1 | gen_check_align(cpu_T[0], 1); |
1675 | 2b29924f | blueswir1 | } |
1676 | 2b29924f | blueswir1 | |
1677 | 2b29924f | blueswir1 | static inline void gen_op_check_align_T0_3(void) |
1678 | 2b29924f | blueswir1 | { |
1679 | 2b29924f | blueswir1 | gen_check_align(cpu_T[0], 3); |
1680 | 2b29924f | blueswir1 | } |
1681 | 2b29924f | blueswir1 | |
1682 | 2b29924f | blueswir1 | static inline void gen_op_check_align_T0_7(void) |
1683 | 2b29924f | blueswir1 | { |
1684 | 2b29924f | blueswir1 | gen_check_align(cpu_T[0], 7); |
1685 | 2b29924f | blueswir1 | } |
1686 | 2b29924f | blueswir1 | |
1687 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1688 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1689 | 0425bee5 | blueswir1 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1690 | 1a2fb1c0 | blueswir1 | { |
1691 | 1a2fb1c0 | blueswir1 | int asi, offset;
|
1692 | 0425bee5 | blueswir1 | TCGv r_asi; |
1693 | 1a2fb1c0 | blueswir1 | |
1694 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1695 | 0425bee5 | blueswir1 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1696 | 1a2fb1c0 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
1697 | 0425bee5 | blueswir1 | tcg_gen_addi_tl(r_addr, r_addr, offset); |
1698 | 0425bee5 | blueswir1 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); |
1699 | 1a2fb1c0 | blueswir1 | } else {
|
1700 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1701 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1702 | 1a2fb1c0 | blueswir1 | } |
1703 | 0425bee5 | blueswir1 | return r_asi;
|
1704 | 0425bee5 | blueswir1 | } |
1705 | 0425bee5 | blueswir1 | |
1706 | 0425bee5 | blueswir1 | static inline void gen_ld_asi(int insn, int size, int sign) |
1707 | 0425bee5 | blueswir1 | { |
1708 | 0425bee5 | blueswir1 | TCGv r_asi; |
1709 | 0425bee5 | blueswir1 | |
1710 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1711 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi, |
1712 | 0425bee5 | blueswir1 | tcg_const_i32(size), tcg_const_i32(sign)); |
1713 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1714 | 1a2fb1c0 | blueswir1 | } |
1715 | 1a2fb1c0 | blueswir1 | |
1716 | 1a2fb1c0 | blueswir1 | static inline void gen_st_asi(int insn, int size) |
1717 | 1a2fb1c0 | blueswir1 | { |
1718 | 0425bee5 | blueswir1 | TCGv r_asi; |
1719 | 1a2fb1c0 | blueswir1 | |
1720 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1721 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, |
1722 | 0425bee5 | blueswir1 | tcg_const_i32(size)); |
1723 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1724 | 1a2fb1c0 | blueswir1 | } |
1725 | 1a2fb1c0 | blueswir1 | |
1726 | 1a2fb1c0 | blueswir1 | static inline void gen_ldf_asi(int insn, int size, int rd) |
1727 | 1a2fb1c0 | blueswir1 | { |
1728 | 0425bee5 | blueswir1 | TCGv r_asi; |
1729 | 1a2fb1c0 | blueswir1 | |
1730 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1731 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
|
1732 | 0425bee5 | blueswir1 | tcg_const_i32(rd)); |
1733 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1734 | 1a2fb1c0 | blueswir1 | } |
1735 | 1a2fb1c0 | blueswir1 | |
1736 | 1a2fb1c0 | blueswir1 | static inline void gen_stf_asi(int insn, int size, int rd) |
1737 | 1a2fb1c0 | blueswir1 | { |
1738 | 0425bee5 | blueswir1 | TCGv r_asi; |
1739 | 1a2fb1c0 | blueswir1 | |
1740 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1741 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
|
1742 | 0425bee5 | blueswir1 | tcg_const_i32(rd)); |
1743 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1744 | 1a2fb1c0 | blueswir1 | } |
1745 | 1a2fb1c0 | blueswir1 | |
1746 | 1a2fb1c0 | blueswir1 | static inline void gen_swap_asi(int insn) |
1747 | 1a2fb1c0 | blueswir1 | { |
1748 | 0425bee5 | blueswir1 | TCGv r_temp, r_asi; |
1749 | 1a2fb1c0 | blueswir1 | |
1750 | 1a2fb1c0 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1751 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1752 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi,
|
1753 | 0425bee5 | blueswir1 | tcg_const_i32(4), tcg_const_i32(0)); |
1754 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
|
1755 | 0425bee5 | blueswir1 | tcg_const_i32(4));
|
1756 | 1a2fb1c0 | blueswir1 | tcg_gen_mov_i32(cpu_T[1], r_temp);
|
1757 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1758 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_temp); |
1759 | 1a2fb1c0 | blueswir1 | } |
1760 | 1a2fb1c0 | blueswir1 | |
1761 | 1a2fb1c0 | blueswir1 | static inline void gen_ldda_asi(int insn) |
1762 | 1a2fb1c0 | blueswir1 | { |
1763 | 0425bee5 | blueswir1 | TCGv r_dword, r_asi; |
1764 | 1a2fb1c0 | blueswir1 | |
1765 | 1a2fb1c0 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1766 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1767 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], r_asi,
|
1768 | 0425bee5 | blueswir1 | tcg_const_i32(8), tcg_const_i32(0)); |
1769 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
|
1770 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(r_dword, r_dword, 32);
|
1771 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
|
1772 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1773 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
1774 | 0425bee5 | blueswir1 | } |
1775 | 0425bee5 | blueswir1 | |
1776 | 0425bee5 | blueswir1 | static inline void gen_stda_asi(int insn, int rd) |
1777 | 0425bee5 | blueswir1 | { |
1778 | 0425bee5 | blueswir1 | TCGv r_dword, r_temp, r_asi; |
1779 | 0425bee5 | blueswir1 | |
1780 | 0425bee5 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1781 | 0425bee5 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1782 | 0425bee5 | blueswir1 | gen_movl_reg_TN(rd + 1, r_temp);
|
1783 | 0425bee5 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
|
1784 | 0425bee5 | blueswir1 | r_temp); |
1785 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1786 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi,
|
1787 | 0425bee5 | blueswir1 | tcg_const_i32(8));
|
1788 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1789 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_temp); |
1790 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
1791 | 1a2fb1c0 | blueswir1 | } |
1792 | 1a2fb1c0 | blueswir1 | |
1793 | 1a2fb1c0 | blueswir1 | static inline void gen_cas_asi(int insn, int rd) |
1794 | 1a2fb1c0 | blueswir1 | { |
1795 | 1a2fb1c0 | blueswir1 | TCGv r_val1, r_asi; |
1796 | 1a2fb1c0 | blueswir1 | |
1797 | 1a2fb1c0 | blueswir1 | r_val1 = tcg_temp_new(TCG_TYPE_I32); |
1798 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1799 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1800 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], |
1801 | 1a2fb1c0 | blueswir1 | r_asi); |
1802 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1803 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_val1); |
1804 | 1a2fb1c0 | blueswir1 | } |
1805 | 1a2fb1c0 | blueswir1 | |
1806 | 1a2fb1c0 | blueswir1 | static inline void gen_casx_asi(int insn, int rd) |
1807 | 1a2fb1c0 | blueswir1 | { |
1808 | 1a2fb1c0 | blueswir1 | TCGv r_val1, r_asi; |
1809 | 1a2fb1c0 | blueswir1 | |
1810 | 1a2fb1c0 | blueswir1 | r_val1 = tcg_temp_new(TCG_TYPE_I64); |
1811 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1812 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1813 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], |
1814 | 1a2fb1c0 | blueswir1 | r_asi); |
1815 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1816 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_val1); |
1817 | 1a2fb1c0 | blueswir1 | } |
1818 | 1a2fb1c0 | blueswir1 | |
1819 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1820 | 1a2fb1c0 | blueswir1 | |
1821 | 1a2fb1c0 | blueswir1 | static inline void gen_ld_asi(int insn, int size, int sign) |
1822 | 1a2fb1c0 | blueswir1 | { |
1823 | 1a2fb1c0 | blueswir1 | int asi;
|
1824 | 0425bee5 | blueswir1 | TCGv r_dword; |
1825 | 1a2fb1c0 | blueswir1 | |
1826 | 1a2fb1c0 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1827 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1828 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
|
1829 | 0425bee5 | blueswir1 | tcg_const_i32(size), tcg_const_i32(sign)); |
1830 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
|
1831 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
1832 | 1a2fb1c0 | blueswir1 | } |
1833 | 1a2fb1c0 | blueswir1 | |
1834 | 1a2fb1c0 | blueswir1 | static inline void gen_st_asi(int insn, int size) |
1835 | 1a2fb1c0 | blueswir1 | { |
1836 | 1a2fb1c0 | blueswir1 | int asi;
|
1837 | 0425bee5 | blueswir1 | TCGv r_dword; |
1838 | 1a2fb1c0 | blueswir1 | |
1839 | 1a2fb1c0 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1840 | 1a2fb1c0 | blueswir1 | tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
|
1841 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1842 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
|
1843 | 0425bee5 | blueswir1 | tcg_const_i32(size)); |
1844 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
1845 | 1a2fb1c0 | blueswir1 | } |
1846 | 1a2fb1c0 | blueswir1 | |
1847 | 1a2fb1c0 | blueswir1 | static inline void gen_swap_asi(int insn) |
1848 | 1a2fb1c0 | blueswir1 | { |
1849 | 1a2fb1c0 | blueswir1 | int asi;
|
1850 | 0425bee5 | blueswir1 | TCGv r_temp; |
1851 | 1a2fb1c0 | blueswir1 | |
1852 | 1a2fb1c0 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1853 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1854 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi),
|
1855 | 0425bee5 | blueswir1 | tcg_const_i32(4), tcg_const_i32(0)); |
1856 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi), |
1857 | 0425bee5 | blueswir1 | tcg_const_i32(4));
|
1858 | 1a2fb1c0 | blueswir1 | tcg_gen_mov_i32(cpu_T[1], r_temp);
|
1859 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_temp); |
1860 | 1a2fb1c0 | blueswir1 | } |
1861 | 1a2fb1c0 | blueswir1 | |
1862 | 1a2fb1c0 | blueswir1 | static inline void gen_ldda_asi(int insn) |
1863 | 1a2fb1c0 | blueswir1 | { |
1864 | 1a2fb1c0 | blueswir1 | int asi;
|
1865 | 0425bee5 | blueswir1 | TCGv r_dword; |
1866 | 1a2fb1c0 | blueswir1 | |
1867 | 1a2fb1c0 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1868 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1869 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
|
1870 | 0425bee5 | blueswir1 | tcg_const_i32(8), tcg_const_i32(0)); |
1871 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
|
1872 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(r_dword, r_dword, 32);
|
1873 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
|
1874 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
1875 | 0425bee5 | blueswir1 | } |
1876 | 0425bee5 | blueswir1 | |
1877 | 0425bee5 | blueswir1 | static inline void gen_stda_asi(int insn, int rd) |
1878 | 0425bee5 | blueswir1 | { |
1879 | 0425bee5 | blueswir1 | int asi;
|
1880 | 0425bee5 | blueswir1 | TCGv r_dword, r_temp; |
1881 | 0425bee5 | blueswir1 | |
1882 | 0425bee5 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1883 | 0425bee5 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1884 | 0425bee5 | blueswir1 | gen_movl_reg_TN(rd + 1, r_temp);
|
1885 | 0425bee5 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], r_temp);
|
1886 | 0425bee5 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1887 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
|
1888 | 0425bee5 | blueswir1 | tcg_const_i32(8));
|
1889 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
1890 | 1a2fb1c0 | blueswir1 | } |
1891 | 1a2fb1c0 | blueswir1 | #endif
|
1892 | 1a2fb1c0 | blueswir1 | |
1893 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1894 | 1a2fb1c0 | blueswir1 | static inline void gen_ldstub_asi(int insn) |
1895 | 1a2fb1c0 | blueswir1 | { |
1896 | 1a2fb1c0 | blueswir1 | int asi;
|
1897 | 1a2fb1c0 | blueswir1 | |
1898 | 1a2fb1c0 | blueswir1 | gen_ld_asi(insn, 1, 0); |
1899 | 1a2fb1c0 | blueswir1 | |
1900 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1901 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xff), |
1902 | 0425bee5 | blueswir1 | tcg_const_i32(asi), tcg_const_i32(1));
|
1903 | 1a2fb1c0 | blueswir1 | } |
1904 | 1a2fb1c0 | blueswir1 | #endif
|
1905 | 1a2fb1c0 | blueswir1 | |
1906 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1907 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1908 | cf495bcf | bellard | { |
1909 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1910 | 7a3f1944 | bellard | |
1911 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1912 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1913 | 7a3f1944 | bellard | |
1914 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1915 | cf495bcf | bellard | switch (opc) {
|
1916 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1917 | 0f8a249a | blueswir1 | { |
1918 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1919 | 0f8a249a | blueswir1 | int32_t target; |
1920 | 0f8a249a | blueswir1 | switch (xop) {
|
1921 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1922 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1923 | 0f8a249a | blueswir1 | { |
1924 | 0f8a249a | blueswir1 | int cc;
|
1925 | 0f8a249a | blueswir1 | |
1926 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1927 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1928 | 0f8a249a | blueswir1 | target <<= 2;
|
1929 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1930 | 0f8a249a | blueswir1 | if (cc == 0) |
1931 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 0);
|
1932 | 0f8a249a | blueswir1 | else if (cc == 2) |
1933 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 1);
|
1934 | 0f8a249a | blueswir1 | else
|
1935 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1936 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1937 | 0f8a249a | blueswir1 | } |
1938 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1939 | 0f8a249a | blueswir1 | { |
1940 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1941 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1942 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1943 | 0f8a249a | blueswir1 | target <<= 2;
|
1944 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1945 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
1946 | 0f8a249a | blueswir1 | do_branch_reg(dc, target, insn); |
1947 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1948 | 0f8a249a | blueswir1 | } |
1949 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1950 | 0f8a249a | blueswir1 | { |
1951 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1952 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1953 | a80dde08 | bellard | goto jmp_insn;
|
1954 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1955 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1956 | 0f8a249a | blueswir1 | target <<= 2;
|
1957 | 0f8a249a | blueswir1 | do_fbranch(dc, target, insn, cc); |
1958 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1959 | 0f8a249a | blueswir1 | } |
1960 | a4d17f19 | blueswir1 | #else
|
1961 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1962 | 0f8a249a | blueswir1 | { |
1963 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1964 | 0f8a249a | blueswir1 | } |
1965 | 0f8a249a | blueswir1 | #endif
|
1966 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1967 | 0f8a249a | blueswir1 | { |
1968 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1969 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1970 | 0f8a249a | blueswir1 | target <<= 2;
|
1971 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 0);
|
1972 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1973 | 0f8a249a | blueswir1 | } |
1974 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1975 | 0f8a249a | blueswir1 | { |
1976 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1977 | a80dde08 | bellard | goto jmp_insn;
|
1978 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1979 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1980 | 0f8a249a | blueswir1 | target <<= 2;
|
1981 | 0f8a249a | blueswir1 | do_fbranch(dc, target, insn, 0);
|
1982 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1983 | 0f8a249a | blueswir1 | } |
1984 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1985 | e80cfcfc | bellard | #define OPTIM
|
1986 | e80cfcfc | bellard | #if defined(OPTIM)
|
1987 | 0f8a249a | blueswir1 | if (rd) { // nop |
1988 | e80cfcfc | bellard | #endif
|
1989 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1990 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[0], value << 10); |
1991 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
1992 | e80cfcfc | bellard | #if defined(OPTIM)
|
1993 | 0f8a249a | blueswir1 | } |
1994 | e80cfcfc | bellard | #endif
|
1995 | 0f8a249a | blueswir1 | break;
|
1996 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1997 | 0f8a249a | blueswir1 | default:
|
1998 | 3475187d | bellard | goto illegal_insn;
|
1999 | 0f8a249a | blueswir1 | } |
2000 | 0f8a249a | blueswir1 | break;
|
2001 | 0f8a249a | blueswir1 | } |
2002 | 0f8a249a | blueswir1 | break;
|
2003 | cf495bcf | bellard | case 1: |
2004 | 0f8a249a | blueswir1 | /*CALL*/ {
|
2005 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
2006 | cf495bcf | bellard | |
2007 | 48d5c82b | blueswir1 | gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
|
2008 | 0f8a249a | blueswir1 | target += dc->pc; |
2009 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
2010 | 0f8a249a | blueswir1 | dc->npc = target; |
2011 | 0f8a249a | blueswir1 | } |
2012 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2013 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
2014 | 0f8a249a | blueswir1 | { |
2015 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
2016 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
2017 | cf495bcf | bellard | int cond;
|
2018 | 3475187d | bellard | |
2019 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2020 | cf495bcf | bellard | gen_movl_reg_T0(rs1); |
2021 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
2022 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
2023 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2); |
2024 | cf495bcf | bellard | } else {
|
2025 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2026 | e80cfcfc | bellard | #if defined(OPTIM)
|
2027 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2028 | e80cfcfc | bellard | #endif
|
2029 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2030 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
2031 | e80cfcfc | bellard | #if defined(OPTIM)
|
2032 | 0f8a249a | blueswir1 | } |
2033 | e80cfcfc | bellard | #endif
|
2034 | cf495bcf | bellard | } |
2035 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
2036 | cf495bcf | bellard | if (cond == 0x8) { |
2037 | a80dde08 | bellard | save_state(dc); |
2038 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
|
2039 | af7bf89b | bellard | } else if (cond != 0) { |
2040 | 748b9d8e | blueswir1 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
2041 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2042 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2043 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2044 | 748b9d8e | blueswir1 | |
2045 | a80dde08 | bellard | save_state(dc); |
2046 | 0f8a249a | blueswir1 | if (cc == 0) |
2047 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2048 | 0f8a249a | blueswir1 | else if (cc == 2) |
2049 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
2050 | 0f8a249a | blueswir1 | else
|
2051 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2052 | 3475187d | bellard | #else
|
2053 | a80dde08 | bellard | save_state(dc); |
2054 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2055 | 3475187d | bellard | #endif
|
2056 | 748b9d8e | blueswir1 | tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
|
2057 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); |
2058 | cf495bcf | bellard | } |
2059 | a80dde08 | bellard | gen_op_next_insn(); |
2060 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2061 | a80dde08 | bellard | dc->is_br = 1;
|
2062 | a80dde08 | bellard | goto jmp_insn;
|
2063 | cf495bcf | bellard | } else if (xop == 0x28) { |
2064 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2065 | cf495bcf | bellard | switch(rs1) {
|
2066 | cf495bcf | bellard | case 0: /* rdy */ |
2067 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2068 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2069 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2070 | 65fe7b09 | blueswir1 | II */
|
2071 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2072 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2073 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2074 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2075 | 65fe7b09 | blueswir1 | microSPARC II */
|
2076 | 65fe7b09 | blueswir1 | #endif
|
2077 | 65fe7b09 | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); |
2078 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
2079 | cf495bcf | bellard | break;
|
2080 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2081 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2082 | d35527d9 | blueswir1 | tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
|
2083 | 3475187d | bellard | gen_movl_T0_reg(rd); |
2084 | 3475187d | bellard | break;
|
2085 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2086 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); |
2087 | 3475187d | bellard | gen_movl_T0_reg(rd); |
2088 | 3475187d | bellard | break;
|
2089 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2090 | ccd4a219 | blueswir1 | { |
2091 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2092 | ccd4a219 | blueswir1 | |
2093 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2094 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2095 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2096 | ccd4a219 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
|
2097 | ccd4a219 | blueswir1 | r_tickptr); |
2098 | ccd4a219 | blueswir1 | gen_movl_T0_reg(rd); |
2099 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
2100 | ccd4a219 | blueswir1 | } |
2101 | 3475187d | bellard | break;
|
2102 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2103 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
2104 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2105 | 0f8a249a | blueswir1 | break;
|
2106 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2107 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); |
2108 | 3475187d | bellard | gen_movl_T0_reg(rd); |
2109 | 3475187d | bellard | break;
|
2110 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2111 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2112 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2113 | 725cb90b | bellard | if (gen_trap_ifnofpu(dc))
|
2114 | 725cb90b | bellard | goto jmp_insn;
|
2115 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); |
2116 | 725cb90b | bellard | gen_movl_T0_reg(rd); |
2117 | 725cb90b | bellard | break;
|
2118 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2119 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); |
2120 | 83469015 | bellard | gen_movl_T0_reg(rd); |
2121 | 83469015 | bellard | break;
|
2122 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2123 | ccd4a219 | blueswir1 | { |
2124 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2125 | ccd4a219 | blueswir1 | |
2126 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2127 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2128 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
2129 | ccd4a219 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
|
2130 | ccd4a219 | blueswir1 | r_tickptr); |
2131 | ccd4a219 | blueswir1 | gen_movl_T0_reg(rd); |
2132 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
2133 | ccd4a219 | blueswir1 | } |
2134 | 83469015 | bellard | break;
|
2135 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2136 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); |
2137 | 83469015 | bellard | gen_movl_T0_reg(rd); |
2138 | 83469015 | bellard | break;
|
2139 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2140 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2141 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2142 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2143 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2144 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
2145 | 3475187d | bellard | #endif
|
2146 | 3475187d | bellard | default:
|
2147 | cf495bcf | bellard | goto illegal_insn;
|
2148 | cf495bcf | bellard | } |
2149 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2150 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2151 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2152 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2153 | 0f8a249a | blueswir1 | goto priv_insn;
|
2154 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
|
2155 | e9ebed4d | blueswir1 | #else
|
2156 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2157 | e9ebed4d | blueswir1 | goto priv_insn;
|
2158 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2159 | e9ebed4d | blueswir1 | switch (rs1) {
|
2160 | e9ebed4d | blueswir1 | case 0: // hpstate |
2161 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2162 | e9ebed4d | blueswir1 | break;
|
2163 | e9ebed4d | blueswir1 | case 1: // htstate |
2164 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2165 | e9ebed4d | blueswir1 | break;
|
2166 | e9ebed4d | blueswir1 | case 3: // hintp |
2167 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); |
2168 | e9ebed4d | blueswir1 | break;
|
2169 | e9ebed4d | blueswir1 | case 5: // htba |
2170 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); |
2171 | e9ebed4d | blueswir1 | break;
|
2172 | e9ebed4d | blueswir1 | case 6: // hver |
2173 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); |
2174 | e9ebed4d | blueswir1 | break;
|
2175 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2176 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
2177 | e9ebed4d | blueswir1 | break;
|
2178 | e9ebed4d | blueswir1 | default:
|
2179 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2180 | e9ebed4d | blueswir1 | } |
2181 | e9ebed4d | blueswir1 | #endif
|
2182 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
2183 | e8af50a3 | bellard | break;
|
2184 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2185 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2186 | 0f8a249a | blueswir1 | goto priv_insn;
|
2187 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2188 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2189 | 0f8a249a | blueswir1 | switch (rs1) {
|
2190 | 0f8a249a | blueswir1 | case 0: // tpc |
2191 | 375ee38b | blueswir1 | { |
2192 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2193 | 375ee38b | blueswir1 | |
2194 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2195 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2196 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2197 | 375ee38b | blueswir1 | tcg_gen_ld_tl(cpu_T[0], r_tsptr,
|
2198 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2199 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2200 | 375ee38b | blueswir1 | } |
2201 | 0f8a249a | blueswir1 | break;
|
2202 | 0f8a249a | blueswir1 | case 1: // tnpc |
2203 | 375ee38b | blueswir1 | { |
2204 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2205 | 375ee38b | blueswir1 | |
2206 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2207 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2208 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2209 | 375ee38b | blueswir1 | tcg_gen_ld_tl(cpu_T[0], r_tsptr,
|
2210 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2211 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2212 | 375ee38b | blueswir1 | } |
2213 | 0f8a249a | blueswir1 | break;
|
2214 | 0f8a249a | blueswir1 | case 2: // tstate |
2215 | 375ee38b | blueswir1 | { |
2216 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2217 | 375ee38b | blueswir1 | |
2218 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2219 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2220 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2221 | 375ee38b | blueswir1 | tcg_gen_ld_tl(cpu_T[0], r_tsptr,
|
2222 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2223 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2224 | 375ee38b | blueswir1 | } |
2225 | 0f8a249a | blueswir1 | break;
|
2226 | 0f8a249a | blueswir1 | case 3: // tt |
2227 | 375ee38b | blueswir1 | { |
2228 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2229 | 375ee38b | blueswir1 | |
2230 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2231 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2232 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2233 | 375ee38b | blueswir1 | tcg_gen_ld_i32(cpu_T[0], r_tsptr,
|
2234 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2235 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2236 | 375ee38b | blueswir1 | } |
2237 | 0f8a249a | blueswir1 | break;
|
2238 | 0f8a249a | blueswir1 | case 4: // tick |
2239 | ccd4a219 | blueswir1 | { |
2240 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2241 | ccd4a219 | blueswir1 | |
2242 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2243 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2244 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2245 | ccd4a219 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
|
2246 | ccd4a219 | blueswir1 | r_tickptr); |
2247 | ccd4a219 | blueswir1 | gen_movl_T0_reg(rd); |
2248 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
2249 | ccd4a219 | blueswir1 | } |
2250 | 0f8a249a | blueswir1 | break;
|
2251 | 0f8a249a | blueswir1 | case 5: // tba |
2252 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
2253 | 0f8a249a | blueswir1 | break;
|
2254 | 0f8a249a | blueswir1 | case 6: // pstate |
2255 | 1a2fb1c0 | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate)); |
2256 | 0f8a249a | blueswir1 | break;
|
2257 | 0f8a249a | blueswir1 | case 7: // tl |
2258 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); |
2259 | 0f8a249a | blueswir1 | break;
|
2260 | 0f8a249a | blueswir1 | case 8: // pil |
2261 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); |
2262 | 0f8a249a | blueswir1 | break;
|
2263 | 0f8a249a | blueswir1 | case 9: // cwp |
2264 | d35527d9 | blueswir1 | tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
|
2265 | 0f8a249a | blueswir1 | break;
|
2266 | 0f8a249a | blueswir1 | case 10: // cansave |
2267 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); |
2268 | 0f8a249a | blueswir1 | break;
|
2269 | 0f8a249a | blueswir1 | case 11: // canrestore |
2270 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); |
2271 | 0f8a249a | blueswir1 | break;
|
2272 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2273 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); |
2274 | 0f8a249a | blueswir1 | break;
|
2275 | 0f8a249a | blueswir1 | case 13: // otherwin |
2276 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); |
2277 | 0f8a249a | blueswir1 | break;
|
2278 | 0f8a249a | blueswir1 | case 14: // wstate |
2279 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); |
2280 | 0f8a249a | blueswir1 | break;
|
2281 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2282 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); |
2283 | e9ebed4d | blueswir1 | break;
|
2284 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2285 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2286 | e9ebed4d | blueswir1 | goto priv_insn;
|
2287 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); |
2288 | e9ebed4d | blueswir1 | break;
|
2289 | 0f8a249a | blueswir1 | case 31: // ver |
2290 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); |
2291 | 0f8a249a | blueswir1 | break;
|
2292 | 0f8a249a | blueswir1 | case 15: // fq |
2293 | 0f8a249a | blueswir1 | default:
|
2294 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2295 | 0f8a249a | blueswir1 | } |
2296 | 3475187d | bellard | #else
|
2297 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); |
2298 | 3475187d | bellard | #endif
|
2299 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
2300 | e8af50a3 | bellard | break;
|
2301 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2302 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2303 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_flushw); |
2304 | 3475187d | bellard | #else
|
2305 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2306 | 0f8a249a | blueswir1 | goto priv_insn;
|
2307 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
2308 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
2309 | 3475187d | bellard | #endif
|
2310 | e8af50a3 | bellard | break;
|
2311 | e8af50a3 | bellard | #endif
|
2312 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2313 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
2314 | a80dde08 | bellard | goto jmp_insn;
|
2315 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2316 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2317 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2318 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2319 | 0f8a249a | blueswir1 | switch (xop) {
|
2320 | 0f8a249a | blueswir1 | case 0x1: /* fmovs */ |
2321 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2322 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2323 | 0f8a249a | blueswir1 | break;
|
2324 | 0f8a249a | blueswir1 | case 0x5: /* fnegs */ |
2325 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2326 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegs); |
2327 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2328 | 0f8a249a | blueswir1 | break;
|
2329 | 0f8a249a | blueswir1 | case 0x9: /* fabss */ |
2330 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2331 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabss); |
2332 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2333 | 0f8a249a | blueswir1 | break;
|
2334 | 0f8a249a | blueswir1 | case 0x29: /* fsqrts */ |
2335 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2336 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2337 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrts); |
2338 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2339 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2340 | 0f8a249a | blueswir1 | break;
|
2341 | 0f8a249a | blueswir1 | case 0x2a: /* fsqrtd */ |
2342 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2343 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2344 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtd); |
2345 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2346 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2347 | 0f8a249a | blueswir1 | break;
|
2348 | 0f8a249a | blueswir1 | case 0x2b: /* fsqrtq */ |
2349 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2350 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2351 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2352 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtq); |
2353 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2354 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2355 | 1f587329 | blueswir1 | break;
|
2356 | 1f587329 | blueswir1 | #else
|
2357 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2358 | 1f587329 | blueswir1 | #endif
|
2359 | 0f8a249a | blueswir1 | case 0x41: |
2360 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2361 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2362 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2363 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fadds); |
2364 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2365 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2366 | 0f8a249a | blueswir1 | break;
|
2367 | 0f8a249a | blueswir1 | case 0x42: |
2368 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2369 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2370 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2371 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddd); |
2372 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2373 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2374 | 0f8a249a | blueswir1 | break;
|
2375 | 0f8a249a | blueswir1 | case 0x43: /* faddq */ |
2376 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2377 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2378 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2379 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2380 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddq); |
2381 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2383 | 1f587329 | blueswir1 | break;
|
2384 | 1f587329 | blueswir1 | #else
|
2385 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2386 | 1f587329 | blueswir1 | #endif
|
2387 | 0f8a249a | blueswir1 | case 0x45: |
2388 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2389 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2390 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2391 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubs); |
2392 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2393 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2394 | 0f8a249a | blueswir1 | break;
|
2395 | 0f8a249a | blueswir1 | case 0x46: |
2396 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2397 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2398 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2399 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubd); |
2400 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2401 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2402 | 0f8a249a | blueswir1 | break;
|
2403 | 0f8a249a | blueswir1 | case 0x47: /* fsubq */ |
2404 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2405 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2406 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2407 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2408 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubq); |
2409 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2410 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2411 | 1f587329 | blueswir1 | break;
|
2412 | 1f587329 | blueswir1 | #else
|
2413 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2414 | 1f587329 | blueswir1 | #endif
|
2415 | 0f8a249a | blueswir1 | case 0x49: |
2416 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2417 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2418 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2419 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuls); |
2420 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2421 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2422 | 0f8a249a | blueswir1 | break;
|
2423 | 0f8a249a | blueswir1 | case 0x4a: |
2424 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2425 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2426 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2427 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld); |
2428 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2429 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2430 | 0f8a249a | blueswir1 | break;
|
2431 | 0f8a249a | blueswir1 | case 0x4b: /* fmulq */ |
2432 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2433 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2434 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2435 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2436 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmulq); |
2437 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2438 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2439 | 1f587329 | blueswir1 | break;
|
2440 | 1f587329 | blueswir1 | #else
|
2441 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2442 | 1f587329 | blueswir1 | #endif
|
2443 | 0f8a249a | blueswir1 | case 0x4d: |
2444 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2445 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2446 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2447 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivs); |
2448 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2449 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2450 | 0f8a249a | blueswir1 | break;
|
2451 | 0f8a249a | blueswir1 | case 0x4e: |
2452 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2453 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2454 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2455 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivd); |
2456 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2457 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2458 | 0f8a249a | blueswir1 | break;
|
2459 | 0f8a249a | blueswir1 | case 0x4f: /* fdivq */ |
2460 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2461 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2462 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2463 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2464 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivq); |
2465 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2466 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2467 | 1f587329 | blueswir1 | break;
|
2468 | 1f587329 | blueswir1 | #else
|
2469 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2470 | 1f587329 | blueswir1 | #endif
|
2471 | 0f8a249a | blueswir1 | case 0x69: |
2472 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2473 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2474 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2475 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsmuld); |
2476 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2477 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2478 | 0f8a249a | blueswir1 | break;
|
2479 | 0f8a249a | blueswir1 | case 0x6e: /* fdmulq */ |
2480 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2481 | 1f587329 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2482 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2483 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2484 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdmulq); |
2485 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2486 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2487 | 1f587329 | blueswir1 | break;
|
2488 | 1f587329 | blueswir1 | #else
|
2489 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2490 | 1f587329 | blueswir1 | #endif
|
2491 | 0f8a249a | blueswir1 | case 0xc4: |
2492 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2493 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2494 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitos); |
2495 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2496 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2497 | 0f8a249a | blueswir1 | break;
|
2498 | 0f8a249a | blueswir1 | case 0xc6: |
2499 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2500 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2501 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtos); |
2502 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2503 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2504 | 0f8a249a | blueswir1 | break;
|
2505 | 0f8a249a | blueswir1 | case 0xc7: /* fqtos */ |
2506 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2507 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2508 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2509 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtos); |
2510 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2511 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
2512 | 1f587329 | blueswir1 | break;
|
2513 | 1f587329 | blueswir1 | #else
|
2514 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2515 | 1f587329 | blueswir1 | #endif
|
2516 | 0f8a249a | blueswir1 | case 0xc8: |
2517 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2518 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitod); |
2519 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2520 | 0f8a249a | blueswir1 | break;
|
2521 | 0f8a249a | blueswir1 | case 0xc9: |
2522 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2523 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstod); |
2524 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2525 | 0f8a249a | blueswir1 | break;
|
2526 | 0f8a249a | blueswir1 | case 0xcb: /* fqtod */ |
2527 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2528 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2529 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2530 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtod); |
2531 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2532 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2533 | 1f587329 | blueswir1 | break;
|
2534 | 1f587329 | blueswir1 | #else
|
2535 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2536 | 1f587329 | blueswir1 | #endif
|
2537 | 0f8a249a | blueswir1 | case 0xcc: /* fitoq */ |
2538 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2539 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2540 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitoq); |
2541 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2542 | 1f587329 | blueswir1 | break;
|
2543 | 1f587329 | blueswir1 | #else
|
2544 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2545 | 1f587329 | blueswir1 | #endif
|
2546 | 0f8a249a | blueswir1 | case 0xcd: /* fstoq */ |
2547 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2548 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2549 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstoq); |
2550 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2551 | 1f587329 | blueswir1 | break;
|
2552 | 1f587329 | blueswir1 | #else
|
2553 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2554 | 1f587329 | blueswir1 | #endif
|
2555 | 0f8a249a | blueswir1 | case 0xce: /* fdtoq */ |
2556 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2557 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2558 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoq); |
2559 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2560 | 1f587329 | blueswir1 | break;
|
2561 | 1f587329 | blueswir1 | #else
|
2562 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2563 | 1f587329 | blueswir1 | #endif
|
2564 | 0f8a249a | blueswir1 | case 0xd1: |
2565 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2566 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2567 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstoi); |
2568 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2569 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2570 | 0f8a249a | blueswir1 | break;
|
2571 | 0f8a249a | blueswir1 | case 0xd2: |
2572 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2573 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2574 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoi); |
2575 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2576 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2577 | 0f8a249a | blueswir1 | break;
|
2578 | 0f8a249a | blueswir1 | case 0xd3: /* fqtoi */ |
2579 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2580 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2581 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2582 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtoi); |
2583 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2584 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
2585 | 1f587329 | blueswir1 | break;
|
2586 | 1f587329 | blueswir1 | #else
|
2587 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2588 | 1f587329 | blueswir1 | #endif
|
2589 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2590 | 0f8a249a | blueswir1 | case 0x2: /* V9 fmovd */ |
2591 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2592 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2593 | 0f8a249a | blueswir1 | break;
|
2594 | 1f587329 | blueswir1 | case 0x3: /* V9 fmovq */ |
2595 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2596 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2597 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2598 | 1f587329 | blueswir1 | break;
|
2599 | 1f587329 | blueswir1 | #else
|
2600 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2601 | 1f587329 | blueswir1 | #endif
|
2602 | 0f8a249a | blueswir1 | case 0x6: /* V9 fnegd */ |
2603 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2604 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegd); |
2605 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2606 | 0f8a249a | blueswir1 | break;
|
2607 | 1f587329 | blueswir1 | case 0x7: /* V9 fnegq */ |
2608 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2609 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2610 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegq); |
2611 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2612 | 1f587329 | blueswir1 | break;
|
2613 | 1f587329 | blueswir1 | #else
|
2614 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2615 | 1f587329 | blueswir1 | #endif
|
2616 | 0f8a249a | blueswir1 | case 0xa: /* V9 fabsd */ |
2617 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2618 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsd); |
2619 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2620 | 0f8a249a | blueswir1 | break;
|
2621 | 1f587329 | blueswir1 | case 0xb: /* V9 fabsq */ |
2622 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2623 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2624 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsq); |
2625 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2626 | 1f587329 | blueswir1 | break;
|
2627 | 1f587329 | blueswir1 | #else
|
2628 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2629 | 1f587329 | blueswir1 | #endif
|
2630 | 0f8a249a | blueswir1 | case 0x81: /* V9 fstox */ |
2631 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2632 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2633 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstox); |
2634 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2635 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2636 | 0f8a249a | blueswir1 | break;
|
2637 | 0f8a249a | blueswir1 | case 0x82: /* V9 fdtox */ |
2638 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2639 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2640 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtox); |
2641 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2642 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2643 | 0f8a249a | blueswir1 | break;
|
2644 | 1f587329 | blueswir1 | case 0x83: /* V9 fqtox */ |
2645 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2646 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2647 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2648 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtox); |
2649 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2650 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2651 | 1f587329 | blueswir1 | break;
|
2652 | 1f587329 | blueswir1 | #else
|
2653 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2654 | 1f587329 | blueswir1 | #endif
|
2655 | 0f8a249a | blueswir1 | case 0x84: /* V9 fxtos */ |
2656 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2657 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2658 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtos); |
2659 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2660 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2661 | 0f8a249a | blueswir1 | break;
|
2662 | 0f8a249a | blueswir1 | case 0x88: /* V9 fxtod */ |
2663 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2664 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2665 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtod); |
2666 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2667 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2668 | 0f8a249a | blueswir1 | break;
|
2669 | 0f8a249a | blueswir1 | case 0x8c: /* V9 fxtoq */ |
2670 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2671 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2672 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2673 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtoq); |
2674 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2675 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2676 | 1f587329 | blueswir1 | break;
|
2677 | 1f587329 | blueswir1 | #else
|
2678 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2679 | 0f8a249a | blueswir1 | #endif
|
2680 | 1f587329 | blueswir1 | #endif
|
2681 | 0f8a249a | blueswir1 | default:
|
2682 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2683 | 0f8a249a | blueswir1 | } |
2684 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2685 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2686 | 0f8a249a | blueswir1 | int cond;
|
2687 | 3475187d | bellard | #endif
|
2688 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
2689 | a80dde08 | bellard | goto jmp_insn;
|
2690 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2691 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2692 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2693 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2694 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2695 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2696 | dcf24905 | blueswir1 | int l1;
|
2697 | dcf24905 | blueswir1 | |
2698 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2699 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2700 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2701 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2702 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
2703 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
2704 | 19f329ad | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2705 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2706 | dcf24905 | blueswir1 | gen_set_label(l1); |
2707 | 0f8a249a | blueswir1 | break;
|
2708 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2709 | dcf24905 | blueswir1 | int l1;
|
2710 | dcf24905 | blueswir1 | |
2711 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2712 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2713 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2714 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2715 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
2716 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
2717 | 19f329ad | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2718 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2719 | dcf24905 | blueswir1 | gen_set_label(l1); |
2720 | 0f8a249a | blueswir1 | break;
|
2721 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2722 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2723 | dcf24905 | blueswir1 | int l1;
|
2724 | dcf24905 | blueswir1 | |
2725 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2726 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2727 | 1f587329 | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2728 | 1f587329 | blueswir1 | gen_movl_reg_T0(rs1); |
2729 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
2730 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
2731 | 19f329ad | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2732 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2733 | dcf24905 | blueswir1 | gen_set_label(l1); |
2734 | 1f587329 | blueswir1 | break;
|
2735 | 1f587329 | blueswir1 | #else
|
2736 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2737 | 1f587329 | blueswir1 | #endif
|
2738 | 0f8a249a | blueswir1 | } |
2739 | 0f8a249a | blueswir1 | #endif
|
2740 | 0f8a249a | blueswir1 | switch (xop) {
|
2741 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2742 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, fcc) \
|
2743 | 19f329ad | blueswir1 | { \ |
2744 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2745 | 19f329ad | blueswir1 | int l1; \
|
2746 | 19f329ad | blueswir1 | \ |
2747 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2748 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2749 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2750 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2751 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ |
2752 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1); \
|
2753 | 19f329ad | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ |
2754 | 19f329ad | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ |
2755 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2756 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); \ |
2757 | 19f329ad | blueswir1 | } |
2758 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2759 | 19f329ad | blueswir1 | FMOVCC(F, 0);
|
2760 | 0f8a249a | blueswir1 | break;
|
2761 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2762 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2763 | 0f8a249a | blueswir1 | break;
|
2764 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2765 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2766 | 19f329ad | blueswir1 | FMOVCC(Q, 0);
|
2767 | 1f587329 | blueswir1 | break;
|
2768 | 1f587329 | blueswir1 | #else
|
2769 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2770 | 1f587329 | blueswir1 | #endif
|
2771 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2772 | 19f329ad | blueswir1 | FMOVCC(F, 1);
|
2773 | 0f8a249a | blueswir1 | break;
|
2774 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2775 | 19f329ad | blueswir1 | FMOVCC(D, 1);
|
2776 | 0f8a249a | blueswir1 | break;
|
2777 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2778 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2779 | 19f329ad | blueswir1 | FMOVCC(Q, 1);
|
2780 | 1f587329 | blueswir1 | break;
|
2781 | 1f587329 | blueswir1 | #else
|
2782 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2783 | 1f587329 | blueswir1 | #endif
|
2784 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2785 | 19f329ad | blueswir1 | FMOVCC(F, 2);
|
2786 | 0f8a249a | blueswir1 | break;
|
2787 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2788 | 19f329ad | blueswir1 | FMOVCC(D, 2);
|
2789 | 0f8a249a | blueswir1 | break;
|
2790 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2791 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2792 | 19f329ad | blueswir1 | FMOVCC(Q, 2);
|
2793 | 1f587329 | blueswir1 | break;
|
2794 | 1f587329 | blueswir1 | #else
|
2795 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2796 | 1f587329 | blueswir1 | #endif
|
2797 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2798 | 19f329ad | blueswir1 | FMOVCC(F, 3);
|
2799 | 0f8a249a | blueswir1 | break;
|
2800 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2801 | 19f329ad | blueswir1 | FMOVCC(D, 3);
|
2802 | 0f8a249a | blueswir1 | break;
|
2803 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2804 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2805 | 19f329ad | blueswir1 | FMOVCC(Q, 3);
|
2806 | 1f587329 | blueswir1 | break;
|
2807 | 1f587329 | blueswir1 | #else
|
2808 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2809 | 1f587329 | blueswir1 | #endif
|
2810 | 19f329ad | blueswir1 | #undef FMOVCC
|
2811 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, icc) \
|
2812 | 19f329ad | blueswir1 | { \ |
2813 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2814 | 19f329ad | blueswir1 | int l1; \
|
2815 | 19f329ad | blueswir1 | \ |
2816 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2817 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2818 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2819 | 19f329ad | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2820 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ |
2821 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1); \
|
2822 | 19f329ad | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ |
2823 | 19f329ad | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ |
2824 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2825 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); \ |
2826 | 19f329ad | blueswir1 | } |
2827 | 19f329ad | blueswir1 | |
2828 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2829 | 19f329ad | blueswir1 | FMOVCC(F, 0);
|
2830 | 0f8a249a | blueswir1 | break;
|
2831 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2832 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2833 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2834 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2835 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2836 | 1f587329 | blueswir1 | break;
|
2837 | 1f587329 | blueswir1 | #else
|
2838 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2839 | 1f587329 | blueswir1 | #endif
|
2840 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2841 | 19f329ad | blueswir1 | FMOVCC(F, 1);
|
2842 | 0f8a249a | blueswir1 | break;
|
2843 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2844 | 19f329ad | blueswir1 | FMOVCC(D, 1);
|
2845 | 0f8a249a | blueswir1 | break;
|
2846 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2847 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2848 | 19f329ad | blueswir1 | FMOVCC(Q, 1);
|
2849 | 1f587329 | blueswir1 | break;
|
2850 | 1f587329 | blueswir1 | #else
|
2851 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2852 | 0f8a249a | blueswir1 | #endif
|
2853 | 19f329ad | blueswir1 | #undef FMOVCC
|
2854 | 1f587329 | blueswir1 | #endif
|
2855 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2856 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2857 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2858 | 7e8c2b6c | blueswir1 | gen_op_fcmps(rd & 3);
|
2859 | 0f8a249a | blueswir1 | break;
|
2860 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2861 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2862 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2863 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2864 | 0f8a249a | blueswir1 | break;
|
2865 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2866 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2867 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2868 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2869 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2870 | 1f587329 | blueswir1 | break;
|
2871 | 1f587329 | blueswir1 | #else /* !defined(CONFIG_USER_ONLY) */ |
2872 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2873 | 1f587329 | blueswir1 | #endif
|
2874 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2875 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2876 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2877 | 7e8c2b6c | blueswir1 | gen_op_fcmpes(rd & 3);
|
2878 | 0f8a249a | blueswir1 | break;
|
2879 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2880 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2881 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2882 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2883 | 0f8a249a | blueswir1 | break;
|
2884 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2885 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2886 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2887 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2888 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2889 | 1f587329 | blueswir1 | break;
|
2890 | 1f587329 | blueswir1 | #else/* !defined(CONFIG_USER_ONLY) */ |
2891 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2892 | 1f587329 | blueswir1 | #endif
|
2893 | 0f8a249a | blueswir1 | default:
|
2894 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2895 | 0f8a249a | blueswir1 | } |
2896 | e80cfcfc | bellard | #if defined(OPTIM)
|
2897 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2898 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2899 | e80cfcfc | bellard | |
2900 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2901 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2902 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2903 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2904 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2905 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[0], (int)rs2); |
2906 | 0f8a249a | blueswir1 | } else { /* register */ |
2907 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2908 | 1a2fb1c0 | blueswir1 | gen_movl_reg_T0(rs2); |
2909 | 0f8a249a | blueswir1 | } |
2910 | 0f8a249a | blueswir1 | } else {
|
2911 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2912 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2913 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2914 | 1a2fb1c0 | blueswir1 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2); |
2915 | 0f8a249a | blueswir1 | } else { /* register */ |
2916 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2917 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2918 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2919 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2920 | 0f8a249a | blueswir1 | gen_op_or_T1_T0(); |
2921 | 0f8a249a | blueswir1 | } |
2922 | 0f8a249a | blueswir1 | } |
2923 | 0f8a249a | blueswir1 | } |
2924 | 1a2fb1c0 | blueswir1 | gen_movl_T0_reg(rd); |
2925 | e80cfcfc | bellard | #endif
|
2926 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2927 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2928 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2929 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2930 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2931 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2932 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2933 | 1a2fb1c0 | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); |
2934 | 1a2fb1c0 | blueswir1 | } else {
|
2935 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2936 | 1a2fb1c0 | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); |
2937 | 1a2fb1c0 | blueswir1 | } |
2938 | 0f8a249a | blueswir1 | } else { /* register */ |
2939 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2940 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2941 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2942 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); |
2943 | 1a2fb1c0 | blueswir1 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2944 | 1a2fb1c0 | blueswir1 | } else {
|
2945 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); |
2946 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2947 | 1a2fb1c0 | blueswir1 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2948 | 1a2fb1c0 | blueswir1 | } |
2949 | 83469015 | bellard | } |
2950 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2951 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2952 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2953 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2954 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2955 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2956 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2957 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); |
2958 | 1a2fb1c0 | blueswir1 | } else {
|
2959 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2960 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); |
2961 | 1a2fb1c0 | blueswir1 | } |
2962 | 0f8a249a | blueswir1 | } else { /* register */ |
2963 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2964 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2965 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2966 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); |
2967 | 1a2fb1c0 | blueswir1 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2968 | 1a2fb1c0 | blueswir1 | } else {
|
2969 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); |
2970 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2971 | 1a2fb1c0 | blueswir1 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2972 | 1a2fb1c0 | blueswir1 | } |
2973 | 83469015 | bellard | } |
2974 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2975 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2976 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2977 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2978 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2979 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2980 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2981 | 1a2fb1c0 | blueswir1 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); |
2982 | 1a2fb1c0 | blueswir1 | } else {
|
2983 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2984 | 1a2fb1c0 | blueswir1 | tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]); |
2985 | 1a2fb1c0 | blueswir1 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); |
2986 | 1a2fb1c0 | blueswir1 | } |
2987 | 0f8a249a | blueswir1 | } else { /* register */ |
2988 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2989 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2990 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2991 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); |
2992 | 1a2fb1c0 | blueswir1 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2993 | 1a2fb1c0 | blueswir1 | } else {
|
2994 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); |
2995 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2996 | 1a2fb1c0 | blueswir1 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2997 | 1a2fb1c0 | blueswir1 | } |
2998 | 83469015 | bellard | } |
2999 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3000 | 83469015 | bellard | #endif
|
3001 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
3002 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3003 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3004 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3005 | cf495bcf | bellard | rs2 = GET_FIELDs(insn, 19, 31); |
3006 | 3475187d | bellard | gen_movl_simm_T1(rs2); |
3007 | 0f8a249a | blueswir1 | } else { /* register */ |
3008 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3009 | cf495bcf | bellard | gen_movl_reg_T1(rs2); |
3010 | cf495bcf | bellard | } |
3011 | cf495bcf | bellard | if (xop < 0x20) { |
3012 | cf495bcf | bellard | switch (xop & ~0x10) { |
3013 | cf495bcf | bellard | case 0x0: |
3014 | cf495bcf | bellard | if (xop & 0x10) |
3015 | cf495bcf | bellard | gen_op_add_T1_T0_cc(); |
3016 | cf495bcf | bellard | else
|
3017 | cf495bcf | bellard | gen_op_add_T1_T0(); |
3018 | cf495bcf | bellard | break;
|
3019 | cf495bcf | bellard | case 0x1: |
3020 | 1a2fb1c0 | blueswir1 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3021 | cf495bcf | bellard | if (xop & 0x10) |
3022 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3023 | cf495bcf | bellard | break;
|
3024 | cf495bcf | bellard | case 0x2: |
3025 | 1a2fb1c0 | blueswir1 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3026 | 0f8a249a | blueswir1 | if (xop & 0x10) |
3027 | 0f8a249a | blueswir1 | gen_op_logic_T0_cc(); |
3028 | 0f8a249a | blueswir1 | break;
|
3029 | cf495bcf | bellard | case 0x3: |
3030 | 1a2fb1c0 | blueswir1 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3031 | cf495bcf | bellard | if (xop & 0x10) |
3032 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3033 | cf495bcf | bellard | break;
|
3034 | cf495bcf | bellard | case 0x4: |
3035 | cf495bcf | bellard | if (xop & 0x10) |
3036 | cf495bcf | bellard | gen_op_sub_T1_T0_cc(); |
3037 | cf495bcf | bellard | else
|
3038 | 1a2fb1c0 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3039 | cf495bcf | bellard | break;
|
3040 | cf495bcf | bellard | case 0x5: |
3041 | 56ec06bb | blueswir1 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3042 | 56ec06bb | blueswir1 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3043 | cf495bcf | bellard | if (xop & 0x10) |
3044 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3045 | cf495bcf | bellard | break;
|
3046 | cf495bcf | bellard | case 0x6: |
3047 | 56ec06bb | blueswir1 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3048 | 56ec06bb | blueswir1 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3049 | cf495bcf | bellard | if (xop & 0x10) |
3050 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3051 | cf495bcf | bellard | break;
|
3052 | cf495bcf | bellard | case 0x7: |
3053 | 56ec06bb | blueswir1 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3054 | 56ec06bb | blueswir1 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3055 | cf495bcf | bellard | if (xop & 0x10) |
3056 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3057 | cf495bcf | bellard | break;
|
3058 | cf495bcf | bellard | case 0x8: |
3059 | cf495bcf | bellard | if (xop & 0x10) |
3060 | af7bf89b | bellard | gen_op_addx_T1_T0_cc(); |
3061 | 38bc628b | blueswir1 | else {
|
3062 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3063 | 38bc628b | blueswir1 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
3064 | 38bc628b | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3065 | 38bc628b | blueswir1 | } |
3066 | cf495bcf | bellard | break;
|
3067 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3068 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3069 | 1a2fb1c0 | blueswir1 | tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
3070 | ded3ab80 | pbrook | break;
|
3071 | ded3ab80 | pbrook | #endif
|
3072 | cf495bcf | bellard | case 0xa: |
3073 | cf495bcf | bellard | gen_op_umul_T1_T0(); |
3074 | cf495bcf | bellard | if (xop & 0x10) |
3075 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3076 | cf495bcf | bellard | break;
|
3077 | cf495bcf | bellard | case 0xb: |
3078 | cf495bcf | bellard | gen_op_smul_T1_T0(); |
3079 | cf495bcf | bellard | if (xop & 0x10) |
3080 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3081 | cf495bcf | bellard | break;
|
3082 | cf495bcf | bellard | case 0xc: |
3083 | cf495bcf | bellard | if (xop & 0x10) |
3084 | af7bf89b | bellard | gen_op_subx_T1_T0_cc(); |
3085 | 38bc628b | blueswir1 | else {
|
3086 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3087 | 38bc628b | blueswir1 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
3088 | 38bc628b | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3089 | 38bc628b | blueswir1 | } |
3090 | cf495bcf | bellard | break;
|
3091 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3092 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3093 | 1a7b60e7 | blueswir1 | gen_trap_ifdivzero_i64(cpu_T[1]);
|
3094 | 1a7b60e7 | blueswir1 | tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
3095 | ded3ab80 | pbrook | break;
|
3096 | ded3ab80 | pbrook | #endif
|
3097 | cf495bcf | bellard | case 0xe: |
3098 | cf495bcf | bellard | gen_op_udiv_T1_T0(); |
3099 | cf495bcf | bellard | if (xop & 0x10) |
3100 | cf495bcf | bellard | gen_op_div_cc(); |
3101 | cf495bcf | bellard | break;
|
3102 | cf495bcf | bellard | case 0xf: |
3103 | cf495bcf | bellard | gen_op_sdiv_T1_T0(); |
3104 | cf495bcf | bellard | if (xop & 0x10) |
3105 | cf495bcf | bellard | gen_op_div_cc(); |
3106 | cf495bcf | bellard | break;
|
3107 | cf495bcf | bellard | default:
|
3108 | cf495bcf | bellard | goto illegal_insn;
|
3109 | cf495bcf | bellard | } |
3110 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3111 | cf495bcf | bellard | } else {
|
3112 | cf495bcf | bellard | switch (xop) {
|
3113 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3114 | 0f8a249a | blueswir1 | gen_op_tadd_T1_T0_cc(); |
3115 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3116 | 0f8a249a | blueswir1 | break;
|
3117 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3118 | 0f8a249a | blueswir1 | gen_op_tsub_T1_T0_cc(); |
3119 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3120 | 0f8a249a | blueswir1 | break;
|
3121 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3122 | 90251fb9 | blueswir1 | save_state(dc); |
3123 | 0f8a249a | blueswir1 | gen_op_tadd_T1_T0_ccTV(); |
3124 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3125 | 0f8a249a | blueswir1 | break;
|
3126 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3127 | 90251fb9 | blueswir1 | save_state(dc); |
3128 | 0f8a249a | blueswir1 | gen_op_tsub_T1_T0_ccTV(); |
3129 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3130 | 0f8a249a | blueswir1 | break;
|
3131 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3132 | cf495bcf | bellard | gen_op_mulscc_T1_T0(); |
3133 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3134 | cf495bcf | bellard | break;
|
3135 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3136 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3137 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
3138 | 1a2fb1c0 | blueswir1 | tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]); |
3139 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3140 | cf495bcf | bellard | break;
|
3141 | 83469015 | bellard | case 0x26: /* srl */ |
3142 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
3143 | 1a2fb1c0 | blueswir1 | tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]); |
3144 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3145 | cf495bcf | bellard | break;
|
3146 | 83469015 | bellard | case 0x27: /* sra */ |
3147 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
3148 | 1a2fb1c0 | blueswir1 | tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]); |
3149 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3150 | cf495bcf | bellard | break;
|
3151 | 83469015 | bellard | #endif
|
3152 | cf495bcf | bellard | case 0x30: |
3153 | cf495bcf | bellard | { |
3154 | cf495bcf | bellard | switch(rd) {
|
3155 | 3475187d | bellard | case 0: /* wry */ |
3156 | 0f8a249a | blueswir1 | gen_op_xor_T1_T0(); |
3157 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); |
3158 | cf495bcf | bellard | break;
|
3159 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3160 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3161 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3162 | 65fe7b09 | blueswir1 | on the microSPARC
|
3163 | 65fe7b09 | blueswir1 | II */
|
3164 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3165 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3166 | 65fe7b09 | blueswir1 | manual, nop on the
|
3167 | 65fe7b09 | blueswir1 | microSPARC II */
|
3168 | 65fe7b09 | blueswir1 | break;
|
3169 | 65fe7b09 | blueswir1 | #else
|
3170 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3171 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
3172 | d35527d9 | blueswir1 | tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
|
3173 | 0f8a249a | blueswir1 | break;
|
3174 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3175 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
3176 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
3177 | 0f8a249a | blueswir1 | break;
|
3178 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3179 | 0f8a249a | blueswir1 | gen_op_xor_T1_T0(); |
3180 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); |
3181 | 3299908c | blueswir1 | save_state(dc); |
3182 | 3299908c | blueswir1 | gen_op_next_insn(); |
3183 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3184 | 3299908c | blueswir1 | dc->is_br = 1;
|
3185 | 0f8a249a | blueswir1 | break;
|
3186 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3187 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3188 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3189 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3190 | 3475187d | bellard | #endif
|
3191 | 0f8a249a | blueswir1 | break;
|
3192 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3193 | 725cb90b | bellard | if (gen_trap_ifnofpu(dc))
|
3194 | 725cb90b | bellard | goto jmp_insn;
|
3195 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
3196 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); |
3197 | 0f8a249a | blueswir1 | break;
|
3198 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3199 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3200 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3201 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3202 | 83469015 | bellard | #endif
|
3203 | ccd4a219 | blueswir1 | { |
3204 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3205 | ccd4a219 | blueswir1 | |
3206 | ccd4a219 | blueswir1 | gen_op_xor_T1_T0(); |
3207 | ccd4a219 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
3208 | ccd4a219 | blueswir1 | tick_cmpr)); |
3209 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3210 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3211 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3212 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3213 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3214 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3215 | ccd4a219 | blueswir1 | } |
3216 | 0f8a249a | blueswir1 | break;
|
3217 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3218 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3219 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3220 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3221 | 83469015 | bellard | #endif
|
3222 | ccd4a219 | blueswir1 | { |
3223 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3224 | ccd4a219 | blueswir1 | |
3225 | ccd4a219 | blueswir1 | gen_op_xor_T1_T0(); |
3226 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3227 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3228 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3229 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3230 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3231 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3232 | ccd4a219 | blueswir1 | } |
3233 | 0f8a249a | blueswir1 | break;
|
3234 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3235 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3236 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3237 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3238 | 3475187d | bellard | #endif
|
3239 | ccd4a219 | blueswir1 | { |
3240 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3241 | ccd4a219 | blueswir1 | |
3242 | ccd4a219 | blueswir1 | gen_op_xor_T1_T0(); |
3243 | ccd4a219 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
3244 | ccd4a219 | blueswir1 | stick_cmpr)); |
3245 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3246 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3247 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3248 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3249 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3250 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3251 | ccd4a219 | blueswir1 | } |
3252 | 0f8a249a | blueswir1 | break;
|
3253 | 83469015 | bellard | |
3254 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3255 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
3256 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3257 | 0f8a249a | blueswir1 | case 0x14: /* Softint set */ |
3258 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear */ |
3259 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
3260 | 83469015 | bellard | #endif
|
3261 | 3475187d | bellard | default:
|
3262 | cf495bcf | bellard | goto illegal_insn;
|
3263 | cf495bcf | bellard | } |
3264 | cf495bcf | bellard | } |
3265 | cf495bcf | bellard | break;
|
3266 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3267 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3268 | e8af50a3 | bellard | { |
3269 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3270 | 0f8a249a | blueswir1 | goto priv_insn;
|
3271 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3272 | 0f8a249a | blueswir1 | switch (rd) {
|
3273 | 0f8a249a | blueswir1 | case 0: |
3274 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_saved); |
3275 | 0f8a249a | blueswir1 | break;
|
3276 | 0f8a249a | blueswir1 | case 1: |
3277 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restored); |
3278 | 0f8a249a | blueswir1 | break;
|
3279 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3280 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3281 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3282 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3283 | e9ebed4d | blueswir1 | // XXX
|
3284 | 0f8a249a | blueswir1 | default:
|
3285 | 3475187d | bellard | goto illegal_insn;
|
3286 | 3475187d | bellard | } |
3287 | 3475187d | bellard | #else
|
3288 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
3289 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
|
3290 | 9e61bde5 | bellard | save_state(dc); |
3291 | 9e61bde5 | bellard | gen_op_next_insn(); |
3292 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3293 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3294 | 3475187d | bellard | #endif
|
3295 | e8af50a3 | bellard | } |
3296 | e8af50a3 | bellard | break;
|
3297 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3298 | e8af50a3 | bellard | { |
3299 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3300 | 0f8a249a | blueswir1 | goto priv_insn;
|
3301 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
3302 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3303 | 0f8a249a | blueswir1 | switch (rd) {
|
3304 | 0f8a249a | blueswir1 | case 0: // tpc |
3305 | 375ee38b | blueswir1 | { |
3306 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3307 | 375ee38b | blueswir1 | |
3308 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3309 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3310 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3311 | 375ee38b | blueswir1 | tcg_gen_st_tl(cpu_T[0], r_tsptr,
|
3312 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3313 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3314 | 375ee38b | blueswir1 | } |
3315 | 0f8a249a | blueswir1 | break;
|
3316 | 0f8a249a | blueswir1 | case 1: // tnpc |
3317 | 375ee38b | blueswir1 | { |
3318 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3319 | 375ee38b | blueswir1 | |
3320 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3321 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3322 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3323 | 375ee38b | blueswir1 | tcg_gen_st_tl(cpu_T[0], r_tsptr,
|
3324 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3325 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3326 | 375ee38b | blueswir1 | } |
3327 | 0f8a249a | blueswir1 | break;
|
3328 | 0f8a249a | blueswir1 | case 2: // tstate |
3329 | 375ee38b | blueswir1 | { |
3330 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3331 | 375ee38b | blueswir1 | |
3332 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3333 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3334 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3335 | 375ee38b | blueswir1 | tcg_gen_st_tl(cpu_T[0], r_tsptr,
|
3336 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
3337 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3338 | 375ee38b | blueswir1 | } |
3339 | 0f8a249a | blueswir1 | break;
|
3340 | 0f8a249a | blueswir1 | case 3: // tt |
3341 | 375ee38b | blueswir1 | { |
3342 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3343 | 375ee38b | blueswir1 | |
3344 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3345 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3346 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3347 | 375ee38b | blueswir1 | tcg_gen_st_i32(cpu_T[0], r_tsptr,
|
3348 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3349 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3350 | 375ee38b | blueswir1 | } |
3351 | 0f8a249a | blueswir1 | break;
|
3352 | 0f8a249a | blueswir1 | case 4: // tick |
3353 | ccd4a219 | blueswir1 | { |
3354 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3355 | ccd4a219 | blueswir1 | |
3356 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3357 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3358 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3359 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3360 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3361 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3362 | ccd4a219 | blueswir1 | } |
3363 | 0f8a249a | blueswir1 | break;
|
3364 | 0f8a249a | blueswir1 | case 5: // tba |
3365 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
3366 | 0f8a249a | blueswir1 | break;
|
3367 | 0f8a249a | blueswir1 | case 6: // pstate |
3368 | ded3ab80 | pbrook | save_state(dc); |
3369 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
|
3370 | ded3ab80 | pbrook | gen_op_next_insn(); |
3371 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3372 | ded3ab80 | pbrook | dc->is_br = 1;
|
3373 | 0f8a249a | blueswir1 | break;
|
3374 | 0f8a249a | blueswir1 | case 7: // tl |
3375 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); |
3376 | 0f8a249a | blueswir1 | break;
|
3377 | 0f8a249a | blueswir1 | case 8: // pil |
3378 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); |
3379 | 0f8a249a | blueswir1 | break;
|
3380 | 0f8a249a | blueswir1 | case 9: // cwp |
3381 | d35527d9 | blueswir1 | tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
|
3382 | 0f8a249a | blueswir1 | break;
|
3383 | 0f8a249a | blueswir1 | case 10: // cansave |
3384 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); |
3385 | 0f8a249a | blueswir1 | break;
|
3386 | 0f8a249a | blueswir1 | case 11: // canrestore |
3387 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); |
3388 | 0f8a249a | blueswir1 | break;
|
3389 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3390 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); |
3391 | 0f8a249a | blueswir1 | break;
|
3392 | 0f8a249a | blueswir1 | case 13: // otherwin |
3393 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); |
3394 | 0f8a249a | blueswir1 | break;
|
3395 | 0f8a249a | blueswir1 | case 14: // wstate |
3396 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); |
3397 | 0f8a249a | blueswir1 | break;
|
3398 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3399 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); |
3400 | e9ebed4d | blueswir1 | break;
|
3401 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3402 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3403 | e9ebed4d | blueswir1 | goto priv_insn;
|
3404 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); |
3405 | e9ebed4d | blueswir1 | break;
|
3406 | 0f8a249a | blueswir1 | default:
|
3407 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3408 | 0f8a249a | blueswir1 | } |
3409 | 3475187d | bellard | #else
|
3410 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1)); |
3411 | 1a2fb1c0 | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wim)); |
3412 | 3475187d | bellard | #endif
|
3413 | e8af50a3 | bellard | } |
3414 | e8af50a3 | bellard | break;
|
3415 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3416 | e8af50a3 | bellard | { |
3417 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3418 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3419 | 0f8a249a | blueswir1 | goto priv_insn;
|
3420 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
3421 | e9ebed4d | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
3422 | e9ebed4d | blueswir1 | #else
|
3423 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3424 | e9ebed4d | blueswir1 | goto priv_insn;
|
3425 | e9ebed4d | blueswir1 | gen_op_xor_T1_T0(); |
3426 | e9ebed4d | blueswir1 | switch (rd) {
|
3427 | e9ebed4d | blueswir1 | case 0: // hpstate |
3428 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3429 | e9ebed4d | blueswir1 | save_state(dc); |
3430 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3431 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3432 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3433 | e9ebed4d | blueswir1 | break;
|
3434 | e9ebed4d | blueswir1 | case 1: // htstate |
3435 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3436 | e9ebed4d | blueswir1 | break;
|
3437 | e9ebed4d | blueswir1 | case 3: // hintp |
3438 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); |
3439 | e9ebed4d | blueswir1 | break;
|
3440 | e9ebed4d | blueswir1 | case 5: // htba |
3441 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); |
3442 | e9ebed4d | blueswir1 | break;
|
3443 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3444 | ccd4a219 | blueswir1 | { |
3445 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3446 | ccd4a219 | blueswir1 | |
3447 | ccd4a219 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
3448 | ccd4a219 | blueswir1 | hstick_cmpr)); |
3449 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3450 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3451 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3452 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3453 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3454 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3455 | ccd4a219 | blueswir1 | } |
3456 | e9ebed4d | blueswir1 | break;
|
3457 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3458 | e9ebed4d | blueswir1 | default:
|
3459 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3460 | e9ebed4d | blueswir1 | } |
3461 | e9ebed4d | blueswir1 | #endif
|
3462 | e8af50a3 | bellard | } |
3463 | e8af50a3 | bellard | break;
|
3464 | e8af50a3 | bellard | #endif
|
3465 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3466 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3467 | 0f8a249a | blueswir1 | { |
3468 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3469 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3470 | 748b9d8e | blueswir1 | TCGv r_cond; |
3471 | 00f219bf | blueswir1 | int l1;
|
3472 | 00f219bf | blueswir1 | |
3473 | 748b9d8e | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
3474 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3475 | 0f8a249a | blueswir1 | if (cc == 0) |
3476 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
3477 | 0f8a249a | blueswir1 | else if (cc == 2) |
3478 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
3479 | 0f8a249a | blueswir1 | else
|
3480 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3481 | 0f8a249a | blueswir1 | } else {
|
3482 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3483 | 0f8a249a | blueswir1 | } |
3484 | 00f219bf | blueswir1 | |
3485 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3486 | 00f219bf | blueswir1 | |
3487 | 748b9d8e | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, |
3488 | 748b9d8e | blueswir1 | tcg_const_tl(0), l1);
|
3489 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3490 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
3491 | 00f219bf | blueswir1 | gen_movl_simm_T1(rs2); |
3492 | 00f219bf | blueswir1 | } else {
|
3493 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3494 | 00f219bf | blueswir1 | gen_movl_reg_T1(rs2); |
3495 | 00f219bf | blueswir1 | } |
3496 | 00f219bf | blueswir1 | gen_movl_T1_reg(rd); |
3497 | 00f219bf | blueswir1 | gen_set_label(l1); |
3498 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); |
3499 | 0f8a249a | blueswir1 | break;
|
3500 | 0f8a249a | blueswir1 | } |
3501 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3502 | 3475187d | bellard | gen_op_sdivx_T1_T0(); |
3503 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3504 | 0f8a249a | blueswir1 | break;
|
3505 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3506 | 0f8a249a | blueswir1 | { |
3507 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3508 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 12); |
3509 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3510 | 0f8a249a | blueswir1 | // XXX optimize: popc(constant)
|
3511 | 0f8a249a | blueswir1 | } |
3512 | 0f8a249a | blueswir1 | else {
|
3513 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3514 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3515 | 0f8a249a | blueswir1 | } |
3516 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_1(helper_popc, cpu_T[0],
|
3517 | 1a2fb1c0 | blueswir1 | cpu_T[1]);
|
3518 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3519 | 0f8a249a | blueswir1 | } |
3520 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3521 | 0f8a249a | blueswir1 | { |
3522 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3523 | 00f219bf | blueswir1 | int l1;
|
3524 | 00f219bf | blueswir1 | |
3525 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3526 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3527 | 00f219bf | blueswir1 | |
3528 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3529 | 00f219bf | blueswir1 | |
3530 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
3531 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
3532 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3533 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
3534 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3535 | 00f219bf | blueswir1 | } else {
|
3536 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3537 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3538 | 0f8a249a | blueswir1 | } |
3539 | 00f219bf | blueswir1 | gen_movl_T1_reg(rd); |
3540 | 00f219bf | blueswir1 | gen_set_label(l1); |
3541 | 0f8a249a | blueswir1 | break;
|
3542 | 0f8a249a | blueswir1 | } |
3543 | 0f8a249a | blueswir1 | #endif
|
3544 | 0f8a249a | blueswir1 | default:
|
3545 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3546 | 0f8a249a | blueswir1 | } |
3547 | 0f8a249a | blueswir1 | } |
3548 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3549 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3550 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3551 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3552 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3553 | e9ebed4d | blueswir1 | if (gen_trap_ifnofpu(dc))
|
3554 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3555 | 3299908c | blueswir1 | |
3556 | 3299908c | blueswir1 | switch (opf) {
|
3557 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3558 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3559 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3560 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3561 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3562 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3563 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3564 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3565 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3566 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3567 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3568 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3569 | e9ebed4d | blueswir1 | // XXX
|
3570 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3571 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3572 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
3573 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
3574 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3575 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3576 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
3577 | e9ebed4d | blueswir1 | break;
|
3578 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3579 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
3580 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
3581 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3582 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3583 | 1f5063fb | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1); |
3584 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
3585 | e9ebed4d | blueswir1 | break;
|
3586 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3587 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
3588 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
3589 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3590 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3591 | 1f5063fb | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); |
3592 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
3593 | e9ebed4d | blueswir1 | break;
|
3594 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3595 | 3299908c | blueswir1 | gen_movl_reg_T0(rs1); |
3596 | 3299908c | blueswir1 | gen_movl_reg_T1(rs2); |
3597 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0], |
3598 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3599 | 3299908c | blueswir1 | gen_movl_T0_reg(rd); |
3600 | 3299908c | blueswir1 | break;
|
3601 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3602 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3603 | 3299908c | blueswir1 | // XXX
|
3604 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3605 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3606 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3607 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3608 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple16); |
3609 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3610 | e9ebed4d | blueswir1 | break;
|
3611 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3612 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3613 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3614 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne16); |
3615 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3616 | 3299908c | blueswir1 | break;
|
3617 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3618 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3619 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3620 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple32); |
3621 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3622 | e9ebed4d | blueswir1 | break;
|
3623 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3624 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3625 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3626 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne32); |
3627 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3628 | e9ebed4d | blueswir1 | break;
|
3629 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3630 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3631 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3632 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt16); |
3633 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3634 | e9ebed4d | blueswir1 | break;
|
3635 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3636 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3637 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3638 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq16); |
3639 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3640 | e9ebed4d | blueswir1 | break;
|
3641 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3642 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3643 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3644 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt32); |
3645 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3646 | e9ebed4d | blueswir1 | break;
|
3647 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3648 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3649 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3650 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq32); |
3651 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3652 | e9ebed4d | blueswir1 | break;
|
3653 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3654 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3655 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3656 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16); |
3657 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3658 | e9ebed4d | blueswir1 | break;
|
3659 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3660 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3661 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3662 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16au); |
3663 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3664 | e9ebed4d | blueswir1 | break;
|
3665 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3666 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3667 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3668 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16al); |
3669 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3670 | e9ebed4d | blueswir1 | break;
|
3671 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3672 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3673 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3674 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8sux16); |
3675 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3676 | e9ebed4d | blueswir1 | break;
|
3677 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3678 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3679 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3680 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
3681 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3682 | e9ebed4d | blueswir1 | break;
|
3683 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3684 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3685 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3686 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
3687 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3688 | e9ebed4d | blueswir1 | break;
|
3689 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3690 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3691 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3692 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
3693 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3694 | e9ebed4d | blueswir1 | break;
|
3695 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3696 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3697 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3698 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3699 | e9ebed4d | blueswir1 | // XXX
|
3700 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3701 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3702 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3703 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3704 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faligndata); |
3705 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3706 | 3299908c | blueswir1 | break;
|
3707 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3708 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3709 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3710 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpmerge); |
3711 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3712 | e9ebed4d | blueswir1 | break;
|
3713 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3714 | e9ebed4d | blueswir1 | // XXX
|
3715 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3716 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3717 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3718 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3719 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fexpand); |
3720 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3721 | e9ebed4d | blueswir1 | break;
|
3722 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3723 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3724 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3725 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16); |
3726 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3727 | e9ebed4d | blueswir1 | break;
|
3728 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3729 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3730 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3731 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16s); |
3732 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3733 | e9ebed4d | blueswir1 | break;
|
3734 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3735 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3736 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3737 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3738 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3739 | e9ebed4d | blueswir1 | break;
|
3740 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3741 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3742 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3743 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32s); |
3744 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3745 | e9ebed4d | blueswir1 | break;
|
3746 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3747 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3748 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3749 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16); |
3750 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3751 | e9ebed4d | blueswir1 | break;
|
3752 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3753 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3754 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3755 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16s); |
3756 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3757 | e9ebed4d | blueswir1 | break;
|
3758 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3759 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3760 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3761 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3762 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3763 | e9ebed4d | blueswir1 | break;
|
3764 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3765 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3766 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3767 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub32s); |
3768 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3769 | e9ebed4d | blueswir1 | break;
|
3770 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3771 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
3772 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3773 | 3299908c | blueswir1 | break;
|
3774 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3775 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3776 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3777 | 3299908c | blueswir1 | break;
|
3778 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3779 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3780 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3781 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnor); |
3782 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3783 | e9ebed4d | blueswir1 | break;
|
3784 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3785 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3786 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3787 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnors); |
3788 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3789 | e9ebed4d | blueswir1 | break;
|
3790 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3791 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3792 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3793 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnot); |
3794 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3795 | e9ebed4d | blueswir1 | break;
|
3796 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3797 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3798 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3799 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnots); |
3800 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3801 | e9ebed4d | blueswir1 | break;
|
3802 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3803 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3804 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3805 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3806 | e9ebed4d | blueswir1 | break;
|
3807 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3808 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3809 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3810 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3811 | e9ebed4d | blueswir1 | break;
|
3812 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3813 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3814 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3815 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnot); |
3816 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3817 | e9ebed4d | blueswir1 | break;
|
3818 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3819 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3820 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3821 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnots); |
3822 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3823 | e9ebed4d | blueswir1 | break;
|
3824 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3825 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3826 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3827 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3828 | e9ebed4d | blueswir1 | break;
|
3829 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3830 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3831 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3832 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3833 | e9ebed4d | blueswir1 | break;
|
3834 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3835 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3836 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3837 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxor); |
3838 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3839 | e9ebed4d | blueswir1 | break;
|
3840 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3841 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3842 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3843 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxors); |
3844 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3845 | e9ebed4d | blueswir1 | break;
|
3846 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3847 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3848 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3849 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnand); |
3850 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3851 | e9ebed4d | blueswir1 | break;
|
3852 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3853 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3854 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3855 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnands); |
3856 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3857 | e9ebed4d | blueswir1 | break;
|
3858 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3859 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3860 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3861 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fand); |
3862 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3863 | e9ebed4d | blueswir1 | break;
|
3864 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3865 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3866 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3867 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fands); |
3868 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3869 | e9ebed4d | blueswir1 | break;
|
3870 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3871 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3872 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3873 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxnor); |
3874 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3875 | e9ebed4d | blueswir1 | break;
|
3876 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3877 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3878 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3879 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxnors); |
3880 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3881 | e9ebed4d | blueswir1 | break;
|
3882 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3883 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3884 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3885 | 3299908c | blueswir1 | break;
|
3886 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3887 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3888 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3889 | 3299908c | blueswir1 | break;
|
3890 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3891 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3892 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3893 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornot); |
3894 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3895 | e9ebed4d | blueswir1 | break;
|
3896 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
3897 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3898 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3899 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornots); |
3900 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3901 | e9ebed4d | blueswir1 | break;
|
3902 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
3903 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3904 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3905 | 3299908c | blueswir1 | break;
|
3906 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
3907 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3908 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3909 | 3299908c | blueswir1 | break;
|
3910 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
3911 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3912 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3913 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornot); |
3914 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3915 | e9ebed4d | blueswir1 | break;
|
3916 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
3917 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3918 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3919 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornots); |
3920 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3921 | e9ebed4d | blueswir1 | break;
|
3922 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
3923 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3924 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3925 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_for); |
3926 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3927 | e9ebed4d | blueswir1 | break;
|
3928 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
3929 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3930 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3931 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fors); |
3932 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3933 | e9ebed4d | blueswir1 | break;
|
3934 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
3935 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
3936 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3937 | 3299908c | blueswir1 | break;
|
3938 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
3939 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
3940 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3941 | 3299908c | blueswir1 | break;
|
3942 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
3943 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
3944 | e9ebed4d | blueswir1 | // XXX
|
3945 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3946 | 3299908c | blueswir1 | default:
|
3947 | 3299908c | blueswir1 | goto illegal_insn;
|
3948 | 3299908c | blueswir1 | } |
3949 | 3299908c | blueswir1 | #else
|
3950 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3951 | 3299908c | blueswir1 | #endif
|
3952 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
3953 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
3954 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3955 | fcc72045 | blueswir1 | #else
|
3956 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3957 | fcc72045 | blueswir1 | #endif
|
3958 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3959 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
3960 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3961 | 1ad21e69 | blueswir1 | save_state(dc); |
3962 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3963 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3964 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3965 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
3966 | 0f8a249a | blueswir1 | } else { /* register */ |
3967 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3968 | 3475187d | bellard | #if defined(OPTIM)
|
3969 | 0f8a249a | blueswir1 | if (rs2) {
|
3970 | 3475187d | bellard | #endif
|
3971 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3972 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3973 | 3475187d | bellard | #if defined(OPTIM)
|
3974 | 0f8a249a | blueswir1 | } |
3975 | 3475187d | bellard | #endif
|
3976 | 3475187d | bellard | } |
3977 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
3978 | 0f8a249a | blueswir1 | gen_mov_pc_npc(dc); |
3979 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3980 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
|
3981 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3982 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3983 | 3475187d | bellard | #endif
|
3984 | 0f8a249a | blueswir1 | } else {
|
3985 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3986 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3987 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3988 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3989 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
3990 | 0f8a249a | blueswir1 | } else { /* register */ |
3991 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3992 | e80cfcfc | bellard | #if defined(OPTIM)
|
3993 | 0f8a249a | blueswir1 | if (rs2) {
|
3994 | e80cfcfc | bellard | #endif
|
3995 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3996 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3997 | e80cfcfc | bellard | #if defined(OPTIM)
|
3998 | 0f8a249a | blueswir1 | } |
3999 | e8af50a3 | bellard | #endif
|
4000 | cf495bcf | bellard | } |
4001 | 0f8a249a | blueswir1 | switch (xop) {
|
4002 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4003 | 0f8a249a | blueswir1 | { |
4004 | 0f8a249a | blueswir1 | if (rd != 0) { |
4005 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[1], dc->pc);
|
4006 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
4007 | 0f8a249a | blueswir1 | } |
4008 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
4009 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4010 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
|
4011 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4012 | 0f8a249a | blueswir1 | } |
4013 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4014 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4015 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4016 | 0f8a249a | blueswir1 | { |
4017 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4018 | 0f8a249a | blueswir1 | goto priv_insn;
|
4019 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
4020 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4021 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
|
4022 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4023 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_rett); |
4024 | 0f8a249a | blueswir1 | } |
4025 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4026 | 0f8a249a | blueswir1 | #endif
|
4027 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4028 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
|
4029 | 0f8a249a | blueswir1 | break;
|
4030 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4031 | 0f8a249a | blueswir1 | save_state(dc); |
4032 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_save); |
4033 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
4034 | 0f8a249a | blueswir1 | break;
|
4035 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4036 | 0f8a249a | blueswir1 | save_state(dc); |
4037 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
4038 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
4039 | 0f8a249a | blueswir1 | break;
|
4040 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4041 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4042 | 0f8a249a | blueswir1 | { |
4043 | 0f8a249a | blueswir1 | switch (rd) {
|
4044 | 0f8a249a | blueswir1 | case 0: |
4045 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4046 | 0f8a249a | blueswir1 | goto priv_insn;
|
4047 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4048 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4049 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_done); |
4050 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4051 | 0f8a249a | blueswir1 | case 1: |
4052 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4053 | 0f8a249a | blueswir1 | goto priv_insn;
|
4054 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4055 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4056 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_retry); |
4057 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4058 | 0f8a249a | blueswir1 | default:
|
4059 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4060 | 0f8a249a | blueswir1 | } |
4061 | 0f8a249a | blueswir1 | } |
4062 | 0f8a249a | blueswir1 | break;
|
4063 | 0f8a249a | blueswir1 | #endif
|
4064 | 0f8a249a | blueswir1 | default:
|
4065 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4066 | 0f8a249a | blueswir1 | } |
4067 | cf495bcf | bellard | } |
4068 | 0f8a249a | blueswir1 | break;
|
4069 | 0f8a249a | blueswir1 | } |
4070 | 0f8a249a | blueswir1 | break;
|
4071 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4072 | 0f8a249a | blueswir1 | { |
4073 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4074 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
4075 | 2371aaa2 | blueswir1 | save_state(dc); |
4076 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
4077 | 81ad8ba2 | blueswir1 | if (xop == 0x3c || xop == 0x3e) |
4078 | 81ad8ba2 | blueswir1 | { |
4079 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4080 | 81ad8ba2 | blueswir1 | gen_movl_reg_T1(rs2); |
4081 | 81ad8ba2 | blueswir1 | } |
4082 | 81ad8ba2 | blueswir1 | else if (IS_IMM) { /* immediate */ |
4083 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4084 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
4085 | 0f8a249a | blueswir1 | } else { /* register */ |
4086 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4087 | e80cfcfc | bellard | #if defined(OPTIM)
|
4088 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4089 | e80cfcfc | bellard | #endif
|
4090 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
4091 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
4092 | e80cfcfc | bellard | #if defined(OPTIM)
|
4093 | 0f8a249a | blueswir1 | } |
4094 | e80cfcfc | bellard | #endif
|
4095 | 0f8a249a | blueswir1 | } |
4096 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4097 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4098 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4099 | 0f8a249a | blueswir1 | switch (xop) {
|
4100 | 1a2fb1c0 | blueswir1 | case 0x0: /* load unsigned word */ |
4101 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4102 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4103 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx); |
4104 | 0f8a249a | blueswir1 | break;
|
4105 | 0f8a249a | blueswir1 | case 0x1: /* load unsigned byte */ |
4106 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4107 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx); |
4108 | 0f8a249a | blueswir1 | break;
|
4109 | 0f8a249a | blueswir1 | case 0x2: /* load unsigned halfword */ |
4110 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4111 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4112 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx); |
4113 | 0f8a249a | blueswir1 | break;
|
4114 | 0f8a249a | blueswir1 | case 0x3: /* load double word */ |
4115 | 0f8a249a | blueswir1 | if (rd & 1) |
4116 | d4218d99 | blueswir1 | goto illegal_insn;
|
4117 | 1a2fb1c0 | blueswir1 | else {
|
4118 | 1a2fb1c0 | blueswir1 | TCGv r_dword; |
4119 | 1a2fb1c0 | blueswir1 | |
4120 | 1a2fb1c0 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
4121 | 1a2fb1c0 | blueswir1 | gen_op_check_align_T0_7(); |
4122 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4123 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
|
4124 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
|
4125 | 1a2fb1c0 | blueswir1 | gen_movl_T0_reg(rd + 1);
|
4126 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(r_dword, r_dword, 32);
|
4127 | 1a2fb1c0 | blueswir1 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
|
4128 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
4129 | 1a2fb1c0 | blueswir1 | } |
4130 | 0f8a249a | blueswir1 | break;
|
4131 | 0f8a249a | blueswir1 | case 0x9: /* load signed byte */ |
4132 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4133 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4134 | 0f8a249a | blueswir1 | break;
|
4135 | 0f8a249a | blueswir1 | case 0xa: /* load signed halfword */ |
4136 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4137 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4138 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4139 | 0f8a249a | blueswir1 | break;
|
4140 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4141 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_i32(cpu_tmp0, 0xff);
|
4142 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4143 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4144 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
|
4145 | 0f8a249a | blueswir1 | break;
|
4146 | 0f8a249a | blueswir1 | case 0x0f: /* swap register with memory. Also atomically */ |
4147 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4148 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rd); |
4149 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4150 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
|
4151 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); |
4152 | 1a2fb1c0 | blueswir1 | tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
|
4153 | 0f8a249a | blueswir1 | break;
|
4154 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4155 | 0f8a249a | blueswir1 | case 0x10: /* load word alternate */ |
4156 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4157 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4158 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4159 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4160 | 0f8a249a | blueswir1 | goto priv_insn;
|
4161 | 6ea4a6c8 | blueswir1 | #endif
|
4162 | 8f577d3d | blueswir1 | gen_op_check_align_T0_3(); |
4163 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 4, 0); |
4164 | 0f8a249a | blueswir1 | break;
|
4165 | 0f8a249a | blueswir1 | case 0x11: /* load unsigned byte alternate */ |
4166 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4167 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4168 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4169 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4170 | 0f8a249a | blueswir1 | goto priv_insn;
|
4171 | 0f8a249a | blueswir1 | #endif
|
4172 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 1, 0); |
4173 | 0f8a249a | blueswir1 | break;
|
4174 | 0f8a249a | blueswir1 | case 0x12: /* load unsigned halfword alternate */ |
4175 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4176 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4177 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4178 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4179 | 0f8a249a | blueswir1 | goto priv_insn;
|
4180 | 6ea4a6c8 | blueswir1 | #endif
|
4181 | 8f577d3d | blueswir1 | gen_op_check_align_T0_1(); |
4182 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 2, 0); |
4183 | 0f8a249a | blueswir1 | break;
|
4184 | 0f8a249a | blueswir1 | case 0x13: /* load double word alternate */ |
4185 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4186 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4187 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4188 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4189 | 0f8a249a | blueswir1 | goto priv_insn;
|
4190 | 3475187d | bellard | #endif
|
4191 | 0f8a249a | blueswir1 | if (rd & 1) |
4192 | d4218d99 | blueswir1 | goto illegal_insn;
|
4193 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4194 | 81ad8ba2 | blueswir1 | gen_ldda_asi(insn); |
4195 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd + 1);
|
4196 | 0f8a249a | blueswir1 | break;
|
4197 | 0f8a249a | blueswir1 | case 0x19: /* load signed byte alternate */ |
4198 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4199 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4200 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4201 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4202 | 0f8a249a | blueswir1 | goto priv_insn;
|
4203 | 0f8a249a | blueswir1 | #endif
|
4204 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 1, 1); |
4205 | 0f8a249a | blueswir1 | break;
|
4206 | 0f8a249a | blueswir1 | case 0x1a: /* load signed halfword alternate */ |
4207 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4208 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4209 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4210 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4211 | 0f8a249a | blueswir1 | goto priv_insn;
|
4212 | 6ea4a6c8 | blueswir1 | #endif
|
4213 | 8f577d3d | blueswir1 | gen_op_check_align_T0_1(); |
4214 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 2, 1); |
4215 | 0f8a249a | blueswir1 | break;
|
4216 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4217 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4218 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4219 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4220 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4221 | 0f8a249a | blueswir1 | goto priv_insn;
|
4222 | 0f8a249a | blueswir1 | #endif
|
4223 | 81ad8ba2 | blueswir1 | gen_ldstub_asi(insn); |
4224 | 0f8a249a | blueswir1 | break;
|
4225 | 0f8a249a | blueswir1 | case 0x1f: /* swap reg with alt. memory. Also atomically */ |
4226 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4227 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4228 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4229 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4230 | 0f8a249a | blueswir1 | goto priv_insn;
|
4231 | 6ea4a6c8 | blueswir1 | #endif
|
4232 | 8f577d3d | blueswir1 | gen_op_check_align_T0_3(); |
4233 | 81ad8ba2 | blueswir1 | gen_movl_reg_T1(rd); |
4234 | 81ad8ba2 | blueswir1 | gen_swap_asi(insn); |
4235 | 0f8a249a | blueswir1 | break;
|
4236 | 3475187d | bellard | |
4237 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4238 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4239 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4240 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4241 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4242 | 3475187d | bellard | #endif
|
4243 | 3475187d | bellard | #endif
|
4244 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4245 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4246 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4247 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4248 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4249 | 0f8a249a | blueswir1 | break;
|
4250 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4251 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4252 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4253 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx); |
4254 | 0f8a249a | blueswir1 | break;
|
4255 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4256 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4257 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 4, 1); |
4258 | 0f8a249a | blueswir1 | break;
|
4259 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4260 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4261 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 8, 0); |
4262 | 0f8a249a | blueswir1 | break;
|
4263 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4264 | 0f8a249a | blueswir1 | goto skip_move;
|
4265 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4266 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4267 | 2382dc6b | blueswir1 | gen_ldf_asi(insn, 4, rd);
|
4268 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4269 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4270 | 3391c818 | blueswir1 | gen_op_check_align_T0_3(); |
4271 | 2382dc6b | blueswir1 | gen_ldf_asi(insn, 8, DFPREG(rd));
|
4272 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4273 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4274 | 0f8a249a | blueswir1 | goto skip_move;
|
4275 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4276 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4277 | 1f587329 | blueswir1 | gen_op_check_align_T0_3(); |
4278 | 2382dc6b | blueswir1 | gen_ldf_asi(insn, 16, QFPREG(rd));
|
4279 | 1f587329 | blueswir1 | goto skip_move;
|
4280 | 1f587329 | blueswir1 | #else
|
4281 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
4282 | 0f8a249a | blueswir1 | #endif
|
4283 | 1f587329 | blueswir1 | #endif
|
4284 | 0f8a249a | blueswir1 | default:
|
4285 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4286 | 0f8a249a | blueswir1 | } |
4287 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
4288 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4289 | 0f8a249a | blueswir1 | skip_move: ;
|
4290 | 3475187d | bellard | #endif
|
4291 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4292 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
4293 | a80dde08 | bellard | goto jmp_insn;
|
4294 | 0f8a249a | blueswir1 | switch (xop) {
|
4295 | 0f8a249a | blueswir1 | case 0x20: /* load fpreg */ |
4296 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4297 | 0f8a249a | blueswir1 | gen_op_ldst(ldf); |
4298 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
4299 | 0f8a249a | blueswir1 | break;
|
4300 | 0f8a249a | blueswir1 | case 0x21: /* load fsr */ |
4301 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4302 | 0f8a249a | blueswir1 | gen_op_ldst(ldf); |
4303 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_ldfsr); |
4304 | 0f8a249a | blueswir1 | break;
|
4305 | 0f8a249a | blueswir1 | case 0x22: /* load quad fpreg */ |
4306 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4307 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
4308 | 1f587329 | blueswir1 | gen_op_ldst(ldqf); |
4309 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4310 | 1f587329 | blueswir1 | break;
|
4311 | 1f587329 | blueswir1 | #else
|
4312 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
4313 | 1f587329 | blueswir1 | #endif
|
4314 | 0f8a249a | blueswir1 | case 0x23: /* load double fpreg */ |
4315 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4316 | 0f8a249a | blueswir1 | gen_op_ldst(lddf); |
4317 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4318 | 0f8a249a | blueswir1 | break;
|
4319 | 0f8a249a | blueswir1 | default:
|
4320 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4321 | 0f8a249a | blueswir1 | } |
4322 | 0f8a249a | blueswir1 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
4323 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4324 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rd); |
4325 | 0f8a249a | blueswir1 | switch (xop) {
|
4326 | 1a2fb1c0 | blueswir1 | case 0x4: /* store word */ |
4327 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4328 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4329 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); |
4330 | 0f8a249a | blueswir1 | break;
|
4331 | 1a2fb1c0 | blueswir1 | case 0x5: /* store byte */ |
4332 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4333 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx); |
4334 | 0f8a249a | blueswir1 | break;
|
4335 | 1a2fb1c0 | blueswir1 | case 0x6: /* store halfword */ |
4336 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4337 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4338 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx); |
4339 | 0f8a249a | blueswir1 | break;
|
4340 | 1a2fb1c0 | blueswir1 | case 0x7: /* store double word */ |
4341 | 0f8a249a | blueswir1 | if (rd & 1) |
4342 | d4218d99 | blueswir1 | goto illegal_insn;
|
4343 | b25deda7 | blueswir1 | #ifndef __i386__
|
4344 | 1a2fb1c0 | blueswir1 | else {
|
4345 | 1a2fb1c0 | blueswir1 | TCGv r_dword, r_low; |
4346 | 1a2fb1c0 | blueswir1 | |
4347 | 1a2fb1c0 | blueswir1 | gen_op_check_align_T0_7(); |
4348 | 1a2fb1c0 | blueswir1 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
4349 | 1a2fb1c0 | blueswir1 | r_low = tcg_temp_new(TCG_TYPE_I32); |
4350 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd + 1, r_low);
|
4351 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
|
4352 | 1a2fb1c0 | blueswir1 | r_low); |
4353 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
|
4354 | 0425bee5 | blueswir1 | tcg_gen_discard_i64(r_dword); |
4355 | 1a2fb1c0 | blueswir1 | } |
4356 | b25deda7 | blueswir1 | #else /* __i386__ */ |
4357 | b25deda7 | blueswir1 | gen_op_check_align_T0_7(); |
4358 | b25deda7 | blueswir1 | flush_T2(dc); |
4359 | b25deda7 | blueswir1 | gen_movl_reg_T2(rd + 1);
|
4360 | b25deda7 | blueswir1 | gen_op_ldst(std); |
4361 | b25deda7 | blueswir1 | #endif /* __i386__ */ |
4362 | 0f8a249a | blueswir1 | break;
|
4363 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4364 | 1a2fb1c0 | blueswir1 | case 0x14: /* store word alternate */ |
4365 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4366 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4367 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4368 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4369 | 0f8a249a | blueswir1 | goto priv_insn;
|
4370 | 3475187d | bellard | #endif
|
4371 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4372 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 4);
|
4373 | d39c0b99 | bellard | break;
|
4374 | 1a2fb1c0 | blueswir1 | case 0x15: /* store byte alternate */ |
4375 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4376 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4377 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4378 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4379 | 0f8a249a | blueswir1 | goto priv_insn;
|
4380 | 3475187d | bellard | #endif
|
4381 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 1);
|
4382 | d39c0b99 | bellard | break;
|
4383 | 1a2fb1c0 | blueswir1 | case 0x16: /* store halfword alternate */ |
4384 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4385 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4386 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4387 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4388 | 0f8a249a | blueswir1 | goto priv_insn;
|
4389 | 3475187d | bellard | #endif
|
4390 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4391 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 2);
|
4392 | d39c0b99 | bellard | break;
|
4393 | 1a2fb1c0 | blueswir1 | case 0x17: /* store double word alternate */ |
4394 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4395 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4396 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4397 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4398 | 0f8a249a | blueswir1 | goto priv_insn;
|
4399 | 3475187d | bellard | #endif
|
4400 | 0f8a249a | blueswir1 | if (rd & 1) |
4401 | d4218d99 | blueswir1 | goto illegal_insn;
|
4402 | 1a2fb1c0 | blueswir1 | else {
|
4403 | 1a2fb1c0 | blueswir1 | gen_op_check_align_T0_7(); |
4404 | 0425bee5 | blueswir1 | gen_stda_asi(insn, rd); |
4405 | 1a2fb1c0 | blueswir1 | } |
4406 | d39c0b99 | bellard | break;
|
4407 | e80cfcfc | bellard | #endif
|
4408 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4409 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4410 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4411 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4412 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx); |
4413 | 0f8a249a | blueswir1 | break;
|
4414 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4415 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4416 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 8);
|
4417 | 0f8a249a | blueswir1 | break;
|
4418 | 3475187d | bellard | #endif
|
4419 | 0f8a249a | blueswir1 | default:
|
4420 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4421 | 0f8a249a | blueswir1 | } |
4422 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4423 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
4424 | a80dde08 | bellard | goto jmp_insn;
|
4425 | 0f8a249a | blueswir1 | switch (xop) {
|
4426 | 0f8a249a | blueswir1 | case 0x24: |
4427 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4428 | e8af50a3 | bellard | gen_op_load_fpr_FT0(rd); |
4429 | 0f8a249a | blueswir1 | gen_op_ldst(stf); |
4430 | 0f8a249a | blueswir1 | break;
|
4431 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4432 | 6ea4a6c8 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
4433 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4434 | 6ea4a6c8 | blueswir1 | #endif
|
4435 | bb5529bb | blueswir1 | tcg_gen_helper_0_0(helper_stfsr); |
4436 | 0f8a249a | blueswir1 | gen_op_ldst(stf); |
4437 | 0f8a249a | blueswir1 | break;
|
4438 | 1f587329 | blueswir1 | case 0x26: |
4439 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4440 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4441 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4442 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
4443 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4444 | 1f587329 | blueswir1 | gen_op_ldst(stqf); |
4445 | 1f587329 | blueswir1 | break;
|
4446 | 1f587329 | blueswir1 | #else
|
4447 | 1f587329 | blueswir1 | goto nfpu_insn;
|
4448 | 1f587329 | blueswir1 | #endif
|
4449 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4450 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4451 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4452 | 1f587329 | blueswir1 | goto illegal_insn;
|
4453 | 1f587329 | blueswir1 | #else
|
4454 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4455 | 0f8a249a | blueswir1 | goto priv_insn;
|
4456 | 0f8a249a | blueswir1 | if (gen_trap_ifnofpu(dc))
|
4457 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4458 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4459 | 0f8a249a | blueswir1 | #endif
|
4460 | 1f587329 | blueswir1 | #endif
|
4461 | 0f8a249a | blueswir1 | case 0x27: |
4462 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4463 | 3475187d | bellard | gen_op_load_fpr_DT0(DFPREG(rd)); |
4464 | 0f8a249a | blueswir1 | gen_op_ldst(stdf); |
4465 | 0f8a249a | blueswir1 | break;
|
4466 | 0f8a249a | blueswir1 | default:
|
4467 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4468 | 0f8a249a | blueswir1 | } |
4469 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4470 | 0f8a249a | blueswir1 | switch (xop) {
|
4471 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4472 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4473 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4474 | 3391c818 | blueswir1 | gen_op_load_fpr_FT0(rd); |
4475 | 2382dc6b | blueswir1 | gen_stf_asi(insn, 4, rd);
|
4476 | 0f8a249a | blueswir1 | break;
|
4477 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4478 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4479 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
4480 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4481 | 2382dc6b | blueswir1 | gen_stf_asi(insn, 16, QFPREG(rd));
|
4482 | 1f587329 | blueswir1 | break;
|
4483 | 1f587329 | blueswir1 | #else
|
4484 | 1f587329 | blueswir1 | goto nfpu_insn;
|
4485 | 1f587329 | blueswir1 | #endif
|
4486 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4487 | 3391c818 | blueswir1 | gen_op_check_align_T0_3(); |
4488 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4489 | 2382dc6b | blueswir1 | gen_stf_asi(insn, 8, DFPREG(rd));
|
4490 | 0f8a249a | blueswir1 | break;
|
4491 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4492 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4493 | 1a2fb1c0 | blueswir1 | gen_cas_asi(insn, rd); |
4494 | 81ad8ba2 | blueswir1 | gen_movl_T1_reg(rd); |
4495 | 0f8a249a | blueswir1 | break;
|
4496 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4497 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4498 | 1a2fb1c0 | blueswir1 | gen_casx_asi(insn, rd); |
4499 | 81ad8ba2 | blueswir1 | gen_movl_T1_reg(rd); |
4500 | 0f8a249a | blueswir1 | break;
|
4501 | a4d17f19 | blueswir1 | #else
|
4502 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4503 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4504 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4505 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4506 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4507 | 0f8a249a | blueswir1 | #endif
|
4508 | 0f8a249a | blueswir1 | default:
|
4509 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4510 | 0f8a249a | blueswir1 | } |
4511 | e8af50a3 | bellard | } |
4512 | 0f8a249a | blueswir1 | else
|
4513 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4514 | 0f8a249a | blueswir1 | } |
4515 | 0f8a249a | blueswir1 | break;
|
4516 | cf495bcf | bellard | } |
4517 | cf495bcf | bellard | /* default case for non jump instructions */
|
4518 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4519 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4520 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4521 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4522 | 72cbca10 | bellard | /* we can do a static jump */
|
4523 | 19f329ad | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
4524 | 72cbca10 | bellard | dc->is_br = 1;
|
4525 | 72cbca10 | bellard | } else {
|
4526 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4527 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4528 | cf495bcf | bellard | } |
4529 | e80cfcfc | bellard | jmp_insn:
|
4530 | cf495bcf | bellard | return;
|
4531 | cf495bcf | bellard | illegal_insn:
|
4532 | 72cbca10 | bellard | save_state(dc); |
4533 | cf495bcf | bellard | gen_op_exception(TT_ILL_INSN); |
4534 | cf495bcf | bellard | dc->is_br = 1;
|
4535 | e8af50a3 | bellard | return;
|
4536 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4537 | e8af50a3 | bellard | priv_insn:
|
4538 | e8af50a3 | bellard | save_state(dc); |
4539 | e8af50a3 | bellard | gen_op_exception(TT_PRIV_INSN); |
4540 | e8af50a3 | bellard | dc->is_br = 1;
|
4541 | e80cfcfc | bellard | return;
|
4542 | e80cfcfc | bellard | nfpu_insn:
|
4543 | e80cfcfc | bellard | save_state(dc); |
4544 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4545 | e80cfcfc | bellard | dc->is_br = 1;
|
4546 | fcc72045 | blueswir1 | return;
|
4547 | 1f587329 | blueswir1 | #ifndef TARGET_SPARC64
|
4548 | 9143e598 | blueswir1 | nfq_insn:
|
4549 | 9143e598 | blueswir1 | save_state(dc); |
4550 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4551 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4552 | 9143e598 | blueswir1 | return;
|
4553 | 9143e598 | blueswir1 | #endif
|
4554 | 1f587329 | blueswir1 | #endif
|
4555 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4556 | fcc72045 | blueswir1 | ncp_insn:
|
4557 | fcc72045 | blueswir1 | save_state(dc); |
4558 | fcc72045 | blueswir1 | gen_op_exception(TT_NCP_INSN); |
4559 | fcc72045 | blueswir1 | dc->is_br = 1;
|
4560 | fcc72045 | blueswir1 | return;
|
4561 | fcc72045 | blueswir1 | #endif
|
4562 | 7a3f1944 | bellard | } |
4563 | 7a3f1944 | bellard | |
4564 | 1a2fb1c0 | blueswir1 | static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) |
4565 | 1a2fb1c0 | blueswir1 | { |
4566 | 1a2fb1c0 | blueswir1 | } |
4567 | 1a2fb1c0 | blueswir1 | |
4568 | cf495bcf | bellard | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
4569 | 0f8a249a | blueswir1 | int spc, CPUSPARCState *env)
|
4570 | 7a3f1944 | bellard | { |
4571 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4572 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4573 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4574 | e8af50a3 | bellard | int j, lj = -1; |
4575 | cf495bcf | bellard | |
4576 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4577 | cf495bcf | bellard | dc->tb = tb; |
4578 | 72cbca10 | bellard | pc_start = tb->pc; |
4579 | cf495bcf | bellard | dc->pc = pc_start; |
4580 | e80cfcfc | bellard | last_pc = dc->pc; |
4581 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4582 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4583 | 6f27aba6 | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4584 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4585 | cf495bcf | bellard | |
4586 | 1a2fb1c0 | blueswir1 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
4587 | 1a2fb1c0 | blueswir1 | |
4588 | cf495bcf | bellard | do {
|
4589 | e8af50a3 | bellard | if (env->nb_breakpoints > 0) { |
4590 | e8af50a3 | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
4591 | e8af50a3 | bellard | if (env->breakpoints[j] == dc->pc) {
|
4592 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4593 | 0f8a249a | blueswir1 | save_state(dc); |
4594 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_debug); |
4595 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4596 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4597 | e80cfcfc | bellard | goto exit_gen_loop;
|
4598 | e8af50a3 | bellard | } |
4599 | e8af50a3 | bellard | } |
4600 | e8af50a3 | bellard | } |
4601 | e8af50a3 | bellard | if (spc) {
|
4602 | e8af50a3 | bellard | if (loglevel > 0) |
4603 | e8af50a3 | bellard | fprintf(logfile, "Search PC...\n");
|
4604 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4605 | e8af50a3 | bellard | if (lj < j) {
|
4606 | e8af50a3 | bellard | lj++; |
4607 | e8af50a3 | bellard | while (lj < j)
|
4608 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4609 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4610 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4611 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4612 | e8af50a3 | bellard | } |
4613 | e8af50a3 | bellard | } |
4614 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4615 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4616 | 0f8a249a | blueswir1 | |
4617 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4618 | 0f8a249a | blueswir1 | break;
|
4619 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4620 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4621 | 0f8a249a | blueswir1 | break;
|
4622 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4623 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4624 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4625 | d39c0b99 | bellard | break;
|
4626 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4627 | e80cfcfc | bellard | generate an exception */
|
4628 | e80cfcfc | bellard | if (env->singlestep_enabled) {
|
4629 | 3475187d | bellard | gen_jmp_im(dc->pc); |
4630 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4631 | e80cfcfc | bellard | break;
|
4632 | e80cfcfc | bellard | } |
4633 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4634 | 0f8a249a | blueswir1 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
4635 | e80cfcfc | bellard | |
4636 | e80cfcfc | bellard | exit_gen_loop:
|
4637 | 72cbca10 | bellard | if (!dc->is_br) {
|
4638 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4639 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4640 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4641 | 46525e1f | blueswir1 | gen_branch(dc, dc->pc, dc->npc); |
4642 | 72cbca10 | bellard | } else {
|
4643 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4644 | 3475187d | bellard | gen_jmp_im(dc->pc); |
4645 | 72cbca10 | bellard | save_npc(dc); |
4646 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4647 | 72cbca10 | bellard | } |
4648 | 72cbca10 | bellard | } |
4649 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4650 | e8af50a3 | bellard | if (spc) {
|
4651 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4652 | e8af50a3 | bellard | lj++; |
4653 | e8af50a3 | bellard | while (lj <= j)
|
4654 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4655 | e8af50a3 | bellard | #if 0
|
4656 | e8af50a3 | bellard | if (loglevel > 0) {
|
4657 | e8af50a3 | bellard | page_dump(logfile);
|
4658 | e8af50a3 | bellard | }
|
4659 | e8af50a3 | bellard | #endif
|
4660 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4661 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4662 | e8af50a3 | bellard | } else {
|
4663 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4664 | e8af50a3 | bellard | } |
4665 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4666 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
4667 | 0f8a249a | blueswir1 | fprintf(logfile, "--------------\n");
|
4668 | 0f8a249a | blueswir1 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
4669 | 0f8a249a | blueswir1 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
4670 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
4671 | cf495bcf | bellard | } |
4672 | 7a3f1944 | bellard | #endif
|
4673 | cf495bcf | bellard | return 0; |
4674 | 7a3f1944 | bellard | } |
4675 | 7a3f1944 | bellard | |
4676 | cf495bcf | bellard | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4677 | 7a3f1944 | bellard | { |
4678 | e8af50a3 | bellard | return gen_intermediate_code_internal(tb, 0, env); |
4679 | 7a3f1944 | bellard | } |
4680 | 7a3f1944 | bellard | |
4681 | cf495bcf | bellard | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4682 | 7a3f1944 | bellard | { |
4683 | e8af50a3 | bellard | return gen_intermediate_code_internal(tb, 1, env); |
4684 | 7a3f1944 | bellard | } |
4685 | 7a3f1944 | bellard | |
4686 | e80cfcfc | bellard | void cpu_reset(CPUSPARCState *env)
|
4687 | e80cfcfc | bellard | { |
4688 | bb05683b | bellard | tlb_flush(env, 1);
|
4689 | cf495bcf | bellard | env->cwp = 0;
|
4690 | cf495bcf | bellard | env->wim = 1;
|
4691 | cf495bcf | bellard | env->regwptr = env->regbase + (env->cwp * 16);
|
4692 | e8af50a3 | bellard | #if defined(CONFIG_USER_ONLY)
|
4693 | cf495bcf | bellard | env->user_mode_only = 1;
|
4694 | 5ef54116 | bellard | #ifdef TARGET_SPARC64
|
4695 | 6ef905f6 | blueswir1 | env->cleanwin = NWINDOWS - 2;
|
4696 | 6ef905f6 | blueswir1 | env->cansave = NWINDOWS - 2;
|
4697 | 6ef905f6 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
4698 | 6ef905f6 | blueswir1 | env->asi = 0x82; // Primary no-fault |
4699 | 5ef54116 | bellard | #endif
|
4700 | e8af50a3 | bellard | #else
|
4701 | 32af58f9 | blueswir1 | env->psret = 0;
|
4702 | e8af50a3 | bellard | env->psrs = 1;
|
4703 | 0bee699e | bellard | env->psrps = 1;
|
4704 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4705 | 83469015 | bellard | env->pstate = PS_PRIV; |
4706 | 6f27aba6 | blueswir1 | env->hpstate = HS_PRIV; |
4707 | 83469015 | bellard | env->pc = 0x1fff0000000ULL;
|
4708 | 375ee38b | blueswir1 | env->tsptr = &env->ts[env->tl]; |
4709 | 3475187d | bellard | #else
|
4710 | 40ce0a9a | blueswir1 | env->pc = 0;
|
4711 | 32af58f9 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
4712 | 6d5f237a | blueswir1 | env->mmuregs[0] |= env->mmu_bm;
|
4713 | 3475187d | bellard | #endif
|
4714 | 83469015 | bellard | env->npc = env->pc + 4;
|
4715 | e8af50a3 | bellard | #endif
|
4716 | e80cfcfc | bellard | } |
4717 | e80cfcfc | bellard | |
4718 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
4719 | e80cfcfc | bellard | { |
4720 | e80cfcfc | bellard | CPUSPARCState *env; |
4721 | aaed909a | bellard | const sparc_def_t *def;
|
4722 | 1a2fb1c0 | blueswir1 | static int inited; |
4723 | f5069b26 | blueswir1 | unsigned int i; |
4724 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4725 | f5069b26 | blueswir1 | NULL, // g0 not used |
4726 | f5069b26 | blueswir1 | "g1",
|
4727 | f5069b26 | blueswir1 | "g2",
|
4728 | f5069b26 | blueswir1 | "g3",
|
4729 | f5069b26 | blueswir1 | "g4",
|
4730 | f5069b26 | blueswir1 | "g5",
|
4731 | f5069b26 | blueswir1 | "g6",
|
4732 | f5069b26 | blueswir1 | "g7",
|
4733 | f5069b26 | blueswir1 | }; |
4734 | aaed909a | bellard | |
4735 | aaed909a | bellard | def = cpu_sparc_find_by_name(cpu_model); |
4736 | aaed909a | bellard | if (!def)
|
4737 | aaed909a | bellard | return NULL; |
4738 | e80cfcfc | bellard | |
4739 | c68ea704 | bellard | env = qemu_mallocz(sizeof(CPUSPARCState));
|
4740 | c68ea704 | bellard | if (!env)
|
4741 | 0f8a249a | blueswir1 | return NULL; |
4742 | c68ea704 | bellard | cpu_exec_init(env); |
4743 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
4744 | aaed909a | bellard | env->version = def->iu_version; |
4745 | aaed909a | bellard | env->fsr = def->fpu_version; |
4746 | aaed909a | bellard | #if !defined(TARGET_SPARC64)
|
4747 | aaed909a | bellard | env->mmu_bm = def->mmu_bm; |
4748 | 3deaeab7 | blueswir1 | env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
4749 | 3deaeab7 | blueswir1 | env->mmu_cxr_mask = def->mmu_cxr_mask; |
4750 | 3deaeab7 | blueswir1 | env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
4751 | 3deaeab7 | blueswir1 | env->mmu_trcr_mask = def->mmu_trcr_mask; |
4752 | aaed909a | bellard | env->mmuregs[0] |= def->mmu_version;
|
4753 | aaed909a | bellard | cpu_sparc_set_id(env, 0);
|
4754 | aaed909a | bellard | #endif
|
4755 | 1a2fb1c0 | blueswir1 | |
4756 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4757 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4758 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4759 | 1a2fb1c0 | blueswir1 | |
4760 | 1a2fb1c0 | blueswir1 | tcg_set_macro_func(&tcg_ctx, tcg_macro_func); |
4761 | 1a2fb1c0 | blueswir1 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
4762 | db4a4ea4 | blueswir1 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4763 | db4a4ea4 | blueswir1 | offsetof(CPUState, regwptr), |
4764 | db4a4ea4 | blueswir1 | "regwptr");
|
4765 | 1a2fb1c0 | blueswir1 | //#if TARGET_LONG_BITS > HOST_LONG_BITS
|
4766 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4767 | 1a2fb1c0 | blueswir1 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
|
4768 | 1a2fb1c0 | blueswir1 | TCG_AREG0, offsetof(CPUState, t0), "T0");
|
4769 | 1a2fb1c0 | blueswir1 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
|
4770 | 1a2fb1c0 | blueswir1 | TCG_AREG0, offsetof(CPUState, t1), "T1");
|
4771 | 1a2fb1c0 | blueswir1 | cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
|
4772 | 1a2fb1c0 | blueswir1 | TCG_AREG0, offsetof(CPUState, t2), "T2");
|
4773 | dc99a3f2 | blueswir1 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4774 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, xcc), |
4775 | dc99a3f2 | blueswir1 | "xcc");
|
4776 | 1a2fb1c0 | blueswir1 | #else
|
4777 | 1a2fb1c0 | blueswir1 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
4778 | 1a2fb1c0 | blueswir1 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
4779 | 1a2fb1c0 | blueswir1 | cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
4780 | 1a2fb1c0 | blueswir1 | #endif
|
4781 | dc99a3f2 | blueswir1 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4782 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_src), |
4783 | dc99a3f2 | blueswir1 | "cc_src");
|
4784 | d9bdab86 | blueswir1 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4785 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4786 | d9bdab86 | blueswir1 | "cc_src2");
|
4787 | dc99a3f2 | blueswir1 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4788 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_dst), |
4789 | dc99a3f2 | blueswir1 | "cc_dst");
|
4790 | dc99a3f2 | blueswir1 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, |
4791 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, psr), |
4792 | dc99a3f2 | blueswir1 | "psr");
|
4793 | 87e92502 | blueswir1 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4794 | 87e92502 | blueswir1 | TCG_AREG0, offsetof(CPUState, fsr), |
4795 | 87e92502 | blueswir1 | "fsr");
|
4796 | 48d5c82b | blueswir1 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4797 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, pc), |
4798 | 48d5c82b | blueswir1 | "pc");
|
4799 | 48d5c82b | blueswir1 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, |
4800 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, npc), |
4801 | 48d5c82b | blueswir1 | "npc");
|
4802 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
4803 | f5069b26 | blueswir1 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4804 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
4805 | f5069b26 | blueswir1 | gregnames[i]); |
4806 | 1a2fb1c0 | blueswir1 | } |
4807 | 1a2fb1c0 | blueswir1 | |
4808 | aaed909a | bellard | cpu_reset(env); |
4809 | aaed909a | bellard | |
4810 | aaed909a | bellard | return env;
|
4811 | aaed909a | bellard | } |
4812 | aaed909a | bellard | |
4813 | aaed909a | bellard | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
4814 | aaed909a | bellard | { |
4815 | aaed909a | bellard | #if !defined(TARGET_SPARC64)
|
4816 | aaed909a | bellard | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
4817 | aaed909a | bellard | #endif
|
4818 | 7a3f1944 | bellard | } |
4819 | 7a3f1944 | bellard | |
4820 | 62724a37 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
4821 | 62724a37 | blueswir1 | #ifdef TARGET_SPARC64
|
4822 | 62724a37 | blueswir1 | { |
4823 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64",
|
4824 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
4825 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4826 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4827 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4828 | 7d77bf20 | blueswir1 | }, |
4829 | 7d77bf20 | blueswir1 | { |
4830 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
4831 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
4832 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4833 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4834 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4835 | 7d77bf20 | blueswir1 | }, |
4836 | 7d77bf20 | blueswir1 | { |
4837 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
4838 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
4839 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4840 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4841 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4842 | 7d77bf20 | blueswir1 | }, |
4843 | 7d77bf20 | blueswir1 | { |
4844 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
4845 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
4846 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4847 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4848 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4849 | 7d77bf20 | blueswir1 | }, |
4850 | 7d77bf20 | blueswir1 | { |
4851 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc I",
|
4852 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
4853 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4854 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4855 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4856 | 7d77bf20 | blueswir1 | }, |
4857 | 7d77bf20 | blueswir1 | { |
4858 | 62724a37 | blueswir1 | .name = "TI UltraSparc II",
|
4859 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
4860 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4861 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4862 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4863 | 7d77bf20 | blueswir1 | }, |
4864 | 7d77bf20 | blueswir1 | { |
4865 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc IIi",
|
4866 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
4867 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4868 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4869 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4870 | 7d77bf20 | blueswir1 | }, |
4871 | 7d77bf20 | blueswir1 | { |
4872 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc IIe",
|
4873 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
4874 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4875 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4876 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4877 | 7d77bf20 | blueswir1 | }, |
4878 | 7d77bf20 | blueswir1 | { |
4879 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc III",
|
4880 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
4881 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4882 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4883 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4884 | 7d77bf20 | blueswir1 | }, |
4885 | 7d77bf20 | blueswir1 | { |
4886 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
4887 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
4888 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4889 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4890 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4891 | 7d77bf20 | blueswir1 | }, |
4892 | 7d77bf20 | blueswir1 | { |
4893 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
4894 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
4895 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4896 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4897 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4898 | 7d77bf20 | blueswir1 | }, |
4899 | 7d77bf20 | blueswir1 | { |
4900 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IV",
|
4901 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
4902 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4903 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4904 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4905 | 7d77bf20 | blueswir1 | }, |
4906 | 7d77bf20 | blueswir1 | { |
4907 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IV+",
|
4908 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
4909 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4910 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4911 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4912 | 7d77bf20 | blueswir1 | }, |
4913 | 7d77bf20 | blueswir1 | { |
4914 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
4915 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
4916 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4917 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4918 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4919 | 7d77bf20 | blueswir1 | }, |
4920 | 7d77bf20 | blueswir1 | { |
4921 | 7d77bf20 | blueswir1 | .name = "NEC UltraSparc I",
|
4922 | 7d77bf20 | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
4923 | 62724a37 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4924 | 62724a37 | blueswir1 | .fpu_version = 0x00000000,
|
4925 | 62724a37 | blueswir1 | .mmu_version = 0,
|
4926 | 62724a37 | blueswir1 | }, |
4927 | 62724a37 | blueswir1 | #else
|
4928 | 62724a37 | blueswir1 | { |
4929 | 406f82e8 | blueswir1 | .name = "Fujitsu MB86900",
|
4930 | 406f82e8 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
4931 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4932 | 406f82e8 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
4933 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4934 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4935 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4936 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4937 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4938 | 406f82e8 | blueswir1 | }, |
4939 | 406f82e8 | blueswir1 | { |
4940 | 62724a37 | blueswir1 | .name = "Fujitsu MB86904",
|
4941 | 62724a37 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
4942 | 62724a37 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4943 | 62724a37 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
4944 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
4945 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
4946 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
4947 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
4948 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
4949 | 62724a37 | blueswir1 | }, |
4950 | e0353fe2 | blueswir1 | { |
4951 | 5ef62c5c | blueswir1 | .name = "Fujitsu MB86907",
|
4952 | 5ef62c5c | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
4953 | 5ef62c5c | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4954 | 5ef62c5c | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
4955 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
4956 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
4957 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
4958 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
4959 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4960 | 5ef62c5c | blueswir1 | }, |
4961 | 5ef62c5c | blueswir1 | { |
4962 | 406f82e8 | blueswir1 | .name = "LSI L64811",
|
4963 | 406f82e8 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
4964 | 406f82e8 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
4965 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4966 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4967 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4968 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4969 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4970 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4971 | 406f82e8 | blueswir1 | }, |
4972 | 406f82e8 | blueswir1 | { |
4973 | 406f82e8 | blueswir1 | .name = "Cypress CY7C601",
|
4974 | 406f82e8 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
4975 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
4976 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4977 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4978 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4979 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4980 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4981 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4982 | 406f82e8 | blueswir1 | }, |
4983 | 406f82e8 | blueswir1 | { |
4984 | 406f82e8 | blueswir1 | .name = "Cypress CY7C611",
|
4985 | 406f82e8 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
4986 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
4987 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4988 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4989 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4990 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4991 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4992 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4993 | 406f82e8 | blueswir1 | }, |
4994 | 406f82e8 | blueswir1 | { |
4995 | 406f82e8 | blueswir1 | .name = "TI SuperSparc II",
|
4996 | 406f82e8 | blueswir1 | .iu_version = 0x40000000,
|
4997 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
4998 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
4999 | 406f82e8 | blueswir1 | .mmu_bm = 0x00002000,
|
5000 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
5001 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
5002 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5003 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5004 | 406f82e8 | blueswir1 | }, |
5005 | 406f82e8 | blueswir1 | { |
5006 | 5ef62c5c | blueswir1 | .name = "TI MicroSparc I",
|
5007 | 5ef62c5c | blueswir1 | .iu_version = 0x41000000,
|
5008 | 5ef62c5c | blueswir1 | .fpu_version = 4 << 17, |
5009 | 5ef62c5c | blueswir1 | .mmu_version = 0x41000000,
|
5010 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
5011 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5012 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5013 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
5014 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x0000003f,
|
5015 | 5ef62c5c | blueswir1 | }, |
5016 | 5ef62c5c | blueswir1 | { |
5017 | 406f82e8 | blueswir1 | .name = "TI MicroSparc II",
|
5018 | 406f82e8 | blueswir1 | .iu_version = 0x42000000,
|
5019 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, |
5020 | 406f82e8 | blueswir1 | .mmu_version = 0x02000000,
|
5021 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5022 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
5023 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
5024 | a3ffaf30 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
5025 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
5026 | 406f82e8 | blueswir1 | }, |
5027 | 406f82e8 | blueswir1 | { |
5028 | 406f82e8 | blueswir1 | .name = "TI MicroSparc IIep",
|
5029 | 406f82e8 | blueswir1 | .iu_version = 0x42000000,
|
5030 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, |
5031 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
5032 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5033 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
5034 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
5035 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016bff,
|
5036 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
5037 | 406f82e8 | blueswir1 | }, |
5038 | 406f82e8 | blueswir1 | { |
5039 | 406f82e8 | blueswir1 | .name = "TI SuperSparc 51",
|
5040 | 406f82e8 | blueswir1 | .iu_version = 0x43000000,
|
5041 | 5ef62c5c | blueswir1 | .fpu_version = 0 << 17, |
5042 | 5ef62c5c | blueswir1 | .mmu_version = 0x04000000,
|
5043 | 6d5f237a | blueswir1 | .mmu_bm = 0x00002000,
|
5044 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
5045 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
5046 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5047 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5048 | 5ef62c5c | blueswir1 | }, |
5049 | 5ef62c5c | blueswir1 | { |
5050 | 406f82e8 | blueswir1 | .name = "TI SuperSparc 61",
|
5051 | 406f82e8 | blueswir1 | .iu_version = 0x44000000,
|
5052 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
5053 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
5054 | 406f82e8 | blueswir1 | .mmu_bm = 0x00002000,
|
5055 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
5056 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
5057 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5058 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5059 | 406f82e8 | blueswir1 | }, |
5060 | 406f82e8 | blueswir1 | { |
5061 | 406f82e8 | blueswir1 | .name = "Ross RT625",
|
5062 | 5ef62c5c | blueswir1 | .iu_version = 0x1e000000,
|
5063 | 5ef62c5c | blueswir1 | .fpu_version = 1 << 17, |
5064 | 406f82e8 | blueswir1 | .mmu_version = 0x1e000000,
|
5065 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5066 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5067 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5068 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5069 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5070 | 406f82e8 | blueswir1 | }, |
5071 | 406f82e8 | blueswir1 | { |
5072 | 406f82e8 | blueswir1 | .name = "Ross RT620",
|
5073 | 406f82e8 | blueswir1 | .iu_version = 0x1f000000,
|
5074 | 406f82e8 | blueswir1 | .fpu_version = 1 << 17, |
5075 | 406f82e8 | blueswir1 | .mmu_version = 0x1f000000,
|
5076 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5077 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5078 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5079 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5080 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5081 | 406f82e8 | blueswir1 | }, |
5082 | 406f82e8 | blueswir1 | { |
5083 | 406f82e8 | blueswir1 | .name = "BIT B5010",
|
5084 | 406f82e8 | blueswir1 | .iu_version = 0x20000000,
|
5085 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
5086 | 406f82e8 | blueswir1 | .mmu_version = 0x20000000,
|
5087 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5088 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5089 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5090 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5091 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5092 | 406f82e8 | blueswir1 | }, |
5093 | 406f82e8 | blueswir1 | { |
5094 | 406f82e8 | blueswir1 | .name = "Matsushita MN10501",
|
5095 | 406f82e8 | blueswir1 | .iu_version = 0x50000000,
|
5096 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
5097 | 406f82e8 | blueswir1 | .mmu_version = 0x50000000,
|
5098 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5099 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5100 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5101 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5102 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5103 | 406f82e8 | blueswir1 | }, |
5104 | 406f82e8 | blueswir1 | { |
5105 | 406f82e8 | blueswir1 | .name = "Weitek W8601",
|
5106 | 406f82e8 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
5107 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
5108 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
5109 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5110 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5111 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5112 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5113 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5114 | 406f82e8 | blueswir1 | }, |
5115 | 406f82e8 | blueswir1 | { |
5116 | 406f82e8 | blueswir1 | .name = "LEON2",
|
5117 | 406f82e8 | blueswir1 | .iu_version = 0xf2000000,
|
5118 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
5119 | 406f82e8 | blueswir1 | .mmu_version = 0xf2000000,
|
5120 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5121 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5122 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5123 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5124 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5125 | 406f82e8 | blueswir1 | }, |
5126 | 406f82e8 | blueswir1 | { |
5127 | 406f82e8 | blueswir1 | .name = "LEON3",
|
5128 | 406f82e8 | blueswir1 | .iu_version = 0xf3000000,
|
5129 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
5130 | 406f82e8 | blueswir1 | .mmu_version = 0xf3000000,
|
5131 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
5132 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5133 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5134 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5135 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5136 | e0353fe2 | blueswir1 | }, |
5137 | 62724a37 | blueswir1 | #endif
|
5138 | 62724a37 | blueswir1 | }; |
5139 | 62724a37 | blueswir1 | |
5140 | aaed909a | bellard | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
5141 | 62724a37 | blueswir1 | { |
5142 | 62724a37 | blueswir1 | unsigned int i; |
5143 | 62724a37 | blueswir1 | |
5144 | 62724a37 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
5145 | 62724a37 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
5146 | aaed909a | bellard | return &sparc_defs[i];
|
5147 | 62724a37 | blueswir1 | } |
5148 | 62724a37 | blueswir1 | } |
5149 | aaed909a | bellard | return NULL; |
5150 | 62724a37 | blueswir1 | } |
5151 | 62724a37 | blueswir1 | |
5152 | 62724a37 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
5153 | 62724a37 | blueswir1 | { |
5154 | 62724a37 | blueswir1 | unsigned int i; |
5155 | 62724a37 | blueswir1 | |
5156 | 62724a37 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
5157 | 62724a37 | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
5158 | 62724a37 | blueswir1 | sparc_defs[i].name, |
5159 | 62724a37 | blueswir1 | sparc_defs[i].iu_version, |
5160 | 62724a37 | blueswir1 | sparc_defs[i].fpu_version, |
5161 | 62724a37 | blueswir1 | sparc_defs[i].mmu_version); |
5162 | 62724a37 | blueswir1 | } |
5163 | 62724a37 | blueswir1 | } |
5164 | 62724a37 | blueswir1 | |
5165 | 7a3f1944 | bellard | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
5166 | 7a3f1944 | bellard | |
5167 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
5168 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
5169 | 7fe48483 | bellard | int flags)
|
5170 | 7a3f1944 | bellard | { |
5171 | cf495bcf | bellard | int i, x;
|
5172 | cf495bcf | bellard | |
5173 | af7bf89b | bellard | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
5174 | 7fe48483 | bellard | cpu_fprintf(f, "General Registers:\n");
|
5175 | cf495bcf | bellard | for (i = 0; i < 4; i++) |
5176 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
5177 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
5178 | cf495bcf | bellard | for (; i < 8; i++) |
5179 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
5180 | 7fe48483 | bellard | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
5181 | cf495bcf | bellard | for (x = 0; x < 3; x++) { |
5182 | 0f8a249a | blueswir1 | for (i = 0; i < 4; i++) |
5183 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
5184 | 0f8a249a | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
5185 | 0f8a249a | blueswir1 | env->regwptr[i + x * 8]);
|
5186 | 0f8a249a | blueswir1 | cpu_fprintf(f, "\n");
|
5187 | 0f8a249a | blueswir1 | for (; i < 8; i++) |
5188 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
5189 | 0f8a249a | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
5190 | 0f8a249a | blueswir1 | env->regwptr[i + x * 8]);
|
5191 | 0f8a249a | blueswir1 | cpu_fprintf(f, "\n");
|
5192 | cf495bcf | bellard | } |
5193 | 7fe48483 | bellard | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
5194 | e8af50a3 | bellard | for (i = 0; i < 32; i++) { |
5195 | e8af50a3 | bellard | if ((i & 3) == 0) |
5196 | 7fe48483 | bellard | cpu_fprintf(f, "%%f%02d:", i);
|
5197 | 7fe48483 | bellard | cpu_fprintf(f, " %016lf", env->fpr[i]);
|
5198 | e8af50a3 | bellard | if ((i & 3) == 3) |
5199 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
5200 | e8af50a3 | bellard | } |
5201 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
5202 | 3299908c | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
5203 | 0f8a249a | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
5204 | ded3ab80 | pbrook | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
5205 | 0f8a249a | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
5206 | 0f8a249a | blueswir1 | env->cleanwin, NWINDOWS - 1 - env->cwp);
|
5207 | ded3ab80 | pbrook | #else
|
5208 | 7fe48483 | bellard | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
5209 | 0f8a249a | blueswir1 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
5210 | 0f8a249a | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
5211 | 0f8a249a | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
5212 | 0f8a249a | blueswir1 | env->psret?'E':'-', env->wim); |
5213 | ded3ab80 | pbrook | #endif
|
5214 | 3475187d | bellard | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
5215 | 7a3f1944 | bellard | } |
5216 | edfcbd99 | bellard | |
5217 | e80cfcfc | bellard | #if defined(CONFIG_USER_ONLY)
|
5218 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
5219 | edfcbd99 | bellard | { |
5220 | edfcbd99 | bellard | return addr;
|
5221 | edfcbd99 | bellard | } |
5222 | 658138bc | bellard | |
5223 | e80cfcfc | bellard | #else
|
5224 | af7bf89b | bellard | extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
5225 | af7bf89b | bellard | int *access_index, target_ulong address, int rw, |
5226 | 6ebbf390 | j_mayer | int mmu_idx);
|
5227 | 0fa85d43 | bellard | |
5228 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
5229 | e80cfcfc | bellard | { |
5230 | af7bf89b | bellard | target_phys_addr_t phys_addr; |
5231 | e80cfcfc | bellard | int prot, access_index;
|
5232 | e80cfcfc | bellard | |
5233 | 9e31b9e2 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
5234 | 9e31b9e2 | blueswir1 | MMU_KERNEL_IDX) != 0)
|
5235 | 9e31b9e2 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
5236 | 9e31b9e2 | blueswir1 | 0, MMU_KERNEL_IDX) != 0) |
5237 | 6b1575b7 | bellard | return -1; |
5238 | 6c36d3fa | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
5239 | 6c36d3fa | blueswir1 | return -1; |
5240 | e80cfcfc | bellard | return phys_addr;
|
5241 | e80cfcfc | bellard | } |
5242 | e80cfcfc | bellard | #endif
|
5243 | e80cfcfc | bellard | |
5244 | 658138bc | bellard | void helper_flush(target_ulong addr)
|
5245 | 658138bc | bellard | { |
5246 | 658138bc | bellard | addr &= ~7;
|
5247 | 658138bc | bellard | tb_invalidate_page_range(addr, addr + 8);
|
5248 | 658138bc | bellard | } |