root / hw / lm832x.c @ 2bc6f59b
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/*
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* National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "i2c.h" |
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#include "qemu-timer.h" |
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#include "console.h" |
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typedef struct { |
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i2c_slave i2c; |
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uint8_t i2c_dir; |
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uint8_t i2c_cycle; |
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uint8_t reg; |
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qemu_irq nirq; |
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uint16_t model; |
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struct {
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qemu_irq out[2];
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int in[2][2]; |
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} mux; |
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uint8_t config; |
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uint8_t status; |
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uint8_t acttime; |
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uint8_t error; |
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uint8_t clock; |
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struct {
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uint16_t pull; |
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uint16_t mask; |
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uint16_t dir; |
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uint16_t level; |
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qemu_irq out[16];
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} gpio; |
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struct {
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uint8_t dbnctime; |
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uint8_t size; |
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uint8_t start; |
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uint8_t len; |
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uint8_t fifo[16];
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} kbd; |
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|
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struct {
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uint16_t file[256];
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uint8_t faddr; |
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uint8_t addr[3];
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QEMUTimer *tm[3];
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} pwm; |
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} LM823KbdState; |
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#define INT_KEYPAD (1 << 0) |
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#define INT_ERROR (1 << 3) |
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#define INT_NOINIT (1 << 4) |
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#define INT_PWMEND(n) (1 << (5 + n)) |
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|
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#define ERR_BADPAR (1 << 0) |
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#define ERR_CMDUNK (1 << 1) |
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#define ERR_KEYOVR (1 << 2) |
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#define ERR_FIFOOVR (1 << 6) |
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static void lm_kbd_irq_update(LM823KbdState *s) |
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{ |
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qemu_set_irq(s->nirq, !s->status); |
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} |
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static void lm_kbd_gpio_update(LM823KbdState *s) |
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{ |
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} |
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static void lm_kbd_reset(LM823KbdState *s) |
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{ |
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s->config = 0x80;
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s->status = INT_NOINIT; |
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s->acttime = 125;
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s->kbd.dbnctime = 3;
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s->kbd.size = 0x33;
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s->clock = 0x08;
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lm_kbd_irq_update(s); |
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lm_kbd_gpio_update(s); |
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} |
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static void lm_kbd_error(LM823KbdState *s, int err) |
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{ |
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s->error |= err; |
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s->status |= INT_ERROR; |
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lm_kbd_irq_update(s); |
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} |
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static void lm_kbd_pwm_tick(LM823KbdState *s, int line) |
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{ |
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} |
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static void lm_kbd_pwm_start(LM823KbdState *s, int line) |
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{ |
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lm_kbd_pwm_tick(s, line); |
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} |
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static void lm_kbd_pwm0_tick(void *opaque) |
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{ |
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lm_kbd_pwm_tick(opaque, 0);
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} |
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static void lm_kbd_pwm1_tick(void *opaque) |
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{ |
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lm_kbd_pwm_tick(opaque, 1);
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} |
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static void lm_kbd_pwm2_tick(void *opaque) |
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{ |
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lm_kbd_pwm_tick(opaque, 2);
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} |
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enum {
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LM832x_CMD_READ_ID = 0x80, /* Read chip ID. */ |
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LM832x_CMD_WRITE_CFG = 0x81, /* Set configuration item. */ |
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LM832x_CMD_READ_INT = 0x82, /* Get interrupt status. */ |
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LM832x_CMD_RESET = 0x83, /* Reset, same as external one */ |
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LM823x_CMD_WRITE_PULL_DOWN = 0x84, /* Select GPIO pull-up/down. */ |
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LM832x_CMD_WRITE_PORT_SEL = 0x85, /* Select GPIO in/out. */ |
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LM832x_CMD_WRITE_PORT_STATE = 0x86, /* Set GPIO pull-up/down. */ |
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LM832x_CMD_READ_PORT_SEL = 0x87, /* Get GPIO in/out. */ |
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LM832x_CMD_READ_PORT_STATE = 0x88, /* Get GPIO pull-up/down. */ |
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LM832x_CMD_READ_FIFO = 0x89, /* Read byte from FIFO. */ |
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LM832x_CMD_RPT_READ_FIFO = 0x8a, /* Read FIFO (no increment). */ |
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LM832x_CMD_SET_ACTIVE = 0x8b, /* Set active time. */ |
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LM832x_CMD_READ_ERROR = 0x8c, /* Get error status. */ |
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LM832x_CMD_READ_ROTATOR = 0x8e, /* Read rotator status. */ |
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LM832x_CMD_SET_DEBOUNCE = 0x8f, /* Set debouncing time. */ |
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LM832x_CMD_SET_KEY_SIZE = 0x90, /* Set keypad size. */ |
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LM832x_CMD_READ_KEY_SIZE = 0x91, /* Get keypad size. */ |
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LM832x_CMD_READ_CFG = 0x92, /* Get configuration item. */ |
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LM832x_CMD_WRITE_CLOCK = 0x93, /* Set clock config. */ |
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LM832x_CMD_READ_CLOCK = 0x94, /* Get clock config. */ |
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LM832x_CMD_PWM_WRITE = 0x95, /* Write PWM script. */ |
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LM832x_CMD_PWM_START = 0x96, /* Start PWM engine. */ |
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LM832x_CMD_PWM_STOP = 0x97, /* Stop PWM engine. */ |
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LM832x_GENERAL_ERROR = 0xff, /* There was one error. |
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Previously was represented by -1
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This is not a command */
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}; |
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#define LM832x_MAX_KPX 8 |
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#define LM832x_MAX_KPY 12 |
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static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte) |
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{ |
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int ret;
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switch (reg) {
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case LM832x_CMD_READ_ID:
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ret = 0x0400;
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break;
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case LM832x_CMD_READ_INT:
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ret = s->status; |
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if (!(s->status & INT_NOINIT)) {
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s->status = 0;
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lm_kbd_irq_update(s); |
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} |
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break;
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case LM832x_CMD_READ_PORT_SEL:
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ret = s->gpio.dir; |
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break;
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case LM832x_CMD_READ_PORT_STATE:
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ret = s->gpio.mask; |
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break;
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case LM832x_CMD_READ_FIFO:
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if (s->kbd.len <= 1) |
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return 0x00; |
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/* Example response from the two commands after a INT_KEYPAD
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* interrupt caused by the key 0x3c being pressed:
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* RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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* READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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* RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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*
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* 55 is the code of the key release event serviced in the previous
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* interrupt handling.
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*
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* TODO: find out whether the FIFO is advanced a single character
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* before reading every byte or the whole size of the FIFO at the
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* last LM832x_CMD_READ_FIFO. This affects LM832x_CMD_RPT_READ_FIFO
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* output in cases where there are more than one event in the FIFO.
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* Assume 0xbc and 0x3c events are in the FIFO:
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* RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
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* READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
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* Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
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*/
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s->kbd.start ++; |
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s->kbd.start &= sizeof(s->kbd.fifo) - 1; |
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s->kbd.len --; |
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return s->kbd.fifo[s->kbd.start];
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case LM832x_CMD_RPT_READ_FIFO:
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if (byte >= s->kbd.len)
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return 0x00; |
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return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)]; |
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case LM832x_CMD_READ_ERROR:
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return s->error;
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case LM832x_CMD_READ_ROTATOR:
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return 0; |
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case LM832x_CMD_READ_KEY_SIZE:
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return s->kbd.size;
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case LM832x_CMD_READ_CFG:
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return s->config & 0xf; |
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case LM832x_CMD_READ_CLOCK:
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return (s->clock & 0xfc) | 2; |
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default:
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lm_kbd_error(s, ERR_CMDUNK); |
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fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg);
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return 0x00; |
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} |
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return ret >> (byte << 3); |
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} |
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static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value) |
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{ |
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switch (reg) {
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case LM832x_CMD_WRITE_CFG:
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s->config = value; |
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/* This must be done whenever s->mux.in is updated (never). */
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if ((s->config >> 1) & 1) /* MUX1EN */ |
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qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]); |
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if ((s->config >> 3) & 1) /* MUX2EN */ |
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qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]); |
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/* TODO: check that this is issued only following the chip reset
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* and not in the middle of operation and that it is followed by
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* the GPIO ports re-resablishing through WRITE_PORT_SEL and
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* WRITE_PORT_STATE (using a timer perhaps) and otherwise output
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* warnings. */
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s->status = 0;
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lm_kbd_irq_update(s); |
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s->kbd.len = 0;
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s->kbd.start = 0;
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s->reg = LM832x_GENERAL_ERROR; |
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break;
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case LM832x_CMD_RESET:
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if (value == 0xaa) |
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lm_kbd_reset(s); |
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else
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lm_kbd_error(s, ERR_BADPAR); |
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s->reg = LM832x_GENERAL_ERROR; |
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break;
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case LM823x_CMD_WRITE_PULL_DOWN:
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if (!byte)
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s->gpio.pull = value; |
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else {
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s->gpio.pull |= value << 8;
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lm_kbd_gpio_update(s); |
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s->reg = LM832x_GENERAL_ERROR; |
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} |
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break;
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case LM832x_CMD_WRITE_PORT_SEL:
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if (!byte)
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s->gpio.dir = value; |
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else {
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s->gpio.dir |= value << 8;
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lm_kbd_gpio_update(s); |
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s->reg = LM832x_GENERAL_ERROR; |
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} |
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break;
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case LM832x_CMD_WRITE_PORT_STATE:
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if (!byte)
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s->gpio.mask = value; |
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else {
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s->gpio.mask |= value << 8;
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lm_kbd_gpio_update(s); |
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s->reg = LM832x_GENERAL_ERROR; |
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} |
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break;
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case LM832x_CMD_SET_ACTIVE:
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s->acttime = value; |
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s->reg = LM832x_GENERAL_ERROR; |
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break;
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case LM832x_CMD_SET_DEBOUNCE:
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s->kbd.dbnctime = value; |
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s->reg = LM832x_GENERAL_ERROR; |
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if (!value)
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lm_kbd_error(s, ERR_BADPAR); |
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break;
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case LM832x_CMD_SET_KEY_SIZE:
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s->kbd.size = value; |
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s->reg = LM832x_GENERAL_ERROR; |
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if (
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(value & 0xf) < 3 || (value & 0xf) > LM832x_MAX_KPY || |
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(value >> 4) < 3 || (value >> 4) > LM832x_MAX_KPX) |
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lm_kbd_error(s, ERR_BADPAR); |
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break;
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|
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case LM832x_CMD_WRITE_CLOCK:
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s->clock = value; |
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s->reg = LM832x_GENERAL_ERROR; |
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if ((value & 3) && (value & 3) != 3) { |
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lm_kbd_error(s, ERR_BADPAR); |
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fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
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__FUNCTION__); |
330 |
} |
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/* TODO: Validate that the command is only issued once */
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break;
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|
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case LM832x_CMD_PWM_WRITE:
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if (byte == 0) { |
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if (!(value & 3) || (value >> 2) > 59) { |
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lm_kbd_error(s, ERR_BADPAR); |
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s->reg = LM832x_GENERAL_ERROR; |
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break;
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} |
341 |
|
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s->pwm.faddr = value; |
343 |
s->pwm.file[s->pwm.faddr] = 0;
|
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} else if (byte == 1) { |
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s->pwm.file[s->pwm.faddr] |= value << 8;
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} else if (byte == 2) { |
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s->pwm.file[s->pwm.faddr] |= value << 0;
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s->reg = LM832x_GENERAL_ERROR; |
349 |
} |
350 |
break;
|
351 |
case LM832x_CMD_PWM_START:
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s->reg = LM832x_GENERAL_ERROR; |
353 |
if (!(value & 3) || (value >> 2) > 59) { |
354 |
lm_kbd_error(s, ERR_BADPAR); |
355 |
break;
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356 |
} |
357 |
|
358 |
s->pwm.addr[(value & 3) - 1] = value >> 2; |
359 |
lm_kbd_pwm_start(s, (value & 3) - 1); |
360 |
break;
|
361 |
case LM832x_CMD_PWM_STOP:
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362 |
s->reg = LM832x_GENERAL_ERROR; |
363 |
if (!(value & 3)) { |
364 |
lm_kbd_error(s, ERR_BADPAR); |
365 |
break;
|
366 |
} |
367 |
|
368 |
qemu_del_timer(s->pwm.tm[(value & 3) - 1]); |
369 |
break;
|
370 |
|
371 |
case LM832x_GENERAL_ERROR:
|
372 |
lm_kbd_error(s, ERR_BADPAR); |
373 |
break;
|
374 |
default:
|
375 |
lm_kbd_error(s, ERR_CMDUNK); |
376 |
fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg);
|
377 |
break;
|
378 |
} |
379 |
} |
380 |
|
381 |
static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event) |
382 |
{ |
383 |
LM823KbdState *s = FROM_I2C_SLAVE(LM823KbdState, i2c); |
384 |
|
385 |
switch (event) {
|
386 |
case I2C_START_RECV:
|
387 |
case I2C_START_SEND:
|
388 |
s->i2c_cycle = 0;
|
389 |
s->i2c_dir = (event == I2C_START_SEND); |
390 |
break;
|
391 |
|
392 |
default:
|
393 |
break;
|
394 |
} |
395 |
} |
396 |
|
397 |
static int lm_i2c_rx(i2c_slave *i2c) |
398 |
{ |
399 |
LM823KbdState *s = FROM_I2C_SLAVE(LM823KbdState, i2c); |
400 |
|
401 |
return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
|
402 |
} |
403 |
|
404 |
static int lm_i2c_tx(i2c_slave *i2c, uint8_t data) |
405 |
{ |
406 |
LM823KbdState *s = (LM823KbdState *) i2c; |
407 |
|
408 |
if (!s->i2c_cycle)
|
409 |
s->reg = data; |
410 |
else
|
411 |
lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
|
412 |
s->i2c_cycle ++; |
413 |
|
414 |
return 0; |
415 |
} |
416 |
|
417 |
static int lm_kbd_post_load(void *opaque, int version_id) |
418 |
{ |
419 |
LM823KbdState *s = opaque; |
420 |
|
421 |
lm_kbd_irq_update(s); |
422 |
lm_kbd_gpio_update(s); |
423 |
|
424 |
return 0; |
425 |
} |
426 |
|
427 |
static const VMStateDescription vmstate_lm_kbd = { |
428 |
.name = "LM8323",
|
429 |
.version_id = 0,
|
430 |
.minimum_version_id = 0,
|
431 |
.minimum_version_id_old = 0,
|
432 |
.post_load = lm_kbd_post_load, |
433 |
.fields = (VMStateField []) { |
434 |
VMSTATE_I2C_SLAVE(i2c, LM823KbdState), |
435 |
VMSTATE_UINT8(i2c_dir, LM823KbdState), |
436 |
VMSTATE_UINT8(i2c_cycle, LM823KbdState), |
437 |
VMSTATE_UINT8(reg, LM823KbdState), |
438 |
VMSTATE_UINT8(config, LM823KbdState), |
439 |
VMSTATE_UINT8(status, LM823KbdState), |
440 |
VMSTATE_UINT8(acttime, LM823KbdState), |
441 |
VMSTATE_UINT8(error, LM823KbdState), |
442 |
VMSTATE_UINT8(clock, LM823KbdState), |
443 |
VMSTATE_UINT16(gpio.pull, LM823KbdState), |
444 |
VMSTATE_UINT16(gpio.mask, LM823KbdState), |
445 |
VMSTATE_UINT16(gpio.dir, LM823KbdState), |
446 |
VMSTATE_UINT16(gpio.level, LM823KbdState), |
447 |
VMSTATE_UINT8(kbd.dbnctime, LM823KbdState), |
448 |
VMSTATE_UINT8(kbd.size, LM823KbdState), |
449 |
VMSTATE_UINT8(kbd.start, LM823KbdState), |
450 |
VMSTATE_UINT8(kbd.len, LM823KbdState), |
451 |
VMSTATE_BUFFER(kbd.fifo, LM823KbdState), |
452 |
VMSTATE_UINT16_ARRAY(pwm.file, LM823KbdState, 256),
|
453 |
VMSTATE_UINT8(pwm.faddr, LM823KbdState), |
454 |
VMSTATE_BUFFER(pwm.addr, LM823KbdState), |
455 |
VMSTATE_TIMER_ARRAY(pwm.tm, LM823KbdState, 3),
|
456 |
VMSTATE_END_OF_LIST() |
457 |
} |
458 |
}; |
459 |
|
460 |
|
461 |
static int lm8323_init(i2c_slave *i2c) |
462 |
{ |
463 |
LM823KbdState *s = FROM_I2C_SLAVE(LM823KbdState, i2c); |
464 |
|
465 |
s->model = 0x8323;
|
466 |
s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s);
|
467 |
s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s);
|
468 |
s->pwm.tm[2] = qemu_new_timer(vm_clock, lm_kbd_pwm2_tick, s);
|
469 |
qdev_init_gpio_out(&i2c->qdev, &s->nirq, 1);
|
470 |
|
471 |
lm_kbd_reset(s); |
472 |
|
473 |
qemu_register_reset((void *) lm_kbd_reset, s);
|
474 |
vmstate_register(-1, &vmstate_lm_kbd, s);
|
475 |
return 0; |
476 |
} |
477 |
|
478 |
void lm832x_key_event(struct i2c_slave *i2c, int key, int state) |
479 |
{ |
480 |
LM823KbdState *s = (LM823KbdState *) i2c; |
481 |
|
482 |
if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
|
483 |
return;
|
484 |
|
485 |
if (s->kbd.len >= sizeof(s->kbd.fifo)) { |
486 |
lm_kbd_error(s, ERR_FIFOOVR); |
487 |
return;
|
488 |
} |
489 |
|
490 |
s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] = |
491 |
key | (state << 7);
|
492 |
|
493 |
/* We never set ERR_KEYOVR because we support multiple keys fine. */
|
494 |
s->status |= INT_KEYPAD; |
495 |
lm_kbd_irq_update(s); |
496 |
} |
497 |
|
498 |
static I2CSlaveInfo lm8323_info = {
|
499 |
.qdev.name = "lm8323",
|
500 |
.qdev.size = sizeof(LM823KbdState),
|
501 |
.init = lm8323_init, |
502 |
.event = lm_i2c_event, |
503 |
.recv = lm_i2c_rx, |
504 |
.send = lm_i2c_tx |
505 |
}; |
506 |
|
507 |
static void lm832x_register_devices(void) |
508 |
{ |
509 |
i2c_register_slave(&lm8323_info); |
510 |
} |
511 |
|
512 |
device_init(lm832x_register_devices) |