root / hw / pxa2xx_mmci.c @ 2bf90458
History | View | Annotate | Download (14.2 kB)
1 |
/*
|
---|---|
2 |
* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
|
3 |
*
|
4 |
* Copyright (c) 2006 Openedhand Ltd.
|
5 |
* Written by Andrzej Zaborowski <balrog@zabor.org>
|
6 |
*
|
7 |
* This code is licensed under the GPLv2.
|
8 |
*/
|
9 |
|
10 |
#include "hw.h" |
11 |
#include "pxa.h" |
12 |
#include "sd.h" |
13 |
#include "qdev.h" |
14 |
|
15 |
struct PXA2xxMMCIState {
|
16 |
MemoryRegion iomem; |
17 |
qemu_irq irq; |
18 |
qemu_irq rx_dma; |
19 |
qemu_irq tx_dma; |
20 |
|
21 |
SDState *card; |
22 |
|
23 |
uint32_t status; |
24 |
uint32_t clkrt; |
25 |
uint32_t spi; |
26 |
uint32_t cmdat; |
27 |
uint32_t resp_tout; |
28 |
uint32_t read_tout; |
29 |
int blklen;
|
30 |
int numblk;
|
31 |
uint32_t intmask; |
32 |
uint32_t intreq; |
33 |
int cmd;
|
34 |
uint32_t arg; |
35 |
|
36 |
int active;
|
37 |
int bytesleft;
|
38 |
uint8_t tx_fifo[64];
|
39 |
int tx_start;
|
40 |
int tx_len;
|
41 |
uint8_t rx_fifo[32];
|
42 |
int rx_start;
|
43 |
int rx_len;
|
44 |
uint16_t resp_fifo[9];
|
45 |
int resp_len;
|
46 |
|
47 |
int cmdreq;
|
48 |
int ac_width;
|
49 |
}; |
50 |
|
51 |
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ |
52 |
#define MMC_STAT 0x04 /* MMC Status register */ |
53 |
#define MMC_CLKRT 0x08 /* MMC Clock Rate register */ |
54 |
#define MMC_SPI 0x0c /* MMC SPI Mode register */ |
55 |
#define MMC_CMDAT 0x10 /* MMC Command/Data register */ |
56 |
#define MMC_RESTO 0x14 /* MMC Response Time-Out register */ |
57 |
#define MMC_RDTO 0x18 /* MMC Read Time-Out register */ |
58 |
#define MMC_BLKLEN 0x1c /* MMC Block Length register */ |
59 |
#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ |
60 |
#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ |
61 |
#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */ |
62 |
#define MMC_I_REG 0x2c /* MMC Interrupt Request register */ |
63 |
#define MMC_CMD 0x30 /* MMC Command register */ |
64 |
#define MMC_ARGH 0x34 /* MMC Argument High register */ |
65 |
#define MMC_ARGL 0x38 /* MMC Argument Low register */ |
66 |
#define MMC_RES 0x3c /* MMC Response FIFO */ |
67 |
#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */ |
68 |
#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */ |
69 |
#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ |
70 |
#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ |
71 |
|
72 |
/* Bitfield masks */
|
73 |
#define STRPCL_STOP_CLK (1 << 0) |
74 |
#define STRPCL_STRT_CLK (1 << 1) |
75 |
#define STAT_TOUT_RES (1 << 1) |
76 |
#define STAT_CLK_EN (1 << 8) |
77 |
#define STAT_DATA_DONE (1 << 11) |
78 |
#define STAT_PRG_DONE (1 << 12) |
79 |
#define STAT_END_CMDRES (1 << 13) |
80 |
#define SPI_SPI_MODE (1 << 0) |
81 |
#define CMDAT_RES_TYPE (3 << 0) |
82 |
#define CMDAT_DATA_EN (1 << 2) |
83 |
#define CMDAT_WR_RD (1 << 3) |
84 |
#define CMDAT_DMA_EN (1 << 7) |
85 |
#define CMDAT_STOP_TRAN (1 << 10) |
86 |
#define INT_DATA_DONE (1 << 0) |
87 |
#define INT_PRG_DONE (1 << 1) |
88 |
#define INT_END_CMD (1 << 2) |
89 |
#define INT_STOP_CMD (1 << 3) |
90 |
#define INT_CLK_OFF (1 << 4) |
91 |
#define INT_RXFIFO_REQ (1 << 5) |
92 |
#define INT_TXFIFO_REQ (1 << 6) |
93 |
#define INT_TINT (1 << 7) |
94 |
#define INT_DAT_ERR (1 << 8) |
95 |
#define INT_RES_ERR (1 << 9) |
96 |
#define INT_RD_STALLED (1 << 10) |
97 |
#define INT_SDIO_INT (1 << 11) |
98 |
#define INT_SDIO_SACK (1 << 12) |
99 |
#define PRTBUF_PRT_BUF (1 << 0) |
100 |
|
101 |
/* Route internal interrupt lines to the global IC and DMA */
|
102 |
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s) |
103 |
{ |
104 |
uint32_t mask = s->intmask; |
105 |
if (s->cmdat & CMDAT_DMA_EN) {
|
106 |
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; |
107 |
|
108 |
qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ)); |
109 |
qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ)); |
110 |
} |
111 |
|
112 |
qemu_set_irq(s->irq, !!(s->intreq & ~mask)); |
113 |
} |
114 |
|
115 |
static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s) |
116 |
{ |
117 |
if (!s->active)
|
118 |
return;
|
119 |
|
120 |
if (s->cmdat & CMDAT_WR_RD) {
|
121 |
while (s->bytesleft && s->tx_len) {
|
122 |
sd_write_data(s->card, s->tx_fifo[s->tx_start ++]); |
123 |
s->tx_start &= 0x1f;
|
124 |
s->tx_len --; |
125 |
s->bytesleft --; |
126 |
} |
127 |
if (s->bytesleft)
|
128 |
s->intreq |= INT_TXFIFO_REQ; |
129 |
} else
|
130 |
while (s->bytesleft && s->rx_len < 32) { |
131 |
s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
|
132 |
sd_read_data(s->card); |
133 |
s->bytesleft --; |
134 |
s->intreq |= INT_RXFIFO_REQ; |
135 |
} |
136 |
|
137 |
if (!s->bytesleft) {
|
138 |
s->active = 0;
|
139 |
s->intreq |= INT_DATA_DONE; |
140 |
s->status |= STAT_DATA_DONE; |
141 |
|
142 |
if (s->cmdat & CMDAT_WR_RD) {
|
143 |
s->intreq |= INT_PRG_DONE; |
144 |
s->status |= STAT_PRG_DONE; |
145 |
} |
146 |
} |
147 |
|
148 |
pxa2xx_mmci_int_update(s); |
149 |
} |
150 |
|
151 |
static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s) |
152 |
{ |
153 |
int rsplen, i;
|
154 |
SDRequest request; |
155 |
uint8_t response[16];
|
156 |
|
157 |
s->active = 1;
|
158 |
s->rx_len = 0;
|
159 |
s->tx_len = 0;
|
160 |
s->cmdreq = 0;
|
161 |
|
162 |
request.cmd = s->cmd; |
163 |
request.arg = s->arg; |
164 |
request.crc = 0; /* FIXME */ |
165 |
|
166 |
rsplen = sd_do_command(s->card, &request, response); |
167 |
s->intreq |= INT_END_CMD; |
168 |
|
169 |
memset(s->resp_fifo, 0, sizeof(s->resp_fifo)); |
170 |
switch (s->cmdat & CMDAT_RES_TYPE) {
|
171 |
#define PXAMMCI_RESP(wd, value0, value1) \
|
172 |
s->resp_fifo[(wd) + 0] |= (value0); \
|
173 |
s->resp_fifo[(wd) + 1] |= (value1) << 8; |
174 |
case 0: /* No response */ |
175 |
goto complete;
|
176 |
|
177 |
case 1: /* R1, R4, R5 or R6 */ |
178 |
if (rsplen < 4) |
179 |
goto timeout;
|
180 |
goto complete;
|
181 |
|
182 |
case 2: /* R2 */ |
183 |
if (rsplen < 16) |
184 |
goto timeout;
|
185 |
goto complete;
|
186 |
|
187 |
case 3: /* R3 */ |
188 |
if (rsplen < 4) |
189 |
goto timeout;
|
190 |
goto complete;
|
191 |
|
192 |
complete:
|
193 |
for (i = 0; rsplen > 0; i ++, rsplen -= 2) { |
194 |
PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]); |
195 |
} |
196 |
s->status |= STAT_END_CMDRES; |
197 |
|
198 |
if (!(s->cmdat & CMDAT_DATA_EN))
|
199 |
s->active = 0;
|
200 |
else
|
201 |
s->bytesleft = s->numblk * s->blklen; |
202 |
|
203 |
s->resp_len = 0;
|
204 |
break;
|
205 |
|
206 |
timeout:
|
207 |
s->active = 0;
|
208 |
s->status |= STAT_TOUT_RES; |
209 |
break;
|
210 |
} |
211 |
|
212 |
pxa2xx_mmci_fifo_update(s); |
213 |
} |
214 |
|
215 |
static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) |
216 |
{ |
217 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
218 |
uint32_t ret; |
219 |
|
220 |
switch (offset) {
|
221 |
case MMC_STRPCL:
|
222 |
return 0; |
223 |
case MMC_STAT:
|
224 |
return s->status;
|
225 |
case MMC_CLKRT:
|
226 |
return s->clkrt;
|
227 |
case MMC_SPI:
|
228 |
return s->spi;
|
229 |
case MMC_CMDAT:
|
230 |
return s->cmdat;
|
231 |
case MMC_RESTO:
|
232 |
return s->resp_tout;
|
233 |
case MMC_RDTO:
|
234 |
return s->read_tout;
|
235 |
case MMC_BLKLEN:
|
236 |
return s->blklen;
|
237 |
case MMC_NUMBLK:
|
238 |
return s->numblk;
|
239 |
case MMC_PRTBUF:
|
240 |
return 0; |
241 |
case MMC_I_MASK:
|
242 |
return s->intmask;
|
243 |
case MMC_I_REG:
|
244 |
return s->intreq;
|
245 |
case MMC_CMD:
|
246 |
return s->cmd | 0x40; |
247 |
case MMC_ARGH:
|
248 |
return s->arg >> 16; |
249 |
case MMC_ARGL:
|
250 |
return s->arg & 0xffff; |
251 |
case MMC_RES:
|
252 |
if (s->resp_len < 9) |
253 |
return s->resp_fifo[s->resp_len ++];
|
254 |
return 0; |
255 |
case MMC_RXFIFO:
|
256 |
ret = 0;
|
257 |
while (s->ac_width -- && s->rx_len) {
|
258 |
ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
|
259 |
s->rx_start &= 0x1f;
|
260 |
s->rx_len --; |
261 |
} |
262 |
s->intreq &= ~INT_RXFIFO_REQ; |
263 |
pxa2xx_mmci_fifo_update(s); |
264 |
return ret;
|
265 |
case MMC_RDWAIT:
|
266 |
return 0; |
267 |
case MMC_BLKS_REM:
|
268 |
return s->numblk;
|
269 |
default:
|
270 |
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
271 |
} |
272 |
|
273 |
return 0; |
274 |
} |
275 |
|
276 |
static void pxa2xx_mmci_write(void *opaque, |
277 |
target_phys_addr_t offset, uint32_t value) |
278 |
{ |
279 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
280 |
|
281 |
switch (offset) {
|
282 |
case MMC_STRPCL:
|
283 |
if (value & STRPCL_STRT_CLK) {
|
284 |
s->status |= STAT_CLK_EN; |
285 |
s->intreq &= ~INT_CLK_OFF; |
286 |
|
287 |
if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
|
288 |
s->status &= STAT_CLK_EN; |
289 |
pxa2xx_mmci_wakequeues(s); |
290 |
} |
291 |
} |
292 |
|
293 |
if (value & STRPCL_STOP_CLK) {
|
294 |
s->status &= ~STAT_CLK_EN; |
295 |
s->intreq |= INT_CLK_OFF; |
296 |
s->active = 0;
|
297 |
} |
298 |
|
299 |
pxa2xx_mmci_int_update(s); |
300 |
break;
|
301 |
|
302 |
case MMC_CLKRT:
|
303 |
s->clkrt = value & 7;
|
304 |
break;
|
305 |
|
306 |
case MMC_SPI:
|
307 |
s->spi = value & 0xf;
|
308 |
if (value & SPI_SPI_MODE)
|
309 |
printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
|
310 |
break;
|
311 |
|
312 |
case MMC_CMDAT:
|
313 |
s->cmdat = value & 0x3dff;
|
314 |
s->active = 0;
|
315 |
s->cmdreq = 1;
|
316 |
if (!(value & CMDAT_STOP_TRAN)) {
|
317 |
s->status &= STAT_CLK_EN; |
318 |
|
319 |
if (s->status & STAT_CLK_EN)
|
320 |
pxa2xx_mmci_wakequeues(s); |
321 |
} |
322 |
|
323 |
pxa2xx_mmci_int_update(s); |
324 |
break;
|
325 |
|
326 |
case MMC_RESTO:
|
327 |
s->resp_tout = value & 0x7f;
|
328 |
break;
|
329 |
|
330 |
case MMC_RDTO:
|
331 |
s->read_tout = value & 0xffff;
|
332 |
break;
|
333 |
|
334 |
case MMC_BLKLEN:
|
335 |
s->blklen = value & 0xfff;
|
336 |
break;
|
337 |
|
338 |
case MMC_NUMBLK:
|
339 |
s->numblk = value & 0xffff;
|
340 |
break;
|
341 |
|
342 |
case MMC_PRTBUF:
|
343 |
if (value & PRTBUF_PRT_BUF) {
|
344 |
s->tx_start ^= 32;
|
345 |
s->tx_len = 0;
|
346 |
} |
347 |
pxa2xx_mmci_fifo_update(s); |
348 |
break;
|
349 |
|
350 |
case MMC_I_MASK:
|
351 |
s->intmask = value & 0x1fff;
|
352 |
pxa2xx_mmci_int_update(s); |
353 |
break;
|
354 |
|
355 |
case MMC_CMD:
|
356 |
s->cmd = value & 0x3f;
|
357 |
break;
|
358 |
|
359 |
case MMC_ARGH:
|
360 |
s->arg &= 0x0000ffff;
|
361 |
s->arg |= value << 16;
|
362 |
break;
|
363 |
|
364 |
case MMC_ARGL:
|
365 |
s->arg &= 0xffff0000;
|
366 |
s->arg |= value & 0x0000ffff;
|
367 |
break;
|
368 |
|
369 |
case MMC_TXFIFO:
|
370 |
while (s->ac_width -- && s->tx_len < 0x20) |
371 |
s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
|
372 |
(value >> (s->ac_width << 3)) & 0xff; |
373 |
s->intreq &= ~INT_TXFIFO_REQ; |
374 |
pxa2xx_mmci_fifo_update(s); |
375 |
break;
|
376 |
|
377 |
case MMC_RDWAIT:
|
378 |
case MMC_BLKS_REM:
|
379 |
break;
|
380 |
|
381 |
default:
|
382 |
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
383 |
} |
384 |
} |
385 |
|
386 |
static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset) |
387 |
{ |
388 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
389 |
s->ac_width = 1;
|
390 |
return pxa2xx_mmci_read(opaque, offset);
|
391 |
} |
392 |
|
393 |
static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset) |
394 |
{ |
395 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
396 |
s->ac_width = 2;
|
397 |
return pxa2xx_mmci_read(opaque, offset);
|
398 |
} |
399 |
|
400 |
static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset) |
401 |
{ |
402 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
403 |
s->ac_width = 4;
|
404 |
return pxa2xx_mmci_read(opaque, offset);
|
405 |
} |
406 |
|
407 |
static void pxa2xx_mmci_writeb(void *opaque, |
408 |
target_phys_addr_t offset, uint32_t value) |
409 |
{ |
410 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
411 |
s->ac_width = 1;
|
412 |
pxa2xx_mmci_write(opaque, offset, value); |
413 |
} |
414 |
|
415 |
static void pxa2xx_mmci_writeh(void *opaque, |
416 |
target_phys_addr_t offset, uint32_t value) |
417 |
{ |
418 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
419 |
s->ac_width = 2;
|
420 |
pxa2xx_mmci_write(opaque, offset, value); |
421 |
} |
422 |
|
423 |
static void pxa2xx_mmci_writew(void *opaque, |
424 |
target_phys_addr_t offset, uint32_t value) |
425 |
{ |
426 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
427 |
s->ac_width = 4;
|
428 |
pxa2xx_mmci_write(opaque, offset, value); |
429 |
} |
430 |
|
431 |
static const MemoryRegionOps pxa2xx_mmci_ops = { |
432 |
.old_mmio = { |
433 |
.read = { pxa2xx_mmci_readb, |
434 |
pxa2xx_mmci_readh, |
435 |
pxa2xx_mmci_readw, }, |
436 |
.write = { pxa2xx_mmci_writeb, |
437 |
pxa2xx_mmci_writeh, |
438 |
pxa2xx_mmci_writew, }, |
439 |
}, |
440 |
.endianness = DEVICE_NATIVE_ENDIAN, |
441 |
}; |
442 |
|
443 |
static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) |
444 |
{ |
445 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
446 |
int i;
|
447 |
|
448 |
qemu_put_be32s(f, &s->status); |
449 |
qemu_put_be32s(f, &s->clkrt); |
450 |
qemu_put_be32s(f, &s->spi); |
451 |
qemu_put_be32s(f, &s->cmdat); |
452 |
qemu_put_be32s(f, &s->resp_tout); |
453 |
qemu_put_be32s(f, &s->read_tout); |
454 |
qemu_put_be32(f, s->blklen); |
455 |
qemu_put_be32(f, s->numblk); |
456 |
qemu_put_be32s(f, &s->intmask); |
457 |
qemu_put_be32s(f, &s->intreq); |
458 |
qemu_put_be32(f, s->cmd); |
459 |
qemu_put_be32s(f, &s->arg); |
460 |
qemu_put_be32(f, s->cmdreq); |
461 |
qemu_put_be32(f, s->active); |
462 |
qemu_put_be32(f, s->bytesleft); |
463 |
|
464 |
qemu_put_byte(f, s->tx_len); |
465 |
for (i = 0; i < s->tx_len; i ++) |
466 |
qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
|
467 |
|
468 |
qemu_put_byte(f, s->rx_len); |
469 |
for (i = 0; i < s->rx_len; i ++) |
470 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
|
471 |
|
472 |
qemu_put_byte(f, s->resp_len); |
473 |
for (i = s->resp_len; i < 9; i ++) |
474 |
qemu_put_be16s(f, &s->resp_fifo[i]); |
475 |
} |
476 |
|
477 |
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) |
478 |
{ |
479 |
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
480 |
int i;
|
481 |
|
482 |
qemu_get_be32s(f, &s->status); |
483 |
qemu_get_be32s(f, &s->clkrt); |
484 |
qemu_get_be32s(f, &s->spi); |
485 |
qemu_get_be32s(f, &s->cmdat); |
486 |
qemu_get_be32s(f, &s->resp_tout); |
487 |
qemu_get_be32s(f, &s->read_tout); |
488 |
s->blklen = qemu_get_be32(f); |
489 |
s->numblk = qemu_get_be32(f); |
490 |
qemu_get_be32s(f, &s->intmask); |
491 |
qemu_get_be32s(f, &s->intreq); |
492 |
s->cmd = qemu_get_be32(f); |
493 |
qemu_get_be32s(f, &s->arg); |
494 |
s->cmdreq = qemu_get_be32(f); |
495 |
s->active = qemu_get_be32(f); |
496 |
s->bytesleft = qemu_get_be32(f); |
497 |
|
498 |
s->tx_len = qemu_get_byte(f); |
499 |
s->tx_start = 0;
|
500 |
if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0) |
501 |
return -EINVAL;
|
502 |
for (i = 0; i < s->tx_len; i ++) |
503 |
s->tx_fifo[i] = qemu_get_byte(f); |
504 |
|
505 |
s->rx_len = qemu_get_byte(f); |
506 |
s->rx_start = 0;
|
507 |
if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0) |
508 |
return -EINVAL;
|
509 |
for (i = 0; i < s->rx_len; i ++) |
510 |
s->rx_fifo[i] = qemu_get_byte(f); |
511 |
|
512 |
s->resp_len = qemu_get_byte(f); |
513 |
if (s->resp_len > 9 || s->resp_len < 0) |
514 |
return -EINVAL;
|
515 |
for (i = s->resp_len; i < 9; i ++) |
516 |
qemu_get_be16s(f, &s->resp_fifo[i]); |
517 |
|
518 |
return 0; |
519 |
} |
520 |
|
521 |
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, |
522 |
target_phys_addr_t base, |
523 |
BlockDriverState *bd, qemu_irq irq, |
524 |
qemu_irq rx_dma, qemu_irq tx_dma) |
525 |
{ |
526 |
PXA2xxMMCIState *s; |
527 |
|
528 |
s = (PXA2xxMMCIState *) g_malloc0(sizeof(PXA2xxMMCIState));
|
529 |
s->irq = irq; |
530 |
s->rx_dma = rx_dma; |
531 |
s->tx_dma = tx_dma; |
532 |
|
533 |
memory_region_init_io(&s->iomem, &pxa2xx_mmci_ops, s, |
534 |
"pxa2xx-mmci", 0x00100000); |
535 |
memory_region_add_subregion(sysmem, base, &s->iomem); |
536 |
|
537 |
/* Instantiate the actual storage */
|
538 |
s->card = sd_init(bd, 0);
|
539 |
|
540 |
register_savevm(NULL, "pxa2xx_mmci", 0, 0, |
541 |
pxa2xx_mmci_save, pxa2xx_mmci_load, s); |
542 |
|
543 |
return s;
|
544 |
} |
545 |
|
546 |
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
|
547 |
qemu_irq coverswitch) |
548 |
{ |
549 |
sd_set_cb(s->card, readonly, coverswitch); |
550 |
} |