Archipelago » qemu

    unsigned int flags;

    sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));

    sc->limit = ldl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit));

    flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));

    sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);

    /* load the interception bitmaps so we do not need to access the

       vmcb in svm mode */

                                                      control.intercept));

    env->intercept_cr_read = lduw_phys(env->vm_vmcb +

                                       offsetof(struct vmcb,

    /* enable intercepts */

    env->hflags |= HF_SVMI_MASK;

                               offsetof(struct vmcb, control.tsc_offset));

                                                      save.gdtr.base));

    env->gdt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,

                                                      save.gdtr.limit));

                                                      save.idtr.base));

    env->idt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,

                                                      save.idtr.limit));

    /* clear exit_info_2 so we behave like the real hardware */

    stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);

                                                             save.cr0)));

                                                             save.cr4)));

                                                             save.cr3)));

    int_ctl = ldl_phys(cs->as,

                       env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));

    env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);

    }

    cpu_load_efer(env,

    env->eflags = 0;

                                                          save.rflags)),

                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));

    CC_OP = CC_OP_EFLAGS;

    svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),

                       R_DS);

                                                           save.cpl)));

    /* FIXME: guest state consistency checks */

    case TLB_CONTROL_DO_NOTHING:

        break;

    case TLB_CONTROL_FLUSH_ALL_ASID:

void helper_vmload(CPUX86State *env, int aflag)

{

    target_ulong addr;

    cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0);

    qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx

                  "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",

                                                          save.fs.base)),

                  env->segs[R_FS].base);

    svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);

#ifdef TARGET_X86_64

                                                 save.kernel_gs_base));

#endif

                                                 save.sysenter_esp));

                                                 save.sysenter_eip));

}

void helper_vmsave(CPUX86State *env, int aflag)

{

    target_ulong addr;

    cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0);

    qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx

                  "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",

                  env->segs[R_FS].base);

    svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),

void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,

                                      uint64_t param)

{

    if (likely(!(env->hflags & HF_SVMI_MASK))) {

        return;

    }

    case SVM_EXIT_MSR:

        if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {

            /* FIXME: this should be read in at vmrun (faster this way?) */

                                     offsetof(struct vmcb,

                                              control.msrpm_base_pa));

            uint32_t t0, t1;

                t1 = 0;

                break;

            }

                helper_vmexit(env, type, param);

            }

        }

void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,

                         uint32_t next_eip_addend)

{

    if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {

        /* FIXME: this should be read in at vmrun (faster this way?) */

                                 offsetof(struct vmcb, control.iopm_base_pa));

        uint16_t mask = (1 << ((param >> 4) & 7)) - 1;

    qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"

                  PRIx64 ", " TARGET_FMT_lx ")!\n",

                  exit_code, exit_info_1,

                                                   control.exit_info_2)),

                  env->eip);

    cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;

    env->tsc_offset = 0;

                                                       save.gdtr.base));

    env->gdt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,

                                                       save.gdtr.limit));

                                                       save.idtr.base));

    env->idt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb,

                                                       save.idtr.limit));

                                                              save.cr0)) |

                       CR0_PE_MASK);

                                                              save.cr4)));

                                                              save.cr3)));

    /* we need to set the efer after the crs so the hidden flags get

       set properly */

                                                         save.efer)));

    env->eflags = 0;

                                                           save.rflags)),

                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));

    CC_OP = CC_OP_EFLAGS;

    svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),

                       R_DS);

                                offsetof(struct vmcb, save.rsp));

                                offsetof(struct vmcb, save.rax));

    /* other setups */

    cpu_x86_set_cpl(env, 0);