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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU PC System Emulator
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "fdc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 87ecb68b | pbrook | #include "block.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "audio/audio.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "smbus.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | cfa2af1f | aurel32 | #include "console.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | 6e02c38d | aliguori | #include "virtio-blk.h" |
37 | bd322087 | aliguori | #include "virtio-balloon.h" |
38 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
39 | 80cabfad | bellard | |
40 | b41a2cd1 | bellard | /* output Bochs bios info messages */
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41 | b41a2cd1 | bellard | //#define DEBUG_BIOS
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42 | b41a2cd1 | bellard | |
43 | 80cabfad | bellard | #define BIOS_FILENAME "bios.bin" |
44 | 80cabfad | bellard | #define VGABIOS_FILENAME "vgabios.bin" |
45 | de9258a8 | bellard | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
46 | 80cabfad | bellard | |
47 | 7fb4fdcf | balrog | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
48 | 7fb4fdcf | balrog | |
49 | a80274c3 | pbrook | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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50 | a80274c3 | pbrook | #define ACPI_DATA_SIZE 0x10000 |
51 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
52 | 80cabfad | bellard | |
53 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
54 | e4bcb14c | ths | |
55 | baca51fa | bellard | static fdctrl_t *floppy_controller;
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56 | b0a21b53 | bellard | static RTCState *rtc_state;
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57 | ec844b96 | bellard | static PITState *pit;
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58 | d592d303 | bellard | static IOAPICState *ioapic;
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59 | a5954d5c | bellard | static PCIDevice *i440fx_state;
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60 | 80cabfad | bellard | |
61 | b41a2cd1 | bellard | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
62 | 80cabfad | bellard | { |
63 | 80cabfad | bellard | } |
64 | 80cabfad | bellard | |
65 | f929aad6 | bellard | /* MSDOS compatibility mode FPU exception support */
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66 | d537cf6c | pbrook | static qemu_irq ferr_irq;
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67 | f929aad6 | bellard | /* XXX: add IGNNE support */
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68 | f929aad6 | bellard | void cpu_set_ferr(CPUX86State *s)
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69 | f929aad6 | bellard | { |
70 | d537cf6c | pbrook | qemu_irq_raise(ferr_irq); |
71 | f929aad6 | bellard | } |
72 | f929aad6 | bellard | |
73 | f929aad6 | bellard | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
74 | f929aad6 | bellard | { |
75 | d537cf6c | pbrook | qemu_irq_lower(ferr_irq); |
76 | f929aad6 | bellard | } |
77 | f929aad6 | bellard | |
78 | 28ab0e2e | bellard | /* TSC handling */
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79 | 28ab0e2e | bellard | uint64_t cpu_get_tsc(CPUX86State *env) |
80 | 28ab0e2e | bellard | { |
81 | 1dce7c3c | bellard | /* Note: when using kqemu, it is more logical to return the host TSC
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82 | 1dce7c3c | bellard | because kqemu does not trap the RDTSC instruction for
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83 | 1dce7c3c | bellard | performance reasons */
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84 | eb38c52c | blueswir1 | #ifdef USE_KQEMU
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85 | 1dce7c3c | bellard | if (env->kqemu_enabled) {
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86 | 1dce7c3c | bellard | return cpu_get_real_ticks();
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87 | 5fafdf24 | ths | } else
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88 | 1dce7c3c | bellard | #endif
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89 | 1dce7c3c | bellard | { |
90 | 1dce7c3c | bellard | return cpu_get_ticks();
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91 | 1dce7c3c | bellard | } |
92 | 28ab0e2e | bellard | } |
93 | 28ab0e2e | bellard | |
94 | a5954d5c | bellard | /* SMM support */
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95 | a5954d5c | bellard | void cpu_smm_update(CPUState *env)
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96 | a5954d5c | bellard | { |
97 | a5954d5c | bellard | if (i440fx_state && env == first_cpu)
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98 | a5954d5c | bellard | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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99 | a5954d5c | bellard | } |
100 | a5954d5c | bellard | |
101 | a5954d5c | bellard | |
102 | 3de388f6 | bellard | /* IRQ handling */
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103 | 3de388f6 | bellard | int cpu_get_pic_interrupt(CPUState *env)
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104 | 3de388f6 | bellard | { |
105 | 3de388f6 | bellard | int intno;
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106 | 3de388f6 | bellard | |
107 | 3de388f6 | bellard | intno = apic_get_interrupt(env); |
108 | 3de388f6 | bellard | if (intno >= 0) { |
109 | 3de388f6 | bellard | /* set irq request if a PIC irq is still pending */
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110 | 3de388f6 | bellard | /* XXX: improve that */
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111 | 5fafdf24 | ths | pic_update_irq(isa_pic); |
112 | 3de388f6 | bellard | return intno;
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113 | 3de388f6 | bellard | } |
114 | 3de388f6 | bellard | /* read the irq from the PIC */
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115 | 0e21e12b | ths | if (!apic_accept_pic_intr(env))
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116 | 0e21e12b | ths | return -1; |
117 | 0e21e12b | ths | |
118 | 3de388f6 | bellard | intno = pic_read_irq(isa_pic); |
119 | 3de388f6 | bellard | return intno;
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120 | 3de388f6 | bellard | } |
121 | 3de388f6 | bellard | |
122 | d537cf6c | pbrook | static void pic_irq_request(void *opaque, int irq, int level) |
123 | 3de388f6 | bellard | { |
124 | a5b38b51 | aurel32 | CPUState *env = first_cpu; |
125 | a5b38b51 | aurel32 | |
126 | d5529471 | aurel32 | if (env->apic_state) {
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127 | d5529471 | aurel32 | while (env) {
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128 | d5529471 | aurel32 | if (apic_accept_pic_intr(env))
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129 | 1a7de94a | aurel32 | apic_deliver_pic_intr(env, level); |
130 | d5529471 | aurel32 | env = env->next_cpu; |
131 | d5529471 | aurel32 | } |
132 | d5529471 | aurel32 | } else {
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133 | b614106a | aurel32 | if (level)
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134 | b614106a | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
135 | b614106a | aurel32 | else
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136 | b614106a | aurel32 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
137 | a5b38b51 | aurel32 | } |
138 | 3de388f6 | bellard | } |
139 | 3de388f6 | bellard | |
140 | b0a21b53 | bellard | /* PC cmos mappings */
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141 | b0a21b53 | bellard | |
142 | 80cabfad | bellard | #define REG_EQUIPMENT_BYTE 0x14 |
143 | 80cabfad | bellard | |
144 | 777428f2 | bellard | static int cmos_get_fd_drive_type(int fd0) |
145 | 777428f2 | bellard | { |
146 | 777428f2 | bellard | int val;
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147 | 777428f2 | bellard | |
148 | 777428f2 | bellard | switch (fd0) {
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149 | 777428f2 | bellard | case 0: |
150 | 777428f2 | bellard | /* 1.44 Mb 3"5 drive */
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151 | 777428f2 | bellard | val = 4;
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152 | 777428f2 | bellard | break;
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153 | 777428f2 | bellard | case 1: |
154 | 777428f2 | bellard | /* 2.88 Mb 3"5 drive */
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155 | 777428f2 | bellard | val = 5;
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156 | 777428f2 | bellard | break;
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157 | 777428f2 | bellard | case 2: |
158 | 777428f2 | bellard | /* 1.2 Mb 5"5 drive */
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159 | 777428f2 | bellard | val = 2;
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160 | 777428f2 | bellard | break;
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161 | 777428f2 | bellard | default:
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162 | 777428f2 | bellard | val = 0;
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163 | 777428f2 | bellard | break;
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164 | 777428f2 | bellard | } |
165 | 777428f2 | bellard | return val;
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166 | 777428f2 | bellard | } |
167 | 777428f2 | bellard | |
168 | 5fafdf24 | ths | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
169 | ba6c2377 | bellard | { |
170 | ba6c2377 | bellard | RTCState *s = rtc_state; |
171 | ba6c2377 | bellard | int cylinders, heads, sectors;
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172 | ba6c2377 | bellard | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
173 | ba6c2377 | bellard | rtc_set_memory(s, type_ofs, 47);
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174 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs, cylinders); |
175 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
176 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 2, heads);
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177 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 3, 0xff); |
178 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 4, 0xff); |
179 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
180 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 6, cylinders);
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181 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
182 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 8, sectors);
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183 | ba6c2377 | bellard | } |
184 | ba6c2377 | bellard | |
185 | 6ac0e82d | balrog | /* convert boot_device letter to something recognizable by the bios */
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186 | 6ac0e82d | balrog | static int boot_device2nibble(char boot_device) |
187 | 6ac0e82d | balrog | { |
188 | 6ac0e82d | balrog | switch(boot_device) {
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189 | 6ac0e82d | balrog | case 'a': |
190 | 6ac0e82d | balrog | case 'b': |
191 | 6ac0e82d | balrog | return 0x01; /* floppy boot */ |
192 | 6ac0e82d | balrog | case 'c': |
193 | 6ac0e82d | balrog | return 0x02; /* hard drive boot */ |
194 | 6ac0e82d | balrog | case 'd': |
195 | 6ac0e82d | balrog | return 0x03; /* CD-ROM boot */ |
196 | 6ac0e82d | balrog | case 'n': |
197 | 6ac0e82d | balrog | return 0x04; /* Network boot */ |
198 | 6ac0e82d | balrog | } |
199 | 6ac0e82d | balrog | return 0; |
200 | 6ac0e82d | balrog | } |
201 | 6ac0e82d | balrog | |
202 | 0ecdffbb | aurel32 | /* copy/pasted from cmos_init, should be made a general function
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203 | 0ecdffbb | aurel32 | and used there as well */
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204 | 3b4366de | blueswir1 | static int pc_boot_set(void *opaque, const char *boot_device) |
205 | 0ecdffbb | aurel32 | { |
206 | 0ecdffbb | aurel32 | #define PC_MAX_BOOT_DEVICES 3 |
207 | 3b4366de | blueswir1 | RTCState *s = (RTCState *)opaque; |
208 | 0ecdffbb | aurel32 | int nbds, bds[3] = { 0, }; |
209 | 0ecdffbb | aurel32 | int i;
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210 | 0ecdffbb | aurel32 | |
211 | 0ecdffbb | aurel32 | nbds = strlen(boot_device); |
212 | 0ecdffbb | aurel32 | if (nbds > PC_MAX_BOOT_DEVICES) {
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213 | 0ecdffbb | aurel32 | term_printf("Too many boot devices for PC\n");
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214 | 0ecdffbb | aurel32 | return(1); |
215 | 0ecdffbb | aurel32 | } |
216 | 0ecdffbb | aurel32 | for (i = 0; i < nbds; i++) { |
217 | 0ecdffbb | aurel32 | bds[i] = boot_device2nibble(boot_device[i]); |
218 | 0ecdffbb | aurel32 | if (bds[i] == 0) { |
219 | 0ecdffbb | aurel32 | term_printf("Invalid boot device for PC: '%c'\n",
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220 | 0ecdffbb | aurel32 | boot_device[i]); |
221 | 0ecdffbb | aurel32 | return(1); |
222 | 0ecdffbb | aurel32 | } |
223 | 0ecdffbb | aurel32 | } |
224 | 0ecdffbb | aurel32 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
225 | 0ecdffbb | aurel32 | rtc_set_memory(s, 0x38, (bds[2] << 4)); |
226 | 0ecdffbb | aurel32 | return(0); |
227 | 0ecdffbb | aurel32 | } |
228 | 0ecdffbb | aurel32 | |
229 | ba6c2377 | bellard | /* hd_table must contain 4 block drivers */
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230 | 00f82b8a | aurel32 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
231 | 00f82b8a | aurel32 | const char *boot_device, BlockDriverState **hd_table) |
232 | 80cabfad | bellard | { |
233 | b0a21b53 | bellard | RTCState *s = rtc_state; |
234 | 28c5af54 | j_mayer | int nbds, bds[3] = { 0, }; |
235 | 80cabfad | bellard | int val;
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236 | b41a2cd1 | bellard | int fd0, fd1, nb;
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237 | ba6c2377 | bellard | int i;
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238 | b0a21b53 | bellard | |
239 | b0a21b53 | bellard | /* various important CMOS locations needed by PC/Bochs bios */
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240 | 80cabfad | bellard | |
241 | 80cabfad | bellard | /* memory size */
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242 | 333190eb | bellard | val = 640; /* base memory in K */ |
243 | 333190eb | bellard | rtc_set_memory(s, 0x15, val);
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244 | 333190eb | bellard | rtc_set_memory(s, 0x16, val >> 8); |
245 | 333190eb | bellard | |
246 | 80cabfad | bellard | val = (ram_size / 1024) - 1024; |
247 | 80cabfad | bellard | if (val > 65535) |
248 | 80cabfad | bellard | val = 65535;
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249 | b0a21b53 | bellard | rtc_set_memory(s, 0x17, val);
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250 | b0a21b53 | bellard | rtc_set_memory(s, 0x18, val >> 8); |
251 | b0a21b53 | bellard | rtc_set_memory(s, 0x30, val);
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252 | b0a21b53 | bellard | rtc_set_memory(s, 0x31, val >> 8); |
253 | 80cabfad | bellard | |
254 | 00f82b8a | aurel32 | if (above_4g_mem_size) {
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255 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
256 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
257 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
258 | 00f82b8a | aurel32 | } |
259 | 00f82b8a | aurel32 | |
260 | 9da98861 | bellard | if (ram_size > (16 * 1024 * 1024)) |
261 | 9da98861 | bellard | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
262 | 9da98861 | bellard | else
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263 | 9da98861 | bellard | val = 0;
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264 | 80cabfad | bellard | if (val > 65535) |
265 | 80cabfad | bellard | val = 65535;
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266 | b0a21b53 | bellard | rtc_set_memory(s, 0x34, val);
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267 | b0a21b53 | bellard | rtc_set_memory(s, 0x35, val >> 8); |
268 | 3b46e624 | ths | |
269 | 298e01b6 | aurel32 | /* set the number of CPU */
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270 | 298e01b6 | aurel32 | rtc_set_memory(s, 0x5f, smp_cpus - 1); |
271 | 298e01b6 | aurel32 | |
272 | 6ac0e82d | balrog | /* set boot devices, and disable floppy signature check if requested */
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273 | 28c5af54 | j_mayer | #define PC_MAX_BOOT_DEVICES 3 |
274 | 28c5af54 | j_mayer | nbds = strlen(boot_device); |
275 | 28c5af54 | j_mayer | if (nbds > PC_MAX_BOOT_DEVICES) {
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276 | 28c5af54 | j_mayer | fprintf(stderr, "Too many boot devices for PC\n");
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277 | 28c5af54 | j_mayer | exit(1);
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278 | 28c5af54 | j_mayer | } |
279 | 28c5af54 | j_mayer | for (i = 0; i < nbds; i++) { |
280 | 28c5af54 | j_mayer | bds[i] = boot_device2nibble(boot_device[i]); |
281 | 28c5af54 | j_mayer | if (bds[i] == 0) { |
282 | 28c5af54 | j_mayer | fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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283 | 28c5af54 | j_mayer | boot_device[i]); |
284 | 28c5af54 | j_mayer | exit(1);
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285 | 28c5af54 | j_mayer | } |
286 | 28c5af54 | j_mayer | } |
287 | 28c5af54 | j_mayer | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
288 | 28c5af54 | j_mayer | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
289 | 80cabfad | bellard | |
290 | b41a2cd1 | bellard | /* floppy type */
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291 | b41a2cd1 | bellard | |
292 | baca51fa | bellard | fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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293 | baca51fa | bellard | fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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294 | 80cabfad | bellard | |
295 | 777428f2 | bellard | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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296 | b0a21b53 | bellard | rtc_set_memory(s, 0x10, val);
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297 | 3b46e624 | ths | |
298 | b0a21b53 | bellard | val = 0;
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299 | b41a2cd1 | bellard | nb = 0;
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300 | 80cabfad | bellard | if (fd0 < 3) |
301 | 80cabfad | bellard | nb++; |
302 | 80cabfad | bellard | if (fd1 < 3) |
303 | 80cabfad | bellard | nb++; |
304 | 80cabfad | bellard | switch (nb) {
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305 | 80cabfad | bellard | case 0: |
306 | 80cabfad | bellard | break;
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307 | 80cabfad | bellard | case 1: |
308 | b0a21b53 | bellard | val |= 0x01; /* 1 drive, ready for boot */ |
309 | 80cabfad | bellard | break;
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310 | 80cabfad | bellard | case 2: |
311 | b0a21b53 | bellard | val |= 0x41; /* 2 drives, ready for boot */ |
312 | 80cabfad | bellard | break;
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313 | 80cabfad | bellard | } |
314 | b0a21b53 | bellard | val |= 0x02; /* FPU is there */ |
315 | b0a21b53 | bellard | val |= 0x04; /* PS/2 mouse installed */ |
316 | b0a21b53 | bellard | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
317 | b0a21b53 | bellard | |
318 | ba6c2377 | bellard | /* hard drives */
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319 | ba6c2377 | bellard | |
320 | ba6c2377 | bellard | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
321 | ba6c2377 | bellard | if (hd_table[0]) |
322 | ba6c2377 | bellard | cmos_init_hd(0x19, 0x1b, hd_table[0]); |
323 | 5fafdf24 | ths | if (hd_table[1]) |
324 | ba6c2377 | bellard | cmos_init_hd(0x1a, 0x24, hd_table[1]); |
325 | ba6c2377 | bellard | |
326 | ba6c2377 | bellard | val = 0;
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327 | 40b6ecc6 | bellard | for (i = 0; i < 4; i++) { |
328 | ba6c2377 | bellard | if (hd_table[i]) {
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329 | 46d4767d | bellard | int cylinders, heads, sectors, translation;
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330 | 46d4767d | bellard | /* NOTE: bdrv_get_geometry_hint() returns the physical
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331 | 46d4767d | bellard | geometry. It is always such that: 1 <= sects <= 63, 1
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332 | 46d4767d | bellard | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
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333 | 46d4767d | bellard | geometry can be different if a translation is done. */
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334 | 46d4767d | bellard | translation = bdrv_get_translation_hint(hd_table[i]); |
335 | 46d4767d | bellard | if (translation == BIOS_ATA_TRANSLATION_AUTO) {
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336 | 46d4767d | bellard | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
337 | 46d4767d | bellard | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
338 | 46d4767d | bellard | /* No translation. */
|
339 | 46d4767d | bellard | translation = 0;
|
340 | 46d4767d | bellard | } else {
|
341 | 46d4767d | bellard | /* LBA translation. */
|
342 | 46d4767d | bellard | translation = 1;
|
343 | 46d4767d | bellard | } |
344 | 40b6ecc6 | bellard | } else {
|
345 | 46d4767d | bellard | translation--; |
346 | ba6c2377 | bellard | } |
347 | ba6c2377 | bellard | val |= translation << (i * 2);
|
348 | ba6c2377 | bellard | } |
349 | 40b6ecc6 | bellard | } |
350 | ba6c2377 | bellard | rtc_set_memory(s, 0x39, val);
|
351 | 80cabfad | bellard | } |
352 | 80cabfad | bellard | |
353 | 59b8ad81 | bellard | void ioport_set_a20(int enable) |
354 | 59b8ad81 | bellard | { |
355 | 59b8ad81 | bellard | /* XXX: send to all CPUs ? */
|
356 | 59b8ad81 | bellard | cpu_x86_set_a20(first_cpu, enable); |
357 | 59b8ad81 | bellard | } |
358 | 59b8ad81 | bellard | |
359 | 59b8ad81 | bellard | int ioport_get_a20(void) |
360 | 59b8ad81 | bellard | { |
361 | 59b8ad81 | bellard | return ((first_cpu->a20_mask >> 20) & 1); |
362 | 59b8ad81 | bellard | } |
363 | 59b8ad81 | bellard | |
364 | e1a23744 | bellard | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
365 | e1a23744 | bellard | { |
366 | 59b8ad81 | bellard | ioport_set_a20((val >> 1) & 1); |
367 | e1a23744 | bellard | /* XXX: bit 0 is fast reset */
|
368 | e1a23744 | bellard | } |
369 | e1a23744 | bellard | |
370 | e1a23744 | bellard | static uint32_t ioport92_read(void *opaque, uint32_t addr) |
371 | e1a23744 | bellard | { |
372 | 59b8ad81 | bellard | return ioport_get_a20() << 1; |
373 | e1a23744 | bellard | } |
374 | e1a23744 | bellard | |
375 | 80cabfad | bellard | /***********************************************************/
|
376 | 80cabfad | bellard | /* Bochs BIOS debug ports */
|
377 | 80cabfad | bellard | |
378 | 9596ebb7 | pbrook | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
379 | 80cabfad | bellard | { |
380 | a2f659ee | bellard | static const char shutdown_str[8] = "Shutdown"; |
381 | a2f659ee | bellard | static int shutdown_index = 0; |
382 | 3b46e624 | ths | |
383 | 80cabfad | bellard | switch(addr) {
|
384 | 80cabfad | bellard | /* Bochs BIOS messages */
|
385 | 80cabfad | bellard | case 0x400: |
386 | 80cabfad | bellard | case 0x401: |
387 | 80cabfad | bellard | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
388 | 80cabfad | bellard | exit(1);
|
389 | 80cabfad | bellard | case 0x402: |
390 | 80cabfad | bellard | case 0x403: |
391 | 80cabfad | bellard | #ifdef DEBUG_BIOS
|
392 | 80cabfad | bellard | fprintf(stderr, "%c", val);
|
393 | 80cabfad | bellard | #endif
|
394 | 80cabfad | bellard | break;
|
395 | a2f659ee | bellard | case 0x8900: |
396 | a2f659ee | bellard | /* same as Bochs power off */
|
397 | a2f659ee | bellard | if (val == shutdown_str[shutdown_index]) {
|
398 | a2f659ee | bellard | shutdown_index++; |
399 | a2f659ee | bellard | if (shutdown_index == 8) { |
400 | a2f659ee | bellard | shutdown_index = 0;
|
401 | a2f659ee | bellard | qemu_system_shutdown_request(); |
402 | a2f659ee | bellard | } |
403 | a2f659ee | bellard | } else {
|
404 | a2f659ee | bellard | shutdown_index = 0;
|
405 | a2f659ee | bellard | } |
406 | a2f659ee | bellard | break;
|
407 | 80cabfad | bellard | |
408 | 80cabfad | bellard | /* LGPL'ed VGA BIOS messages */
|
409 | 80cabfad | bellard | case 0x501: |
410 | 80cabfad | bellard | case 0x502: |
411 | 80cabfad | bellard | fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
412 | 80cabfad | bellard | exit(1);
|
413 | 80cabfad | bellard | case 0x500: |
414 | 80cabfad | bellard | case 0x503: |
415 | 80cabfad | bellard | #ifdef DEBUG_BIOS
|
416 | 80cabfad | bellard | fprintf(stderr, "%c", val);
|
417 | 80cabfad | bellard | #endif
|
418 | 80cabfad | bellard | break;
|
419 | 80cabfad | bellard | } |
420 | 80cabfad | bellard | } |
421 | 80cabfad | bellard | |
422 | 9596ebb7 | pbrook | static void bochs_bios_init(void) |
423 | 80cabfad | bellard | { |
424 | 3cce6243 | blueswir1 | void *fw_cfg;
|
425 | 3cce6243 | blueswir1 | |
426 | b41a2cd1 | bellard | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
427 | b41a2cd1 | bellard | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
428 | b41a2cd1 | bellard | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
429 | b41a2cd1 | bellard | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
430 | a2f659ee | bellard | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
431 | b41a2cd1 | bellard | |
432 | b41a2cd1 | bellard | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
433 | b41a2cd1 | bellard | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
434 | b41a2cd1 | bellard | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
435 | b41a2cd1 | bellard | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
436 | 3cce6243 | blueswir1 | |
437 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
438 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
439 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
440 | 80cabfad | bellard | } |
441 | 80cabfad | bellard | |
442 | 642a4f96 | ths | /* Generate an initial boot sector which sets state and jump to
|
443 | 642a4f96 | ths | a specified vector */
|
444 | 4fc9af53 | aliguori | static void generate_bootsect(uint8_t *option_rom, |
445 | 4fc9af53 | aliguori | uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
446 | 642a4f96 | ths | { |
447 | 4fc9af53 | aliguori | uint8_t rom[512], *p, *reloc;
|
448 | 4fc9af53 | aliguori | uint8_t sum; |
449 | 642a4f96 | ths | int i;
|
450 | 642a4f96 | ths | |
451 | 4fc9af53 | aliguori | memset(rom, 0, sizeof(rom)); |
452 | 4fc9af53 | aliguori | |
453 | 4fc9af53 | aliguori | p = rom; |
454 | 4fc9af53 | aliguori | /* Make sure we have an option rom signature */
|
455 | 4fc9af53 | aliguori | *p++ = 0x55;
|
456 | 4fc9af53 | aliguori | *p++ = 0xaa;
|
457 | 642a4f96 | ths | |
458 | 4fc9af53 | aliguori | /* ROM size in sectors*/
|
459 | 4fc9af53 | aliguori | *p++ = 1;
|
460 | 642a4f96 | ths | |
461 | 4fc9af53 | aliguori | /* Hook int19 */
|
462 | 642a4f96 | ths | |
463 | 4fc9af53 | aliguori | *p++ = 0x50; /* push ax */ |
464 | 4fc9af53 | aliguori | *p++ = 0x1e; /* push ds */ |
465 | 4fc9af53 | aliguori | *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ |
466 | 4fc9af53 | aliguori | *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ |
467 | 642a4f96 | ths | |
468 | 4fc9af53 | aliguori | *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
469 | 4fc9af53 | aliguori | *p++ = 0x64; *p++ = 0x00; |
470 | 4fc9af53 | aliguori | reloc = p; |
471 | 4fc9af53 | aliguori | *p++ = 0x00; *p++ = 0x00; |
472 | 4fc9af53 | aliguori | |
473 | 4fc9af53 | aliguori | *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ |
474 | 4fc9af53 | aliguori | *p++ = 0x66; *p++ = 0x00; |
475 | 4fc9af53 | aliguori | |
476 | 4fc9af53 | aliguori | *p++ = 0x1f; /* pop ds */ |
477 | 4fc9af53 | aliguori | *p++ = 0x58; /* pop ax */ |
478 | 4fc9af53 | aliguori | *p++ = 0xcb; /* lret */ |
479 | 4fc9af53 | aliguori | |
480 | 642a4f96 | ths | /* Actual code */
|
481 | 4fc9af53 | aliguori | *reloc = (p - rom); |
482 | 4fc9af53 | aliguori | |
483 | 642a4f96 | ths | *p++ = 0xfa; /* CLI */ |
484 | 642a4f96 | ths | *p++ = 0xfc; /* CLD */ |
485 | 642a4f96 | ths | |
486 | 642a4f96 | ths | for (i = 0; i < 6; i++) { |
487 | 642a4f96 | ths | if (i == 1) /* Skip CS */ |
488 | 642a4f96 | ths | continue;
|
489 | 642a4f96 | ths | |
490 | 642a4f96 | ths | *p++ = 0xb8; /* MOV AX,imm16 */ |
491 | 642a4f96 | ths | *p++ = segs[i]; |
492 | 642a4f96 | ths | *p++ = segs[i] >> 8;
|
493 | 642a4f96 | ths | *p++ = 0x8e; /* MOV <seg>,AX */ |
494 | 642a4f96 | ths | *p++ = 0xc0 + (i << 3); |
495 | 642a4f96 | ths | } |
496 | 642a4f96 | ths | |
497 | 642a4f96 | ths | for (i = 0; i < 8; i++) { |
498 | 642a4f96 | ths | *p++ = 0x66; /* 32-bit operand size */ |
499 | 642a4f96 | ths | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ |
500 | 642a4f96 | ths | *p++ = gpr[i]; |
501 | 642a4f96 | ths | *p++ = gpr[i] >> 8;
|
502 | 642a4f96 | ths | *p++ = gpr[i] >> 16;
|
503 | 642a4f96 | ths | *p++ = gpr[i] >> 24;
|
504 | 642a4f96 | ths | } |
505 | 642a4f96 | ths | |
506 | 642a4f96 | ths | *p++ = 0xea; /* JMP FAR */ |
507 | 642a4f96 | ths | *p++ = ip; /* IP */
|
508 | 642a4f96 | ths | *p++ = ip >> 8;
|
509 | 642a4f96 | ths | *p++ = segs[1]; /* CS */ |
510 | 642a4f96 | ths | *p++ = segs[1] >> 8; |
511 | 642a4f96 | ths | |
512 | 4fc9af53 | aliguori | /* sign rom */
|
513 | 4fc9af53 | aliguori | sum = 0;
|
514 | 4fc9af53 | aliguori | for (i = 0; i < (sizeof(rom) - 1); i++) |
515 | 4fc9af53 | aliguori | sum += rom[i]; |
516 | 4fc9af53 | aliguori | rom[sizeof(rom) - 1] = -sum; |
517 | 4fc9af53 | aliguori | |
518 | 4fc9af53 | aliguori | memcpy(option_rom, rom, sizeof(rom));
|
519 | 642a4f96 | ths | } |
520 | 80cabfad | bellard | |
521 | 642a4f96 | ths | static long get_file_size(FILE *f) |
522 | 642a4f96 | ths | { |
523 | 642a4f96 | ths | long where, size;
|
524 | 642a4f96 | ths | |
525 | 642a4f96 | ths | /* XXX: on Unix systems, using fstat() probably makes more sense */
|
526 | 642a4f96 | ths | |
527 | 642a4f96 | ths | where = ftell(f); |
528 | 642a4f96 | ths | fseek(f, 0, SEEK_END);
|
529 | 642a4f96 | ths | size = ftell(f); |
530 | 642a4f96 | ths | fseek(f, where, SEEK_SET); |
531 | 642a4f96 | ths | |
532 | 642a4f96 | ths | return size;
|
533 | 642a4f96 | ths | } |
534 | 642a4f96 | ths | |
535 | 4fc9af53 | aliguori | static void load_linux(uint8_t *option_rom, |
536 | 4fc9af53 | aliguori | const char *kernel_filename, |
537 | 642a4f96 | ths | const char *initrd_filename, |
538 | 642a4f96 | ths | const char *kernel_cmdline) |
539 | 642a4f96 | ths | { |
540 | 642a4f96 | ths | uint16_t protocol; |
541 | 642a4f96 | ths | uint32_t gpr[8];
|
542 | 642a4f96 | ths | uint16_t seg[6];
|
543 | 642a4f96 | ths | uint16_t real_seg; |
544 | 642a4f96 | ths | int setup_size, kernel_size, initrd_size, cmdline_size;
|
545 | 642a4f96 | ths | uint32_t initrd_max; |
546 | 642a4f96 | ths | uint8_t header[1024];
|
547 | a37af289 | blueswir1 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr; |
548 | 642a4f96 | ths | FILE *f, *fi; |
549 | 642a4f96 | ths | |
550 | 642a4f96 | ths | /* Align to 16 bytes as a paranoia measure */
|
551 | 642a4f96 | ths | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
552 | 642a4f96 | ths | |
553 | 642a4f96 | ths | /* load the kernel header */
|
554 | 642a4f96 | ths | f = fopen(kernel_filename, "rb");
|
555 | 642a4f96 | ths | if (!f || !(kernel_size = get_file_size(f)) ||
|
556 | 642a4f96 | ths | fread(header, 1, 1024, f) != 1024) { |
557 | 642a4f96 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
558 | 642a4f96 | ths | kernel_filename); |
559 | 642a4f96 | ths | exit(1);
|
560 | 642a4f96 | ths | } |
561 | 642a4f96 | ths | |
562 | 642a4f96 | ths | /* kernel protocol version */
|
563 | bc4edd79 | bellard | #if 0
|
564 | 642a4f96 | ths | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
565 | bc4edd79 | bellard | #endif
|
566 | 642a4f96 | ths | if (ldl_p(header+0x202) == 0x53726448) |
567 | 642a4f96 | ths | protocol = lduw_p(header+0x206);
|
568 | 642a4f96 | ths | else
|
569 | 642a4f96 | ths | protocol = 0;
|
570 | 642a4f96 | ths | |
571 | 642a4f96 | ths | if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
572 | 642a4f96 | ths | /* Low kernel */
|
573 | a37af289 | blueswir1 | real_addr = 0x90000;
|
574 | a37af289 | blueswir1 | cmdline_addr = 0x9a000 - cmdline_size;
|
575 | a37af289 | blueswir1 | prot_addr = 0x10000;
|
576 | 642a4f96 | ths | } else if (protocol < 0x202) { |
577 | 642a4f96 | ths | /* High but ancient kernel */
|
578 | a37af289 | blueswir1 | real_addr = 0x90000;
|
579 | a37af289 | blueswir1 | cmdline_addr = 0x9a000 - cmdline_size;
|
580 | a37af289 | blueswir1 | prot_addr = 0x100000;
|
581 | 642a4f96 | ths | } else {
|
582 | 642a4f96 | ths | /* High and recent kernel */
|
583 | a37af289 | blueswir1 | real_addr = 0x10000;
|
584 | a37af289 | blueswir1 | cmdline_addr = 0x20000;
|
585 | a37af289 | blueswir1 | prot_addr = 0x100000;
|
586 | 642a4f96 | ths | } |
587 | 642a4f96 | ths | |
588 | bc4edd79 | bellard | #if 0
|
589 | 642a4f96 | ths | fprintf(stderr,
|
590 | 526ccb7a | balrog | "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
591 | 526ccb7a | balrog | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
592 | 526ccb7a | balrog | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
593 | a37af289 | blueswir1 | real_addr,
|
594 | a37af289 | blueswir1 | cmdline_addr,
|
595 | a37af289 | blueswir1 | prot_addr);
|
596 | bc4edd79 | bellard | #endif
|
597 | 642a4f96 | ths | |
598 | 642a4f96 | ths | /* highest address for loading the initrd */
|
599 | 642a4f96 | ths | if (protocol >= 0x203) |
600 | 642a4f96 | ths | initrd_max = ldl_p(header+0x22c);
|
601 | 642a4f96 | ths | else
|
602 | 642a4f96 | ths | initrd_max = 0x37ffffff;
|
603 | 642a4f96 | ths | |
604 | 642a4f96 | ths | if (initrd_max >= ram_size-ACPI_DATA_SIZE)
|
605 | 642a4f96 | ths | initrd_max = ram_size-ACPI_DATA_SIZE-1;
|
606 | 642a4f96 | ths | |
607 | 642a4f96 | ths | /* kernel command line */
|
608 | a37af289 | blueswir1 | pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
|
609 | 642a4f96 | ths | |
610 | 642a4f96 | ths | if (protocol >= 0x202) { |
611 | a37af289 | blueswir1 | stl_p(header+0x228, cmdline_addr);
|
612 | 642a4f96 | ths | } else {
|
613 | 642a4f96 | ths | stw_p(header+0x20, 0xA33F); |
614 | 642a4f96 | ths | stw_p(header+0x22, cmdline_addr-real_addr);
|
615 | 642a4f96 | ths | } |
616 | 642a4f96 | ths | |
617 | 642a4f96 | ths | /* loader type */
|
618 | 642a4f96 | ths | /* High nybble = B reserved for Qemu; low nybble is revision number.
|
619 | 642a4f96 | ths | If this code is substantially changed, you may want to consider
|
620 | 642a4f96 | ths | incrementing the revision. */
|
621 | 642a4f96 | ths | if (protocol >= 0x200) |
622 | 642a4f96 | ths | header[0x210] = 0xB0; |
623 | 642a4f96 | ths | |
624 | 642a4f96 | ths | /* heap */
|
625 | 642a4f96 | ths | if (protocol >= 0x201) { |
626 | 642a4f96 | ths | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
627 | 642a4f96 | ths | stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
628 | 642a4f96 | ths | } |
629 | 642a4f96 | ths | |
630 | 642a4f96 | ths | /* load initrd */
|
631 | 642a4f96 | ths | if (initrd_filename) {
|
632 | 642a4f96 | ths | if (protocol < 0x200) { |
633 | 642a4f96 | ths | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
634 | 642a4f96 | ths | exit(1);
|
635 | 642a4f96 | ths | } |
636 | 642a4f96 | ths | |
637 | 642a4f96 | ths | fi = fopen(initrd_filename, "rb");
|
638 | 642a4f96 | ths | if (!fi) {
|
639 | 642a4f96 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
640 | 642a4f96 | ths | initrd_filename); |
641 | 642a4f96 | ths | exit(1);
|
642 | 642a4f96 | ths | } |
643 | 642a4f96 | ths | |
644 | 642a4f96 | ths | initrd_size = get_file_size(fi); |
645 | a37af289 | blueswir1 | initrd_addr = (initrd_max-initrd_size) & ~4095;
|
646 | 642a4f96 | ths | |
647 | 526ccb7a | balrog | fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
|
648 | 526ccb7a | balrog | "\n", initrd_size, initrd_addr);
|
649 | 642a4f96 | ths | |
650 | a37af289 | blueswir1 | if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
|
651 | 642a4f96 | ths | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
|
652 | 642a4f96 | ths | initrd_filename); |
653 | 642a4f96 | ths | exit(1);
|
654 | 642a4f96 | ths | } |
655 | 642a4f96 | ths | fclose(fi); |
656 | 642a4f96 | ths | |
657 | a37af289 | blueswir1 | stl_p(header+0x218, initrd_addr);
|
658 | 642a4f96 | ths | stl_p(header+0x21c, initrd_size);
|
659 | 642a4f96 | ths | } |
660 | 642a4f96 | ths | |
661 | 642a4f96 | ths | /* store the finalized header and load the rest of the kernel */
|
662 | a37af289 | blueswir1 | cpu_physical_memory_write(real_addr, header, 1024);
|
663 | 642a4f96 | ths | |
664 | 642a4f96 | ths | setup_size = header[0x1f1];
|
665 | 642a4f96 | ths | if (setup_size == 0) |
666 | 642a4f96 | ths | setup_size = 4;
|
667 | 642a4f96 | ths | |
668 | 642a4f96 | ths | setup_size = (setup_size+1)*512; |
669 | 642a4f96 | ths | kernel_size -= setup_size; /* Size of protected-mode code */
|
670 | 642a4f96 | ths | |
671 | a37af289 | blueswir1 | if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) || |
672 | a37af289 | blueswir1 | !fread_targphys_ok(prot_addr, kernel_size, f)) { |
673 | 642a4f96 | ths | fprintf(stderr, "qemu: read error on kernel '%s'\n",
|
674 | 642a4f96 | ths | kernel_filename); |
675 | 642a4f96 | ths | exit(1);
|
676 | 642a4f96 | ths | } |
677 | 642a4f96 | ths | fclose(f); |
678 | 642a4f96 | ths | |
679 | 642a4f96 | ths | /* generate bootsector to set up the initial register state */
|
680 | a37af289 | blueswir1 | real_seg = real_addr >> 4;
|
681 | 642a4f96 | ths | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
682 | 642a4f96 | ths | seg[1] = real_seg+0x20; /* CS */ |
683 | 642a4f96 | ths | memset(gpr, 0, sizeof gpr); |
684 | 642a4f96 | ths | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ |
685 | 642a4f96 | ths | |
686 | 4fc9af53 | aliguori | generate_bootsect(option_rom, gpr, seg, 0);
|
687 | 642a4f96 | ths | } |
688 | 642a4f96 | ths | |
689 | 59b8ad81 | bellard | static void main_cpu_reset(void *opaque) |
690 | 59b8ad81 | bellard | { |
691 | 59b8ad81 | bellard | CPUState *env = opaque; |
692 | 59b8ad81 | bellard | cpu_reset(env); |
693 | 59b8ad81 | bellard | } |
694 | 59b8ad81 | bellard | |
695 | b41a2cd1 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
696 | b41a2cd1 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
697 | b41a2cd1 | bellard | static const int ide_irq[2] = { 14, 15 }; |
698 | b41a2cd1 | bellard | |
699 | b41a2cd1 | bellard | #define NE2000_NB_MAX 6 |
700 | b41a2cd1 | bellard | |
701 | 8d11df9e | bellard | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
702 | b41a2cd1 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
703 | b41a2cd1 | bellard | |
704 | 8d11df9e | bellard | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
705 | 8d11df9e | bellard | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
706 | 8d11df9e | bellard | |
707 | 6508fe59 | bellard | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
708 | 6508fe59 | bellard | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
709 | 6508fe59 | bellard | |
710 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
711 | d537cf6c | pbrook | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
712 | 6a36d84e | bellard | { |
713 | 6a36d84e | bellard | struct soundhw *c;
|
714 | 6a36d84e | bellard | int audio_enabled = 0; |
715 | 6a36d84e | bellard | |
716 | 6a36d84e | bellard | for (c = soundhw; !audio_enabled && c->name; ++c) {
|
717 | 6a36d84e | bellard | audio_enabled = c->enabled; |
718 | 6a36d84e | bellard | } |
719 | 6a36d84e | bellard | |
720 | 6a36d84e | bellard | if (audio_enabled) {
|
721 | 6a36d84e | bellard | AudioState *s; |
722 | 6a36d84e | bellard | |
723 | 6a36d84e | bellard | s = AUD_init (); |
724 | 6a36d84e | bellard | if (s) {
|
725 | 6a36d84e | bellard | for (c = soundhw; c->name; ++c) {
|
726 | 6a36d84e | bellard | if (c->enabled) {
|
727 | 6a36d84e | bellard | if (c->isa) {
|
728 | d537cf6c | pbrook | c->init.init_isa (s, pic); |
729 | 6a36d84e | bellard | } |
730 | 6a36d84e | bellard | else {
|
731 | 6a36d84e | bellard | if (pci_bus) {
|
732 | 6a36d84e | bellard | c->init.init_pci (pci_bus, s); |
733 | 6a36d84e | bellard | } |
734 | 6a36d84e | bellard | } |
735 | 6a36d84e | bellard | } |
736 | 6a36d84e | bellard | } |
737 | 6a36d84e | bellard | } |
738 | 6a36d84e | bellard | } |
739 | 6a36d84e | bellard | } |
740 | 6a36d84e | bellard | #endif
|
741 | 6a36d84e | bellard | |
742 | d537cf6c | pbrook | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
743 | a41b2ff2 | pbrook | { |
744 | a41b2ff2 | pbrook | static int nb_ne2k = 0; |
745 | a41b2ff2 | pbrook | |
746 | a41b2ff2 | pbrook | if (nb_ne2k == NE2000_NB_MAX)
|
747 | a41b2ff2 | pbrook | return;
|
748 | d537cf6c | pbrook | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
749 | a41b2ff2 | pbrook | nb_ne2k++; |
750 | a41b2ff2 | pbrook | } |
751 | a41b2ff2 | pbrook | |
752 | 80cabfad | bellard | /* PC hardware initialisation */
|
753 | 00f82b8a | aurel32 | static void pc_init1(ram_addr_t ram_size, int vga_ram_size, |
754 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
755 | b5ff2d6e | bellard | const char *kernel_filename, const char *kernel_cmdline, |
756 | 3dbbdc25 | bellard | const char *initrd_filename, |
757 | a049de61 | bellard | int pci_enabled, const char *cpu_model) |
758 | 80cabfad | bellard | { |
759 | 80cabfad | bellard | char buf[1024]; |
760 | 642a4f96 | ths | int ret, linux_boot, i;
|
761 | 970ac5a3 | bellard | ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset; |
762 | 00f82b8a | aurel32 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
763 | 970ac5a3 | bellard | int bios_size, isa_bios_size, vga_bios_size;
|
764 | 46e50e9d | bellard | PCIBus *pci_bus; |
765 | 5c3ff3a7 | pbrook | int piix3_devfn = -1; |
766 | 59b8ad81 | bellard | CPUState *env; |
767 | a41b2ff2 | pbrook | NICInfo *nd; |
768 | d537cf6c | pbrook | qemu_irq *cpu_irq; |
769 | d537cf6c | pbrook | qemu_irq *i8259; |
770 | e4bcb14c | ths | int index;
|
771 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
772 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
773 | d592d303 | bellard | |
774 | 00f82b8a | aurel32 | if (ram_size >= 0xe0000000 ) { |
775 | 00f82b8a | aurel32 | above_4g_mem_size = ram_size - 0xe0000000;
|
776 | 00f82b8a | aurel32 | below_4g_mem_size = 0xe0000000;
|
777 | 00f82b8a | aurel32 | } else {
|
778 | 00f82b8a | aurel32 | below_4g_mem_size = ram_size; |
779 | 00f82b8a | aurel32 | } |
780 | 00f82b8a | aurel32 | |
781 | 80cabfad | bellard | linux_boot = (kernel_filename != NULL);
|
782 | 80cabfad | bellard | |
783 | 59b8ad81 | bellard | /* init CPUs */
|
784 | a049de61 | bellard | if (cpu_model == NULL) { |
785 | a049de61 | bellard | #ifdef TARGET_X86_64
|
786 | a049de61 | bellard | cpu_model = "qemu64";
|
787 | a049de61 | bellard | #else
|
788 | a049de61 | bellard | cpu_model = "qemu32";
|
789 | a049de61 | bellard | #endif
|
790 | a049de61 | bellard | } |
791 | a049de61 | bellard | |
792 | 59b8ad81 | bellard | for(i = 0; i < smp_cpus; i++) { |
793 | aaed909a | bellard | env = cpu_init(cpu_model); |
794 | aaed909a | bellard | if (!env) {
|
795 | aaed909a | bellard | fprintf(stderr, "Unable to find x86 CPU definition\n");
|
796 | aaed909a | bellard | exit(1);
|
797 | aaed909a | bellard | } |
798 | 59b8ad81 | bellard | if (i != 0) |
799 | ce5232c5 | bellard | env->halted = 1;
|
800 | 59b8ad81 | bellard | if (smp_cpus > 1) { |
801 | 59b8ad81 | bellard | /* XXX: enable it in all cases */
|
802 | 59b8ad81 | bellard | env->cpuid_features |= CPUID_APIC; |
803 | 59b8ad81 | bellard | } |
804 | 59b8ad81 | bellard | qemu_register_reset(main_cpu_reset, env); |
805 | 59b8ad81 | bellard | if (pci_enabled) {
|
806 | 59b8ad81 | bellard | apic_init(env); |
807 | 59b8ad81 | bellard | } |
808 | 59b8ad81 | bellard | } |
809 | 59b8ad81 | bellard | |
810 | 26fb5e48 | aurel32 | vmport_init(); |
811 | 26fb5e48 | aurel32 | |
812 | 80cabfad | bellard | /* allocate RAM */
|
813 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(0xa0000);
|
814 | 82b36dc3 | aliguori | cpu_register_physical_memory(0, 0xa0000, ram_addr); |
815 | 82b36dc3 | aliguori | |
816 | 82b36dc3 | aliguori | /* Allocate, even though we won't register, so we don't break the
|
817 | 82b36dc3 | aliguori | * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
|
818 | 82b36dc3 | aliguori | * and some bios areas, which will be registered later
|
819 | 82b36dc3 | aliguori | */
|
820 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); |
821 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
|
822 | 82b36dc3 | aliguori | cpu_register_physical_memory(0x100000,
|
823 | 82b36dc3 | aliguori | below_4g_mem_size - 0x100000,
|
824 | 82b36dc3 | aliguori | ram_addr); |
825 | 00f82b8a | aurel32 | |
826 | 00f82b8a | aurel32 | /* above 4giga memory allocation */
|
827 | 00f82b8a | aurel32 | if (above_4g_mem_size > 0) { |
828 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(above_4g_mem_size); |
829 | 82b36dc3 | aliguori | cpu_register_physical_memory(0x100000000ULL,
|
830 | 526ccb7a | balrog | above_4g_mem_size, |
831 | 82b36dc3 | aliguori | ram_addr); |
832 | 00f82b8a | aurel32 | } |
833 | 80cabfad | bellard | |
834 | 82b36dc3 | aliguori | |
835 | 970ac5a3 | bellard | /* allocate VGA RAM */
|
836 | 970ac5a3 | bellard | vga_ram_addr = qemu_ram_alloc(vga_ram_size); |
837 | 7587cf44 | bellard | |
838 | 970ac5a3 | bellard | /* BIOS load */
|
839 | 1192dad8 | j_mayer | if (bios_name == NULL) |
840 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
841 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
842 | 7587cf44 | bellard | bios_size = get_image_size(buf); |
843 | 5fafdf24 | ths | if (bios_size <= 0 || |
844 | 970ac5a3 | bellard | (bios_size % 65536) != 0) { |
845 | 7587cf44 | bellard | goto bios_error;
|
846 | 7587cf44 | bellard | } |
847 | 970ac5a3 | bellard | bios_offset = qemu_ram_alloc(bios_size); |
848 | 7587cf44 | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
849 | 7587cf44 | bellard | if (ret != bios_size) {
|
850 | 7587cf44 | bellard | bios_error:
|
851 | 970ac5a3 | bellard | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
|
852 | 80cabfad | bellard | exit(1);
|
853 | 80cabfad | bellard | } |
854 | 7587cf44 | bellard | |
855 | 80cabfad | bellard | /* VGA BIOS load */
|
856 | de9258a8 | bellard | if (cirrus_vga_enabled) {
|
857 | de9258a8 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME); |
858 | de9258a8 | bellard | } else {
|
859 | de9258a8 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
860 | de9258a8 | bellard | } |
861 | 970ac5a3 | bellard | vga_bios_size = get_image_size(buf); |
862 | 5fafdf24 | ths | if (vga_bios_size <= 0 || vga_bios_size > 65536) |
863 | 970ac5a3 | bellard | goto vga_bios_error;
|
864 | 970ac5a3 | bellard | vga_bios_offset = qemu_ram_alloc(65536);
|
865 | 970ac5a3 | bellard | |
866 | 7587cf44 | bellard | ret = load_image(buf, phys_ram_base + vga_bios_offset); |
867 | 970ac5a3 | bellard | if (ret != vga_bios_size) {
|
868 | 970ac5a3 | bellard | vga_bios_error:
|
869 | 970ac5a3 | bellard | fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
|
870 | 970ac5a3 | bellard | exit(1);
|
871 | 970ac5a3 | bellard | } |
872 | 970ac5a3 | bellard | |
873 | 80cabfad | bellard | /* setup basic memory access */
|
874 | 5fafdf24 | ths | cpu_register_physical_memory(0xc0000, 0x10000, |
875 | 7587cf44 | bellard | vga_bios_offset | IO_MEM_ROM); |
876 | 7587cf44 | bellard | |
877 | 7587cf44 | bellard | /* map the last 128KB of the BIOS in ISA space */
|
878 | 7587cf44 | bellard | isa_bios_size = bios_size; |
879 | 7587cf44 | bellard | if (isa_bios_size > (128 * 1024)) |
880 | 7587cf44 | bellard | isa_bios_size = 128 * 1024; |
881 | 5fafdf24 | ths | cpu_register_physical_memory(0x100000 - isa_bios_size,
|
882 | 5fafdf24 | ths | isa_bios_size, |
883 | 7587cf44 | bellard | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
884 | 9ae02555 | ths | |
885 | 970ac5a3 | bellard | { |
886 | 970ac5a3 | bellard | ram_addr_t option_rom_offset; |
887 | 970ac5a3 | bellard | int size, offset;
|
888 | 970ac5a3 | bellard | |
889 | 970ac5a3 | bellard | offset = 0;
|
890 | 4fc9af53 | aliguori | if (linux_boot) {
|
891 | 4fc9af53 | aliguori | option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE); |
892 | 4fc9af53 | aliguori | load_linux(phys_ram_base + option_rom_offset, |
893 | 4fc9af53 | aliguori | kernel_filename, initrd_filename, kernel_cmdline); |
894 | 4fc9af53 | aliguori | cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE,
|
895 | 4fc9af53 | aliguori | option_rom_offset | IO_MEM_ROM); |
896 | 4fc9af53 | aliguori | offset = TARGET_PAGE_SIZE; |
897 | 4fc9af53 | aliguori | } |
898 | 4fc9af53 | aliguori | |
899 | 970ac5a3 | bellard | for (i = 0; i < nb_option_roms; i++) { |
900 | 970ac5a3 | bellard | size = get_image_size(option_rom[i]); |
901 | 970ac5a3 | bellard | if (size < 0) { |
902 | 5fafdf24 | ths | fprintf(stderr, "Could not load option rom '%s'\n",
|
903 | 970ac5a3 | bellard | option_rom[i]); |
904 | 970ac5a3 | bellard | exit(1);
|
905 | 970ac5a3 | bellard | } |
906 | 970ac5a3 | bellard | if (size > (0x10000 - offset)) |
907 | 970ac5a3 | bellard | goto option_rom_error;
|
908 | 970ac5a3 | bellard | option_rom_offset = qemu_ram_alloc(size); |
909 | 970ac5a3 | bellard | ret = load_image(option_rom[i], phys_ram_base + option_rom_offset); |
910 | 970ac5a3 | bellard | if (ret != size) {
|
911 | 970ac5a3 | bellard | option_rom_error:
|
912 | 970ac5a3 | bellard | fprintf(stderr, "Too many option ROMS\n");
|
913 | 970ac5a3 | bellard | exit(1);
|
914 | 970ac5a3 | bellard | } |
915 | 970ac5a3 | bellard | size = (size + 4095) & ~4095; |
916 | 970ac5a3 | bellard | cpu_register_physical_memory(0xd0000 + offset,
|
917 | 970ac5a3 | bellard | size, option_rom_offset | IO_MEM_ROM); |
918 | 970ac5a3 | bellard | offset += size; |
919 | 970ac5a3 | bellard | } |
920 | 9ae02555 | ths | } |
921 | 9ae02555 | ths | |
922 | 7587cf44 | bellard | /* map all the bios at the top of memory */
|
923 | 5fafdf24 | ths | cpu_register_physical_memory((uint32_t)(-bios_size), |
924 | 7587cf44 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
925 | 3b46e624 | ths | |
926 | 80cabfad | bellard | bochs_bios_init(); |
927 | 80cabfad | bellard | |
928 | a5b38b51 | aurel32 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
929 | d537cf6c | pbrook | i8259 = i8259_init(cpu_irq[0]);
|
930 | d537cf6c | pbrook | ferr_irq = i8259[13];
|
931 | d537cf6c | pbrook | |
932 | 69b91039 | bellard | if (pci_enabled) {
|
933 | d537cf6c | pbrook | pci_bus = i440fx_init(&i440fx_state, i8259); |
934 | 8f1c91d8 | ths | piix3_devfn = piix3_init(pci_bus, -1);
|
935 | 46e50e9d | bellard | } else {
|
936 | 46e50e9d | bellard | pci_bus = NULL;
|
937 | 69b91039 | bellard | } |
938 | 69b91039 | bellard | |
939 | 80cabfad | bellard | /* init basic PC hardware */
|
940 | b41a2cd1 | bellard | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
941 | 80cabfad | bellard | |
942 | f929aad6 | bellard | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
943 | f929aad6 | bellard | |
944 | 1f04275e | bellard | if (cirrus_vga_enabled) {
|
945 | 1f04275e | bellard | if (pci_enabled) {
|
946 | 5fafdf24 | ths | pci_cirrus_vga_init(pci_bus, |
947 | 5fafdf24 | ths | ds, phys_ram_base + vga_ram_addr, |
948 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size); |
949 | 1f04275e | bellard | } else {
|
950 | 5fafdf24 | ths | isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr, |
951 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size); |
952 | 1f04275e | bellard | } |
953 | d34cab9f | ths | } else if (vmsvga_enabled) { |
954 | d34cab9f | ths | if (pci_enabled)
|
955 | 45e4522e | balrog | pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
956 | 45e4522e | balrog | vga_ram_addr, vga_ram_size); |
957 | d34cab9f | ths | else
|
958 | d34cab9f | ths | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
959 | 1f04275e | bellard | } else {
|
960 | 89b6b508 | bellard | if (pci_enabled) {
|
961 | 5fafdf24 | ths | pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
962 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size, 0, 0); |
963 | 89b6b508 | bellard | } else {
|
964 | 5fafdf24 | ths | isa_vga_init(ds, phys_ram_base + vga_ram_addr, |
965 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size); |
966 | 89b6b508 | bellard | } |
967 | 1f04275e | bellard | } |
968 | 80cabfad | bellard | |
969 | d537cf6c | pbrook | rtc_state = rtc_init(0x70, i8259[8]); |
970 | 80cabfad | bellard | |
971 | 3b4366de | blueswir1 | qemu_register_boot_set(pc_boot_set, rtc_state); |
972 | 3b4366de | blueswir1 | |
973 | e1a23744 | bellard | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
974 | e1a23744 | bellard | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
975 | e1a23744 | bellard | |
976 | d592d303 | bellard | if (pci_enabled) {
|
977 | d592d303 | bellard | ioapic = ioapic_init(); |
978 | d592d303 | bellard | } |
979 | d537cf6c | pbrook | pit = pit_init(0x40, i8259[0]); |
980 | fd06c375 | bellard | pcspk_init(pit); |
981 | 16b29ae1 | aliguori | if (!no_hpet) {
|
982 | 16b29ae1 | aliguori | hpet_init(i8259); |
983 | 16b29ae1 | aliguori | } |
984 | d592d303 | bellard | if (pci_enabled) {
|
985 | d592d303 | bellard | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); |
986 | d592d303 | bellard | } |
987 | b41a2cd1 | bellard | |
988 | 8d11df9e | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
989 | 8d11df9e | bellard | if (serial_hds[i]) {
|
990 | b6cd0ea1 | aurel32 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
|
991 | b6cd0ea1 | aurel32 | serial_hds[i]); |
992 | 8d11df9e | bellard | } |
993 | 8d11df9e | bellard | } |
994 | b41a2cd1 | bellard | |
995 | 6508fe59 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
996 | 6508fe59 | bellard | if (parallel_hds[i]) {
|
997 | d537cf6c | pbrook | parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
998 | d537cf6c | pbrook | parallel_hds[i]); |
999 | 6508fe59 | bellard | } |
1000 | 6508fe59 | bellard | } |
1001 | 6508fe59 | bellard | |
1002 | a41b2ff2 | pbrook | for(i = 0; i < nb_nics; i++) { |
1003 | a41b2ff2 | pbrook | nd = &nd_table[i]; |
1004 | a41b2ff2 | pbrook | if (!nd->model) {
|
1005 | a41b2ff2 | pbrook | if (pci_enabled) {
|
1006 | a41b2ff2 | pbrook | nd->model = "ne2k_pci";
|
1007 | a41b2ff2 | pbrook | } else {
|
1008 | a41b2ff2 | pbrook | nd->model = "ne2k_isa";
|
1009 | a41b2ff2 | pbrook | } |
1010 | 69b91039 | bellard | } |
1011 | a41b2ff2 | pbrook | if (strcmp(nd->model, "ne2k_isa") == 0) { |
1012 | d537cf6c | pbrook | pc_init_ne2k_isa(nd, i8259); |
1013 | a41b2ff2 | pbrook | } else if (pci_enabled) { |
1014 | c4a7060c | blueswir1 | if (strcmp(nd->model, "?") == 0) |
1015 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
|
1016 | abcebc7e | ths | pci_nic_init(pci_bus, nd, -1);
|
1017 | c4a7060c | blueswir1 | } else if (strcmp(nd->model, "?") == 0) { |
1018 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
|
1019 | c4a7060c | blueswir1 | exit(1);
|
1020 | a41b2ff2 | pbrook | } else {
|
1021 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
1022 | a41b2ff2 | pbrook | exit(1);
|
1023 | 69b91039 | bellard | } |
1024 | a41b2ff2 | pbrook | } |
1025 | b41a2cd1 | bellard | |
1026 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
1027 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
1028 | e4bcb14c | ths | exit(1);
|
1029 | e4bcb14c | ths | } |
1030 | e4bcb14c | ths | |
1031 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
1032 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
1033 | e4bcb14c | ths | if (index != -1) |
1034 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
1035 | e4bcb14c | ths | else
|
1036 | e4bcb14c | ths | hd[i] = NULL;
|
1037 | e4bcb14c | ths | } |
1038 | e4bcb14c | ths | |
1039 | a41b2ff2 | pbrook | if (pci_enabled) {
|
1040 | e4bcb14c | ths | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
|
1041 | a41b2ff2 | pbrook | } else {
|
1042 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) { |
1043 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
1044 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
1045 | 69b91039 | bellard | } |
1046 | b41a2cd1 | bellard | } |
1047 | 69b91039 | bellard | |
1048 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
1049 | 7c29d0c0 | bellard | DMA_init(0);
|
1050 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
1051 | d537cf6c | pbrook | audio_init(pci_enabled ? pci_bus : NULL, i8259);
|
1052 | fb065187 | bellard | #endif
|
1053 | 80cabfad | bellard | |
1054 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
1055 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, i);
|
1056 | e4bcb14c | ths | if (index != -1) |
1057 | e4bcb14c | ths | fd[i] = drives_table[index].bdrv; |
1058 | e4bcb14c | ths | else
|
1059 | e4bcb14c | ths | fd[i] = NULL;
|
1060 | e4bcb14c | ths | } |
1061 | e4bcb14c | ths | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
1062 | b41a2cd1 | bellard | |
1063 | 00f82b8a | aurel32 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
1064 | 69b91039 | bellard | |
1065 | bb36d470 | bellard | if (pci_enabled && usb_enabled) {
|
1066 | afcc3cdf | ths | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
1067 | bb36d470 | bellard | } |
1068 | bb36d470 | bellard | |
1069 | 6515b203 | bellard | if (pci_enabled && acpi_enabled) {
|
1070 | 3fffc223 | ths | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
1071 | 0ff596d0 | pbrook | i2c_bus *smbus; |
1072 | 0ff596d0 | pbrook | |
1073 | 0ff596d0 | pbrook | /* TODO: Populate SPD eeprom data. */
|
1074 | cf7a2fe2 | aurel32 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
1075 | 3fffc223 | ths | for (i = 0; i < 8; i++) { |
1076 | 0ff596d0 | pbrook | smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256)); |
1077 | 3fffc223 | ths | } |
1078 | 6515b203 | bellard | } |
1079 | 3b46e624 | ths | |
1080 | a5954d5c | bellard | if (i440fx_state) {
|
1081 | a5954d5c | bellard | i440fx_init_memory_mappings(i440fx_state); |
1082 | a5954d5c | bellard | } |
1083 | e4bcb14c | ths | |
1084 | 7d8406be | pbrook | if (pci_enabled) {
|
1085 | e4bcb14c | ths | int max_bus;
|
1086 | e4bcb14c | ths | int bus, unit;
|
1087 | 7d8406be | pbrook | void *scsi;
|
1088 | 96d30e48 | ths | |
1089 | e4bcb14c | ths | max_bus = drive_get_max_bus(IF_SCSI); |
1090 | e4bcb14c | ths | |
1091 | e4bcb14c | ths | for (bus = 0; bus <= max_bus; bus++) { |
1092 | e4bcb14c | ths | scsi = lsi_scsi_init(pci_bus, -1);
|
1093 | e4bcb14c | ths | for (unit = 0; unit < LSI_MAX_DEVS; unit++) { |
1094 | e4bcb14c | ths | index = drive_get_index(IF_SCSI, bus, unit); |
1095 | e4bcb14c | ths | if (index == -1) |
1096 | e4bcb14c | ths | continue;
|
1097 | e4bcb14c | ths | lsi_scsi_attach(scsi, drives_table[index].bdrv, unit); |
1098 | e4bcb14c | ths | } |
1099 | e4bcb14c | ths | } |
1100 | 7d8406be | pbrook | } |
1101 | 6e02c38d | aliguori | |
1102 | 6e02c38d | aliguori | /* Add virtio block devices */
|
1103 | 6e02c38d | aliguori | if (pci_enabled) {
|
1104 | 6e02c38d | aliguori | int index;
|
1105 | 6e02c38d | aliguori | int unit_id = 0; |
1106 | 6e02c38d | aliguori | |
1107 | 6e02c38d | aliguori | while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { |
1108 | 9b32d5a5 | aliguori | virtio_blk_init(pci_bus, drives_table[index].bdrv); |
1109 | 6e02c38d | aliguori | unit_id++; |
1110 | 6e02c38d | aliguori | } |
1111 | 6e02c38d | aliguori | } |
1112 | bd322087 | aliguori | |
1113 | bd322087 | aliguori | /* Add virtio balloon device */
|
1114 | bd322087 | aliguori | if (pci_enabled)
|
1115 | bd322087 | aliguori | virtio_balloon_init(pci_bus); |
1116 | 80cabfad | bellard | } |
1117 | b5ff2d6e | bellard | |
1118 | 00f82b8a | aurel32 | static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size, |
1119 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1120 | 5fafdf24 | ths | const char *kernel_filename, |
1121 | 3dbbdc25 | bellard | const char *kernel_cmdline, |
1122 | 94fc95cd | j_mayer | const char *initrd_filename, |
1123 | 94fc95cd | j_mayer | const char *cpu_model) |
1124 | 3dbbdc25 | bellard | { |
1125 | b881c2c6 | blueswir1 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
1126 | 3dbbdc25 | bellard | kernel_filename, kernel_cmdline, |
1127 | a049de61 | bellard | initrd_filename, 1, cpu_model);
|
1128 | 3dbbdc25 | bellard | } |
1129 | 3dbbdc25 | bellard | |
1130 | 00f82b8a | aurel32 | static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size, |
1131 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1132 | 5fafdf24 | ths | const char *kernel_filename, |
1133 | 3dbbdc25 | bellard | const char *kernel_cmdline, |
1134 | 94fc95cd | j_mayer | const char *initrd_filename, |
1135 | 94fc95cd | j_mayer | const char *cpu_model) |
1136 | 3dbbdc25 | bellard | { |
1137 | b881c2c6 | blueswir1 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
1138 | 3dbbdc25 | bellard | kernel_filename, kernel_cmdline, |
1139 | a049de61 | bellard | initrd_filename, 0, cpu_model);
|
1140 | 3dbbdc25 | bellard | } |
1141 | 3dbbdc25 | bellard | |
1142 | 0bacd130 | aliguori | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
1143 | 0bacd130 | aliguori | BIOS will read it and start S3 resume at POST Entry */
|
1144 | 0bacd130 | aliguori | void cmos_set_s3_resume(void) |
1145 | 0bacd130 | aliguori | { |
1146 | 0bacd130 | aliguori | if (rtc_state)
|
1147 | 0bacd130 | aliguori | rtc_set_memory(rtc_state, 0xF, 0xFE); |
1148 | 0bacd130 | aliguori | } |
1149 | 0bacd130 | aliguori | |
1150 | b5ff2d6e | bellard | QEMUMachine pc_machine = { |
1151 | a245f2e7 | aurel32 | .name = "pc",
|
1152 | a245f2e7 | aurel32 | .desc = "Standard PC",
|
1153 | a245f2e7 | aurel32 | .init = pc_init_pci, |
1154 | a245f2e7 | aurel32 | .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, |
1155 | b2097003 | aliguori | .max_cpus = 255,
|
1156 | 3dbbdc25 | bellard | }; |
1157 | 3dbbdc25 | bellard | |
1158 | 3dbbdc25 | bellard | QEMUMachine isapc_machine = { |
1159 | a245f2e7 | aurel32 | .name = "isapc",
|
1160 | a245f2e7 | aurel32 | .desc = "ISA-only PC",
|
1161 | a245f2e7 | aurel32 | .init = pc_init_isa, |
1162 | a245f2e7 | aurel32 | .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, |
1163 | b2097003 | aliguori | .max_cpus = 1,
|
1164 | b5ff2d6e | bellard | }; |