root / hw / ppc4xx_pci.c @ 2c277908
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1 | 825bb581 | aurel32 | /*
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2 | 825bb581 | aurel32 | * This program is free software; you can redistribute it and/or modify
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3 | 825bb581 | aurel32 | * it under the terms of the GNU General Public License, version 2, as
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4 | 825bb581 | aurel32 | * published by the Free Software Foundation.
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5 | 825bb581 | aurel32 | *
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6 | 825bb581 | aurel32 | * This program is distributed in the hope that it will be useful,
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7 | 825bb581 | aurel32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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8 | 825bb581 | aurel32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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9 | 825bb581 | aurel32 | * GNU General Public License for more details.
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10 | 825bb581 | aurel32 | *
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11 | 825bb581 | aurel32 | * You should have received a copy of the GNU General Public License
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12 | 825bb581 | aurel32 | * along with this program; if not, write to the Free Software
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13 | 825bb581 | aurel32 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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14 | 825bb581 | aurel32 | *
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15 | 825bb581 | aurel32 | * Copyright IBM Corp. 2008
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16 | 825bb581 | aurel32 | *
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17 | 825bb581 | aurel32 | * Authors: Hollis Blanchard <hollisb@us.ibm.com>
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18 | 825bb581 | aurel32 | */
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19 | 825bb581 | aurel32 | |
20 | 825bb581 | aurel32 | /* This file implements emulation of the 32-bit PCI controller found in some
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21 | 825bb581 | aurel32 | * 4xx SoCs, such as the 440EP. */
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22 | 825bb581 | aurel32 | |
23 | 825bb581 | aurel32 | #include "hw.h" |
24 | 0c34a5d7 | aurel32 | #include "ppc.h" |
25 | 0c34a5d7 | aurel32 | #include "ppc4xx.h" |
26 | 825bb581 | aurel32 | |
27 | 825bb581 | aurel32 | typedef target_phys_addr_t pci_addr_t;
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28 | 825bb581 | aurel32 | #include "pci.h" |
29 | 825bb581 | aurel32 | #include "pci_host.h" |
30 | 825bb581 | aurel32 | #include "bswap.h" |
31 | 825bb581 | aurel32 | |
32 | 825bb581 | aurel32 | #undef DEBUG
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33 | 825bb581 | aurel32 | #ifdef DEBUG
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34 | 825bb581 | aurel32 | #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0) |
35 | 825bb581 | aurel32 | #else
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36 | 825bb581 | aurel32 | #define DPRINTF(fmt, args...)
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37 | 825bb581 | aurel32 | #endif /* DEBUG */ |
38 | 825bb581 | aurel32 | |
39 | 825bb581 | aurel32 | struct PCIMasterMap {
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40 | 825bb581 | aurel32 | uint32_t la; |
41 | 825bb581 | aurel32 | uint32_t ma; |
42 | 825bb581 | aurel32 | uint32_t pcila; |
43 | 825bb581 | aurel32 | uint32_t pciha; |
44 | 825bb581 | aurel32 | }; |
45 | 825bb581 | aurel32 | |
46 | 825bb581 | aurel32 | struct PCITargetMap {
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47 | 825bb581 | aurel32 | uint32_t ms; |
48 | 825bb581 | aurel32 | uint32_t la; |
49 | 825bb581 | aurel32 | }; |
50 | 825bb581 | aurel32 | |
51 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PMMS 3 |
52 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PTMS 2 |
53 | 825bb581 | aurel32 | |
54 | 825bb581 | aurel32 | struct PPC4xxPCIState {
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55 | 825bb581 | aurel32 | struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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56 | 825bb581 | aurel32 | struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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57 | 825bb581 | aurel32 | |
58 | 825bb581 | aurel32 | PCIHostState pci_state; |
59 | 825bb581 | aurel32 | PCIDevice *pci_dev; |
60 | 825bb581 | aurel32 | }; |
61 | 825bb581 | aurel32 | typedef struct PPC4xxPCIState PPC4xxPCIState; |
62 | 825bb581 | aurel32 | |
63 | 825bb581 | aurel32 | #define PCIC0_CFGADDR 0x0 |
64 | 825bb581 | aurel32 | #define PCIC0_CFGDATA 0x4 |
65 | 825bb581 | aurel32 | |
66 | 825bb581 | aurel32 | /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
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67 | 825bb581 | aurel32 | * PCI accesses. */
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68 | 825bb581 | aurel32 | #define PCIL0_PMM0LA 0x0 |
69 | 825bb581 | aurel32 | #define PCIL0_PMM0MA 0x4 |
70 | 825bb581 | aurel32 | #define PCIL0_PMM0PCILA 0x8 |
71 | 825bb581 | aurel32 | #define PCIL0_PMM0PCIHA 0xc |
72 | 825bb581 | aurel32 | #define PCIL0_PMM1LA 0x10 |
73 | 825bb581 | aurel32 | #define PCIL0_PMM1MA 0x14 |
74 | 825bb581 | aurel32 | #define PCIL0_PMM1PCILA 0x18 |
75 | 825bb581 | aurel32 | #define PCIL0_PMM1PCIHA 0x1c |
76 | 825bb581 | aurel32 | #define PCIL0_PMM2LA 0x20 |
77 | 825bb581 | aurel32 | #define PCIL0_PMM2MA 0x24 |
78 | 825bb581 | aurel32 | #define PCIL0_PMM2PCILA 0x28 |
79 | 825bb581 | aurel32 | #define PCIL0_PMM2PCIHA 0x2c |
80 | 825bb581 | aurel32 | |
81 | 825bb581 | aurel32 | /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
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82 | 825bb581 | aurel32 | * PLB accesses. */
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83 | 825bb581 | aurel32 | #define PCIL0_PTM1MS 0x30 |
84 | 825bb581 | aurel32 | #define PCIL0_PTM1LA 0x34 |
85 | 825bb581 | aurel32 | #define PCIL0_PTM2MS 0x38 |
86 | 825bb581 | aurel32 | #define PCIL0_PTM2LA 0x3c |
87 | 825bb581 | aurel32 | #define PCI_REG_SIZE 0x40 |
88 | 825bb581 | aurel32 | |
89 | 825bb581 | aurel32 | |
90 | 825bb581 | aurel32 | static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr) |
91 | 825bb581 | aurel32 | { |
92 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
93 | 825bb581 | aurel32 | |
94 | 825bb581 | aurel32 | return ppc4xx_pci->pci_state.config_reg;
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95 | 825bb581 | aurel32 | } |
96 | 825bb581 | aurel32 | |
97 | 825bb581 | aurel32 | static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
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98 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
99 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
100 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
101 | 825bb581 | aurel32 | }; |
102 | 825bb581 | aurel32 | |
103 | 825bb581 | aurel32 | static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, |
104 | 825bb581 | aurel32 | uint32_t value) |
105 | 825bb581 | aurel32 | { |
106 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
107 | 825bb581 | aurel32 | |
108 | 825bb581 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
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109 | 825bb581 | aurel32 | value = bswap32(value); |
110 | 825bb581 | aurel32 | #endif
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111 | 825bb581 | aurel32 | |
112 | 825bb581 | aurel32 | ppc4xx_pci->pci_state.config_reg = value & ~0x3;
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113 | 825bb581 | aurel32 | } |
114 | 825bb581 | aurel32 | |
115 | 825bb581 | aurel32 | static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
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116 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
117 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
118 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
119 | 825bb581 | aurel32 | }; |
120 | 825bb581 | aurel32 | |
121 | 825bb581 | aurel32 | static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
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122 | 825bb581 | aurel32 | &pci_host_data_readb, |
123 | 825bb581 | aurel32 | &pci_host_data_readw, |
124 | 825bb581 | aurel32 | &pci_host_data_readl, |
125 | 825bb581 | aurel32 | }; |
126 | 825bb581 | aurel32 | |
127 | 825bb581 | aurel32 | static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
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128 | 825bb581 | aurel32 | &pci_host_data_writeb, |
129 | 825bb581 | aurel32 | &pci_host_data_writew, |
130 | 825bb581 | aurel32 | &pci_host_data_writel, |
131 | 825bb581 | aurel32 | }; |
132 | 825bb581 | aurel32 | |
133 | 825bb581 | aurel32 | static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, |
134 | 825bb581 | aurel32 | uint32_t value) |
135 | 825bb581 | aurel32 | { |
136 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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137 | 825bb581 | aurel32 | |
138 | 825bb581 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
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139 | 825bb581 | aurel32 | value = bswap32(value); |
140 | 825bb581 | aurel32 | #endif
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141 | 825bb581 | aurel32 | |
142 | 825bb581 | aurel32 | /* We ignore all target attempts at PCI configuration, effectively
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143 | 825bb581 | aurel32 | * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
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144 | 825bb581 | aurel32 | |
145 | 825bb581 | aurel32 | switch (offset) {
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146 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
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147 | 825bb581 | aurel32 | pci->pmm[0].la = value;
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148 | 825bb581 | aurel32 | break;
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149 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
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150 | 825bb581 | aurel32 | pci->pmm[0].ma = value;
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151 | 825bb581 | aurel32 | break;
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152 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
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153 | 825bb581 | aurel32 | pci->pmm[0].pciha = value;
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154 | 825bb581 | aurel32 | break;
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155 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
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156 | 825bb581 | aurel32 | pci->pmm[0].pcila = value;
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157 | 825bb581 | aurel32 | break;
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158 | 825bb581 | aurel32 | |
159 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
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160 | 825bb581 | aurel32 | pci->pmm[1].la = value;
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161 | 825bb581 | aurel32 | break;
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162 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
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163 | 825bb581 | aurel32 | pci->pmm[1].ma = value;
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164 | 825bb581 | aurel32 | break;
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165 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
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166 | 825bb581 | aurel32 | pci->pmm[1].pciha = value;
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167 | 825bb581 | aurel32 | break;
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168 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
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169 | 825bb581 | aurel32 | pci->pmm[1].pcila = value;
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170 | 825bb581 | aurel32 | break;
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171 | 825bb581 | aurel32 | |
172 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
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173 | 825bb581 | aurel32 | pci->pmm[2].la = value;
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174 | 825bb581 | aurel32 | break;
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175 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
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176 | 825bb581 | aurel32 | pci->pmm[2].ma = value;
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177 | 825bb581 | aurel32 | break;
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178 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
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179 | 825bb581 | aurel32 | pci->pmm[2].pciha = value;
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180 | 825bb581 | aurel32 | break;
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181 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
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182 | 825bb581 | aurel32 | pci->pmm[2].pcila = value;
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183 | 825bb581 | aurel32 | break;
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184 | 825bb581 | aurel32 | |
185 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
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186 | 825bb581 | aurel32 | pci->ptm[0].ms = value;
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187 | 825bb581 | aurel32 | break;
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188 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
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189 | 825bb581 | aurel32 | pci->ptm[0].la = value;
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190 | 825bb581 | aurel32 | break;
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191 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
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192 | 825bb581 | aurel32 | pci->ptm[1].ms = value;
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193 | 825bb581 | aurel32 | break;
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194 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
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195 | 825bb581 | aurel32 | pci->ptm[1].la = value;
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196 | 825bb581 | aurel32 | break;
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197 | 825bb581 | aurel32 | |
198 | 825bb581 | aurel32 | default:
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199 | 825bb581 | aurel32 | printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
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200 | 825bb581 | aurel32 | (unsigned long)offset); |
201 | 825bb581 | aurel32 | break;
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202 | 825bb581 | aurel32 | } |
203 | 825bb581 | aurel32 | } |
204 | 825bb581 | aurel32 | |
205 | 825bb581 | aurel32 | static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) |
206 | 825bb581 | aurel32 | { |
207 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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208 | 825bb581 | aurel32 | uint32_t value; |
209 | 825bb581 | aurel32 | |
210 | 825bb581 | aurel32 | switch (offset) {
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211 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
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212 | 825bb581 | aurel32 | value = pci->pmm[0].la;
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213 | 825bb581 | aurel32 | break;
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214 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
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215 | 825bb581 | aurel32 | value = pci->pmm[0].ma;
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216 | 825bb581 | aurel32 | break;
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217 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
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218 | 825bb581 | aurel32 | value = pci->pmm[0].pciha;
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219 | 825bb581 | aurel32 | break;
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220 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
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221 | 825bb581 | aurel32 | value = pci->pmm[0].pcila;
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222 | 825bb581 | aurel32 | break;
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223 | 825bb581 | aurel32 | |
224 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
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225 | 825bb581 | aurel32 | value = pci->pmm[1].la;
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226 | 825bb581 | aurel32 | break;
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227 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
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228 | 825bb581 | aurel32 | value = pci->pmm[1].ma;
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229 | 825bb581 | aurel32 | break;
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230 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
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231 | 825bb581 | aurel32 | value = pci->pmm[1].pciha;
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232 | 825bb581 | aurel32 | break;
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233 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
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234 | 825bb581 | aurel32 | value = pci->pmm[1].pcila;
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235 | 825bb581 | aurel32 | break;
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236 | 825bb581 | aurel32 | |
237 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
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238 | 825bb581 | aurel32 | value = pci->pmm[2].la;
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239 | 825bb581 | aurel32 | break;
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240 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
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241 | 825bb581 | aurel32 | value = pci->pmm[2].ma;
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242 | 825bb581 | aurel32 | break;
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243 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
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244 | 825bb581 | aurel32 | value = pci->pmm[2].pciha;
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245 | 825bb581 | aurel32 | break;
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246 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
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247 | 825bb581 | aurel32 | value = pci->pmm[2].pcila;
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248 | 825bb581 | aurel32 | break;
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249 | 825bb581 | aurel32 | |
250 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
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251 | 825bb581 | aurel32 | value = pci->ptm[0].ms;
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252 | 825bb581 | aurel32 | break;
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253 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
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254 | 825bb581 | aurel32 | value = pci->ptm[0].la;
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255 | 825bb581 | aurel32 | break;
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256 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
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257 | 825bb581 | aurel32 | value = pci->ptm[1].ms;
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258 | 825bb581 | aurel32 | break;
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259 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
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260 | 825bb581 | aurel32 | value = pci->ptm[1].la;
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261 | 825bb581 | aurel32 | break;
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262 | 825bb581 | aurel32 | |
263 | 825bb581 | aurel32 | default:
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264 | 825bb581 | aurel32 | printf("%s: invalid PCI internal register 0x%lx\n", __func__,
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265 | 825bb581 | aurel32 | (unsigned long)offset); |
266 | 825bb581 | aurel32 | value = 0;
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267 | 825bb581 | aurel32 | } |
268 | 825bb581 | aurel32 | |
269 | 825bb581 | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
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270 | 825bb581 | aurel32 | value = bswap32(value); |
271 | 825bb581 | aurel32 | #endif
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272 | 825bb581 | aurel32 | |
273 | 825bb581 | aurel32 | return value;
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274 | 825bb581 | aurel32 | } |
275 | 825bb581 | aurel32 | |
276 | 825bb581 | aurel32 | static CPUReadMemoryFunc *pci_reg_read[] = {
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277 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
278 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
279 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
280 | 825bb581 | aurel32 | }; |
281 | 825bb581 | aurel32 | |
282 | 825bb581 | aurel32 | static CPUWriteMemoryFunc *pci_reg_write[] = {
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283 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
284 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
285 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
286 | 825bb581 | aurel32 | }; |
287 | 825bb581 | aurel32 | |
288 | 825bb581 | aurel32 | static void ppc4xx_pci_reset(void *opaque) |
289 | 825bb581 | aurel32 | { |
290 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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291 | 825bb581 | aurel32 | |
292 | 825bb581 | aurel32 | memset(pci->pmm, 0, sizeof(pci->pmm)); |
293 | 825bb581 | aurel32 | memset(pci->ptm, 0, sizeof(pci->ptm)); |
294 | 825bb581 | aurel32 | } |
295 | 825bb581 | aurel32 | |
296 | 825bb581 | aurel32 | /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
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297 | 825bb581 | aurel32 | * may need further refactoring for other boards. */
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298 | 825bb581 | aurel32 | static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
299 | 825bb581 | aurel32 | { |
300 | 825bb581 | aurel32 | int slot = pci_dev->devfn >> 3; |
301 | 825bb581 | aurel32 | |
302 | 825bb581 | aurel32 | DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
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303 | 825bb581 | aurel32 | pci_dev->devfn, irq_num, slot); |
304 | 825bb581 | aurel32 | |
305 | 825bb581 | aurel32 | return slot - 1; |
306 | 825bb581 | aurel32 | } |
307 | 825bb581 | aurel32 | |
308 | 825bb581 | aurel32 | static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level) |
309 | 825bb581 | aurel32 | { |
310 | 825bb581 | aurel32 | DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
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311 | 825bb581 | aurel32 | qemu_set_irq(pci_irqs[irq_num], level); |
312 | 825bb581 | aurel32 | } |
313 | 825bb581 | aurel32 | |
314 | 825bb581 | aurel32 | static void ppc4xx_pci_save(QEMUFile *f, void *opaque) |
315 | 825bb581 | aurel32 | { |
316 | 825bb581 | aurel32 | PPC4xxPCIState *controller = opaque; |
317 | 825bb581 | aurel32 | int i;
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318 | 825bb581 | aurel32 | |
319 | 3476f891 | aurel32 | pci_device_save(controller->pci_dev, f); |
320 | 825bb581 | aurel32 | |
321 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) { |
322 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].la); |
323 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].ma); |
324 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].pcila); |
325 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].pciha); |
326 | 825bb581 | aurel32 | } |
327 | 825bb581 | aurel32 | |
328 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) { |
329 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->ptm[i].ms); |
330 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->ptm[i].la); |
331 | 825bb581 | aurel32 | } |
332 | 825bb581 | aurel32 | } |
333 | 825bb581 | aurel32 | |
334 | 825bb581 | aurel32 | static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id) |
335 | 825bb581 | aurel32 | { |
336 | 825bb581 | aurel32 | PPC4xxPCIState *controller = opaque; |
337 | 825bb581 | aurel32 | int i;
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338 | 825bb581 | aurel32 | |
339 | 825bb581 | aurel32 | if (version_id != 1) |
340 | 825bb581 | aurel32 | return -EINVAL;
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341 | 825bb581 | aurel32 | |
342 | 3476f891 | aurel32 | pci_device_load(controller->pci_dev, f); |
343 | 825bb581 | aurel32 | |
344 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) { |
345 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].la); |
346 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].ma); |
347 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].pcila); |
348 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].pciha); |
349 | 825bb581 | aurel32 | } |
350 | 825bb581 | aurel32 | |
351 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) { |
352 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->ptm[i].ms); |
353 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->ptm[i].la); |
354 | 825bb581 | aurel32 | } |
355 | 825bb581 | aurel32 | |
356 | 825bb581 | aurel32 | return 0; |
357 | 825bb581 | aurel32 | } |
358 | 825bb581 | aurel32 | |
359 | 825bb581 | aurel32 | /* XXX Interrupt acknowledge cycles not supported. */
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360 | 825bb581 | aurel32 | PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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361 | 825bb581 | aurel32 | target_phys_addr_t config_space, |
362 | 825bb581 | aurel32 | target_phys_addr_t int_ack, |
363 | 825bb581 | aurel32 | target_phys_addr_t special_cycle, |
364 | 825bb581 | aurel32 | target_phys_addr_t registers) |
365 | 825bb581 | aurel32 | { |
366 | 825bb581 | aurel32 | PPC4xxPCIState *controller; |
367 | 825bb581 | aurel32 | int index;
|
368 | 825bb581 | aurel32 | static int ppc4xx_pci_id; |
369 | 825bb581 | aurel32 | |
370 | 825bb581 | aurel32 | controller = qemu_mallocz(sizeof(PPC4xxPCIState));
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371 | 825bb581 | aurel32 | if (!controller)
|
372 | 825bb581 | aurel32 | return NULL; |
373 | 825bb581 | aurel32 | |
374 | 825bb581 | aurel32 | controller->pci_state.bus = pci_register_bus(ppc4xx_pci_set_irq, |
375 | 825bb581 | aurel32 | ppc4xx_pci_map_irq, |
376 | 825bb581 | aurel32 | pci_irqs, 0, 4); |
377 | 825bb581 | aurel32 | |
378 | 825bb581 | aurel32 | controller->pci_dev = pci_register_device(controller->pci_state.bus, |
379 | 825bb581 | aurel32 | "host bridge", sizeof(PCIDevice), |
380 | 825bb581 | aurel32 | 0, NULL, NULL); |
381 | 825bb581 | aurel32 | controller->pci_dev->config[0x00] = 0x14; // vendor_id |
382 | 825bb581 | aurel32 | controller->pci_dev->config[0x01] = 0x10; |
383 | 825bb581 | aurel32 | controller->pci_dev->config[0x02] = 0x7f; // device_id |
384 | 825bb581 | aurel32 | controller->pci_dev->config[0x03] = 0x02; |
385 | 825bb581 | aurel32 | controller->pci_dev->config[0x0a] = 0x80; // class_sub = other bridge type |
386 | 825bb581 | aurel32 | controller->pci_dev->config[0x0b] = 0x06; // class_base = PCI_bridge |
387 | 825bb581 | aurel32 | |
388 | 825bb581 | aurel32 | /* CFGADDR */
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389 | 825bb581 | aurel32 | index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
|
390 | 825bb581 | aurel32 | pci4xx_cfgaddr_write, controller); |
391 | 825bb581 | aurel32 | if (index < 0) |
392 | 825bb581 | aurel32 | goto free;
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393 | 825bb581 | aurel32 | cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
|
394 | 825bb581 | aurel32 | |
395 | 825bb581 | aurel32 | /* CFGDATA */
|
396 | 825bb581 | aurel32 | index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
|
397 | 825bb581 | aurel32 | pci4xx_cfgdata_write, |
398 | 825bb581 | aurel32 | &controller->pci_state); |
399 | 825bb581 | aurel32 | if (index < 0) |
400 | 825bb581 | aurel32 | goto free;
|
401 | 825bb581 | aurel32 | cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
|
402 | 825bb581 | aurel32 | |
403 | 825bb581 | aurel32 | /* Internal registers */
|
404 | 825bb581 | aurel32 | index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, controller);
|
405 | 825bb581 | aurel32 | if (index < 0) |
406 | 825bb581 | aurel32 | goto free;
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407 | 825bb581 | aurel32 | cpu_register_physical_memory(registers, PCI_REG_SIZE, index); |
408 | 825bb581 | aurel32 | |
409 | 825bb581 | aurel32 | qemu_register_reset(ppc4xx_pci_reset, controller); |
410 | 825bb581 | aurel32 | |
411 | 825bb581 | aurel32 | /* XXX load/save code not tested. */
|
412 | 825bb581 | aurel32 | register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1, |
413 | 825bb581 | aurel32 | ppc4xx_pci_save, ppc4xx_pci_load, controller); |
414 | 825bb581 | aurel32 | |
415 | 825bb581 | aurel32 | return controller->pci_state.bus;
|
416 | 825bb581 | aurel32 | |
417 | 825bb581 | aurel32 | free:
|
418 | 825bb581 | aurel32 | printf("%s error\n", __func__);
|
419 | 825bb581 | aurel32 | qemu_free(controller); |
420 | 825bb581 | aurel32 | return NULL; |
421 | 825bb581 | aurel32 | } |