root / hw / etraxfs_ser.c @ 2c44375d
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1 | 83fa1010 | ths | /*
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2 | 83fa1010 | ths | * QEMU ETRAX System Emulator
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | |
25 | 83fa1010 | ths | #include <stdio.h> |
26 | 83fa1010 | ths | #include <ctype.h> |
27 | 87ecb68b | pbrook | #include "hw.h" |
28 | f062058f | edgar_igl | #include "qemu-char.h" |
29 | 83fa1010 | ths | |
30 | bbaf29c7 | edgar_igl | #define D(x)
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31 | bbaf29c7 | edgar_igl | |
32 | f062058f | edgar_igl | #define RW_TR_CTRL 0x00 |
33 | f062058f | edgar_igl | #define RW_TR_DMA_EN 0x04 |
34 | f062058f | edgar_igl | #define RW_REC_CTRL 0x08 |
35 | f062058f | edgar_igl | #define RW_DOUT 0x1c |
36 | f062058f | edgar_igl | #define RS_STAT_DIN 0x20 |
37 | f062058f | edgar_igl | #define R_STAT_DIN 0x24 |
38 | f062058f | edgar_igl | #define RW_INTR_MASK 0x2c |
39 | f062058f | edgar_igl | #define RW_ACK_INTR 0x30 |
40 | f062058f | edgar_igl | #define R_INTR 0x34 |
41 | f062058f | edgar_igl | #define R_MASKED_INTR 0x38 |
42 | 83fa1010 | ths | |
43 | f062058f | edgar_igl | #define STAT_DAV 16 |
44 | f062058f | edgar_igl | #define STAT_TR_IDLE 22 |
45 | f062058f | edgar_igl | #define STAT_TR_RDY 24 |
46 | f062058f | edgar_igl | |
47 | f062058f | edgar_igl | struct etrax_serial_t
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48 | 83fa1010 | ths | { |
49 | f062058f | edgar_igl | CPUState *env; |
50 | f062058f | edgar_igl | CharDriverState *chr; |
51 | f062058f | edgar_igl | qemu_irq *irq; |
52 | f062058f | edgar_igl | |
53 | f062058f | edgar_igl | target_phys_addr_t base; |
54 | f062058f | edgar_igl | |
55 | f062058f | edgar_igl | int pending_tx;
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56 | f062058f | edgar_igl | |
57 | f062058f | edgar_igl | /* Control registers. */
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58 | f062058f | edgar_igl | uint32_t rw_tr_ctrl; |
59 | f062058f | edgar_igl | uint32_t rw_tr_dma_en; |
60 | f062058f | edgar_igl | uint32_t rw_rec_ctrl; |
61 | f062058f | edgar_igl | uint32_t rs_stat_din; |
62 | f062058f | edgar_igl | uint32_t r_stat_din; |
63 | f062058f | edgar_igl | uint32_t rw_intr_mask; |
64 | f062058f | edgar_igl | uint32_t rw_ack_intr; |
65 | f062058f | edgar_igl | uint32_t r_intr; |
66 | f062058f | edgar_igl | uint32_t r_masked_intr; |
67 | f062058f | edgar_igl | }; |
68 | f062058f | edgar_igl | |
69 | f062058f | edgar_igl | static void ser_update_irq(struct etrax_serial_t *s) |
70 | f062058f | edgar_igl | { |
71 | f062058f | edgar_igl | uint32_t o_irq = s->r_masked_intr; |
72 | f062058f | edgar_igl | |
73 | f062058f | edgar_igl | s->r_intr &= ~(s->rw_ack_intr); |
74 | f062058f | edgar_igl | s->r_masked_intr = s->r_intr & s->rw_intr_mask; |
75 | f062058f | edgar_igl | |
76 | f062058f | edgar_igl | if (o_irq != s->r_masked_intr) {
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77 | f062058f | edgar_igl | D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
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78 | f062058f | edgar_igl | s->rw_intr_mask, s->r_intr, |
79 | f062058f | edgar_igl | s->r_masked_intr, s->rw_ack_intr)); |
80 | f062058f | edgar_igl | if (s->r_masked_intr)
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81 | f062058f | edgar_igl | qemu_irq_raise(s->irq[0]);
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82 | f062058f | edgar_igl | else
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83 | f062058f | edgar_igl | qemu_irq_lower(s->irq[0]);
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84 | f062058f | edgar_igl | } |
85 | f062058f | edgar_igl | s->rw_ack_intr = 0;
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86 | 83fa1010 | ths | } |
87 | f062058f | edgar_igl | |
88 | f062058f | edgar_igl | |
89 | f062058f | edgar_igl | static uint32_t ser_readb (void *opaque, target_phys_addr_t addr) |
90 | 83fa1010 | ths | { |
91 | ca87d03b | edgar_igl | D(CPUState *env = opaque); |
92 | bbaf29c7 | edgar_igl | D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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93 | ca87d03b | edgar_igl | return 0; |
94 | 83fa1010 | ths | } |
95 | 83fa1010 | ths | |
96 | 83fa1010 | ths | static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) |
97 | 83fa1010 | ths | { |
98 | f062058f | edgar_igl | struct etrax_serial_t *s = opaque;
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99 | f062058f | edgar_igl | D(CPUState *env = s->env); |
100 | 83fa1010 | ths | uint32_t r = 0;
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101 | 83fa1010 | ths | |
102 | bbaf29c7 | edgar_igl | switch (addr & 0xfff) |
103 | 83fa1010 | ths | { |
104 | f062058f | edgar_igl | case RW_TR_CTRL:
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105 | f062058f | edgar_igl | r = s->rw_tr_ctrl; |
106 | f062058f | edgar_igl | break;
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107 | 83fa1010 | ths | case RW_TR_DMA_EN:
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108 | f062058f | edgar_igl | r = s->rw_tr_dma_en; |
109 | f062058f | edgar_igl | break;
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110 | f062058f | edgar_igl | case RS_STAT_DIN:
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111 | f062058f | edgar_igl | r = s->rs_stat_din; |
112 | f062058f | edgar_igl | /* clear dav. */
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113 | f062058f | edgar_igl | s->rs_stat_din &= ~(1 << STAT_DAV);
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114 | 83fa1010 | ths | break;
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115 | 83fa1010 | ths | case R_STAT_DIN:
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116 | f062058f | edgar_igl | r = s->rs_stat_din; |
117 | f062058f | edgar_igl | break;
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118 | f062058f | edgar_igl | case RW_ACK_INTR:
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119 | f062058f | edgar_igl | D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
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120 | f062058f | edgar_igl | r = s->rw_ack_intr; |
121 | f062058f | edgar_igl | break;
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122 | f062058f | edgar_igl | case RW_INTR_MASK:
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123 | f062058f | edgar_igl | r = s->rw_intr_mask; |
124 | f062058f | edgar_igl | break;
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125 | f062058f | edgar_igl | case R_INTR:
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126 | f062058f | edgar_igl | D(printf("load r_intr=%x\n", s->r_intr));
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127 | f062058f | edgar_igl | r = s->r_intr; |
128 | f062058f | edgar_igl | break;
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129 | f062058f | edgar_igl | case R_MASKED_INTR:
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130 | f062058f | edgar_igl | D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
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131 | f062058f | edgar_igl | r = s->r_masked_intr; |
132 | 83fa1010 | ths | break;
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133 | 83fa1010 | ths | |
134 | 83fa1010 | ths | default:
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135 | e62b5b13 | edgar_igl | D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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136 | 83fa1010 | ths | break;
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137 | 83fa1010 | ths | } |
138 | 83fa1010 | ths | return r;
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139 | 83fa1010 | ths | } |
140 | 83fa1010 | ths | |
141 | 83fa1010 | ths | static void |
142 | 83fa1010 | ths | ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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143 | 83fa1010 | ths | { |
144 | f062058f | edgar_igl | D(struct etrax_serial_t *s = opaque);
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145 | f062058f | edgar_igl | D(CPUState *env = s->env); |
146 | bbaf29c7 | edgar_igl | D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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147 | 83fa1010 | ths | } |
148 | 83fa1010 | ths | static void |
149 | 83fa1010 | ths | ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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150 | 83fa1010 | ths | { |
151 | f062058f | edgar_igl | struct etrax_serial_t *s = opaque;
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152 | f062058f | edgar_igl | unsigned char ch = value; |
153 | f062058f | edgar_igl | D(CPUState *env = s->env); |
154 | 83fa1010 | ths | |
155 | bbaf29c7 | edgar_igl | switch (addr & 0xfff) |
156 | 83fa1010 | ths | { |
157 | f062058f | edgar_igl | case RW_TR_CTRL:
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158 | f062058f | edgar_igl | D(printf("rw_tr_ctrl=%x\n", value));
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159 | f062058f | edgar_igl | s->rw_tr_ctrl = value; |
160 | f062058f | edgar_igl | break;
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161 | 83fa1010 | ths | case RW_TR_DMA_EN:
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162 | f062058f | edgar_igl | D(printf("rw_tr_dma_en=%x\n", value));
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163 | f062058f | edgar_igl | s->rw_tr_dma_en = value; |
164 | 83fa1010 | ths | break;
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165 | 83fa1010 | ths | case RW_DOUT:
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166 | f062058f | edgar_igl | qemu_chr_write(s->chr, &ch, 1);
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167 | f062058f | edgar_igl | s->r_intr |= 1;
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168 | f062058f | edgar_igl | s->pending_tx = 1;
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169 | f062058f | edgar_igl | break;
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170 | f062058f | edgar_igl | case RW_ACK_INTR:
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171 | f062058f | edgar_igl | D(printf("rw_ack_intr=%x\n", value));
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172 | f062058f | edgar_igl | s->rw_ack_intr = value; |
173 | f062058f | edgar_igl | if (s->pending_tx && (s->rw_ack_intr & 1)) { |
174 | f062058f | edgar_igl | s->r_intr |= 1;
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175 | f062058f | edgar_igl | s->pending_tx = 0;
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176 | f062058f | edgar_igl | s->rw_ack_intr &= ~1;
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177 | f062058f | edgar_igl | } |
178 | f062058f | edgar_igl | break;
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179 | f062058f | edgar_igl | case RW_INTR_MASK:
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180 | f062058f | edgar_igl | D(printf("r_intr_mask=%x\n", value));
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181 | f062058f | edgar_igl | s->rw_intr_mask = value; |
182 | 83fa1010 | ths | break;
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183 | 83fa1010 | ths | default:
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184 | e62b5b13 | edgar_igl | D(printf ("%s %x %x pc=%x\n",
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185 | e62b5b13 | edgar_igl | __func__, addr, value, env->pc)); |
186 | 83fa1010 | ths | break;
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187 | 83fa1010 | ths | } |
188 | f062058f | edgar_igl | ser_update_irq(s); |
189 | 83fa1010 | ths | } |
190 | 83fa1010 | ths | |
191 | 83fa1010 | ths | static CPUReadMemoryFunc *ser_read[] = {
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192 | ca87d03b | edgar_igl | &ser_readb, |
193 | f062058f | edgar_igl | &ser_readb, |
194 | ca87d03b | edgar_igl | &ser_readl, |
195 | 83fa1010 | ths | }; |
196 | 83fa1010 | ths | |
197 | 83fa1010 | ths | static CPUWriteMemoryFunc *ser_write[] = {
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198 | ca87d03b | edgar_igl | &ser_writeb, |
199 | f062058f | edgar_igl | &ser_writeb, |
200 | ca87d03b | edgar_igl | &ser_writel, |
201 | 83fa1010 | ths | }; |
202 | 83fa1010 | ths | |
203 | f062058f | edgar_igl | static void serial_receive(void *opaque, const uint8_t *buf, int size) |
204 | 83fa1010 | ths | { |
205 | f062058f | edgar_igl | struct etrax_serial_t *s = opaque;
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206 | f062058f | edgar_igl | |
207 | f062058f | edgar_igl | s->r_intr |= 8;
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208 | f062058f | edgar_igl | s->rs_stat_din &= ~0xff;
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209 | f062058f | edgar_igl | s->rs_stat_din |= (buf[0] & 0xff); |
210 | f062058f | edgar_igl | s->rs_stat_din |= (1 << STAT_DAV); /* dav. */ |
211 | f062058f | edgar_igl | ser_update_irq(s); |
212 | f062058f | edgar_igl | } |
213 | f062058f | edgar_igl | |
214 | f062058f | edgar_igl | static int serial_can_receive(void *opaque) |
215 | f062058f | edgar_igl | { |
216 | f062058f | edgar_igl | struct etrax_serial_t *s = opaque;
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217 | f062058f | edgar_igl | int r;
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218 | f062058f | edgar_igl | |
219 | f062058f | edgar_igl | /* Is the receiver enabled? */
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220 | f062058f | edgar_igl | r = s->rw_rec_ctrl & 1;
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221 | f062058f | edgar_igl | |
222 | f062058f | edgar_igl | /* Pending rx data? */
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223 | f062058f | edgar_igl | r |= !(s->r_intr & 8);
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224 | f062058f | edgar_igl | return r;
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225 | f062058f | edgar_igl | } |
226 | f062058f | edgar_igl | |
227 | f062058f | edgar_igl | static void serial_event(void *opaque, int event) |
228 | f062058f | edgar_igl | { |
229 | f062058f | edgar_igl | |
230 | f062058f | edgar_igl | } |
231 | f062058f | edgar_igl | |
232 | f062058f | edgar_igl | void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
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233 | f062058f | edgar_igl | target_phys_addr_t base) |
234 | f062058f | edgar_igl | { |
235 | f062058f | edgar_igl | struct etrax_serial_t *s;
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236 | 83fa1010 | ths | int ser_regs;
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237 | f062058f | edgar_igl | |
238 | f062058f | edgar_igl | s = qemu_mallocz(sizeof *s);
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239 | f062058f | edgar_igl | if (!s)
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240 | f062058f | edgar_igl | return;
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241 | f062058f | edgar_igl | |
242 | f062058f | edgar_igl | s->env = env; |
243 | f062058f | edgar_igl | s->irq = irq; |
244 | f062058f | edgar_igl | s->base = base; |
245 | f062058f | edgar_igl | |
246 | f062058f | edgar_igl | s->chr = chr; |
247 | f062058f | edgar_igl | |
248 | f062058f | edgar_igl | /* transmitter begins ready and idle. */
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249 | f062058f | edgar_igl | s->rs_stat_din |= (1 << STAT_TR_RDY);
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250 | f062058f | edgar_igl | s->rs_stat_din |= (1 << STAT_TR_IDLE);
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251 | f062058f | edgar_igl | |
252 | f062058f | edgar_igl | qemu_chr_add_handlers(chr, serial_can_receive, serial_receive, |
253 | f062058f | edgar_igl | serial_event, s); |
254 | f062058f | edgar_igl | |
255 | f062058f | edgar_igl | ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
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256 | ca87d03b | edgar_igl | cpu_register_physical_memory (base, 0x3c, ser_regs);
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257 | 83fa1010 | ths | } |