root / hw / slavio_misc.c @ 2c44375d
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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | |
28 | 3475187d | bellard | /* debug misc */
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29 | 3475187d | bellard | //#define DEBUG_MISC
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30 | 3475187d | bellard | |
31 | 3475187d | bellard | /*
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32 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
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33 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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34 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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35 | 3475187d | bellard | *
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36 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
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37 | 3475187d | bellard | */
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38 | 3475187d | bellard | |
39 | 3475187d | bellard | #ifdef DEBUG_MISC
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40 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...) \
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41 | 3475187d | bellard | do { printf("MISC: " fmt , ##args); } while (0) |
42 | 3475187d | bellard | #else
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43 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...)
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44 | 3475187d | bellard | #endif
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45 | 3475187d | bellard | |
46 | 3475187d | bellard | typedef struct MiscState { |
47 | d537cf6c | pbrook | qemu_irq irq; |
48 | 3475187d | bellard | uint8_t config; |
49 | 3475187d | bellard | uint8_t aux1, aux2; |
50 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
51 | bfa30a38 | blueswir1 | uint32_t sysctrl; |
52 | 6a3b9cc9 | blueswir1 | uint16_t leds; |
53 | 0019ad53 | blueswir1 | CPUState *env; |
54 | 2be17ebd | blueswir1 | qemu_irq fdc_tc; |
55 | 3475187d | bellard | } MiscState; |
56 | 3475187d | bellard | |
57 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
58 | bfa30a38 | blueswir1 | #define SYSCTRL_MAXADDR 3 |
59 | bfa30a38 | blueswir1 | #define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1) |
60 | d5296cb5 | blueswir1 | #define LED_MAXADDR 1 |
61 | 6a3b9cc9 | blueswir1 | #define LED_SIZE (LED_MAXADDR + 1) |
62 | 3475187d | bellard | |
63 | 7debeb82 | blueswir1 | #define MISC_MASK 0x0fff0000 |
64 | 7debeb82 | blueswir1 | #define MISC_LEDS 0x01600000 |
65 | 7debeb82 | blueswir1 | #define MISC_CFG 0x01800000 |
66 | 7debeb82 | blueswir1 | #define MISC_DIAG 0x01a00000 |
67 | 7debeb82 | blueswir1 | #define MISC_MDM 0x01b00000 |
68 | 7debeb82 | blueswir1 | #define MISC_SYS 0x01f00000 |
69 | 7debeb82 | blueswir1 | |
70 | 2be17ebd | blueswir1 | #define AUX1_TC 0x02 |
71 | 2be17ebd | blueswir1 | |
72 | 7debeb82 | blueswir1 | #define AUX2_PWROFF 0x01 |
73 | 7debeb82 | blueswir1 | #define AUX2_PWRINTCLR 0x02 |
74 | 7debeb82 | blueswir1 | #define AUX2_PWRFAIL 0x20 |
75 | 7debeb82 | blueswir1 | |
76 | 7debeb82 | blueswir1 | #define CFG_PWRINTEN 0x08 |
77 | 7debeb82 | blueswir1 | |
78 | 7debeb82 | blueswir1 | #define SYS_RESET 0x01 |
79 | 7debeb82 | blueswir1 | #define SYS_RESETSTAT 0x02 |
80 | 7debeb82 | blueswir1 | |
81 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
82 | 3475187d | bellard | { |
83 | 3475187d | bellard | MiscState *s = opaque; |
84 | 3475187d | bellard | |
85 | 7debeb82 | blueswir1 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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86 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
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87 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
88 | 3475187d | bellard | } else {
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89 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
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90 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
91 | 3475187d | bellard | } |
92 | 3475187d | bellard | } |
93 | 3475187d | bellard | |
94 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
95 | 3475187d | bellard | { |
96 | 3475187d | bellard | MiscState *s = opaque; |
97 | 3475187d | bellard | |
98 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
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99 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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100 | 3475187d | bellard | } |
101 | 3475187d | bellard | |
102 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing) |
103 | 3475187d | bellard | { |
104 | 3475187d | bellard | MiscState *s = opaque; |
105 | 3475187d | bellard | |
106 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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107 | 7debeb82 | blueswir1 | if (power_failing && (s->config & CFG_PWRINTEN)) {
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108 | 7debeb82 | blueswir1 | s->aux2 |= AUX2_PWRFAIL; |
109 | 3475187d | bellard | } else {
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110 | 7debeb82 | blueswir1 | s->aux2 &= ~AUX2_PWRFAIL; |
111 | 3475187d | bellard | } |
112 | 3475187d | bellard | slavio_misc_update_irq(s); |
113 | 3475187d | bellard | } |
114 | 3475187d | bellard | |
115 | bfa30a38 | blueswir1 | static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, |
116 | bfa30a38 | blueswir1 | uint32_t val) |
117 | 3475187d | bellard | { |
118 | 3475187d | bellard | MiscState *s = opaque; |
119 | 3475187d | bellard | |
120 | 7debeb82 | blueswir1 | switch (addr & MISC_MASK) {
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121 | 7debeb82 | blueswir1 | case MISC_CFG:
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122 | f930d07e | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
123 | f930d07e | blueswir1 | s->config = val & 0xff;
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124 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
125 | f930d07e | blueswir1 | break;
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126 | 7debeb82 | blueswir1 | case MISC_DIAG:
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127 | f930d07e | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
128 | f930d07e | blueswir1 | s->diag = val & 0xff;
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129 | f930d07e | blueswir1 | break;
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130 | 7debeb82 | blueswir1 | case MISC_MDM:
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131 | f930d07e | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
132 | f930d07e | blueswir1 | s->mctrl = val & 0xff;
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133 | f930d07e | blueswir1 | break;
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134 | df33e639 | blueswir1 | default:
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135 | f930d07e | blueswir1 | break;
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136 | 3475187d | bellard | } |
137 | 3475187d | bellard | } |
138 | 3475187d | bellard | |
139 | 3475187d | bellard | static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) |
140 | 3475187d | bellard | { |
141 | 3475187d | bellard | MiscState *s = opaque; |
142 | 3475187d | bellard | uint32_t ret = 0;
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143 | 3475187d | bellard | |
144 | 7debeb82 | blueswir1 | switch (addr & MISC_MASK) {
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145 | 7debeb82 | blueswir1 | case MISC_CFG:
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146 | f930d07e | blueswir1 | ret = s->config; |
147 | f930d07e | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
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148 | f930d07e | blueswir1 | break;
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149 | 7debeb82 | blueswir1 | case MISC_DIAG:
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150 | f930d07e | blueswir1 | ret = s->diag; |
151 | f930d07e | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
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152 | f930d07e | blueswir1 | break;
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153 | 7debeb82 | blueswir1 | case MISC_MDM:
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154 | f930d07e | blueswir1 | ret = s->mctrl; |
155 | f930d07e | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
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156 | f930d07e | blueswir1 | break;
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157 | df33e639 | blueswir1 | default:
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158 | f930d07e | blueswir1 | break;
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159 | 3475187d | bellard | } |
160 | 3475187d | bellard | return ret;
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161 | 3475187d | bellard | } |
162 | 3475187d | bellard | |
163 | 3475187d | bellard | static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { |
164 | 3475187d | bellard | slavio_misc_mem_readb, |
165 | 7c560456 | blueswir1 | NULL,
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166 | 7c560456 | blueswir1 | NULL,
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167 | 3475187d | bellard | }; |
168 | 3475187d | bellard | |
169 | 3475187d | bellard | static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { |
170 | 3475187d | bellard | slavio_misc_mem_writeb, |
171 | 7c560456 | blueswir1 | NULL,
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172 | 7c560456 | blueswir1 | NULL,
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173 | 3475187d | bellard | }; |
174 | 3475187d | bellard | |
175 | 0019ad53 | blueswir1 | static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, |
176 | 0019ad53 | blueswir1 | uint32_t val) |
177 | 0019ad53 | blueswir1 | { |
178 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
179 | 0019ad53 | blueswir1 | |
180 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
181 | 2be17ebd | blueswir1 | if (val & AUX1_TC) {
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182 | 2be17ebd | blueswir1 | // Send a pulse to floppy terminal count line
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183 | 2be17ebd | blueswir1 | if (s->fdc_tc) {
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184 | 2be17ebd | blueswir1 | qemu_irq_raise(s->fdc_tc); |
185 | 2be17ebd | blueswir1 | qemu_irq_lower(s->fdc_tc); |
186 | 2be17ebd | blueswir1 | } |
187 | 2be17ebd | blueswir1 | val &= ~AUX1_TC; |
188 | 2be17ebd | blueswir1 | } |
189 | 0019ad53 | blueswir1 | s->aux1 = val & 0xff;
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190 | 0019ad53 | blueswir1 | } |
191 | 0019ad53 | blueswir1 | |
192 | 0019ad53 | blueswir1 | static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) |
193 | 0019ad53 | blueswir1 | { |
194 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
195 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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196 | 0019ad53 | blueswir1 | |
197 | 0019ad53 | blueswir1 | ret = s->aux1; |
198 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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199 | 0019ad53 | blueswir1 | |
200 | 0019ad53 | blueswir1 | return ret;
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201 | 0019ad53 | blueswir1 | } |
202 | 0019ad53 | blueswir1 | |
203 | 0019ad53 | blueswir1 | static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = { |
204 | 0019ad53 | blueswir1 | slavio_aux1_mem_readb, |
205 | 0019ad53 | blueswir1 | NULL,
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206 | 0019ad53 | blueswir1 | NULL,
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207 | 0019ad53 | blueswir1 | }; |
208 | 0019ad53 | blueswir1 | |
209 | 0019ad53 | blueswir1 | static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = { |
210 | 0019ad53 | blueswir1 | slavio_aux1_mem_writeb, |
211 | 0019ad53 | blueswir1 | NULL,
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212 | 0019ad53 | blueswir1 | NULL,
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213 | 0019ad53 | blueswir1 | }; |
214 | 0019ad53 | blueswir1 | |
215 | 0019ad53 | blueswir1 | static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, |
216 | 0019ad53 | blueswir1 | uint32_t val) |
217 | 0019ad53 | blueswir1 | { |
218 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
219 | 0019ad53 | blueswir1 | |
220 | 0019ad53 | blueswir1 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
221 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
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222 | 0019ad53 | blueswir1 | val |= s->aux2 & AUX2_PWRFAIL; |
223 | 0019ad53 | blueswir1 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
224 | 0019ad53 | blueswir1 | val &= AUX2_PWROFF; |
225 | 0019ad53 | blueswir1 | s->aux2 = val; |
226 | 0019ad53 | blueswir1 | if (val & AUX2_PWROFF)
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227 | 0019ad53 | blueswir1 | qemu_system_shutdown_request(); |
228 | 0019ad53 | blueswir1 | slavio_misc_update_irq(s); |
229 | 0019ad53 | blueswir1 | } |
230 | 0019ad53 | blueswir1 | |
231 | 0019ad53 | blueswir1 | static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) |
232 | 0019ad53 | blueswir1 | { |
233 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
234 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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235 | 0019ad53 | blueswir1 | |
236 | 0019ad53 | blueswir1 | ret = s->aux2; |
237 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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238 | 0019ad53 | blueswir1 | |
239 | 0019ad53 | blueswir1 | return ret;
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240 | 0019ad53 | blueswir1 | } |
241 | 0019ad53 | blueswir1 | |
242 | 0019ad53 | blueswir1 | static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = { |
243 | 0019ad53 | blueswir1 | slavio_aux2_mem_readb, |
244 | 0019ad53 | blueswir1 | NULL,
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245 | 0019ad53 | blueswir1 | NULL,
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246 | 0019ad53 | blueswir1 | }; |
247 | 0019ad53 | blueswir1 | |
248 | 0019ad53 | blueswir1 | static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = { |
249 | 0019ad53 | blueswir1 | slavio_aux2_mem_writeb, |
250 | 0019ad53 | blueswir1 | NULL,
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251 | 0019ad53 | blueswir1 | NULL,
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252 | 0019ad53 | blueswir1 | }; |
253 | 0019ad53 | blueswir1 | |
254 | 0019ad53 | blueswir1 | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
255 | 0019ad53 | blueswir1 | { |
256 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
257 | 0019ad53 | blueswir1 | |
258 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
259 | 0019ad53 | blueswir1 | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
260 | 0019ad53 | blueswir1 | } |
261 | 0019ad53 | blueswir1 | |
262 | 0019ad53 | blueswir1 | static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) |
263 | 0019ad53 | blueswir1 | { |
264 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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265 | 0019ad53 | blueswir1 | |
266 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
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267 | 0019ad53 | blueswir1 | return ret;
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268 | 0019ad53 | blueswir1 | } |
269 | 0019ad53 | blueswir1 | |
270 | 0019ad53 | blueswir1 | static CPUReadMemoryFunc *apc_mem_read[3] = { |
271 | 0019ad53 | blueswir1 | apc_mem_readb, |
272 | 0019ad53 | blueswir1 | NULL,
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273 | 0019ad53 | blueswir1 | NULL,
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274 | 0019ad53 | blueswir1 | }; |
275 | 0019ad53 | blueswir1 | |
276 | 0019ad53 | blueswir1 | static CPUWriteMemoryFunc *apc_mem_write[3] = { |
277 | 0019ad53 | blueswir1 | apc_mem_writeb, |
278 | 0019ad53 | blueswir1 | NULL,
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279 | 0019ad53 | blueswir1 | NULL,
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280 | 0019ad53 | blueswir1 | }; |
281 | 0019ad53 | blueswir1 | |
282 | bfa30a38 | blueswir1 | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
283 | bfa30a38 | blueswir1 | { |
284 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
285 | bfa30a38 | blueswir1 | uint32_t ret = 0, saddr;
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286 | bfa30a38 | blueswir1 | |
287 | bfa30a38 | blueswir1 | saddr = addr & SYSCTRL_MAXADDR; |
288 | bfa30a38 | blueswir1 | switch (saddr) {
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289 | bfa30a38 | blueswir1 | case 0: |
290 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
291 | bfa30a38 | blueswir1 | break;
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292 | bfa30a38 | blueswir1 | default:
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293 | bfa30a38 | blueswir1 | break;
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294 | bfa30a38 | blueswir1 | } |
295 | bfa30a38 | blueswir1 | MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr, |
296 | bfa30a38 | blueswir1 | ret); |
297 | bfa30a38 | blueswir1 | return ret;
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298 | bfa30a38 | blueswir1 | } |
299 | bfa30a38 | blueswir1 | |
300 | bfa30a38 | blueswir1 | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
301 | bfa30a38 | blueswir1 | uint32_t val) |
302 | bfa30a38 | blueswir1 | { |
303 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
304 | bfa30a38 | blueswir1 | uint32_t saddr; |
305 | bfa30a38 | blueswir1 | |
306 | bfa30a38 | blueswir1 | saddr = addr & SYSCTRL_MAXADDR; |
307 | bfa30a38 | blueswir1 | MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr, |
308 | bfa30a38 | blueswir1 | val); |
309 | bfa30a38 | blueswir1 | switch (saddr) {
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310 | bfa30a38 | blueswir1 | case 0: |
311 | 7debeb82 | blueswir1 | if (val & SYS_RESET) {
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312 | 7debeb82 | blueswir1 | s->sysctrl = SYS_RESETSTAT; |
313 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
314 | bfa30a38 | blueswir1 | } |
315 | bfa30a38 | blueswir1 | break;
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316 | bfa30a38 | blueswir1 | default:
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317 | bfa30a38 | blueswir1 | break;
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318 | bfa30a38 | blueswir1 | } |
319 | bfa30a38 | blueswir1 | } |
320 | bfa30a38 | blueswir1 | |
321 | bfa30a38 | blueswir1 | static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = { |
322 | 7c560456 | blueswir1 | NULL,
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323 | 7c560456 | blueswir1 | NULL,
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324 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
325 | bfa30a38 | blueswir1 | }; |
326 | bfa30a38 | blueswir1 | |
327 | bfa30a38 | blueswir1 | static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = { |
328 | 7c560456 | blueswir1 | NULL,
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329 | 7c560456 | blueswir1 | NULL,
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330 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
331 | bfa30a38 | blueswir1 | }; |
332 | bfa30a38 | blueswir1 | |
333 | 7c560456 | blueswir1 | static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) |
334 | 6a3b9cc9 | blueswir1 | { |
335 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
336 | 6a3b9cc9 | blueswir1 | uint32_t ret = 0, saddr;
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337 | 6a3b9cc9 | blueswir1 | |
338 | 6a3b9cc9 | blueswir1 | saddr = addr & LED_MAXADDR; |
339 | 6a3b9cc9 | blueswir1 | switch (saddr) {
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340 | 6a3b9cc9 | blueswir1 | case 0: |
341 | 6a3b9cc9 | blueswir1 | ret = s->leds; |
342 | 6a3b9cc9 | blueswir1 | break;
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343 | 6a3b9cc9 | blueswir1 | default:
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344 | 6a3b9cc9 | blueswir1 | break;
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345 | 6a3b9cc9 | blueswir1 | } |
346 | 6a3b9cc9 | blueswir1 | MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, |
347 | 6a3b9cc9 | blueswir1 | ret); |
348 | 6a3b9cc9 | blueswir1 | return ret;
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349 | 6a3b9cc9 | blueswir1 | } |
350 | 6a3b9cc9 | blueswir1 | |
351 | 7c560456 | blueswir1 | static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, |
352 | 6a3b9cc9 | blueswir1 | uint32_t val) |
353 | 6a3b9cc9 | blueswir1 | { |
354 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
355 | 6a3b9cc9 | blueswir1 | uint32_t saddr; |
356 | 6a3b9cc9 | blueswir1 | |
357 | 6a3b9cc9 | blueswir1 | saddr = addr & LED_MAXADDR; |
358 | 6a3b9cc9 | blueswir1 | MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, |
359 | 6a3b9cc9 | blueswir1 | val); |
360 | 6a3b9cc9 | blueswir1 | switch (saddr) {
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361 | 6a3b9cc9 | blueswir1 | case 0: |
362 | d5296cb5 | blueswir1 | s->leds = val; |
363 | 6a3b9cc9 | blueswir1 | break;
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364 | 6a3b9cc9 | blueswir1 | default:
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365 | 6a3b9cc9 | blueswir1 | break;
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366 | 6a3b9cc9 | blueswir1 | } |
367 | 6a3b9cc9 | blueswir1 | } |
368 | 6a3b9cc9 | blueswir1 | |
369 | 6a3b9cc9 | blueswir1 | static CPUReadMemoryFunc *slavio_led_mem_read[3] = { |
370 | 7c560456 | blueswir1 | NULL,
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371 | 7c560456 | blueswir1 | slavio_led_mem_readw, |
372 | 7c560456 | blueswir1 | NULL,
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373 | 6a3b9cc9 | blueswir1 | }; |
374 | 6a3b9cc9 | blueswir1 | |
375 | 6a3b9cc9 | blueswir1 | static CPUWriteMemoryFunc *slavio_led_mem_write[3] = { |
376 | 7c560456 | blueswir1 | NULL,
|
377 | 7c560456 | blueswir1 | slavio_led_mem_writew, |
378 | 7c560456 | blueswir1 | NULL,
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379 | 6a3b9cc9 | blueswir1 | }; |
380 | 6a3b9cc9 | blueswir1 | |
381 | 3475187d | bellard | static void slavio_misc_save(QEMUFile *f, void *opaque) |
382 | 3475187d | bellard | { |
383 | 3475187d | bellard | MiscState *s = opaque; |
384 | 22548760 | blueswir1 | uint32_t tmp = 0;
|
385 | bfa30a38 | blueswir1 | uint8_t tmp8; |
386 | 3475187d | bellard | |
387 | d537cf6c | pbrook | qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
|
388 | 3475187d | bellard | qemu_put_8s(f, &s->config); |
389 | 3475187d | bellard | qemu_put_8s(f, &s->aux1); |
390 | 3475187d | bellard | qemu_put_8s(f, &s->aux2); |
391 | 3475187d | bellard | qemu_put_8s(f, &s->diag); |
392 | 3475187d | bellard | qemu_put_8s(f, &s->mctrl); |
393 | bfa30a38 | blueswir1 | tmp8 = s->sysctrl & 0xff;
|
394 | bfa30a38 | blueswir1 | qemu_put_8s(f, &tmp8); |
395 | 3475187d | bellard | } |
396 | 3475187d | bellard | |
397 | 3475187d | bellard | static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
398 | 3475187d | bellard | { |
399 | 3475187d | bellard | MiscState *s = opaque; |
400 | 22548760 | blueswir1 | uint32_t tmp; |
401 | bfa30a38 | blueswir1 | uint8_t tmp8; |
402 | 3475187d | bellard | |
403 | 3475187d | bellard | if (version_id != 1) |
404 | 3475187d | bellard | return -EINVAL;
|
405 | 3475187d | bellard | |
406 | d537cf6c | pbrook | qemu_get_be32s(f, &tmp); |
407 | 3475187d | bellard | qemu_get_8s(f, &s->config); |
408 | 3475187d | bellard | qemu_get_8s(f, &s->aux1); |
409 | 3475187d | bellard | qemu_get_8s(f, &s->aux2); |
410 | 3475187d | bellard | qemu_get_8s(f, &s->diag); |
411 | 3475187d | bellard | qemu_get_8s(f, &s->mctrl); |
412 | bfa30a38 | blueswir1 | qemu_get_8s(f, &tmp8); |
413 | bfa30a38 | blueswir1 | s->sysctrl = (uint32_t)tmp8; |
414 | 3475187d | bellard | return 0; |
415 | 3475187d | bellard | } |
416 | 3475187d | bellard | |
417 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
|
418 | 0019ad53 | blueswir1 | target_phys_addr_t aux1_base, |
419 | 0019ad53 | blueswir1 | target_phys_addr_t aux2_base, qemu_irq irq, |
420 | 2be17ebd | blueswir1 | CPUState *env, qemu_irq **fdc_tc) |
421 | 3475187d | bellard | { |
422 | 0019ad53 | blueswir1 | int io;
|
423 | 3475187d | bellard | MiscState *s; |
424 | 3475187d | bellard | |
425 | 3475187d | bellard | s = qemu_mallocz(sizeof(MiscState));
|
426 | 3475187d | bellard | if (!s)
|
427 | 3475187d | bellard | return NULL; |
428 | 3475187d | bellard | |
429 | 0019ad53 | blueswir1 | if (base) {
|
430 | 0019ad53 | blueswir1 | /* 8 bit registers */
|
431 | 0019ad53 | blueswir1 | io = cpu_register_io_memory(0, slavio_misc_mem_read,
|
432 | 0019ad53 | blueswir1 | slavio_misc_mem_write, s); |
433 | 0019ad53 | blueswir1 | // Slavio control
|
434 | 0019ad53 | blueswir1 | cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io); |
435 | 0019ad53 | blueswir1 | // Diagnostics
|
436 | 0019ad53 | blueswir1 | cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io); |
437 | 0019ad53 | blueswir1 | // Modem control
|
438 | 0019ad53 | blueswir1 | cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io); |
439 | 0019ad53 | blueswir1 | |
440 | 0019ad53 | blueswir1 | /* 16 bit registers */
|
441 | 0019ad53 | blueswir1 | io = cpu_register_io_memory(0, slavio_led_mem_read,
|
442 | 0019ad53 | blueswir1 | slavio_led_mem_write, s); |
443 | 0019ad53 | blueswir1 | /* ss600mp diag LEDs */
|
444 | 0019ad53 | blueswir1 | cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io); |
445 | 0019ad53 | blueswir1 | |
446 | 0019ad53 | blueswir1 | /* 32 bit registers */
|
447 | 0019ad53 | blueswir1 | io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
|
448 | 0019ad53 | blueswir1 | slavio_sysctrl_mem_write, s); |
449 | 0019ad53 | blueswir1 | // System control
|
450 | 0019ad53 | blueswir1 | cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io); |
451 | 0019ad53 | blueswir1 | } |
452 | 0019ad53 | blueswir1 | |
453 | 0019ad53 | blueswir1 | // AUX 1 (Misc System Functions)
|
454 | 0019ad53 | blueswir1 | if (aux1_base) {
|
455 | 0019ad53 | blueswir1 | io = cpu_register_io_memory(0, slavio_aux1_mem_read,
|
456 | 0019ad53 | blueswir1 | slavio_aux1_mem_write, s); |
457 | 0019ad53 | blueswir1 | cpu_register_physical_memory(aux1_base, MISC_SIZE, io); |
458 | 0019ad53 | blueswir1 | } |
459 | 0019ad53 | blueswir1 | |
460 | 0019ad53 | blueswir1 | // AUX 2 (Software Powerdown Control)
|
461 | 0019ad53 | blueswir1 | if (aux2_base) {
|
462 | 0019ad53 | blueswir1 | io = cpu_register_io_memory(0, slavio_aux2_mem_read,
|
463 | 0019ad53 | blueswir1 | slavio_aux2_mem_write, s); |
464 | 0019ad53 | blueswir1 | cpu_register_physical_memory(aux2_base, MISC_SIZE, io); |
465 | 0019ad53 | blueswir1 | } |
466 | 0019ad53 | blueswir1 | |
467 | 0019ad53 | blueswir1 | // Power management (APC) XXX: not a Slavio device
|
468 | 0019ad53 | blueswir1 | if (power_base) {
|
469 | 0019ad53 | blueswir1 | io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
|
470 | 0019ad53 | blueswir1 | cpu_register_physical_memory(power_base, MISC_SIZE, io); |
471 | 0019ad53 | blueswir1 | } |
472 | bfa30a38 | blueswir1 | |
473 | 3475187d | bellard | s->irq = irq; |
474 | 0019ad53 | blueswir1 | s->env = env; |
475 | 2be17ebd | blueswir1 | *fdc_tc = &s->fdc_tc; |
476 | 3475187d | bellard | |
477 | bfa30a38 | blueswir1 | register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, |
478 | bfa30a38 | blueswir1 | s); |
479 | 3475187d | bellard | qemu_register_reset(slavio_misc_reset, s); |
480 | 3475187d | bellard | slavio_misc_reset(s); |
481 | 0019ad53 | blueswir1 | |
482 | 3475187d | bellard | return s;
|
483 | 3475187d | bellard | } |