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1	2c0262af	bellard	/*
2	2c0262af	bellard	* i386 translation
3	2c0262af	bellard	*
4	2c0262af	bellard	* Copyright (c) 2003 Fabrice Bellard
5	2c0262af	bellard	*
6	2c0262af	bellard	* This library is free software; you can redistribute it and/or
7	2c0262af	bellard	* modify it under the terms of the GNU Lesser General Public
8	2c0262af	bellard	* License as published by the Free Software Foundation; either
9	2c0262af	bellard	* version 2 of the License, or (at your option) any later version.
10	2c0262af	bellard	*
11	2c0262af	bellard	* This library is distributed in the hope that it will be useful,
12	2c0262af	bellard	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	2c0262af	bellard	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	2c0262af	bellard	* Lesser General Public License for more details.
15	2c0262af	bellard	*
16	2c0262af	bellard	* You should have received a copy of the GNU Lesser General Public
17	2c0262af	bellard	* License along with this library; if not, write to the Free Software
18	2c0262af	bellard	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	2c0262af	bellard	*/
20	2c0262af	bellard	#include <stdarg.h>
21	2c0262af	bellard	#include <stdlib.h>
22	2c0262af	bellard	#include <stdio.h>
23	2c0262af	bellard	#include <string.h>
24	2c0262af	bellard	#include <inttypes.h>
25	2c0262af	bellard	#include <signal.h>
26	2c0262af	bellard	#include <assert.h>
27	2c0262af	bellard
28	2c0262af	bellard	#include "cpu.h"
29	2c0262af	bellard	#include "exec-all.h"
30	2c0262af	bellard	#include "disas.h"
31	2c0262af	bellard
32	2c0262af	bellard	/* XXX: move that elsewhere */
33	2c0262af	bellard	static uint16_t *gen_opc_ptr;
34	2c0262af	bellard	static uint32_t *gen_opparam_ptr;
35	2c0262af	bellard
36	2c0262af	bellard	#define PREFIX_REPZ 0x01
37	2c0262af	bellard	#define PREFIX_REPNZ 0x02
38	2c0262af	bellard	#define PREFIX_LOCK 0x04
39	2c0262af	bellard	#define PREFIX_DATA 0x08
40	2c0262af	bellard	#define PREFIX_ADR 0x10
41	2c0262af	bellard
42	14ce26e7	bellard	#ifdef TARGET_X86_64
43	14ce26e7	bellard	#define X86_64_ONLY(x) x
44	14ce26e7	bellard	#define X86_64_DEF(x...) x
45	14ce26e7	bellard	#define CODE64(s) ((s)->code64)
46	14ce26e7	bellard	#define REX_X(s) ((s)->rex_x)
47	14ce26e7	bellard	#define REX_B(s) ((s)->rex_b)
48	14ce26e7	bellard	/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49	14ce26e7	bellard	#if 1
50	14ce26e7	bellard	#define BUGGY_64(x) NULL
51	14ce26e7	bellard	#endif
52	14ce26e7	bellard	#else
53	14ce26e7	bellard	#define X86_64_ONLY(x) NULL
54	14ce26e7	bellard	#define X86_64_DEF(x...)
55	14ce26e7	bellard	#define CODE64(s) 0
56	14ce26e7	bellard	#define REX_X(s) 0
57	14ce26e7	bellard	#define REX_B(s) 0
58	14ce26e7	bellard	#endif
59	14ce26e7	bellard
60	14ce26e7	bellard	#ifdef TARGET_X86_64
61	14ce26e7	bellard	static int x86_64_hregs;
62	14ce26e7	bellard	#endif
63	14ce26e7	bellard
64	ae063a68	bellard	#ifdef USE_DIRECT_JUMP
65	ae063a68	bellard	#define TBPARAM(x)
66	ae063a68	bellard	#else
67	ae063a68	bellard	#define TBPARAM(x) (long)(x)
68	ae063a68	bellard	#endif
69	ae063a68	bellard
70	2c0262af	bellard	typedef struct DisasContext {
71	2c0262af	bellard	/* current insn context */
72	2c0262af	bellard	int override; /* -1 if no override */
73	2c0262af	bellard	int prefix;
74	2c0262af	bellard	int aflag, dflag;
75	14ce26e7	bellard	target_ulong pc; /* pc = eip + cs_base */
76	2c0262af	bellard	int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
77	2c0262af	bellard	static state change (stop translation) */
78	2c0262af	bellard	/* current block context */
79	14ce26e7	bellard	target_ulong cs_base; /* base of CS segment */
80	2c0262af	bellard	int pe; /* protected mode */
81	2c0262af	bellard	int code32; /* 32 bit code segment */
82	14ce26e7	bellard	#ifdef TARGET_X86_64
83	14ce26e7	bellard	int lma; /* long mode active */
84	14ce26e7	bellard	int code64; /* 64 bit code segment */
85	14ce26e7	bellard	int rex_x, rex_b;
86	14ce26e7	bellard	#endif
87	2c0262af	bellard	int ss32; /* 32 bit stack segment */
88	2c0262af	bellard	int cc_op; /* current CC operation */
89	2c0262af	bellard	int addseg; /* non zero if either DS/ES/SS have a non zero base */
90	2c0262af	bellard	int f_st; /* currently unused */
91	2c0262af	bellard	int vm86; /* vm86 mode */
92	2c0262af	bellard	int cpl;
93	2c0262af	bellard	int iopl;
94	2c0262af	bellard	int tf; /* TF cpu flag */
95	34865134	bellard	int singlestep_enabled; /* "hardware" single step enabled */
96	2c0262af	bellard	int jmp_opt; /* use direct block chaining for direct jumps */
97	2c0262af	bellard	int mem_index; /* select memory access functions */
98	7eee2a50	bellard	int flags; /* all execution flags */
99	2c0262af	bellard	struct TranslationBlock *tb;
100	2c0262af	bellard	int popl_esp_hack; /* for correct popl with esp base handling */
101	14ce26e7	bellard	int rip_offset; /* only used in x86_64, but left for simplicity */
102	14ce26e7	bellard	int cpuid_features;
103	2c0262af	bellard	} DisasContext;
104	2c0262af	bellard
105	2c0262af	bellard	static void gen_eob(DisasContext *s);
106	14ce26e7	bellard	static void gen_jmp(DisasContext *s, target_ulong eip);
107	14ce26e7	bellard	static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
108	2c0262af	bellard
109	2c0262af	bellard	/* i386 arith/logic operations */
110	2c0262af	bellard	enum {
111	2c0262af	bellard	OP_ADDL,
112	2c0262af	bellard	OP_ORL,
113	2c0262af	bellard	OP_ADCL,
114	2c0262af	bellard	OP_SBBL,
115	2c0262af	bellard	OP_ANDL,
116	2c0262af	bellard	OP_SUBL,
117	2c0262af	bellard	OP_XORL,
118	2c0262af	bellard	OP_CMPL,
119	2c0262af	bellard	};
120	2c0262af	bellard
121	2c0262af	bellard	/* i386 shift ops */
122	2c0262af	bellard	enum {
123	2c0262af	bellard	OP_ROL,
124	2c0262af	bellard	OP_ROR,
125	2c0262af	bellard	OP_RCL,
126	2c0262af	bellard	OP_RCR,
127	2c0262af	bellard	OP_SHL,
128	2c0262af	bellard	OP_SHR,
129	2c0262af	bellard	OP_SHL1, /* undocumented */
130	2c0262af	bellard	OP_SAR = 7,
131	2c0262af	bellard	};
132	2c0262af	bellard
133	2c0262af	bellard	enum {
134	2c0262af	bellard	#define DEF(s, n, copy_size) INDEX_op_ ## s,
135	2c0262af	bellard	#include "opc.h"
136	2c0262af	bellard	#undef DEF
137	2c0262af	bellard	NB_OPS,
138	2c0262af	bellard	};
139	2c0262af	bellard
140	2c0262af	bellard	#include "gen-op.h"
141	2c0262af	bellard
142	2c0262af	bellard	/* operand size */
143	2c0262af	bellard	enum {
144	2c0262af	bellard	OT_BYTE = 0,
145	2c0262af	bellard	OT_WORD,
146	2c0262af	bellard	OT_LONG,
147	2c0262af	bellard	OT_QUAD,
148	2c0262af	bellard	};
149	2c0262af	bellard
150	2c0262af	bellard	enum {
151	2c0262af	bellard	/* I386 int registers */
152	2c0262af	bellard	OR_EAX, /* MUST be even numbered */
153	2c0262af	bellard	OR_ECX,
154	2c0262af	bellard	OR_EDX,
155	2c0262af	bellard	OR_EBX,
156	2c0262af	bellard	OR_ESP,
157	2c0262af	bellard	OR_EBP,
158	2c0262af	bellard	OR_ESI,
159	2c0262af	bellard	OR_EDI,
160	14ce26e7	bellard
161	14ce26e7	bellard	OR_TMP0 = 16, /* temporary operand register */
162	2c0262af	bellard	OR_TMP1,
163	2c0262af	bellard	OR_A0, /* temporary register used when doing address evaluation */
164	2c0262af	bellard	};
165	2c0262af	bellard
166	14ce26e7	bellard	#ifdef TARGET_X86_64
167	14ce26e7	bellard
168	14ce26e7	bellard	#define NB_OP_SIZES 4
169	14ce26e7	bellard
170	14ce26e7	bellard	#define DEF_REGS(prefix, suffix) \
171	14ce26e7	bellard	prefix ## EAX ## suffix,\
172	14ce26e7	bellard	prefix ## ECX ## suffix,\
173	14ce26e7	bellard	prefix ## EDX ## suffix,\
174	14ce26e7	bellard	prefix ## EBX ## suffix,\
175	14ce26e7	bellard	prefix ## ESP ## suffix,\
176	14ce26e7	bellard	prefix ## EBP ## suffix,\
177	14ce26e7	bellard	prefix ## ESI ## suffix,\
178	14ce26e7	bellard	prefix ## EDI ## suffix,\
179	14ce26e7	bellard	prefix ## R8 ## suffix,\
180	14ce26e7	bellard	prefix ## R9 ## suffix,\
181	14ce26e7	bellard	prefix ## R10 ## suffix,\
182	14ce26e7	bellard	prefix ## R11 ## suffix,\
183	14ce26e7	bellard	prefix ## R12 ## suffix,\
184	14ce26e7	bellard	prefix ## R13 ## suffix,\
185	14ce26e7	bellard	prefix ## R14 ## suffix,\
186	14ce26e7	bellard	prefix ## R15 ## suffix,
187	14ce26e7	bellard
188	14ce26e7	bellard	#define DEF_BREGS(prefixb, prefixh, suffix) \
189	14ce26e7	bellard	\
190	14ce26e7	bellard	static void prefixb ## ESP ## suffix ## _wrapper(void) \
191	14ce26e7	bellard	{ \
192	14ce26e7	bellard	if (x86_64_hregs) \
193	14ce26e7	bellard	prefixb ## ESP ## suffix (); \
194	14ce26e7	bellard	else \
195	14ce26e7	bellard	prefixh ## EAX ## suffix (); \
196	14ce26e7	bellard	} \
197	14ce26e7	bellard	\
198	14ce26e7	bellard	static void prefixb ## EBP ## suffix ## _wrapper(void) \
199	14ce26e7	bellard	{ \
200	14ce26e7	bellard	if (x86_64_hregs) \
201	14ce26e7	bellard	prefixb ## EBP ## suffix (); \
202	14ce26e7	bellard	else \
203	14ce26e7	bellard	prefixh ## ECX ## suffix (); \
204	14ce26e7	bellard	} \
205	14ce26e7	bellard	\
206	14ce26e7	bellard	static void prefixb ## ESI ## suffix ## _wrapper(void) \
207	14ce26e7	bellard	{ \
208	14ce26e7	bellard	if (x86_64_hregs) \
209	14ce26e7	bellard	prefixb ## ESI ## suffix (); \
210	14ce26e7	bellard	else \
211	14ce26e7	bellard	prefixh ## EDX ## suffix (); \
212	14ce26e7	bellard	} \
213	14ce26e7	bellard	\
214	14ce26e7	bellard	static void prefixb ## EDI ## suffix ## _wrapper(void) \
215	14ce26e7	bellard	{ \
216	14ce26e7	bellard	if (x86_64_hregs) \
217	14ce26e7	bellard	prefixb ## EDI ## suffix (); \
218	14ce26e7	bellard	else \
219	14ce26e7	bellard	prefixh ## EBX ## suffix (); \
220	14ce26e7	bellard	}
221	14ce26e7	bellard
222	14ce26e7	bellard	DEF_BREGS(gen_op_movb_, gen_op_movh_, _T0)
223	14ce26e7	bellard	DEF_BREGS(gen_op_movb_, gen_op_movh_, _T1)
224	14ce26e7	bellard	DEF_BREGS(gen_op_movl_T0_, gen_op_movh_T0_, )
225	14ce26e7	bellard	DEF_BREGS(gen_op_movl_T1_, gen_op_movh_T1_, )
226	14ce26e7	bellard
227	14ce26e7	bellard	#else /* !TARGET_X86_64 */
228	14ce26e7	bellard
229	14ce26e7	bellard	#define NB_OP_SIZES 3
230	14ce26e7	bellard
231	14ce26e7	bellard	#define DEF_REGS(prefix, suffix) \
232	14ce26e7	bellard	prefix ## EAX ## suffix,\
233	14ce26e7	bellard	prefix ## ECX ## suffix,\
234	14ce26e7	bellard	prefix ## EDX ## suffix,\
235	14ce26e7	bellard	prefix ## EBX ## suffix,\
236	14ce26e7	bellard	prefix ## ESP ## suffix,\
237	14ce26e7	bellard	prefix ## EBP ## suffix,\
238	14ce26e7	bellard	prefix ## ESI ## suffix,\
239	14ce26e7	bellard	prefix ## EDI ## suffix,
240	14ce26e7	bellard
241	14ce26e7	bellard	#endif /* !TARGET_X86_64 */
242	14ce26e7	bellard
243	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_T0[NB_OP_SIZES][CPU_NB_REGS] = {
244	2c0262af	bellard	[OT_BYTE] = {
245	2c0262af	bellard	gen_op_movb_EAX_T0,
246	2c0262af	bellard	gen_op_movb_ECX_T0,
247	2c0262af	bellard	gen_op_movb_EDX_T0,
248	2c0262af	bellard	gen_op_movb_EBX_T0,
249	14ce26e7	bellard	#ifdef TARGET_X86_64
250	14ce26e7	bellard	gen_op_movb_ESP_T0_wrapper,
251	14ce26e7	bellard	gen_op_movb_EBP_T0_wrapper,
252	14ce26e7	bellard	gen_op_movb_ESI_T0_wrapper,
253	14ce26e7	bellard	gen_op_movb_EDI_T0_wrapper,
254	14ce26e7	bellard	gen_op_movb_R8_T0,
255	14ce26e7	bellard	gen_op_movb_R9_T0,
256	14ce26e7	bellard	gen_op_movb_R10_T0,
257	14ce26e7	bellard	gen_op_movb_R11_T0,
258	14ce26e7	bellard	gen_op_movb_R12_T0,
259	14ce26e7	bellard	gen_op_movb_R13_T0,
260	14ce26e7	bellard	gen_op_movb_R14_T0,
261	14ce26e7	bellard	gen_op_movb_R15_T0,
262	14ce26e7	bellard	#else
263	2c0262af	bellard	gen_op_movh_EAX_T0,
264	2c0262af	bellard	gen_op_movh_ECX_T0,
265	2c0262af	bellard	gen_op_movh_EDX_T0,
266	2c0262af	bellard	gen_op_movh_EBX_T0,
267	14ce26e7	bellard	#endif
268	2c0262af	bellard	},
269	2c0262af	bellard	[OT_WORD] = {
270	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _T0)
271	2c0262af	bellard	},
272	2c0262af	bellard	[OT_LONG] = {
273	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _T0)
274	2c0262af	bellard	},
275	14ce26e7	bellard	#ifdef TARGET_X86_64
276	14ce26e7	bellard	[OT_QUAD] = {
277	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _T0)
278	14ce26e7	bellard	},
279	14ce26e7	bellard	#endif
280	2c0262af	bellard	};
281	2c0262af	bellard
282	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_T1[NB_OP_SIZES][CPU_NB_REGS] = {
283	2c0262af	bellard	[OT_BYTE] = {
284	2c0262af	bellard	gen_op_movb_EAX_T1,
285	2c0262af	bellard	gen_op_movb_ECX_T1,
286	2c0262af	bellard	gen_op_movb_EDX_T1,
287	2c0262af	bellard	gen_op_movb_EBX_T1,
288	14ce26e7	bellard	#ifdef TARGET_X86_64
289	14ce26e7	bellard	gen_op_movb_ESP_T1_wrapper,
290	14ce26e7	bellard	gen_op_movb_EBP_T1_wrapper,
291	14ce26e7	bellard	gen_op_movb_ESI_T1_wrapper,
292	14ce26e7	bellard	gen_op_movb_EDI_T1_wrapper,
293	14ce26e7	bellard	gen_op_movb_R8_T1,
294	14ce26e7	bellard	gen_op_movb_R9_T1,
295	14ce26e7	bellard	gen_op_movb_R10_T1,
296	14ce26e7	bellard	gen_op_movb_R11_T1,
297	14ce26e7	bellard	gen_op_movb_R12_T1,
298	14ce26e7	bellard	gen_op_movb_R13_T1,
299	14ce26e7	bellard	gen_op_movb_R14_T1,
300	14ce26e7	bellard	gen_op_movb_R15_T1,
301	14ce26e7	bellard	#else
302	2c0262af	bellard	gen_op_movh_EAX_T1,
303	2c0262af	bellard	gen_op_movh_ECX_T1,
304	2c0262af	bellard	gen_op_movh_EDX_T1,
305	2c0262af	bellard	gen_op_movh_EBX_T1,
306	14ce26e7	bellard	#endif
307	2c0262af	bellard	},
308	2c0262af	bellard	[OT_WORD] = {
309	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _T1)
310	2c0262af	bellard	},
311	2c0262af	bellard	[OT_LONG] = {
312	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _T1)
313	14ce26e7	bellard	},
314	14ce26e7	bellard	#ifdef TARGET_X86_64
315	14ce26e7	bellard	[OT_QUAD] = {
316	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _T1)
317	2c0262af	bellard	},
318	14ce26e7	bellard	#endif
319	2c0262af	bellard	};
320	2c0262af	bellard
321	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_A0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
322	2c0262af	bellard	[0] = {
323	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _A0)
324	2c0262af	bellard	},
325	2c0262af	bellard	[1] = {
326	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _A0)
327	14ce26e7	bellard	},
328	14ce26e7	bellard	#ifdef TARGET_X86_64
329	14ce26e7	bellard	[2] = {
330	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _A0)
331	2c0262af	bellard	},
332	14ce26e7	bellard	#endif
333	2c0262af	bellard	};
334	2c0262af	bellard
335	14ce26e7	bellard	static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
336	2c0262af	bellard	{
337	2c0262af	bellard	[OT_BYTE] = {
338	2c0262af	bellard	{
339	2c0262af	bellard	gen_op_movl_T0_EAX,
340	2c0262af	bellard	gen_op_movl_T0_ECX,
341	2c0262af	bellard	gen_op_movl_T0_EDX,
342	2c0262af	bellard	gen_op_movl_T0_EBX,
343	14ce26e7	bellard	#ifdef TARGET_X86_64
344	14ce26e7	bellard	gen_op_movl_T0_ESP_wrapper,
345	14ce26e7	bellard	gen_op_movl_T0_EBP_wrapper,
346	14ce26e7	bellard	gen_op_movl_T0_ESI_wrapper,
347	14ce26e7	bellard	gen_op_movl_T0_EDI_wrapper,
348	14ce26e7	bellard	gen_op_movl_T0_R8,
349	14ce26e7	bellard	gen_op_movl_T0_R9,
350	14ce26e7	bellard	gen_op_movl_T0_R10,
351	14ce26e7	bellard	gen_op_movl_T0_R11,
352	14ce26e7	bellard	gen_op_movl_T0_R12,
353	14ce26e7	bellard	gen_op_movl_T0_R13,
354	14ce26e7	bellard	gen_op_movl_T0_R14,
355	14ce26e7	bellard	gen_op_movl_T0_R15,
356	14ce26e7	bellard	#else
357	2c0262af	bellard	gen_op_movh_T0_EAX,
358	2c0262af	bellard	gen_op_movh_T0_ECX,
359	2c0262af	bellard	gen_op_movh_T0_EDX,
360	2c0262af	bellard	gen_op_movh_T0_EBX,
361	14ce26e7	bellard	#endif
362	2c0262af	bellard	},
363	2c0262af	bellard	{
364	2c0262af	bellard	gen_op_movl_T1_EAX,
365	2c0262af	bellard	gen_op_movl_T1_ECX,
366	2c0262af	bellard	gen_op_movl_T1_EDX,
367	2c0262af	bellard	gen_op_movl_T1_EBX,
368	14ce26e7	bellard	#ifdef TARGET_X86_64
369	14ce26e7	bellard	gen_op_movl_T1_ESP_wrapper,
370	14ce26e7	bellard	gen_op_movl_T1_EBP_wrapper,
371	14ce26e7	bellard	gen_op_movl_T1_ESI_wrapper,
372	14ce26e7	bellard	gen_op_movl_T1_EDI_wrapper,
373	14ce26e7	bellard	gen_op_movl_T1_R8,
374	14ce26e7	bellard	gen_op_movl_T1_R9,
375	14ce26e7	bellard	gen_op_movl_T1_R10,
376	14ce26e7	bellard	gen_op_movl_T1_R11,
377	14ce26e7	bellard	gen_op_movl_T1_R12,
378	14ce26e7	bellard	gen_op_movl_T1_R13,
379	14ce26e7	bellard	gen_op_movl_T1_R14,
380	14ce26e7	bellard	gen_op_movl_T1_R15,
381	14ce26e7	bellard	#else
382	2c0262af	bellard	gen_op_movh_T1_EAX,
383	2c0262af	bellard	gen_op_movh_T1_ECX,
384	2c0262af	bellard	gen_op_movh_T1_EDX,
385	2c0262af	bellard	gen_op_movh_T1_EBX,
386	14ce26e7	bellard	#endif
387	2c0262af	bellard	},
388	2c0262af	bellard	},
389	2c0262af	bellard	[OT_WORD] = {
390	2c0262af	bellard	{
391	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
392	2c0262af	bellard	},
393	2c0262af	bellard	{
394	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
395	2c0262af	bellard	},
396	2c0262af	bellard	},
397	2c0262af	bellard	[OT_LONG] = {
398	2c0262af	bellard	{
399	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
400	2c0262af	bellard	},
401	2c0262af	bellard	{
402	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
403	2c0262af	bellard	},
404	2c0262af	bellard	},
405	14ce26e7	bellard	#ifdef TARGET_X86_64
406	14ce26e7	bellard	[OT_QUAD] = {
407	14ce26e7	bellard	{
408	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
409	14ce26e7	bellard	},
410	14ce26e7	bellard	{
411	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
412	14ce26e7	bellard	},
413	14ce26e7	bellard	},
414	14ce26e7	bellard	#endif
415	2c0262af	bellard	};
416	2c0262af	bellard
417	14ce26e7	bellard	static GenOpFunc *gen_op_movl_A0_reg[CPU_NB_REGS] = {
418	14ce26e7	bellard	DEF_REGS(gen_op_movl_A0_, )
419	2c0262af	bellard	};
420	2c0262af	bellard
421	14ce26e7	bellard	static GenOpFunc *gen_op_addl_A0_reg_sN[4][CPU_NB_REGS] = {
422	2c0262af	bellard	[0] = {
423	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, )
424	2c0262af	bellard	},
425	2c0262af	bellard	[1] = {
426	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s1)
427	2c0262af	bellard	},
428	2c0262af	bellard	[2] = {
429	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s2)
430	2c0262af	bellard	},
431	2c0262af	bellard	[3] = {
432	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s3)
433	2c0262af	bellard	},
434	2c0262af	bellard	};
435	2c0262af	bellard
436	14ce26e7	bellard	#ifdef TARGET_X86_64
437	14ce26e7	bellard	static GenOpFunc *gen_op_movq_A0_reg[CPU_NB_REGS] = {
438	14ce26e7	bellard	DEF_REGS(gen_op_movq_A0_, )
439	14ce26e7	bellard	};
440	14ce26e7	bellard
441	14ce26e7	bellard	static GenOpFunc *gen_op_addq_A0_reg_sN[4][CPU_NB_REGS] = {
442	2c0262af	bellard	[0] = {
443	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, )
444	2c0262af	bellard	},
445	2c0262af	bellard	[1] = {
446	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s1)
447	14ce26e7	bellard	},
448	14ce26e7	bellard	[2] = {
449	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s2)
450	14ce26e7	bellard	},
451	14ce26e7	bellard	[3] = {
452	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s3)
453	2c0262af	bellard	},
454	2c0262af	bellard	};
455	14ce26e7	bellard	#endif
456	14ce26e7	bellard
457	14ce26e7	bellard	static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
458	14ce26e7	bellard	[0] = {
459	14ce26e7	bellard	DEF_REGS(gen_op_cmovw_, _T1_T0)
460	14ce26e7	bellard	},
461	14ce26e7	bellard	[1] = {
462	14ce26e7	bellard	DEF_REGS(gen_op_cmovl_, _T1_T0)
463	14ce26e7	bellard	},
464	14ce26e7	bellard	#ifdef TARGET_X86_64
465	14ce26e7	bellard	[2] = {
466	14ce26e7	bellard	DEF_REGS(gen_op_cmovq_, _T1_T0)
467	14ce26e7	bellard	},
468	14ce26e7	bellard	#endif
469	14ce26e7	bellard	};
470	2c0262af	bellard
471	2c0262af	bellard	static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
472	2c0262af	bellard	NULL,
473	2c0262af	bellard	gen_op_orl_T0_T1,
474	2c0262af	bellard	NULL,
475	2c0262af	bellard	NULL,
476	2c0262af	bellard	gen_op_andl_T0_T1,
477	2c0262af	bellard	NULL,
478	2c0262af	bellard	gen_op_xorl_T0_T1,
479	2c0262af	bellard	NULL,
480	2c0262af	bellard	};
481	2c0262af	bellard
482	4f31916f	bellard	#define DEF_ARITHC(SUFFIX)\
483	4f31916f	bellard	{\
484	4f31916f	bellard	gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
485	4f31916f	bellard	gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
486	4f31916f	bellard	},\
487	4f31916f	bellard	{\
488	4f31916f	bellard	gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
489	4f31916f	bellard	gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
490	4f31916f	bellard	},\
491	4f31916f	bellard	{\
492	4f31916f	bellard	gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
493	4f31916f	bellard	gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
494	14ce26e7	bellard	},\
495	14ce26e7	bellard	{\
496	14ce26e7	bellard	X86_64_ONLY(gen_op_adcq ## SUFFIX ## _T0_T1_cc),\
497	14ce26e7	bellard	X86_64_ONLY(gen_op_sbbq ## SUFFIX ## _T0_T1_cc),\
498	2c0262af	bellard	},
499	4f31916f	bellard
500	14ce26e7	bellard	static GenOpFunc *gen_op_arithc_T0_T1_cc[4][2] = {
501	4bb2fcc7	bellard	DEF_ARITHC( )
502	2c0262af	bellard	};
503	2c0262af	bellard
504	14ce26e7	bellard	static GenOpFunc gen_op_arithc_mem_T0_T1_cc[3 4][2] = {
505	4f31916f	bellard	DEF_ARITHC(_raw)
506	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
507	4f31916f	bellard	DEF_ARITHC(_kernel)
508	4f31916f	bellard	DEF_ARITHC(_user)
509	4f31916f	bellard	#endif
510	2c0262af	bellard	};
511	2c0262af	bellard
512	2c0262af	bellard	static const int cc_op_arithb[8] = {
513	2c0262af	bellard	CC_OP_ADDB,
514	2c0262af	bellard	CC_OP_LOGICB,
515	2c0262af	bellard	CC_OP_ADDB,
516	2c0262af	bellard	CC_OP_SUBB,
517	2c0262af	bellard	CC_OP_LOGICB,
518	2c0262af	bellard	CC_OP_SUBB,
519	2c0262af	bellard	CC_OP_LOGICB,
520	2c0262af	bellard	CC_OP_SUBB,
521	2c0262af	bellard	};
522	2c0262af	bellard
523	4f31916f	bellard	#define DEF_CMPXCHG(SUFFIX)\
524	4f31916f	bellard	gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
525	4f31916f	bellard	gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
526	14ce26e7	bellard	gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,\
527	14ce26e7	bellard	X86_64_ONLY(gen_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc),
528	4f31916f	bellard
529	14ce26e7	bellard	static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[4] = {
530	4bb2fcc7	bellard	DEF_CMPXCHG( )
531	2c0262af	bellard	};
532	2c0262af	bellard
533	14ce26e7	bellard	static GenOpFunc gen_op_cmpxchg_mem_T0_T1_EAX_cc[3 4] = {
534	4f31916f	bellard	DEF_CMPXCHG(_raw)
535	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
536	4f31916f	bellard	DEF_CMPXCHG(_kernel)
537	4f31916f	bellard	DEF_CMPXCHG(_user)
538	4f31916f	bellard	#endif
539	2c0262af	bellard	};
540	2c0262af	bellard
541	4f31916f	bellard	#define DEF_SHIFT(SUFFIX)\
542	4f31916f	bellard	{\
543	4f31916f	bellard	gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
544	4f31916f	bellard	gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
545	4f31916f	bellard	gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
546	4f31916f	bellard	gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
547	4f31916f	bellard	gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
548	4f31916f	bellard	gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
549	4f31916f	bellard	gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
550	4f31916f	bellard	gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
551	4f31916f	bellard	},\
552	4f31916f	bellard	{\
553	4f31916f	bellard	gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
554	4f31916f	bellard	gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
555	4f31916f	bellard	gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
556	4f31916f	bellard	gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
557	4f31916f	bellard	gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
558	4f31916f	bellard	gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
559	4f31916f	bellard	gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
560	4f31916f	bellard	gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
561	4f31916f	bellard	},\
562	4f31916f	bellard	{\
563	4f31916f	bellard	gen_op_roll ## SUFFIX ## _T0_T1_cc,\
564	4f31916f	bellard	gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
565	4f31916f	bellard	gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
566	4f31916f	bellard	gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
567	4f31916f	bellard	gen_op_shll ## SUFFIX ## _T0_T1_cc,\
568	4f31916f	bellard	gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
569	4f31916f	bellard	gen_op_shll ## SUFFIX ## _T0_T1_cc,\
570	4f31916f	bellard	gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
571	14ce26e7	bellard	},\
572	14ce26e7	bellard	{\
573	14ce26e7	bellard	X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\
574	14ce26e7	bellard	X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\
575	14ce26e7	bellard	X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\
576	14ce26e7	bellard	X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\
577	14ce26e7	bellard	X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
578	14ce26e7	bellard	X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\
579	14ce26e7	bellard	X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
580	14ce26e7	bellard	X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\
581	2c0262af	bellard	},
582	4f31916f	bellard
583	14ce26e7	bellard	static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {
584	4bb2fcc7	bellard	DEF_SHIFT( )
585	2c0262af	bellard	};
586	2c0262af	bellard
587	14ce26e7	bellard	static GenOpFunc gen_op_shift_mem_T0_T1_cc[3 4][8] = {
588	4f31916f	bellard	DEF_SHIFT(_raw)
589	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
590	4f31916f	bellard	DEF_SHIFT(_kernel)
591	4f31916f	bellard	DEF_SHIFT(_user)
592	4f31916f	bellard	#endif
593	2c0262af	bellard	};
594	2c0262af	bellard
595	4f31916f	bellard	#define DEF_SHIFTD(SUFFIX, op)\
596	4f31916f	bellard	{\
597	4f31916f	bellard	NULL,\
598	4f31916f	bellard	NULL,\
599	4f31916f	bellard	},\
600	4f31916f	bellard	{\
601	4f31916f	bellard	gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
602	4f31916f	bellard	gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
603	31313213	bellard	},\
604	4f31916f	bellard	{\
605	4f31916f	bellard	gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
606	4f31916f	bellard	gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
607	14ce26e7	bellard	},\
608	14ce26e7	bellard	{\
609	31313213	bellard	X86_64_DEF(gen_op_shldq ## SUFFIX ## _T0_T1_ ## op ## _cc,\
610	31313213	bellard	gen_op_shrdq ## SUFFIX ## _T0_T1_ ## op ## _cc,)\
611	2c0262af	bellard	},
612	4f31916f	bellard
613	14ce26e7	bellard	static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {
614	4f31916f	bellard	DEF_SHIFTD(, im)
615	2c0262af	bellard	};
616	2c0262af	bellard
617	14ce26e7	bellard	static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {
618	4f31916f	bellard	DEF_SHIFTD(, ECX)
619	2c0262af	bellard	};
620	2c0262af	bellard
621	14ce26e7	bellard	static GenOpFunc1 gen_op_shiftd_mem_T0_T1_im_cc[3 4][2] = {
622	4f31916f	bellard	DEF_SHIFTD(_raw, im)
623	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
624	4f31916f	bellard	DEF_SHIFTD(_kernel, im)
625	4f31916f	bellard	DEF_SHIFTD(_user, im)
626	4f31916f	bellard	#endif
627	2c0262af	bellard	};
628	2c0262af	bellard
629	14ce26e7	bellard	static GenOpFunc gen_op_shiftd_mem_T0_T1_ECX_cc[3 4][2] = {
630	4f31916f	bellard	DEF_SHIFTD(_raw, ECX)
631	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
632	4f31916f	bellard	DEF_SHIFTD(_kernel, ECX)
633	4f31916f	bellard	DEF_SHIFTD(_user, ECX)
634	4f31916f	bellard	#endif
635	2c0262af	bellard	};
636	2c0262af	bellard
637	14ce26e7	bellard	static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {
638	2c0262af	bellard	[0] = {
639	2c0262af	bellard	gen_op_btw_T0_T1_cc,
640	2c0262af	bellard	gen_op_btsw_T0_T1_cc,
641	2c0262af	bellard	gen_op_btrw_T0_T1_cc,
642	2c0262af	bellard	gen_op_btcw_T0_T1_cc,
643	2c0262af	bellard	},
644	2c0262af	bellard	[1] = {
645	2c0262af	bellard	gen_op_btl_T0_T1_cc,
646	2c0262af	bellard	gen_op_btsl_T0_T1_cc,
647	2c0262af	bellard	gen_op_btrl_T0_T1_cc,
648	2c0262af	bellard	gen_op_btcl_T0_T1_cc,
649	2c0262af	bellard	},
650	14ce26e7	bellard	#ifdef TARGET_X86_64
651	14ce26e7	bellard	[2] = {
652	14ce26e7	bellard	gen_op_btq_T0_T1_cc,
653	14ce26e7	bellard	gen_op_btsq_T0_T1_cc,
654	14ce26e7	bellard	gen_op_btrq_T0_T1_cc,
655	14ce26e7	bellard	gen_op_btcq_T0_T1_cc,
656	14ce26e7	bellard	},
657	14ce26e7	bellard	#endif
658	14ce26e7	bellard	};
659	14ce26e7	bellard
660	14ce26e7	bellard	static GenOpFunc *gen_op_add_bit_A0_T1[3] = {
661	14ce26e7	bellard	gen_op_add_bitw_A0_T1,
662	14ce26e7	bellard	gen_op_add_bitl_A0_T1,
663	14ce26e7	bellard	X86_64_ONLY(gen_op_add_bitq_A0_T1),
664	2c0262af	bellard	};
665	2c0262af	bellard
666	14ce26e7	bellard	static GenOpFunc *gen_op_bsx_T0_cc[3][2] = {
667	2c0262af	bellard	[0] = {
668	2c0262af	bellard	gen_op_bsfw_T0_cc,
669	2c0262af	bellard	gen_op_bsrw_T0_cc,
670	2c0262af	bellard	},
671	2c0262af	bellard	[1] = {
672	2c0262af	bellard	gen_op_bsfl_T0_cc,
673	2c0262af	bellard	gen_op_bsrl_T0_cc,
674	2c0262af	bellard	},
675	14ce26e7	bellard	#ifdef TARGET_X86_64
676	14ce26e7	bellard	[2] = {
677	14ce26e7	bellard	gen_op_bsfq_T0_cc,
678	14ce26e7	bellard	gen_op_bsrq_T0_cc,
679	14ce26e7	bellard	},
680	14ce26e7	bellard	#endif
681	2c0262af	bellard	};
682	2c0262af	bellard
683	14ce26e7	bellard	static GenOpFunc gen_op_lds_T0_A0[3 4] = {
684	61382a50	bellard	gen_op_ldsb_raw_T0_A0,
685	61382a50	bellard	gen_op_ldsw_raw_T0_A0,
686	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_raw_T0_A0),
687	2c0262af	bellard	NULL,
688	61382a50	bellard	#ifndef CONFIG_USER_ONLY
689	2c0262af	bellard	gen_op_ldsb_kernel_T0_A0,
690	2c0262af	bellard	gen_op_ldsw_kernel_T0_A0,
691	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_kernel_T0_A0),
692	2c0262af	bellard	NULL,
693	2c0262af	bellard
694	2c0262af	bellard	gen_op_ldsb_user_T0_A0,
695	2c0262af	bellard	gen_op_ldsw_user_T0_A0,
696	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_user_T0_A0),
697	2c0262af	bellard	NULL,
698	61382a50	bellard	#endif
699	2c0262af	bellard	};
700	2c0262af	bellard
701	14ce26e7	bellard	static GenOpFunc gen_op_ldu_T0_A0[3 4] = {
702	61382a50	bellard	gen_op_ldub_raw_T0_A0,
703	61382a50	bellard	gen_op_lduw_raw_T0_A0,
704	2c0262af	bellard	NULL,
705	14ce26e7	bellard	NULL,
706	2c0262af	bellard
707	61382a50	bellard	#ifndef CONFIG_USER_ONLY
708	2c0262af	bellard	gen_op_ldub_kernel_T0_A0,
709	2c0262af	bellard	gen_op_lduw_kernel_T0_A0,
710	2c0262af	bellard	NULL,
711	14ce26e7	bellard	NULL,
712	2c0262af	bellard
713	2c0262af	bellard	gen_op_ldub_user_T0_A0,
714	2c0262af	bellard	gen_op_lduw_user_T0_A0,
715	2c0262af	bellard	NULL,
716	14ce26e7	bellard	NULL,
717	61382a50	bellard	#endif
718	2c0262af	bellard	};
719	2c0262af	bellard
720	2c0262af	bellard	/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
721	14ce26e7	bellard	static GenOpFunc gen_op_ld_T0_A0[3 4] = {
722	61382a50	bellard	gen_op_ldub_raw_T0_A0,
723	61382a50	bellard	gen_op_lduw_raw_T0_A0,
724	61382a50	bellard	gen_op_ldl_raw_T0_A0,
725	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_raw_T0_A0),
726	2c0262af	bellard
727	61382a50	bellard	#ifndef CONFIG_USER_ONLY
728	2c0262af	bellard	gen_op_ldub_kernel_T0_A0,
729	2c0262af	bellard	gen_op_lduw_kernel_T0_A0,
730	2c0262af	bellard	gen_op_ldl_kernel_T0_A0,
731	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_kernel_T0_A0),
732	2c0262af	bellard
733	2c0262af	bellard	gen_op_ldub_user_T0_A0,
734	2c0262af	bellard	gen_op_lduw_user_T0_A0,
735	2c0262af	bellard	gen_op_ldl_user_T0_A0,
736	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_user_T0_A0),
737	61382a50	bellard	#endif
738	2c0262af	bellard	};
739	2c0262af	bellard
740	14ce26e7	bellard	static GenOpFunc gen_op_ld_T1_A0[3 4] = {
741	61382a50	bellard	gen_op_ldub_raw_T1_A0,
742	61382a50	bellard	gen_op_lduw_raw_T1_A0,
743	61382a50	bellard	gen_op_ldl_raw_T1_A0,
744	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_raw_T1_A0),
745	2c0262af	bellard
746	61382a50	bellard	#ifndef CONFIG_USER_ONLY
747	2c0262af	bellard	gen_op_ldub_kernel_T1_A0,
748	2c0262af	bellard	gen_op_lduw_kernel_T1_A0,
749	2c0262af	bellard	gen_op_ldl_kernel_T1_A0,
750	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_kernel_T1_A0),
751	2c0262af	bellard
752	2c0262af	bellard	gen_op_ldub_user_T1_A0,
753	2c0262af	bellard	gen_op_lduw_user_T1_A0,
754	2c0262af	bellard	gen_op_ldl_user_T1_A0,
755	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_user_T1_A0),
756	61382a50	bellard	#endif
757	2c0262af	bellard	};
758	2c0262af	bellard
759	14ce26e7	bellard	static GenOpFunc gen_op_st_T0_A0[3 4] = {
760	61382a50	bellard	gen_op_stb_raw_T0_A0,
761	61382a50	bellard	gen_op_stw_raw_T0_A0,
762	61382a50	bellard	gen_op_stl_raw_T0_A0,
763	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_raw_T0_A0),
764	2c0262af	bellard
765	61382a50	bellard	#ifndef CONFIG_USER_ONLY
766	2c0262af	bellard	gen_op_stb_kernel_T0_A0,
767	2c0262af	bellard	gen_op_stw_kernel_T0_A0,
768	2c0262af	bellard	gen_op_stl_kernel_T0_A0,
769	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_kernel_T0_A0),
770	2c0262af	bellard
771	2c0262af	bellard	gen_op_stb_user_T0_A0,
772	2c0262af	bellard	gen_op_stw_user_T0_A0,
773	2c0262af	bellard	gen_op_stl_user_T0_A0,
774	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_user_T0_A0),
775	61382a50	bellard	#endif
776	2c0262af	bellard	};
777	2c0262af	bellard
778	14ce26e7	bellard	static GenOpFunc gen_op_st_T1_A0[3 4] = {
779	4f31916f	bellard	NULL,
780	4f31916f	bellard	gen_op_stw_raw_T1_A0,
781	4f31916f	bellard	gen_op_stl_raw_T1_A0,
782	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_raw_T1_A0),
783	4f31916f	bellard
784	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
785	4f31916f	bellard	NULL,
786	4f31916f	bellard	gen_op_stw_kernel_T1_A0,
787	4f31916f	bellard	gen_op_stl_kernel_T1_A0,
788	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_kernel_T1_A0),
789	4f31916f	bellard
790	4f31916f	bellard	NULL,
791	4f31916f	bellard	gen_op_stw_user_T1_A0,
792	4f31916f	bellard	gen_op_stl_user_T1_A0,
793	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_user_T1_A0),
794	4f31916f	bellard	#endif
795	4f31916f	bellard	};
796	4f31916f	bellard
797	14ce26e7	bellard	static inline void gen_jmp_im(target_ulong pc)
798	14ce26e7	bellard	{
799	14ce26e7	bellard	#ifdef TARGET_X86_64
800	14ce26e7	bellard	if (pc == (uint32_t)pc) {
801	14ce26e7	bellard	gen_op_movl_eip_im(pc);
802	14ce26e7	bellard	} else if (pc == (int32_t)pc) {
803	14ce26e7	bellard	gen_op_movq_eip_im(pc);
804	14ce26e7	bellard	} else {
805	14ce26e7	bellard	gen_op_movq_eip_im64(pc >> 32, pc);
806	14ce26e7	bellard	}
807	14ce26e7	bellard	#else
808	14ce26e7	bellard	gen_op_movl_eip_im(pc);
809	14ce26e7	bellard	#endif
810	14ce26e7	bellard	}
811	14ce26e7	bellard
812	2c0262af	bellard	static inline void gen_string_movl_A0_ESI(DisasContext *s)
813	2c0262af	bellard	{
814	2c0262af	bellard	int override;
815	2c0262af	bellard
816	2c0262af	bellard	override = s->override;
817	14ce26e7	bellard	#ifdef TARGET_X86_64
818	14ce26e7	bellard	if (s->aflag == 2) {
819	14ce26e7	bellard	if (override >= 0) {
820	14ce26e7	bellard	gen_op_movq_A0_seg(offsetof(CPUX86State,segs[override].base));
821	14ce26e7	bellard	gen_op_addq_A0_reg_sN[0][R_ESI]();
822	14ce26e7	bellard	} else {
823	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESI]();
824	14ce26e7	bellard	}
825	14ce26e7	bellard	} else
826	14ce26e7	bellard	#endif
827	2c0262af	bellard	if (s->aflag) {
828	2c0262af	bellard	/* 32 bit address */
829	2c0262af	bellard	if (s->addseg && override < 0)
830	2c0262af	bellard	override = R_DS;
831	2c0262af	bellard	if (override >= 0) {
832	2c0262af	bellard	gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
833	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
834	2c0262af	bellard	} else {
835	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
836	2c0262af	bellard	}
837	2c0262af	bellard	} else {
838	2c0262af	bellard	/* 16 address, always override */
839	2c0262af	bellard	if (override < 0)
840	2c0262af	bellard	override = R_DS;
841	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
842	2c0262af	bellard	gen_op_andl_A0_ffff();
843	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
844	2c0262af	bellard	}
845	2c0262af	bellard	}
846	2c0262af	bellard
847	2c0262af	bellard	static inline void gen_string_movl_A0_EDI(DisasContext *s)
848	2c0262af	bellard	{
849	14ce26e7	bellard	#ifdef TARGET_X86_64
850	14ce26e7	bellard	if (s->aflag == 2) {
851	14ce26e7	bellard	gen_op_movq_A0_reg[R_EDI]();
852	14ce26e7	bellard	} else
853	14ce26e7	bellard	#endif
854	2c0262af	bellard	if (s->aflag) {
855	2c0262af	bellard	if (s->addseg) {
856	2c0262af	bellard	gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
857	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
858	2c0262af	bellard	} else {
859	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
860	2c0262af	bellard	}
861	2c0262af	bellard	} else {
862	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
863	2c0262af	bellard	gen_op_andl_A0_ffff();
864	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
865	2c0262af	bellard	}
866	2c0262af	bellard	}
867	2c0262af	bellard
868	14ce26e7	bellard	static GenOpFunc *gen_op_movl_T0_Dshift[4] = {
869	2c0262af	bellard	gen_op_movl_T0_Dshiftb,
870	2c0262af	bellard	gen_op_movl_T0_Dshiftw,
871	2c0262af	bellard	gen_op_movl_T0_Dshiftl,
872	14ce26e7	bellard	X86_64_ONLY(gen_op_movl_T0_Dshiftq),
873	2c0262af	bellard	};
874	2c0262af	bellard
875	14ce26e7	bellard	static GenOpFunc1 *gen_op_jnz_ecx[3] = {
876	14ce26e7	bellard	gen_op_jnz_ecxw,
877	14ce26e7	bellard	gen_op_jnz_ecxl,
878	14ce26e7	bellard	X86_64_ONLY(gen_op_jnz_ecxq),
879	2c0262af	bellard	};
880	2c0262af	bellard
881	14ce26e7	bellard	static GenOpFunc1 *gen_op_jz_ecx[3] = {
882	14ce26e7	bellard	gen_op_jz_ecxw,
883	14ce26e7	bellard	gen_op_jz_ecxl,
884	14ce26e7	bellard	X86_64_ONLY(gen_op_jz_ecxq),
885	2c0262af	bellard	};
886	2c0262af	bellard
887	14ce26e7	bellard	static GenOpFunc *gen_op_dec_ECX[3] = {
888	2c0262af	bellard	gen_op_decw_ECX,
889	2c0262af	bellard	gen_op_decl_ECX,
890	14ce26e7	bellard	X86_64_ONLY(gen_op_decq_ECX),
891	2c0262af	bellard	};
892	2c0262af	bellard
893	14ce26e7	bellard	static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {
894	2c0262af	bellard	{
895	14ce26e7	bellard	gen_op_jnz_subb,
896	14ce26e7	bellard	gen_op_jnz_subw,
897	14ce26e7	bellard	gen_op_jnz_subl,
898	14ce26e7	bellard	X86_64_ONLY(gen_op_jnz_subq),
899	2c0262af	bellard	},
900	2c0262af	bellard	{
901	14ce26e7	bellard	gen_op_jz_subb,
902	14ce26e7	bellard	gen_op_jz_subw,
903	14ce26e7	bellard	gen_op_jz_subl,
904	14ce26e7	bellard	X86_64_ONLY(gen_op_jz_subq),
905	2c0262af	bellard	},
906	2c0262af	bellard	};
907	2c0262af	bellard
908	2c0262af	bellard	static GenOpFunc *gen_op_in_DX_T0[3] = {
909	2c0262af	bellard	gen_op_inb_DX_T0,
910	2c0262af	bellard	gen_op_inw_DX_T0,
911	2c0262af	bellard	gen_op_inl_DX_T0,
912	2c0262af	bellard	};
913	2c0262af	bellard
914	2c0262af	bellard	static GenOpFunc *gen_op_out_DX_T0[3] = {
915	2c0262af	bellard	gen_op_outb_DX_T0,
916	2c0262af	bellard	gen_op_outw_DX_T0,
917	2c0262af	bellard	gen_op_outl_DX_T0,
918	2c0262af	bellard	};
919	2c0262af	bellard
920	f115e911	bellard	static GenOpFunc *gen_op_in[3] = {
921	f115e911	bellard	gen_op_inb_T0_T1,
922	f115e911	bellard	gen_op_inw_T0_T1,
923	f115e911	bellard	gen_op_inl_T0_T1,
924	f115e911	bellard	};
925	f115e911	bellard
926	f115e911	bellard	static GenOpFunc *gen_op_out[3] = {
927	f115e911	bellard	gen_op_outb_T0_T1,
928	f115e911	bellard	gen_op_outw_T0_T1,
929	f115e911	bellard	gen_op_outl_T0_T1,
930	f115e911	bellard	};
931	f115e911	bellard
932	f115e911	bellard	static GenOpFunc *gen_check_io_T0[3] = {
933	f115e911	bellard	gen_op_check_iob_T0,
934	f115e911	bellard	gen_op_check_iow_T0,
935	f115e911	bellard	gen_op_check_iol_T0,
936	f115e911	bellard	};
937	f115e911	bellard
938	f115e911	bellard	static GenOpFunc *gen_check_io_DX[3] = {
939	f115e911	bellard	gen_op_check_iob_DX,
940	f115e911	bellard	gen_op_check_iow_DX,
941	f115e911	bellard	gen_op_check_iol_DX,
942	f115e911	bellard	};
943	f115e911	bellard
944	14ce26e7	bellard	static void gen_check_io(DisasContext *s, int ot, int use_dx, target_ulong cur_eip)
945	f115e911	bellard	{
946	f115e911	bellard	if (s->pe && (s->cpl > s->iopl \|\| s->vm86)) {
947	f115e911	bellard	if (s->cc_op != CC_OP_DYNAMIC)
948	f115e911	bellard	gen_op_set_cc_op(s->cc_op);
949	14ce26e7	bellard	gen_jmp_im(cur_eip);
950	f115e911	bellard	if (use_dx)
951	f115e911	bellard	gen_check_io_DX[ot]();
952	f115e911	bellard	else
953	f115e911	bellard	gen_check_io_T0[ot]();
954	f115e911	bellard	}
955	f115e911	bellard	}
956	f115e911	bellard
957	2c0262af	bellard	static inline void gen_movs(DisasContext *s, int ot)
958	2c0262af	bellard	{
959	2c0262af	bellard	gen_string_movl_A0_ESI(s);
960	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
961	2c0262af	bellard	gen_string_movl_A0_EDI(s);
962	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
963	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
964	14ce26e7	bellard	#ifdef TARGET_X86_64
965	14ce26e7	bellard	if (s->aflag == 2) {
966	14ce26e7	bellard	gen_op_addq_ESI_T0();
967	14ce26e7	bellard	gen_op_addq_EDI_T0();
968	14ce26e7	bellard	} else
969	14ce26e7	bellard	#endif
970	2c0262af	bellard	if (s->aflag) {
971	2c0262af	bellard	gen_op_addl_ESI_T0();
972	2c0262af	bellard	gen_op_addl_EDI_T0();
973	2c0262af	bellard	} else {
974	2c0262af	bellard	gen_op_addw_ESI_T0();
975	2c0262af	bellard	gen_op_addw_EDI_T0();
976	2c0262af	bellard	}
977	2c0262af	bellard	}
978	2c0262af	bellard
979	2c0262af	bellard	static inline void gen_update_cc_op(DisasContext *s)
980	2c0262af	bellard	{
981	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
982	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
983	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC;
984	2c0262af	bellard	}
985	2c0262af	bellard	}
986	2c0262af	bellard
987	14ce26e7	bellard	/* XXX: does not work with gdbstub "ice" single step - not a
988	14ce26e7	bellard	serious problem */
989	14ce26e7	bellard	static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
990	2c0262af	bellard	{
991	14ce26e7	bellard	int l1, l2;
992	14ce26e7	bellard
993	14ce26e7	bellard	l1 = gen_new_label();
994	14ce26e7	bellard	l2 = gen_new_label();
995	14ce26e7	bellard	gen_op_jnz_ecx[s->aflag](l1);
996	14ce26e7	bellard	gen_set_label(l2);
997	14ce26e7	bellard	gen_jmp_tb(s, next_eip, 1);
998	14ce26e7	bellard	gen_set_label(l1);
999	14ce26e7	bellard	return l2;
1000	2c0262af	bellard	}
1001	2c0262af	bellard
1002	2c0262af	bellard	static inline void gen_stos(DisasContext *s, int ot)
1003	2c0262af	bellard	{
1004	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1005	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1006	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1007	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1008	14ce26e7	bellard	#ifdef TARGET_X86_64
1009	14ce26e7	bellard	if (s->aflag == 2) {
1010	14ce26e7	bellard	gen_op_addq_EDI_T0();
1011	14ce26e7	bellard	} else
1012	14ce26e7	bellard	#endif
1013	2c0262af	bellard	if (s->aflag) {
1014	2c0262af	bellard	gen_op_addl_EDI_T0();
1015	2c0262af	bellard	} else {
1016	2c0262af	bellard	gen_op_addw_EDI_T0();
1017	2c0262af	bellard	}
1018	2c0262af	bellard	}
1019	2c0262af	bellard
1020	2c0262af	bellard	static inline void gen_lods(DisasContext *s, int ot)
1021	2c0262af	bellard	{
1022	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1023	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1024	2c0262af	bellard	gen_op_mov_reg_T0[ot][R_EAX]();
1025	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1026	14ce26e7	bellard	#ifdef TARGET_X86_64
1027	14ce26e7	bellard	if (s->aflag == 2) {
1028	14ce26e7	bellard	gen_op_addq_ESI_T0();
1029	14ce26e7	bellard	} else
1030	14ce26e7	bellard	#endif
1031	2c0262af	bellard	if (s->aflag) {
1032	2c0262af	bellard	gen_op_addl_ESI_T0();
1033	2c0262af	bellard	} else {
1034	2c0262af	bellard	gen_op_addw_ESI_T0();
1035	2c0262af	bellard	}
1036	2c0262af	bellard	}
1037	2c0262af	bellard
1038	2c0262af	bellard	static inline void gen_scas(DisasContext *s, int ot)
1039	2c0262af	bellard	{
1040	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1041	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1042	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
1043	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1044	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1045	14ce26e7	bellard	#ifdef TARGET_X86_64
1046	14ce26e7	bellard	if (s->aflag == 2) {
1047	14ce26e7	bellard	gen_op_addq_EDI_T0();
1048	14ce26e7	bellard	} else
1049	14ce26e7	bellard	#endif
1050	2c0262af	bellard	if (s->aflag) {
1051	2c0262af	bellard	gen_op_addl_EDI_T0();
1052	2c0262af	bellard	} else {
1053	2c0262af	bellard	gen_op_addw_EDI_T0();
1054	2c0262af	bellard	}
1055	2c0262af	bellard	}
1056	2c0262af	bellard
1057	2c0262af	bellard	static inline void gen_cmps(DisasContext *s, int ot)
1058	2c0262af	bellard	{
1059	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1060	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1061	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1062	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
1063	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1064	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1065	14ce26e7	bellard	#ifdef TARGET_X86_64
1066	14ce26e7	bellard	if (s->aflag == 2) {
1067	14ce26e7	bellard	gen_op_addq_ESI_T0();
1068	14ce26e7	bellard	gen_op_addq_EDI_T0();
1069	14ce26e7	bellard	} else
1070	14ce26e7	bellard	#endif
1071	2c0262af	bellard	if (s->aflag) {
1072	2c0262af	bellard	gen_op_addl_ESI_T0();
1073	2c0262af	bellard	gen_op_addl_EDI_T0();
1074	2c0262af	bellard	} else {
1075	2c0262af	bellard	gen_op_addw_ESI_T0();
1076	2c0262af	bellard	gen_op_addw_EDI_T0();
1077	2c0262af	bellard	}
1078	2c0262af	bellard	}
1079	2c0262af	bellard
1080	2c0262af	bellard	static inline void gen_ins(DisasContext *s, int ot)
1081	2c0262af	bellard	{
1082	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1083	9772c73b	bellard	gen_op_movl_T0_0();
1084	9772c73b	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1085	9772c73b	bellard	gen_op_in_DX_T0[ot]();
1086	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1087	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1088	14ce26e7	bellard	#ifdef TARGET_X86_64
1089	14ce26e7	bellard	if (s->aflag == 2) {
1090	14ce26e7	bellard	gen_op_addq_EDI_T0();
1091	14ce26e7	bellard	} else
1092	14ce26e7	bellard	#endif
1093	2c0262af	bellard	if (s->aflag) {
1094	2c0262af	bellard	gen_op_addl_EDI_T0();
1095	2c0262af	bellard	} else {
1096	2c0262af	bellard	gen_op_addw_EDI_T0();
1097	2c0262af	bellard	}
1098	2c0262af	bellard	}
1099	2c0262af	bellard
1100	2c0262af	bellard	static inline void gen_outs(DisasContext *s, int ot)
1101	2c0262af	bellard	{
1102	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1103	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1104	2c0262af	bellard	gen_op_out_DX_T0[ot]();
1105	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1106	14ce26e7	bellard	#ifdef TARGET_X86_64
1107	14ce26e7	bellard	if (s->aflag == 2) {
1108	14ce26e7	bellard	gen_op_addq_ESI_T0();
1109	14ce26e7	bellard	} else
1110	14ce26e7	bellard	#endif
1111	2c0262af	bellard	if (s->aflag) {
1112	2c0262af	bellard	gen_op_addl_ESI_T0();
1113	2c0262af	bellard	} else {
1114	2c0262af	bellard	gen_op_addw_ESI_T0();
1115	2c0262af	bellard	}
1116	2c0262af	bellard	}
1117	2c0262af	bellard
1118	2c0262af	bellard	/* same method as Valgrind : we generate jumps to current or next
1119	2c0262af	bellard	instruction */
1120	2c0262af	bellard	#define GEN_REPZ(op) \
1121	2c0262af	bellard	static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1122	14ce26e7	bellard	target_ulong cur_eip, target_ulong next_eip) \
1123	2c0262af	bellard	{ \
1124	14ce26e7	bellard	int l2;\
1125	2c0262af	bellard	gen_update_cc_op(s); \
1126	14ce26e7	bellard	l2 = gen_jz_ecx_string(s, next_eip); \
1127	2c0262af	bellard	gen_ ## op(s, ot); \
1128	2c0262af	bellard	gen_op_dec_ECX[s->aflag](); \
1129	2c0262af	bellard	/* a loop would cause two single step exceptions if ECX = 1 \
1130	2c0262af	bellard	before rep string_insn */ \
1131	2c0262af	bellard	if (!s->jmp_opt) \
1132	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l2); \
1133	2c0262af	bellard	gen_jmp(s, cur_eip); \
1134	2c0262af	bellard	}
1135	2c0262af	bellard
1136	2c0262af	bellard	#define GEN_REPZ2(op) \
1137	2c0262af	bellard	static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1138	14ce26e7	bellard	target_ulong cur_eip, \
1139	14ce26e7	bellard	target_ulong next_eip, \
1140	2c0262af	bellard	int nz) \
1141	2c0262af	bellard	{ \
1142	14ce26e7	bellard	int l2;\
1143	2c0262af	bellard	gen_update_cc_op(s); \
1144	14ce26e7	bellard	l2 = gen_jz_ecx_string(s, next_eip); \
1145	2c0262af	bellard	gen_ ## op(s, ot); \
1146	2c0262af	bellard	gen_op_dec_ECX[s->aflag](); \
1147	2c0262af	bellard	gen_op_set_cc_op(CC_OP_SUBB + ot); \
1148	14ce26e7	bellard	gen_op_string_jnz_sub[nz][ot](l2);\
1149	2c0262af	bellard	if (!s->jmp_opt) \
1150	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l2); \
1151	2c0262af	bellard	gen_jmp(s, cur_eip); \
1152	2c0262af	bellard	}
1153	2c0262af	bellard
1154	2c0262af	bellard	GEN_REPZ(movs)
1155	2c0262af	bellard	GEN_REPZ(stos)
1156	2c0262af	bellard	GEN_REPZ(lods)
1157	2c0262af	bellard	GEN_REPZ(ins)
1158	2c0262af	bellard	GEN_REPZ(outs)
1159	2c0262af	bellard	GEN_REPZ2(scas)
1160	2c0262af	bellard	GEN_REPZ2(cmps)
1161	2c0262af	bellard
1162	2c0262af	bellard	enum {
1163	2c0262af	bellard	JCC_O,
1164	2c0262af	bellard	JCC_B,
1165	2c0262af	bellard	JCC_Z,
1166	2c0262af	bellard	JCC_BE,
1167	2c0262af	bellard	JCC_S,
1168	2c0262af	bellard	JCC_P,
1169	2c0262af	bellard	JCC_L,
1170	2c0262af	bellard	JCC_LE,
1171	2c0262af	bellard	};
1172	2c0262af	bellard
1173	14ce26e7	bellard	static GenOpFunc1 *gen_jcc_sub[4][8] = {
1174	2c0262af	bellard	[OT_BYTE] = {
1175	2c0262af	bellard	NULL,
1176	2c0262af	bellard	gen_op_jb_subb,
1177	2c0262af	bellard	gen_op_jz_subb,
1178	2c0262af	bellard	gen_op_jbe_subb,
1179	2c0262af	bellard	gen_op_js_subb,
1180	2c0262af	bellard	NULL,
1181	2c0262af	bellard	gen_op_jl_subb,
1182	2c0262af	bellard	gen_op_jle_subb,
1183	2c0262af	bellard	},
1184	2c0262af	bellard	[OT_WORD] = {
1185	2c0262af	bellard	NULL,
1186	2c0262af	bellard	gen_op_jb_subw,
1187	2c0262af	bellard	gen_op_jz_subw,
1188	2c0262af	bellard	gen_op_jbe_subw,
1189	2c0262af	bellard	gen_op_js_subw,
1190	2c0262af	bellard	NULL,
1191	2c0262af	bellard	gen_op_jl_subw,
1192	2c0262af	bellard	gen_op_jle_subw,
1193	2c0262af	bellard	},
1194	2c0262af	bellard	[OT_LONG] = {
1195	2c0262af	bellard	NULL,
1196	2c0262af	bellard	gen_op_jb_subl,
1197	2c0262af	bellard	gen_op_jz_subl,
1198	2c0262af	bellard	gen_op_jbe_subl,
1199	2c0262af	bellard	gen_op_js_subl,
1200	2c0262af	bellard	NULL,
1201	2c0262af	bellard	gen_op_jl_subl,
1202	2c0262af	bellard	gen_op_jle_subl,
1203	2c0262af	bellard	},
1204	14ce26e7	bellard	#ifdef TARGET_X86_64
1205	14ce26e7	bellard	[OT_QUAD] = {
1206	14ce26e7	bellard	NULL,
1207	14ce26e7	bellard	BUGGY_64(gen_op_jb_subq),
1208	14ce26e7	bellard	gen_op_jz_subq,
1209	14ce26e7	bellard	BUGGY_64(gen_op_jbe_subq),
1210	14ce26e7	bellard	gen_op_js_subq,
1211	14ce26e7	bellard	NULL,
1212	14ce26e7	bellard	BUGGY_64(gen_op_jl_subq),
1213	14ce26e7	bellard	BUGGY_64(gen_op_jle_subq),
1214	14ce26e7	bellard	},
1215	14ce26e7	bellard	#endif
1216	2c0262af	bellard	};
1217	14ce26e7	bellard	static GenOpFunc1 *gen_op_loop[3][4] = {
1218	2c0262af	bellard	[0] = {
1219	2c0262af	bellard	gen_op_loopnzw,
1220	2c0262af	bellard	gen_op_loopzw,
1221	14ce26e7	bellard	gen_op_jnz_ecxw,
1222	2c0262af	bellard	},
1223	2c0262af	bellard	[1] = {
1224	2c0262af	bellard	gen_op_loopnzl,
1225	2c0262af	bellard	gen_op_loopzl,
1226	14ce26e7	bellard	gen_op_jnz_ecxl,
1227	14ce26e7	bellard	},
1228	14ce26e7	bellard	#ifdef TARGET_X86_64
1229	14ce26e7	bellard	[2] = {
1230	14ce26e7	bellard	gen_op_loopnzq,
1231	14ce26e7	bellard	gen_op_loopzq,
1232	14ce26e7	bellard	gen_op_jnz_ecxq,
1233	2c0262af	bellard	},
1234	14ce26e7	bellard	#endif
1235	2c0262af	bellard	};
1236	2c0262af	bellard
1237	2c0262af	bellard	static GenOpFunc *gen_setcc_slow[8] = {
1238	2c0262af	bellard	gen_op_seto_T0_cc,
1239	2c0262af	bellard	gen_op_setb_T0_cc,
1240	2c0262af	bellard	gen_op_setz_T0_cc,
1241	2c0262af	bellard	gen_op_setbe_T0_cc,
1242	2c0262af	bellard	gen_op_sets_T0_cc,
1243	2c0262af	bellard	gen_op_setp_T0_cc,
1244	2c0262af	bellard	gen_op_setl_T0_cc,
1245	2c0262af	bellard	gen_op_setle_T0_cc,
1246	2c0262af	bellard	};
1247	2c0262af	bellard
1248	14ce26e7	bellard	static GenOpFunc *gen_setcc_sub[4][8] = {
1249	2c0262af	bellard	[OT_BYTE] = {
1250	2c0262af	bellard	NULL,
1251	2c0262af	bellard	gen_op_setb_T0_subb,
1252	2c0262af	bellard	gen_op_setz_T0_subb,
1253	2c0262af	bellard	gen_op_setbe_T0_subb,
1254	2c0262af	bellard	gen_op_sets_T0_subb,
1255	2c0262af	bellard	NULL,
1256	2c0262af	bellard	gen_op_setl_T0_subb,
1257	2c0262af	bellard	gen_op_setle_T0_subb,
1258	2c0262af	bellard	},
1259	2c0262af	bellard	[OT_WORD] = {
1260	2c0262af	bellard	NULL,
1261	2c0262af	bellard	gen_op_setb_T0_subw,
1262	2c0262af	bellard	gen_op_setz_T0_subw,
1263	2c0262af	bellard	gen_op_setbe_T0_subw,
1264	2c0262af	bellard	gen_op_sets_T0_subw,
1265	2c0262af	bellard	NULL,
1266	2c0262af	bellard	gen_op_setl_T0_subw,
1267	2c0262af	bellard	gen_op_setle_T0_subw,
1268	2c0262af	bellard	},
1269	2c0262af	bellard	[OT_LONG] = {
1270	2c0262af	bellard	NULL,
1271	2c0262af	bellard	gen_op_setb_T0_subl,
1272	2c0262af	bellard	gen_op_setz_T0_subl,
1273	2c0262af	bellard	gen_op_setbe_T0_subl,
1274	2c0262af	bellard	gen_op_sets_T0_subl,
1275	2c0262af	bellard	NULL,
1276	2c0262af	bellard	gen_op_setl_T0_subl,
1277	2c0262af	bellard	gen_op_setle_T0_subl,
1278	2c0262af	bellard	},
1279	14ce26e7	bellard	#ifdef TARGET_X86_64
1280	14ce26e7	bellard	[OT_QUAD] = {
1281	14ce26e7	bellard	NULL,
1282	14ce26e7	bellard	gen_op_setb_T0_subq,
1283	14ce26e7	bellard	gen_op_setz_T0_subq,
1284	14ce26e7	bellard	gen_op_setbe_T0_subq,
1285	14ce26e7	bellard	gen_op_sets_T0_subq,
1286	14ce26e7	bellard	NULL,
1287	14ce26e7	bellard	gen_op_setl_T0_subq,
1288	14ce26e7	bellard	gen_op_setle_T0_subq,
1289	14ce26e7	bellard	},
1290	14ce26e7	bellard	#endif
1291	2c0262af	bellard	};
1292	2c0262af	bellard
1293	2c0262af	bellard	static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1294	2c0262af	bellard	gen_op_fadd_ST0_FT0,
1295	2c0262af	bellard	gen_op_fmul_ST0_FT0,
1296	2c0262af	bellard	gen_op_fcom_ST0_FT0,
1297	2c0262af	bellard	gen_op_fcom_ST0_FT0,
1298	2c0262af	bellard	gen_op_fsub_ST0_FT0,
1299	2c0262af	bellard	gen_op_fsubr_ST0_FT0,
1300	2c0262af	bellard	gen_op_fdiv_ST0_FT0,
1301	2c0262af	bellard	gen_op_fdivr_ST0_FT0,
1302	2c0262af	bellard	};
1303	2c0262af	bellard
1304	2c0262af	bellard	/* NOTE the exception in "r" op ordering */
1305	2c0262af	bellard	static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1306	2c0262af	bellard	gen_op_fadd_STN_ST0,
1307	2c0262af	bellard	gen_op_fmul_STN_ST0,
1308	2c0262af	bellard	NULL,
1309	2c0262af	bellard	NULL,
1310	2c0262af	bellard	gen_op_fsubr_STN_ST0,
1311	2c0262af	bellard	gen_op_fsub_STN_ST0,
1312	2c0262af	bellard	gen_op_fdivr_STN_ST0,
1313	2c0262af	bellard	gen_op_fdiv_STN_ST0,
1314	2c0262af	bellard	};
1315	2c0262af	bellard
1316	2c0262af	bellard	/* if d == OR_TMP0, it means memory operand (address in A0) */
1317	2c0262af	bellard	static void gen_op(DisasContext *s1, int op, int ot, int d)
1318	2c0262af	bellard	{
1319	2c0262af	bellard	GenOpFunc *gen_update_cc;
1320	2c0262af	bellard
1321	2c0262af	bellard	if (d != OR_TMP0) {
1322	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1323	2c0262af	bellard	} else {
1324	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1325	2c0262af	bellard	}
1326	2c0262af	bellard	switch(op) {
1327	2c0262af	bellard	case OP_ADCL:
1328	2c0262af	bellard	case OP_SBBL:
1329	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1330	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1331	2c0262af	bellard	if (d != OR_TMP0) {
1332	2c0262af	bellard	gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1333	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1334	2c0262af	bellard	} else {
1335	4f31916f	bellard	gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1336	2c0262af	bellard	}
1337	2c0262af	bellard	s1->cc_op = CC_OP_DYNAMIC;
1338	2c0262af	bellard	goto the_end;
1339	2c0262af	bellard	case OP_ADDL:
1340	2c0262af	bellard	gen_op_addl_T0_T1();
1341	2c0262af	bellard	s1->cc_op = CC_OP_ADDB + ot;
1342	2c0262af	bellard	gen_update_cc = gen_op_update2_cc;
1343	2c0262af	bellard	break;
1344	2c0262af	bellard	case OP_SUBL:
1345	2c0262af	bellard	gen_op_subl_T0_T1();
1346	2c0262af	bellard	s1->cc_op = CC_OP_SUBB + ot;
1347	2c0262af	bellard	gen_update_cc = gen_op_update2_cc;
1348	2c0262af	bellard	break;
1349	2c0262af	bellard	default:
1350	2c0262af	bellard	case OP_ANDL:
1351	2c0262af	bellard	case OP_ORL:
1352	2c0262af	bellard	case OP_XORL:
1353	2c0262af	bellard	gen_op_arith_T0_T1_cc[op]();
1354	2c0262af	bellard	s1->cc_op = CC_OP_LOGICB + ot;
1355	2c0262af	bellard	gen_update_cc = gen_op_update1_cc;
1356	2c0262af	bellard	break;
1357	2c0262af	bellard	case OP_CMPL:
1358	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1359	2c0262af	bellard	s1->cc_op = CC_OP_SUBB + ot;
1360	2c0262af	bellard	gen_update_cc = NULL;
1361	2c0262af	bellard	break;
1362	2c0262af	bellard	}
1363	2c0262af	bellard	if (op != OP_CMPL) {
1364	2c0262af	bellard	if (d != OR_TMP0)
1365	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1366	2c0262af	bellard	else
1367	2c0262af	bellard	gen_op_st_T0_A0[ot + s1->mem_index]();
1368	2c0262af	bellard	}
1369	2c0262af	bellard	/* the flags update must happen after the memory write (precise
1370	2c0262af	bellard	exception support) */
1371	2c0262af	bellard	if (gen_update_cc)
1372	2c0262af	bellard	gen_update_cc();
1373	2c0262af	bellard	the_end: ;
1374	2c0262af	bellard	}
1375	2c0262af	bellard
1376	2c0262af	bellard	/* if d == OR_TMP0, it means memory operand (address in A0) */
1377	2c0262af	bellard	static void gen_inc(DisasContext *s1, int ot, int d, int c)
1378	2c0262af	bellard	{
1379	2c0262af	bellard	if (d != OR_TMP0)
1380	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1381	2c0262af	bellard	else
1382	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1383	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1384	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1385	2c0262af	bellard	if (c > 0) {
1386	2c0262af	bellard	gen_op_incl_T0();
1387	2c0262af	bellard	s1->cc_op = CC_OP_INCB + ot;
1388	2c0262af	bellard	} else {
1389	2c0262af	bellard	gen_op_decl_T0();
1390	2c0262af	bellard	s1->cc_op = CC_OP_DECB + ot;
1391	2c0262af	bellard	}
1392	2c0262af	bellard	if (d != OR_TMP0)
1393	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1394	2c0262af	bellard	else
1395	2c0262af	bellard	gen_op_st_T0_A0[ot + s1->mem_index]();
1396	2c0262af	bellard	gen_op_update_inc_cc();
1397	2c0262af	bellard	}
1398	2c0262af	bellard
1399	2c0262af	bellard	static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1400	2c0262af	bellard	{
1401	2c0262af	bellard	if (d != OR_TMP0)
1402	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1403	2c0262af	bellard	else
1404	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1405	2c0262af	bellard	if (s != OR_TMP1)
1406	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][s]();
1407	2c0262af	bellard	/* for zero counts, flags are not updated, so must do it dynamically */
1408	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1409	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1410	2c0262af	bellard
1411	2c0262af	bellard	if (d != OR_TMP0)
1412	2c0262af	bellard	gen_op_shift_T0_T1_cc[ot][op]();
1413	2c0262af	bellard	else
1414	4f31916f	bellard	gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1415	2c0262af	bellard	if (d != OR_TMP0)
1416	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1417	2c0262af	bellard	s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1418	2c0262af	bellard	}
1419	2c0262af	bellard
1420	2c0262af	bellard	static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1421	2c0262af	bellard	{
1422	2c0262af	bellard	/* currently not optimized */
1423	2c0262af	bellard	gen_op_movl_T1_im(c);
1424	2c0262af	bellard	gen_shift(s1, op, ot, d, OR_TMP1);
1425	2c0262af	bellard	}
1426	2c0262af	bellard
1427	2c0262af	bellard	static void gen_lea_modrm(DisasContext s, int modrm, int reg_ptr, int *offset_ptr)
1428	2c0262af	bellard	{
1429	14ce26e7	bellard	target_long disp;
1430	2c0262af	bellard	int havesib;
1431	14ce26e7	bellard	int base;
1432	2c0262af	bellard	int index;
1433	2c0262af	bellard	int scale;
1434	2c0262af	bellard	int opreg;
1435	2c0262af	bellard	int mod, rm, code, override, must_add_seg;
1436	2c0262af	bellard
1437	2c0262af	bellard	override = s->override;
1438	2c0262af	bellard	must_add_seg = s->addseg;
1439	2c0262af	bellard	if (override >= 0)
1440	2c0262af	bellard	must_add_seg = 1;
1441	2c0262af	bellard	mod = (modrm >> 6) & 3;
1442	2c0262af	bellard	rm = modrm & 7;
1443	2c0262af	bellard
1444	2c0262af	bellard	if (s->aflag) {
1445	2c0262af	bellard
1446	2c0262af	bellard	havesib = 0;
1447	2c0262af	bellard	base = rm;
1448	2c0262af	bellard	index = 0;
1449	2c0262af	bellard	scale = 0;
1450	2c0262af	bellard
1451	2c0262af	bellard	if (base == 4) {
1452	2c0262af	bellard	havesib = 1;
1453	61382a50	bellard	code = ldub_code(s->pc++);
1454	2c0262af	bellard	scale = (code >> 6) & 3;
1455	14ce26e7	bellard	index = ((code >> 3) & 7) \| REX_X(s);
1456	14ce26e7	bellard	base = (code & 7);
1457	2c0262af	bellard	}
1458	14ce26e7	bellard	base \|= REX_B(s);
1459	2c0262af	bellard
1460	2c0262af	bellard	switch (mod) {
1461	2c0262af	bellard	case 0:
1462	14ce26e7	bellard	if ((base & 7) == 5) {
1463	2c0262af	bellard	base = -1;
1464	14ce26e7	bellard	disp = (int32_t)ldl_code(s->pc);
1465	2c0262af	bellard	s->pc += 4;
1466	14ce26e7	bellard	if (CODE64(s) && !havesib) {
1467	14ce26e7	bellard	disp += s->pc + s->rip_offset;
1468	14ce26e7	bellard	}
1469	2c0262af	bellard	} else {
1470	2c0262af	bellard	disp = 0;
1471	2c0262af	bellard	}
1472	2c0262af	bellard	break;
1473	2c0262af	bellard	case 1:
1474	61382a50	bellard	disp = (int8_t)ldub_code(s->pc++);
1475	2c0262af	bellard	break;
1476	2c0262af	bellard	default:
1477	2c0262af	bellard	case 2:
1478	61382a50	bellard	disp = ldl_code(s->pc);
1479	2c0262af	bellard	s->pc += 4;
1480	2c0262af	bellard	break;
1481	2c0262af	bellard	}
1482	2c0262af	bellard
1483	2c0262af	bellard	if (base >= 0) {
1484	2c0262af	bellard	/* for correct popl handling with esp */
1485	2c0262af	bellard	if (base == 4 && s->popl_esp_hack)
1486	2c0262af	bellard	disp += s->popl_esp_hack;
1487	14ce26e7	bellard	#ifdef TARGET_X86_64
1488	14ce26e7	bellard	if (s->aflag == 2) {
1489	14ce26e7	bellard	gen_op_movq_A0_reg[base]();
1490	14ce26e7	bellard	if (disp != 0) {
1491	14ce26e7	bellard	if ((int32_t)disp == disp)
1492	14ce26e7	bellard	gen_op_addq_A0_im(disp);
1493	14ce26e7	bellard	else
1494	14ce26e7	bellard	gen_op_addq_A0_im64(disp >> 32, disp);
1495	14ce26e7	bellard	}
1496	14ce26e7	bellard	} else
1497	14ce26e7	bellard	#endif
1498	14ce26e7	bellard	{
1499	14ce26e7	bellard	gen_op_movl_A0_reg[base]();
1500	14ce26e7	bellard	if (disp != 0)
1501	14ce26e7	bellard	gen_op_addl_A0_im(disp);
1502	14ce26e7	bellard	}
1503	2c0262af	bellard	} else {
1504	14ce26e7	bellard	#ifdef TARGET_X86_64
1505	14ce26e7	bellard	if (s->aflag == 2) {
1506	14ce26e7	bellard	if ((int32_t)disp == disp)
1507	14ce26e7	bellard	gen_op_movq_A0_im(disp);
1508	14ce26e7	bellard	else
1509	14ce26e7	bellard	gen_op_movq_A0_im64(disp >> 32, disp);
1510	14ce26e7	bellard	} else
1511	14ce26e7	bellard	#endif
1512	14ce26e7	bellard	{
1513	14ce26e7	bellard	gen_op_movl_A0_im(disp);
1514	14ce26e7	bellard	}
1515	2c0262af	bellard	}
1516	2c0262af	bellard	/* XXX: index == 4 is always invalid */
1517	2c0262af	bellard	if (havesib && (index != 4 \|\| scale != 0)) {
1518	14ce26e7	bellard	#ifdef TARGET_X86_64
1519	14ce26e7	bellard	if (s->aflag == 2) {
1520	14ce26e7	bellard	gen_op_addq_A0_reg_sN[scale][index]();
1521	14ce26e7	bellard	} else
1522	14ce26e7	bellard	#endif
1523	14ce26e7	bellard	{
1524	14ce26e7	bellard	gen_op_addl_A0_reg_sN[scale][index]();
1525	14ce26e7	bellard	}
1526	2c0262af	bellard	}
1527	2c0262af	bellard	if (must_add_seg) {
1528	2c0262af	bellard	if (override < 0) {
1529	2c0262af	bellard	if (base == R_EBP \|\| base == R_ESP)
1530	2c0262af	bellard	override = R_SS;
1531	2c0262af	bellard	else
1532	2c0262af	bellard	override = R_DS;
1533	2c0262af	bellard	}
1534	14ce26e7	bellard	#ifdef TARGET_X86_64
1535	14ce26e7	bellard	if (s->aflag == 2) {
1536	14ce26e7	bellard	gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1537	14ce26e7	bellard	} else
1538	14ce26e7	bellard	#endif
1539	14ce26e7	bellard	{
1540	14ce26e7	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1541	14ce26e7	bellard	}
1542	2c0262af	bellard	}
1543	2c0262af	bellard	} else {
1544	2c0262af	bellard	switch (mod) {
1545	2c0262af	bellard	case 0:
1546	2c0262af	bellard	if (rm == 6) {
1547	61382a50	bellard	disp = lduw_code(s->pc);
1548	2c0262af	bellard	s->pc += 2;
1549	2c0262af	bellard	gen_op_movl_A0_im(disp);
1550	2c0262af	bellard	rm = 0; /* avoid SS override */
1551	2c0262af	bellard	goto no_rm;
1552	2c0262af	bellard	} else {
1553	2c0262af	bellard	disp = 0;
1554	2c0262af	bellard	}
1555	2c0262af	bellard	break;
1556	2c0262af	bellard	case 1:
1557	61382a50	bellard	disp = (int8_t)ldub_code(s->pc++);
1558	2c0262af	bellard	break;
1559	2c0262af	bellard	default:
1560	2c0262af	bellard	case 2:
1561	61382a50	bellard	disp = lduw_code(s->pc);
1562	2c0262af	bellard	s->pc += 2;
1563	2c0262af	bellard	break;
1564	2c0262af	bellard	}
1565	2c0262af	bellard	switch(rm) {
1566	2c0262af	bellard	case 0:
1567	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1568	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
1569	2c0262af	bellard	break;
1570	2c0262af	bellard	case 1:
1571	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1572	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
1573	2c0262af	bellard	break;
1574	2c0262af	bellard	case 2:
1575	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1576	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
1577	2c0262af	bellard	break;
1578	2c0262af	bellard	case 3:
1579	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1580	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
1581	2c0262af	bellard	break;
1582	2c0262af	bellard	case 4:
1583	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
1584	2c0262af	bellard	break;
1585	2c0262af	bellard	case 5:
1586	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
1587	2c0262af	bellard	break;
1588	2c0262af	bellard	case 6:
1589	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1590	2c0262af	bellard	break;
1591	2c0262af	bellard	default:
1592	2c0262af	bellard	case 7:
1593	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1594	2c0262af	bellard	break;
1595	2c0262af	bellard	}
1596	2c0262af	bellard	if (disp != 0)
1597	2c0262af	bellard	gen_op_addl_A0_im(disp);
1598	2c0262af	bellard	gen_op_andl_A0_ffff();
1599	2c0262af	bellard	no_rm:
1600	2c0262af	bellard	if (must_add_seg) {
1601	2c0262af	bellard	if (override < 0) {
1602	2c0262af	bellard	if (rm == 2 \|\| rm == 3 \|\| rm == 6)
1603	2c0262af	bellard	override = R_SS;
1604	2c0262af	bellard	else
1605	2c0262af	bellard	override = R_DS;
1606	2c0262af	bellard	}
1607	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1608	2c0262af	bellard	}
1609	2c0262af	bellard	}
1610	2c0262af	bellard
1611	2c0262af	bellard	opreg = OR_A0;
1612	2c0262af	bellard	disp = 0;
1613	2c0262af	bellard	*reg_ptr = opreg;
1614	2c0262af	bellard	*offset_ptr = disp;
1615	2c0262af	bellard	}
1616	2c0262af	bellard
1617	664e0f19	bellard	/* used for LEA and MOV AX, mem */
1618	664e0f19	bellard	static void gen_add_A0_ds_seg(DisasContext *s)
1619	664e0f19	bellard	{
1620	664e0f19	bellard	int override, must_add_seg;
1621	664e0f19	bellard	must_add_seg = s->addseg;
1622	664e0f19	bellard	override = R_DS;
1623	664e0f19	bellard	if (s->override >= 0) {
1624	664e0f19	bellard	override = s->override;
1625	664e0f19	bellard	must_add_seg = 1;
1626	664e0f19	bellard	} else {
1627	664e0f19	bellard	override = R_DS;
1628	664e0f19	bellard	}
1629	664e0f19	bellard	if (must_add_seg) {
1630	8f091a59	bellard	#ifdef TARGET_X86_64
1631	8f091a59	bellard	if (CODE64(s)) {
1632	8f091a59	bellard	gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1633	8f091a59	bellard	} else
1634	8f091a59	bellard	#endif
1635	8f091a59	bellard	{
1636	8f091a59	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1637	8f091a59	bellard	}
1638	664e0f19	bellard	}
1639	664e0f19	bellard	}
1640	664e0f19	bellard
1641	2c0262af	bellard	/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1642	2c0262af	bellard	OR_TMP0 */
1643	2c0262af	bellard	static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1644	2c0262af	bellard	{
1645	2c0262af	bellard	int mod, rm, opreg, disp;
1646	2c0262af	bellard
1647	2c0262af	bellard	mod = (modrm >> 6) & 3;
1648	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
1649	2c0262af	bellard	if (mod == 3) {
1650	2c0262af	bellard	if (is_store) {
1651	2c0262af	bellard	if (reg != OR_TMP0)
1652	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
1653	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
1654	2c0262af	bellard	} else {
1655	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
1656	2c0262af	bellard	if (reg != OR_TMP0)
1657	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
1658	2c0262af	bellard	}
1659	2c0262af	bellard	} else {
1660	2c0262af	bellard	gen_lea_modrm(s, modrm, &opreg, &disp);
1661	2c0262af	bellard	if (is_store) {
1662	2c0262af	bellard	if (reg != OR_TMP0)
1663	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
1664	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1665	2c0262af	bellard	} else {
1666	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1667	2c0262af	bellard	if (reg != OR_TMP0)
1668	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
1669	2c0262af	bellard	}
1670	2c0262af	bellard	}
1671	2c0262af	bellard	}
1672	2c0262af	bellard
1673	2c0262af	bellard	static inline uint32_t insn_get(DisasContext *s, int ot)
1674	2c0262af	bellard	{
1675	2c0262af	bellard	uint32_t ret;
1676	2c0262af	bellard
1677	2c0262af	bellard	switch(ot) {
1678	2c0262af	bellard	case OT_BYTE:
1679	61382a50	bellard	ret = ldub_code(s->pc);
1680	2c0262af	bellard	s->pc++;
1681	2c0262af	bellard	break;
1682	2c0262af	bellard	case OT_WORD:
1683	61382a50	bellard	ret = lduw_code(s->pc);
1684	2c0262af	bellard	s->pc += 2;
1685	2c0262af	bellard	break;
1686	2c0262af	bellard	default:
1687	2c0262af	bellard	case OT_LONG:
1688	61382a50	bellard	ret = ldl_code(s->pc);
1689	2c0262af	bellard	s->pc += 4;
1690	2c0262af	bellard	break;
1691	2c0262af	bellard	}
1692	2c0262af	bellard	return ret;
1693	2c0262af	bellard	}
1694	2c0262af	bellard
1695	14ce26e7	bellard	static inline int insn_const_size(unsigned int ot)
1696	14ce26e7	bellard	{
1697	14ce26e7	bellard	if (ot <= OT_LONG)
1698	14ce26e7	bellard	return 1 << ot;
1699	14ce26e7	bellard	else
1700	14ce26e7	bellard	return 4;
1701	14ce26e7	bellard	}
1702	14ce26e7	bellard
1703	14ce26e7	bellard	static inline void gen_jcc(DisasContext *s, int b,
1704	14ce26e7	bellard	target_ulong val, target_ulong next_eip)
1705	2c0262af	bellard	{
1706	2c0262af	bellard	TranslationBlock *tb;
1707	2c0262af	bellard	int inv, jcc_op;
1708	14ce26e7	bellard	GenOpFunc1 *func;
1709	14ce26e7	bellard	target_ulong tmp;
1710	14ce26e7	bellard	int l1, l2;
1711	2c0262af	bellard
1712	2c0262af	bellard	inv = b & 1;
1713	2c0262af	bellard	jcc_op = (b >> 1) & 7;
1714	2c0262af	bellard
1715	2c0262af	bellard	if (s->jmp_opt) {
1716	2c0262af	bellard	switch(s->cc_op) {
1717	2c0262af	bellard	/* we optimize the cmp/jcc case */
1718	2c0262af	bellard	case CC_OP_SUBB:
1719	2c0262af	bellard	case CC_OP_SUBW:
1720	2c0262af	bellard	case CC_OP_SUBL:
1721	14ce26e7	bellard	case CC_OP_SUBQ:
1722	2c0262af	bellard	func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1723	2c0262af	bellard	break;
1724	2c0262af	bellard
1725	2c0262af	bellard	/* some jumps are easy to compute */
1726	2c0262af	bellard	case CC_OP_ADDB:
1727	2c0262af	bellard	case CC_OP_ADDW:
1728	2c0262af	bellard	case CC_OP_ADDL:
1729	14ce26e7	bellard	case CC_OP_ADDQ:
1730	14ce26e7	bellard
1731	2c0262af	bellard	case CC_OP_ADCB:
1732	2c0262af	bellard	case CC_OP_ADCW:
1733	2c0262af	bellard	case CC_OP_ADCL:
1734	14ce26e7	bellard	case CC_OP_ADCQ:
1735	14ce26e7	bellard
1736	2c0262af	bellard	case CC_OP_SBBB:
1737	2c0262af	bellard	case CC_OP_SBBW:
1738	2c0262af	bellard	case CC_OP_SBBL:
1739	14ce26e7	bellard	case CC_OP_SBBQ:
1740	14ce26e7	bellard
1741	2c0262af	bellard	case CC_OP_LOGICB:
1742	2c0262af	bellard	case CC_OP_LOGICW:
1743	2c0262af	bellard	case CC_OP_LOGICL:
1744	14ce26e7	bellard	case CC_OP_LOGICQ:
1745	14ce26e7	bellard
1746	2c0262af	bellard	case CC_OP_INCB:
1747	2c0262af	bellard	case CC_OP_INCW:
1748	2c0262af	bellard	case CC_OP_INCL:
1749	14ce26e7	bellard	case CC_OP_INCQ:
1750	14ce26e7	bellard
1751	2c0262af	bellard	case CC_OP_DECB:
1752	2c0262af	bellard	case CC_OP_DECW:
1753	2c0262af	bellard	case CC_OP_DECL:
1754	14ce26e7	bellard	case CC_OP_DECQ:
1755	14ce26e7	bellard
1756	2c0262af	bellard	case CC_OP_SHLB:
1757	2c0262af	bellard	case CC_OP_SHLW:
1758	2c0262af	bellard	case CC_OP_SHLL:
1759	14ce26e7	bellard	case CC_OP_SHLQ:
1760	14ce26e7	bellard
1761	2c0262af	bellard	case CC_OP_SARB:
1762	2c0262af	bellard	case CC_OP_SARW:
1763	2c0262af	bellard	case CC_OP_SARL:
1764	14ce26e7	bellard	case CC_OP_SARQ:
1765	2c0262af	bellard	switch(jcc_op) {
1766	2c0262af	bellard	case JCC_Z:
1767	14ce26e7	bellard	func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1768	2c0262af	bellard	break;
1769	2c0262af	bellard	case JCC_S:
1770	14ce26e7	bellard	func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1771	2c0262af	bellard	break;
1772	2c0262af	bellard	default:
1773	2c0262af	bellard	func = NULL;
1774	2c0262af	bellard	break;
1775	2c0262af	bellard	}
1776	2c0262af	bellard	break;
1777	2c0262af	bellard	default:
1778	2c0262af	bellard	func = NULL;
1779	2c0262af	bellard	break;
1780	2c0262af	bellard	}
1781	2c0262af	bellard
1782	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1783	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1784	2c0262af	bellard
1785	2c0262af	bellard	if (!func) {
1786	2c0262af	bellard	gen_setcc_slow[jcc_op]();
1787	14ce26e7	bellard	func = gen_op_jnz_T0_label;
1788	2c0262af	bellard	}
1789	2c0262af	bellard
1790	14ce26e7	bellard	if (inv) {
1791	14ce26e7	bellard	tmp = val;
1792	14ce26e7	bellard	val = next_eip;
1793	14ce26e7	bellard	next_eip = tmp;
1794	2c0262af	bellard	}
1795	14ce26e7	bellard	tb = s->tb;
1796	14ce26e7	bellard
1797	14ce26e7	bellard	l1 = gen_new_label();
1798	14ce26e7	bellard	func(l1);
1799	14ce26e7	bellard
1800	ae063a68	bellard	gen_op_goto_tb0(TBPARAM(tb));
1801	14ce26e7	bellard	gen_jmp_im(next_eip);
1802	14ce26e7	bellard	gen_op_movl_T0_im((long)tb + 0);
1803	14ce26e7	bellard	gen_op_exit_tb();
1804	14ce26e7	bellard
1805	14ce26e7	bellard	gen_set_label(l1);
1806	ae063a68	bellard	gen_op_goto_tb1(TBPARAM(tb));
1807	14ce26e7	bellard	gen_jmp_im(val);
1808	14ce26e7	bellard	gen_op_movl_T0_im((long)tb + 1);
1809	14ce26e7	bellard	gen_op_exit_tb();
1810	14ce26e7	bellard
1811	2c0262af	bellard	s->is_jmp = 3;
1812	2c0262af	bellard	} else {
1813	14ce26e7	bellard
1814	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
1815	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1816	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC;
1817	2c0262af	bellard	}
1818	2c0262af	bellard	gen_setcc_slow[jcc_op]();
1819	14ce26e7	bellard	if (inv) {
1820	14ce26e7	bellard	tmp = val;
1821	14ce26e7	bellard	val = next_eip;
1822	14ce26e7	bellard	next_eip = tmp;
1823	2c0262af	bellard	}
1824	14ce26e7	bellard	l1 = gen_new_label();
1825	14ce26e7	bellard	l2 = gen_new_label();
1826	14ce26e7	bellard	gen_op_jnz_T0_label(l1);
1827	14ce26e7	bellard	gen_jmp_im(next_eip);
1828	14ce26e7	bellard	gen_op_jmp_label(l2);
1829	14ce26e7	bellard	gen_set_label(l1);
1830	14ce26e7	bellard	gen_jmp_im(val);
1831	14ce26e7	bellard	gen_set_label(l2);
1832	2c0262af	bellard	gen_eob(s);
1833	2c0262af	bellard	}
1834	2c0262af	bellard	}
1835	2c0262af	bellard
1836	2c0262af	bellard	static void gen_setcc(DisasContext *s, int b)
1837	2c0262af	bellard	{
1838	2c0262af	bellard	int inv, jcc_op;
1839	2c0262af	bellard	GenOpFunc *func;
1840	2c0262af	bellard
1841	2c0262af	bellard	inv = b & 1;
1842	2c0262af	bellard	jcc_op = (b >> 1) & 7;
1843	2c0262af	bellard	switch(s->cc_op) {
1844	2c0262af	bellard	/* we optimize the cmp/jcc case */
1845	2c0262af	bellard	case CC_OP_SUBB:
1846	2c0262af	bellard	case CC_OP_SUBW:
1847	2c0262af	bellard	case CC_OP_SUBL:
1848	14ce26e7	bellard	case CC_OP_SUBQ:
1849	2c0262af	bellard	func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1850	2c0262af	bellard	if (!func)
1851	2c0262af	bellard	goto slow_jcc;
1852	2c0262af	bellard	break;
1853	2c0262af	bellard
1854	2c0262af	bellard	/* some jumps are easy to compute */
1855	2c0262af	bellard	case CC_OP_ADDB:
1856	2c0262af	bellard	case CC_OP_ADDW:
1857	2c0262af	bellard	case CC_OP_ADDL:
1858	14ce26e7	bellard	case CC_OP_ADDQ:
1859	14ce26e7	bellard
1860	2c0262af	bellard	case CC_OP_LOGICB:
1861	2c0262af	bellard	case CC_OP_LOGICW:
1862	2c0262af	bellard	case CC_OP_LOGICL:
1863	14ce26e7	bellard	case CC_OP_LOGICQ:
1864	14ce26e7	bellard
1865	2c0262af	bellard	case CC_OP_INCB:
1866	2c0262af	bellard	case CC_OP_INCW:
1867	2c0262af	bellard	case CC_OP_INCL:
1868	14ce26e7	bellard	case CC_OP_INCQ:
1869	14ce26e7	bellard
1870	2c0262af	bellard	case CC_OP_DECB:
1871	2c0262af	bellard	case CC_OP_DECW:
1872	2c0262af	bellard	case CC_OP_DECL:
1873	14ce26e7	bellard	case CC_OP_DECQ:
1874	14ce26e7	bellard
1875	2c0262af	bellard	case CC_OP_SHLB:
1876	2c0262af	bellard	case CC_OP_SHLW:
1877	2c0262af	bellard	case CC_OP_SHLL:
1878	14ce26e7	bellard	case CC_OP_SHLQ:
1879	2c0262af	bellard	switch(jcc_op) {
1880	2c0262af	bellard	case JCC_Z:
1881	14ce26e7	bellard	func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1882	2c0262af	bellard	break;
1883	2c0262af	bellard	case JCC_S:
1884	14ce26e7	bellard	func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1885	2c0262af	bellard	break;
1886	2c0262af	bellard	default:
1887	2c0262af	bellard	goto slow_jcc;
1888	2c0262af	bellard	}
1889	2c0262af	bellard	break;
1890	2c0262af	bellard	default:
1891	2c0262af	bellard	slow_jcc:
1892	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1893	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1894	2c0262af	bellard	func = gen_setcc_slow[jcc_op];
1895	2c0262af	bellard	break;
1896	2c0262af	bellard	}
1897	2c0262af	bellard	func();
1898	2c0262af	bellard	if (inv) {
1899	2c0262af	bellard	gen_op_xor_T0_1();
1900	2c0262af	bellard	}
1901	2c0262af	bellard	}
1902	2c0262af	bellard
1903	2c0262af	bellard	/* move T0 to seg_reg and compute if the CPU state may change. Never
1904	2c0262af	bellard	call this function with seg_reg == R_CS */
1905	14ce26e7	bellard	static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
1906	2c0262af	bellard	{
1907	3415a4dd	bellard	if (s->pe && !s->vm86) {
1908	3415a4dd	bellard	/* XXX: optimize by finding processor state dynamically */
1909	3415a4dd	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1910	3415a4dd	bellard	gen_op_set_cc_op(s->cc_op);
1911	14ce26e7	bellard	gen_jmp_im(cur_eip);
1912	3415a4dd	bellard	gen_op_movl_seg_T0(seg_reg);
1913	dc196a57	bellard	/* abort translation because the addseg value may change or
1914	dc196a57	bellard	because ss32 may change. For R_SS, translation must always
1915	dc196a57	bellard	stop as a special handling must be done to disable hardware
1916	dc196a57	bellard	interrupts for the next instruction */
1917	dc196a57	bellard	if (seg_reg == R_SS \|\| (s->code32 && seg_reg < R_FS))
1918	dc196a57	bellard	s->is_jmp = 3;
1919	3415a4dd	bellard	} else {
1920	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1921	dc196a57	bellard	if (seg_reg == R_SS)
1922	dc196a57	bellard	s->is_jmp = 3;
1923	3415a4dd	bellard	}
1924	2c0262af	bellard	}
1925	2c0262af	bellard
1926	4f31916f	bellard	static inline void gen_stack_update(DisasContext *s, int addend)
1927	4f31916f	bellard	{
1928	14ce26e7	bellard	#ifdef TARGET_X86_64
1929	14ce26e7	bellard	if (CODE64(s)) {
1930	14ce26e7	bellard	if (addend == 8)
1931	14ce26e7	bellard	gen_op_addq_ESP_8();
1932	14ce26e7	bellard	else
1933	14ce26e7	bellard	gen_op_addq_ESP_im(addend);
1934	14ce26e7	bellard	} else
1935	14ce26e7	bellard	#endif
1936	4f31916f	bellard	if (s->ss32) {
1937	4f31916f	bellard	if (addend == 2)
1938	4f31916f	bellard	gen_op_addl_ESP_2();
1939	4f31916f	bellard	else if (addend == 4)
1940	4f31916f	bellard	gen_op_addl_ESP_4();
1941	4f31916f	bellard	else
1942	4f31916f	bellard	gen_op_addl_ESP_im(addend);
1943	4f31916f	bellard	} else {
1944	4f31916f	bellard	if (addend == 2)
1945	4f31916f	bellard	gen_op_addw_ESP_2();
1946	4f31916f	bellard	else if (addend == 4)
1947	4f31916f	bellard	gen_op_addw_ESP_4();
1948	4f31916f	bellard	else
1949	4f31916f	bellard	gen_op_addw_ESP_im(addend);
1950	4f31916f	bellard	}
1951	4f31916f	bellard	}
1952	4f31916f	bellard
1953	2c0262af	bellard	/* generate a push. It depends on ss32, addseg and dflag */
1954	2c0262af	bellard	static void gen_push_T0(DisasContext *s)
1955	2c0262af	bellard	{
1956	14ce26e7	bellard	#ifdef TARGET_X86_64
1957	14ce26e7	bellard	if (CODE64(s)) {
1958	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
1959	8f091a59	bellard	if (s->dflag) {
1960	8f091a59	bellard	gen_op_subq_A0_8();
1961	8f091a59	bellard	gen_op_st_T0_A0[OT_QUAD + s->mem_index]();
1962	8f091a59	bellard	} else {
1963	8f091a59	bellard	gen_op_subq_A0_2();
1964	8f091a59	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
1965	8f091a59	bellard	}
1966	14ce26e7	bellard	gen_op_movq_ESP_A0();
1967	14ce26e7	bellard	} else
1968	14ce26e7	bellard	#endif
1969	14ce26e7	bellard	{
1970	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
1971	14ce26e7	bellard	if (!s->dflag)
1972	14ce26e7	bellard	gen_op_subl_A0_2();
1973	14ce26e7	bellard	else
1974	14ce26e7	bellard	gen_op_subl_A0_4();
1975	14ce26e7	bellard	if (s->ss32) {
1976	14ce26e7	bellard	if (s->addseg) {
1977	14ce26e7	bellard	gen_op_movl_T1_A0();
1978	14ce26e7	bellard	gen_op_addl_A0_SS();
1979	14ce26e7	bellard	}
1980	14ce26e7	bellard	} else {
1981	14ce26e7	bellard	gen_op_andl_A0_ffff();
1982	4f31916f	bellard	gen_op_movl_T1_A0();
1983	4f31916f	bellard	gen_op_addl_A0_SS();
1984	2c0262af	bellard	}
1985	14ce26e7	bellard	gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
1986	14ce26e7	bellard	if (s->ss32 && !s->addseg)
1987	14ce26e7	bellard	gen_op_movl_ESP_A0();
1988	14ce26e7	bellard	else
1989	14ce26e7	bellard	gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
1990	2c0262af	bellard	}
1991	2c0262af	bellard	}
1992	2c0262af	bellard
1993	4f31916f	bellard	/* generate a push. It depends on ss32, addseg and dflag */
1994	4f31916f	bellard	/* slower version for T1, only used for call Ev */
1995	4f31916f	bellard	static void gen_push_T1(DisasContext *s)
1996	2c0262af	bellard	{
1997	14ce26e7	bellard	#ifdef TARGET_X86_64
1998	14ce26e7	bellard	if (CODE64(s)) {
1999	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
2000	8f091a59	bellard	if (s->dflag) {
2001	8f091a59	bellard	gen_op_subq_A0_8();
2002	8f091a59	bellard	gen_op_st_T1_A0[OT_QUAD + s->mem_index]();
2003	8f091a59	bellard	} else {
2004	8f091a59	bellard	gen_op_subq_A0_2();
2005	8f091a59	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2006	8f091a59	bellard	}
2007	14ce26e7	bellard	gen_op_movq_ESP_A0();
2008	14ce26e7	bellard	} else
2009	14ce26e7	bellard	#endif
2010	14ce26e7	bellard	{
2011	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
2012	14ce26e7	bellard	if (!s->dflag)
2013	14ce26e7	bellard	gen_op_subl_A0_2();
2014	14ce26e7	bellard	else
2015	14ce26e7	bellard	gen_op_subl_A0_4();
2016	14ce26e7	bellard	if (s->ss32) {
2017	14ce26e7	bellard	if (s->addseg) {
2018	14ce26e7	bellard	gen_op_addl_A0_SS();
2019	14ce26e7	bellard	}
2020	14ce26e7	bellard	} else {
2021	14ce26e7	bellard	gen_op_andl_A0_ffff();
2022	4f31916f	bellard	gen_op_addl_A0_SS();
2023	2c0262af	bellard	}
2024	14ce26e7	bellard	gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
2025	14ce26e7	bellard
2026	14ce26e7	bellard	if (s->ss32 && !s->addseg)
2027	14ce26e7	bellard	gen_op_movl_ESP_A0();
2028	14ce26e7	bellard	else
2029	14ce26e7	bellard	gen_stack_update(s, (-2) << s->dflag);
2030	2c0262af	bellard	}
2031	2c0262af	bellard	}
2032	2c0262af	bellard
2033	4f31916f	bellard	/* two step pop is necessary for precise exceptions */
2034	4f31916f	bellard	static void gen_pop_T0(DisasContext *s)
2035	2c0262af	bellard	{
2036	14ce26e7	bellard	#ifdef TARGET_X86_64
2037	14ce26e7	bellard	if (CODE64(s)) {
2038	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
2039	8f091a59	bellard	gen_op_ld_T0_A0[(s->dflag ? OT_QUAD : OT_WORD) + s->mem_index]();
2040	14ce26e7	bellard	} else
2041	14ce26e7	bellard	#endif
2042	14ce26e7	bellard	{
2043	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
2044	14ce26e7	bellard	if (s->ss32) {
2045	14ce26e7	bellard	if (s->addseg)
2046	14ce26e7	bellard	gen_op_addl_A0_SS();
2047	14ce26e7	bellard	} else {
2048	14ce26e7	bellard	gen_op_andl_A0_ffff();
2049	4f31916f	bellard	gen_op_addl_A0_SS();
2050	14ce26e7	bellard	}
2051	14ce26e7	bellard	gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
2052	2c0262af	bellard	}
2053	2c0262af	bellard	}
2054	2c0262af	bellard
2055	2c0262af	bellard	static void gen_pop_update(DisasContext *s)
2056	2c0262af	bellard	{
2057	14ce26e7	bellard	#ifdef TARGET_X86_64
2058	8f091a59	bellard	if (CODE64(s) && s->dflag) {
2059	14ce26e7	bellard	gen_stack_update(s, 8);
2060	14ce26e7	bellard	} else
2061	14ce26e7	bellard	#endif
2062	14ce26e7	bellard	{
2063	14ce26e7	bellard	gen_stack_update(s, 2 << s->dflag);
2064	14ce26e7	bellard	}
2065	2c0262af	bellard	}
2066	2c0262af	bellard
2067	2c0262af	bellard	static void gen_stack_A0(DisasContext *s)
2068	2c0262af	bellard	{
2069	2c0262af	bellard	gen_op_movl_A0_ESP();
2070	2c0262af	bellard	if (!s->ss32)
2071	2c0262af	bellard	gen_op_andl_A0_ffff();
2072	2c0262af	bellard	gen_op_movl_T1_A0();
2073	2c0262af	bellard	if (s->addseg)
2074	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2075	2c0262af	bellard	}
2076	2c0262af	bellard
2077	2c0262af	bellard	/* NOTE: wrap around in 16 bit not fully handled */
2078	2c0262af	bellard	static void gen_pusha(DisasContext *s)
2079	2c0262af	bellard	{
2080	2c0262af	bellard	int i;
2081	2c0262af	bellard	gen_op_movl_A0_ESP();
2082	2c0262af	bellard	gen_op_addl_A0_im(-16 << s->dflag);
2083	2c0262af	bellard	if (!s->ss32)
2084	2c0262af	bellard	gen_op_andl_A0_ffff();
2085	2c0262af	bellard	gen_op_movl_T1_A0();
2086	2c0262af	bellard	if (s->addseg)
2087	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2088	2c0262af	bellard	for(i = 0;i < 8; i++) {
2089	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
2090	2c0262af	bellard	gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2091	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
2092	2c0262af	bellard	}
2093	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2094	2c0262af	bellard	}
2095	2c0262af	bellard
2096	2c0262af	bellard	/* NOTE: wrap around in 16 bit not fully handled */
2097	2c0262af	bellard	static void gen_popa(DisasContext *s)
2098	2c0262af	bellard	{
2099	2c0262af	bellard	int i;
2100	2c0262af	bellard	gen_op_movl_A0_ESP();
2101	2c0262af	bellard	if (!s->ss32)
2102	2c0262af	bellard	gen_op_andl_A0_ffff();
2103	2c0262af	bellard	gen_op_movl_T1_A0();
2104	2c0262af	bellard	gen_op_addl_T1_im(16 << s->dflag);
2105	2c0262af	bellard	if (s->addseg)
2106	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2107	2c0262af	bellard	for(i = 0;i < 8; i++) {
2108	2c0262af	bellard	/* ESP is not reloaded */
2109	2c0262af	bellard	if (i != 3) {
2110	2c0262af	bellard	gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2111	2c0262af	bellard	gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
2112	2c0262af	bellard	}
2113	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
2114	2c0262af	bellard	}
2115	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2116	2c0262af	bellard	}
2117	2c0262af	bellard
2118	2c0262af	bellard	static void gen_enter(DisasContext *s, int esp_addend, int level)
2119	2c0262af	bellard	{
2120	61a8c4ec	bellard	int ot, opsize;
2121	2c0262af	bellard
2122	2c0262af	bellard	level &= 0x1f;
2123	8f091a59	bellard	#ifdef TARGET_X86_64
2124	8f091a59	bellard	if (CODE64(s)) {
2125	8f091a59	bellard	ot = s->dflag ? OT_QUAD : OT_WORD;
2126	8f091a59	bellard	opsize = 1 << ot;
2127	8f091a59	bellard
2128	8f091a59	bellard	gen_op_movl_A0_ESP();
2129	8f091a59	bellard	gen_op_addq_A0_im(-opsize);
2130	8f091a59	bellard	gen_op_movl_T1_A0();
2131	8f091a59	bellard
2132	8f091a59	bellard	/* push bp */
2133	8f091a59	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2134	8f091a59	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
2135	8f091a59	bellard	if (level) {
2136	8f091a59	bellard	gen_op_enter64_level(level, (ot == OT_QUAD));
2137	8f091a59	bellard	}
2138	8f091a59	bellard	gen_op_mov_reg_T1[ot][R_EBP]();
2139	8f091a59	bellard	gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2140	8f091a59	bellard	gen_op_mov_reg_T1[OT_QUAD][R_ESP]();
2141	8f091a59	bellard	} else
2142	8f091a59	bellard	#endif
2143	8f091a59	bellard	{
2144	8f091a59	bellard	ot = s->dflag + OT_WORD;
2145	8f091a59	bellard	opsize = 2 << s->dflag;
2146	8f091a59	bellard
2147	8f091a59	bellard	gen_op_movl_A0_ESP();
2148	8f091a59	bellard	gen_op_addl_A0_im(-opsize);
2149	8f091a59	bellard	if (!s->ss32)
2150	8f091a59	bellard	gen_op_andl_A0_ffff();
2151	8f091a59	bellard	gen_op_movl_T1_A0();
2152	8f091a59	bellard	if (s->addseg)
2153	8f091a59	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2154	8f091a59	bellard	/* push bp */
2155	8f091a59	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2156	8f091a59	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
2157	8f091a59	bellard	if (level) {
2158	8f091a59	bellard	gen_op_enter_level(level, s->dflag);
2159	8f091a59	bellard	}
2160	8f091a59	bellard	gen_op_mov_reg_T1[ot][R_EBP]();
2161	8f091a59	bellard	gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2162	8f091a59	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2163	2c0262af	bellard	}
2164	2c0262af	bellard	}
2165	2c0262af	bellard
2166	14ce26e7	bellard	static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2167	2c0262af	bellard	{
2168	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2169	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2170	14ce26e7	bellard	gen_jmp_im(cur_eip);
2171	2c0262af	bellard	gen_op_raise_exception(trapno);
2172	2c0262af	bellard	s->is_jmp = 3;
2173	2c0262af	bellard	}
2174	2c0262af	bellard
2175	2c0262af	bellard	/* an interrupt is different from an exception because of the
2176	2c0262af	bellard	priviledge checks */
2177	2c0262af	bellard	static void gen_interrupt(DisasContext *s, int intno,
2178	14ce26e7	bellard	target_ulong cur_eip, target_ulong next_eip)
2179	2c0262af	bellard	{
2180	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2181	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2182	14ce26e7	bellard	gen_jmp_im(cur_eip);
2183	a8ede8ba	bellard	gen_op_raise_interrupt(intno, (int)(next_eip - cur_eip));
2184	2c0262af	bellard	s->is_jmp = 3;
2185	2c0262af	bellard	}
2186	2c0262af	bellard
2187	14ce26e7	bellard	static void gen_debug(DisasContext *s, target_ulong cur_eip)
2188	2c0262af	bellard	{
2189	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2190	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2191	14ce26e7	bellard	gen_jmp_im(cur_eip);
2192	2c0262af	bellard	gen_op_debug();
2193	2c0262af	bellard	s->is_jmp = 3;
2194	2c0262af	bellard	}
2195	2c0262af	bellard
2196	2c0262af	bellard	/* generate a generic end of block. Trace exception is also generated
2197	2c0262af	bellard	if needed */
2198	2c0262af	bellard	static void gen_eob(DisasContext *s)
2199	2c0262af	bellard	{
2200	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2201	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2202	a2cc3b24	bellard	if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2203	a2cc3b24	bellard	gen_op_reset_inhibit_irq();
2204	a2cc3b24	bellard	}
2205	34865134	bellard	if (s->singlestep_enabled) {
2206	34865134	bellard	gen_op_debug();
2207	34865134	bellard	} else if (s->tf) {
2208	2c0262af	bellard	gen_op_raise_exception(EXCP01_SSTP);
2209	2c0262af	bellard	} else {
2210	2c0262af	bellard	gen_op_movl_T0_0();
2211	2c0262af	bellard	gen_op_exit_tb();
2212	2c0262af	bellard	}
2213	2c0262af	bellard	s->is_jmp = 3;
2214	2c0262af	bellard	}
2215	2c0262af	bellard
2216	2c0262af	bellard	/* generate a jump to eip. No segment change must happen before as a
2217	2c0262af	bellard	direct call to the next block may occur */
2218	14ce26e7	bellard	static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2219	2c0262af	bellard	{
2220	2c0262af	bellard	TranslationBlock *tb = s->tb;
2221	2c0262af	bellard
2222	2c0262af	bellard	if (s->jmp_opt) {
2223	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2224	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2225	14ce26e7	bellard	if (tb_num)
2226	ae063a68	bellard	gen_op_goto_tb1(TBPARAM(tb));
2227	14ce26e7	bellard	else
2228	ae063a68	bellard	gen_op_goto_tb0(TBPARAM(tb));
2229	14ce26e7	bellard	gen_jmp_im(eip);
2230	14ce26e7	bellard	gen_op_movl_T0_im((long)tb + tb_num);
2231	14ce26e7	bellard	gen_op_exit_tb();
2232	2c0262af	bellard	s->is_jmp = 3;
2233	2c0262af	bellard	} else {
2234	14ce26e7	bellard	gen_jmp_im(eip);
2235	2c0262af	bellard	gen_eob(s);
2236	2c0262af	bellard	}
2237	2c0262af	bellard	}
2238	2c0262af	bellard
2239	14ce26e7	bellard	static void gen_jmp(DisasContext *s, target_ulong eip)
2240	14ce26e7	bellard	{
2241	14ce26e7	bellard	gen_jmp_tb(s, eip, 0);
2242	14ce26e7	bellard	}
2243	14ce26e7	bellard
2244	14ce26e7	bellard	static void gen_movtl_T0_im(target_ulong val)
2245	14ce26e7	bellard	{
2246	14ce26e7	bellard	#ifdef TARGET_X86_64
2247	14ce26e7	bellard	if ((int32_t)val == val) {
2248	14ce26e7	bellard	gen_op_movl_T0_im(val);
2249	14ce26e7	bellard	} else {
2250	14ce26e7	bellard	gen_op_movq_T0_im64(val >> 32, val);
2251	14ce26e7	bellard	}
2252	14ce26e7	bellard	#else
2253	14ce26e7	bellard	gen_op_movl_T0_im(val);
2254	14ce26e7	bellard	#endif
2255	14ce26e7	bellard	}
2256	14ce26e7	bellard
2257	1ef38687	bellard	static void gen_movtl_T1_im(target_ulong val)
2258	1ef38687	bellard	{
2259	1ef38687	bellard	#ifdef TARGET_X86_64
2260	1ef38687	bellard	if ((int32_t)val == val) {
2261	1ef38687	bellard	gen_op_movl_T1_im(val);
2262	1ef38687	bellard	} else {
2263	1ef38687	bellard	gen_op_movq_T1_im64(val >> 32, val);
2264	1ef38687	bellard	}
2265	1ef38687	bellard	#else
2266	1ef38687	bellard	gen_op_movl_T1_im(val);
2267	1ef38687	bellard	#endif
2268	1ef38687	bellard	}
2269	1ef38687	bellard
2270	aba9d61e	bellard	static void gen_add_A0_im(DisasContext *s, int val)
2271	aba9d61e	bellard	{
2272	aba9d61e	bellard	#ifdef TARGET_X86_64
2273	aba9d61e	bellard	if (CODE64(s))
2274	aba9d61e	bellard	gen_op_addq_A0_im(val);
2275	aba9d61e	bellard	else
2276	aba9d61e	bellard	#endif
2277	aba9d61e	bellard	gen_op_addl_A0_im(val);
2278	aba9d61e	bellard	}
2279	aba9d61e	bellard
2280	664e0f19	bellard	static GenOpFunc1 *gen_ldq_env_A0[3] = {
2281	664e0f19	bellard	gen_op_ldq_raw_env_A0,
2282	664e0f19	bellard	#ifndef CONFIG_USER_ONLY
2283	664e0f19	bellard	gen_op_ldq_kernel_env_A0,
2284	664e0f19	bellard	gen_op_ldq_user_env_A0,
2285	664e0f19	bellard	#endif
2286	664e0f19	bellard	};
2287	664e0f19	bellard
2288	664e0f19	bellard	static GenOpFunc1 *gen_stq_env_A0[3] = {
2289	664e0f19	bellard	gen_op_stq_raw_env_A0,
2290	664e0f19	bellard	#ifndef CONFIG_USER_ONLY
2291	664e0f19	bellard	gen_op_stq_kernel_env_A0,
2292	664e0f19	bellard	gen_op_stq_user_env_A0,
2293	664e0f19	bellard	#endif
2294	664e0f19	bellard	};
2295	664e0f19	bellard
2296	14ce26e7	bellard	static GenOpFunc1 *gen_ldo_env_A0[3] = {
2297	14ce26e7	bellard	gen_op_ldo_raw_env_A0,
2298	14ce26e7	bellard	#ifndef CONFIG_USER_ONLY
2299	14ce26e7	bellard	gen_op_ldo_kernel_env_A0,
2300	14ce26e7	bellard	gen_op_ldo_user_env_A0,
2301	14ce26e7	bellard	#endif
2302	14ce26e7	bellard	};
2303	14ce26e7	bellard
2304	14ce26e7	bellard	static GenOpFunc1 *gen_sto_env_A0[3] = {
2305	14ce26e7	bellard	gen_op_sto_raw_env_A0,
2306	14ce26e7	bellard	#ifndef CONFIG_USER_ONLY
2307	14ce26e7	bellard	gen_op_sto_kernel_env_A0,
2308	14ce26e7	bellard	gen_op_sto_user_env_A0,
2309	14ce26e7	bellard	#endif
2310	14ce26e7	bellard	};
2311	14ce26e7	bellard
2312	664e0f19	bellard	#define SSE_SPECIAL ((GenOpFunc2 *)1)
2313	664e0f19	bellard
2314	664e0f19	bellard	#define MMX_OP2(x) { gen_op_ ## x ## _mmx, gen_op_ ## x ## _xmm }
2315	664e0f19	bellard	#define SSE_FOP(x) { gen_op_ ## x ## ps, gen_op_ ## x ## pd, \
2316	664e0f19	bellard	gen_op_ ## x ## ss, gen_op_ ## x ## sd, }
2317	664e0f19	bellard
2318	664e0f19	bellard	static GenOpFunc2 *sse_op_table1[256][4] = {
2319	664e0f19	bellard	/* pure SSE operations */
2320	664e0f19	bellard	[0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2321	664e0f19	bellard	[0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2322	664e0f19	bellard	[0x12] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2323	664e0f19	bellard	[0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2324	664e0f19	bellard	[0x14] = { gen_op_punpckldq_xmm, gen_op_punpcklqdq_xmm },
2325	664e0f19	bellard	[0x15] = { gen_op_punpckhdq_xmm, gen_op_punpckhqdq_xmm },
2326	664e0f19	bellard	[0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2327	664e0f19	bellard	[0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2328	664e0f19	bellard
2329	664e0f19	bellard	[0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2330	664e0f19	bellard	[0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2331	664e0f19	bellard	[0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2332	664e0f19	bellard	[0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2333	664e0f19	bellard	[0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2334	664e0f19	bellard	[0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2335	664e0f19	bellard	[0x2e] = { gen_op_ucomiss, gen_op_ucomisd },
2336	664e0f19	bellard	[0x2f] = { gen_op_comiss, gen_op_comisd },
2337	664e0f19	bellard	[0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2338	664e0f19	bellard	[0x51] = SSE_FOP(sqrt),
2339	664e0f19	bellard	[0x52] = { gen_op_rsqrtps, NULL, gen_op_rsqrtss, NULL },
2340	664e0f19	bellard	[0x53] = { gen_op_rcpps, NULL, gen_op_rcpss, NULL },
2341	664e0f19	bellard	[0x54] = { gen_op_pand_xmm, gen_op_pand_xmm }, /* andps, andpd */
2342	664e0f19	bellard	[0x55] = { gen_op_pandn_xmm, gen_op_pandn_xmm }, /* andnps, andnpd */
2343	664e0f19	bellard	[0x56] = { gen_op_por_xmm, gen_op_por_xmm }, /* orps, orpd */
2344	664e0f19	bellard	[0x57] = { gen_op_pxor_xmm, gen_op_pxor_xmm }, /* xorps, xorpd */
2345	664e0f19	bellard	[0x58] = SSE_FOP(add),
2346	664e0f19	bellard	[0x59] = SSE_FOP(mul),
2347	664e0f19	bellard	[0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
2348	664e0f19	bellard	gen_op_cvtss2sd, gen_op_cvtsd2ss },
2349	664e0f19	bellard	[0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
2350	664e0f19	bellard	[0x5c] = SSE_FOP(sub),
2351	664e0f19	bellard	[0x5d] = SSE_FOP(min),
2352	664e0f19	bellard	[0x5e] = SSE_FOP(div),
2353	664e0f19	bellard	[0x5f] = SSE_FOP(max),
2354	664e0f19	bellard
2355	664e0f19	bellard	[0xc2] = SSE_FOP(cmpeq),
2356	d52cf7a6	bellard	[0xc6] = { (GenOpFunc2 )gen_op_shufps, (GenOpFunc2 )gen_op_shufpd },
2357	664e0f19	bellard
2358	664e0f19	bellard	/* MMX ops and their SSE extensions */
2359	664e0f19	bellard	[0x60] = MMX_OP2(punpcklbw),
2360	664e0f19	bellard	[0x61] = MMX_OP2(punpcklwd),
2361	664e0f19	bellard	[0x62] = MMX_OP2(punpckldq),
2362	664e0f19	bellard	[0x63] = MMX_OP2(packsswb),
2363	664e0f19	bellard	[0x64] = MMX_OP2(pcmpgtb),
2364	664e0f19	bellard	[0x65] = MMX_OP2(pcmpgtw),
2365	664e0f19	bellard	[0x66] = MMX_OP2(pcmpgtl),
2366	664e0f19	bellard	[0x67] = MMX_OP2(packuswb),
2367	664e0f19	bellard	[0x68] = MMX_OP2(punpckhbw),
2368	664e0f19	bellard	[0x69] = MMX_OP2(punpckhwd),
2369	664e0f19	bellard	[0x6a] = MMX_OP2(punpckhdq),
2370	664e0f19	bellard	[0x6b] = MMX_OP2(packssdw),
2371	664e0f19	bellard	[0x6c] = { NULL, gen_op_punpcklqdq_xmm },
2372	664e0f19	bellard	[0x6d] = { NULL, gen_op_punpckhqdq_xmm },
2373	664e0f19	bellard	[0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2374	664e0f19	bellard	[0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2375	664e0f19	bellard	[0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
2376	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshufd_xmm,
2377	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshufhw_xmm,
2378	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshuflw_xmm },
2379	664e0f19	bellard	[0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2380	664e0f19	bellard	[0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2381	664e0f19	bellard	[0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2382	664e0f19	bellard	[0x74] = MMX_OP2(pcmpeqb),
2383	664e0f19	bellard	[0x75] = MMX_OP2(pcmpeqw),
2384	664e0f19	bellard	[0x76] = MMX_OP2(pcmpeql),
2385	664e0f19	bellard	[0x77] = { SSE_SPECIAL }, /* emms */
2386	664e0f19	bellard	[0x7c] = { NULL, gen_op_haddpd, NULL, gen_op_haddps },
2387	664e0f19	bellard	[0x7d] = { NULL, gen_op_hsubpd, NULL, gen_op_hsubps },
2388	664e0f19	bellard	[0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2389	664e0f19	bellard	[0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2390	664e0f19	bellard	[0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2391	664e0f19	bellard	[0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2392	664e0f19	bellard	[0xd0] = { NULL, gen_op_addsubpd, NULL, gen_op_addsubps },
2393	664e0f19	bellard	[0xd1] = MMX_OP2(psrlw),
2394	664e0f19	bellard	[0xd2] = MMX_OP2(psrld),
2395	664e0f19	bellard	[0xd3] = MMX_OP2(psrlq),
2396	664e0f19	bellard	[0xd4] = MMX_OP2(paddq),
2397	664e0f19	bellard	[0xd5] = MMX_OP2(pmullw),
2398	664e0f19	bellard	[0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2399	664e0f19	bellard	[0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2400	664e0f19	bellard	[0xd8] = MMX_OP2(psubusb),
2401	664e0f19	bellard	[0xd9] = MMX_OP2(psubusw),
2402	664e0f19	bellard	[0xda] = MMX_OP2(pminub),
2403	664e0f19	bellard	[0xdb] = MMX_OP2(pand),
2404	664e0f19	bellard	[0xdc] = MMX_OP2(paddusb),
2405	664e0f19	bellard	[0xdd] = MMX_OP2(paddusw),
2406	664e0f19	bellard	[0xde] = MMX_OP2(pmaxub),
2407	664e0f19	bellard	[0xdf] = MMX_OP2(pandn),
2408	664e0f19	bellard	[0xe0] = MMX_OP2(pavgb),
2409	664e0f19	bellard	[0xe1] = MMX_OP2(psraw),
2410	664e0f19	bellard	[0xe2] = MMX_OP2(psrad),
2411	664e0f19	bellard	[0xe3] = MMX_OP2(pavgw),
2412	664e0f19	bellard	[0xe4] = MMX_OP2(pmulhuw),
2413	664e0f19	bellard	[0xe5] = MMX_OP2(pmulhw),
2414	664e0f19	bellard	[0xe6] = { NULL, gen_op_cvttpd2dq, gen_op_cvtdq2pd, gen_op_cvtpd2dq },
2415	664e0f19	bellard	[0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2416	664e0f19	bellard	[0xe8] = MMX_OP2(psubsb),
2417	664e0f19	bellard	[0xe9] = MMX_OP2(psubsw),
2418	664e0f19	bellard	[0xea] = MMX_OP2(pminsw),
2419	664e0f19	bellard	[0xeb] = MMX_OP2(por),
2420	664e0f19	bellard	[0xec] = MMX_OP2(paddsb),
2421	664e0f19	bellard	[0xed] = MMX_OP2(paddsw),
2422	664e0f19	bellard	[0xee] = MMX_OP2(pmaxsw),
2423	664e0f19	bellard	[0xef] = MMX_OP2(pxor),
2424	664e0f19	bellard	[0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu (PNI) */
2425	664e0f19	bellard	[0xf1] = MMX_OP2(psllw),
2426	664e0f19	bellard	[0xf2] = MMX_OP2(pslld),
2427	664e0f19	bellard	[0xf3] = MMX_OP2(psllq),
2428	664e0f19	bellard	[0xf4] = MMX_OP2(pmuludq),
2429	664e0f19	bellard	[0xf5] = MMX_OP2(pmaddwd),
2430	664e0f19	bellard	[0xf6] = MMX_OP2(psadbw),
2431	664e0f19	bellard	[0xf7] = MMX_OP2(maskmov),
2432	664e0f19	bellard	[0xf8] = MMX_OP2(psubb),
2433	664e0f19	bellard	[0xf9] = MMX_OP2(psubw),
2434	664e0f19	bellard	[0xfa] = MMX_OP2(psubl),
2435	664e0f19	bellard	[0xfb] = MMX_OP2(psubq),
2436	664e0f19	bellard	[0xfc] = MMX_OP2(paddb),
2437	664e0f19	bellard	[0xfd] = MMX_OP2(paddw),
2438	664e0f19	bellard	[0xfe] = MMX_OP2(paddl),
2439	664e0f19	bellard	};
2440	664e0f19	bellard
2441	664e0f19	bellard	static GenOpFunc2 sse_op_table2[3 8][2] = {
2442	664e0f19	bellard	[0 + 2] = MMX_OP2(psrlw),
2443	664e0f19	bellard	[0 + 4] = MMX_OP2(psraw),
2444	664e0f19	bellard	[0 + 6] = MMX_OP2(psllw),
2445	664e0f19	bellard	[8 + 2] = MMX_OP2(psrld),
2446	664e0f19	bellard	[8 + 4] = MMX_OP2(psrad),
2447	664e0f19	bellard	[8 + 6] = MMX_OP2(pslld),
2448	664e0f19	bellard	[16 + 2] = MMX_OP2(psrlq),
2449	664e0f19	bellard	[16 + 3] = { NULL, gen_op_psrldq_xmm },
2450	664e0f19	bellard	[16 + 6] = MMX_OP2(psllq),
2451	664e0f19	bellard	[16 + 7] = { NULL, gen_op_pslldq_xmm },
2452	664e0f19	bellard	};
2453	664e0f19	bellard
2454	664e0f19	bellard	static GenOpFunc1 sse_op_table3[4 3] = {
2455	664e0f19	bellard	gen_op_cvtsi2ss,
2456	664e0f19	bellard	gen_op_cvtsi2sd,
2457	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsq2ss),
2458	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsq2sd),
2459	664e0f19	bellard
2460	664e0f19	bellard	gen_op_cvttss2si,
2461	664e0f19	bellard	gen_op_cvttsd2si,
2462	664e0f19	bellard	X86_64_ONLY(gen_op_cvttss2sq),
2463	664e0f19	bellard	X86_64_ONLY(gen_op_cvttsd2sq),
2464	664e0f19	bellard
2465	664e0f19	bellard	gen_op_cvtss2si,
2466	664e0f19	bellard	gen_op_cvtsd2si,
2467	664e0f19	bellard	X86_64_ONLY(gen_op_cvtss2sq),
2468	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsd2sq),
2469	664e0f19	bellard	};
2470	664e0f19	bellard
2471	664e0f19	bellard	static GenOpFunc2 *sse_op_table4[8][4] = {
2472	664e0f19	bellard	SSE_FOP(cmpeq),
2473	664e0f19	bellard	SSE_FOP(cmplt),
2474	664e0f19	bellard	SSE_FOP(cmple),
2475	664e0f19	bellard	SSE_FOP(cmpunord),
2476	664e0f19	bellard	SSE_FOP(cmpneq),
2477	664e0f19	bellard	SSE_FOP(cmpnlt),
2478	664e0f19	bellard	SSE_FOP(cmpnle),
2479	664e0f19	bellard	SSE_FOP(cmpord),
2480	664e0f19	bellard	};
2481	664e0f19	bellard
2482	664e0f19	bellard	static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2483	664e0f19	bellard	{
2484	664e0f19	bellard	int b1, op1_offset, op2_offset, is_xmm, val, ot;
2485	664e0f19	bellard	int modrm, mod, rm, reg, reg_addr, offset_addr;
2486	664e0f19	bellard	GenOpFunc2 *sse_op2;
2487	664e0f19	bellard	GenOpFunc3 *sse_op3;
2488	664e0f19	bellard
2489	664e0f19	bellard	b &= 0xff;
2490	664e0f19	bellard	if (s->prefix & PREFIX_DATA)
2491	664e0f19	bellard	b1 = 1;
2492	664e0f19	bellard	else if (s->prefix & PREFIX_REPZ)
2493	664e0f19	bellard	b1 = 2;
2494	664e0f19	bellard	else if (s->prefix & PREFIX_REPNZ)
2495	664e0f19	bellard	b1 = 3;
2496	664e0f19	bellard	else
2497	664e0f19	bellard	b1 = 0;
2498	664e0f19	bellard	sse_op2 = sse_op_table1[b][b1];
2499	664e0f19	bellard	if (!sse_op2)
2500	664e0f19	bellard	goto illegal_op;
2501	664e0f19	bellard	if (b <= 0x5f \|\| b == 0xc6 \|\| b == 0xc2) {
2502	664e0f19	bellard	is_xmm = 1;
2503	664e0f19	bellard	} else {
2504	664e0f19	bellard	if (b1 == 0) {
2505	664e0f19	bellard	/* MMX case */
2506	664e0f19	bellard	is_xmm = 0;
2507	664e0f19	bellard	} else {
2508	664e0f19	bellard	is_xmm = 1;
2509	664e0f19	bellard	}
2510	664e0f19	bellard	}
2511	664e0f19	bellard	/* simple MMX/SSE operation */
2512	664e0f19	bellard	if (s->flags & HF_TS_MASK) {
2513	664e0f19	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2514	664e0f19	bellard	return;
2515	664e0f19	bellard	}
2516	664e0f19	bellard	if (s->flags & HF_EM_MASK) {
2517	664e0f19	bellard	illegal_op:
2518	664e0f19	bellard	gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2519	664e0f19	bellard	return;
2520	664e0f19	bellard	}
2521	664e0f19	bellard	if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2522	664e0f19	bellard	goto illegal_op;
2523	664e0f19	bellard	if (b == 0x77) {
2524	664e0f19	bellard	/* emms */
2525	664e0f19	bellard	gen_op_emms();
2526	664e0f19	bellard	return;
2527	664e0f19	bellard	}
2528	664e0f19	bellard	/* prepare MMX state (XXX: optimize by storing fptt and fptags in
2529	664e0f19	bellard	the static cpu state) */
2530	664e0f19	bellard	if (!is_xmm) {
2531	664e0f19	bellard	gen_op_enter_mmx();
2532	664e0f19	bellard	}
2533	664e0f19	bellard
2534	664e0f19	bellard	modrm = ldub_code(s->pc++);
2535	664e0f19	bellard	reg = ((modrm >> 3) & 7);
2536	664e0f19	bellard	if (is_xmm)
2537	664e0f19	bellard	reg \|= rex_r;
2538	664e0f19	bellard	mod = (modrm >> 6) & 3;
2539	664e0f19	bellard	if (sse_op2 == SSE_SPECIAL) {
2540	664e0f19	bellard	b \|= (b1 << 8);
2541	664e0f19	bellard	switch(b) {
2542	664e0f19	bellard	case 0x0e7: /* movntq */
2543	664e0f19	bellard	if (mod == 3)
2544	664e0f19	bellard	goto illegal_op;
2545	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2546	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2547	664e0f19	bellard	break;
2548	664e0f19	bellard	case 0x1e7: /* movntdq */
2549	664e0f19	bellard	case 0x02b: /* movntps */
2550	664e0f19	bellard	case 0x12b: /* movntps */
2551	664e0f19	bellard	case 0x2f0: /* lddqu */
2552	664e0f19	bellard	if (mod == 3)
2553	664e0f19	bellard	goto illegal_op;
2554	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2555	664e0f19	bellard	gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2556	664e0f19	bellard	break;
2557	664e0f19	bellard	case 0x6e: /* movd mm, ea */
2558	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2559	664e0f19	bellard	gen_op_movl_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2560	664e0f19	bellard	break;
2561	664e0f19	bellard	case 0x16e: /* movd xmm, ea */
2562	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2563	664e0f19	bellard	gen_op_movl_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2564	664e0f19	bellard	break;
2565	664e0f19	bellard	case 0x6f: /* movq mm, ea */
2566	664e0f19	bellard	if (mod != 3) {
2567	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2568	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2569	664e0f19	bellard	} else {
2570	664e0f19	bellard	rm = (modrm & 7);
2571	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx),
2572	664e0f19	bellard	offsetof(CPUX86State,fpregs[rm].mmx));
2573	664e0f19	bellard	}
2574	664e0f19	bellard	break;
2575	664e0f19	bellard	case 0x010: /* movups */
2576	664e0f19	bellard	case 0x110: /* movupd */
2577	664e0f19	bellard	case 0x028: /* movaps */
2578	664e0f19	bellard	case 0x128: /* movapd */
2579	664e0f19	bellard	case 0x16f: /* movdqa xmm, ea */
2580	664e0f19	bellard	case 0x26f: /* movdqu xmm, ea */
2581	664e0f19	bellard	if (mod != 3) {
2582	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2583	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2584	664e0f19	bellard	} else {
2585	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2586	664e0f19	bellard	gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
2587	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm]));
2588	664e0f19	bellard	}
2589	664e0f19	bellard	break;
2590	664e0f19	bellard	case 0x210: /* movss xmm, ea */
2591	664e0f19	bellard	if (mod != 3) {
2592	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2593	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2594	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2595	664e0f19	bellard	gen_op_movl_T0_0();
2596	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2597	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2598	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2599	664e0f19	bellard	} else {
2600	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2601	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2602	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
2603	664e0f19	bellard	}
2604	664e0f19	bellard	break;
2605	664e0f19	bellard	case 0x310: /* movsd xmm, ea */
2606	664e0f19	bellard	if (mod != 3) {
2607	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2608	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2609	664e0f19	bellard	gen_op_movl_T0_0();
2610	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2611	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2612	664e0f19	bellard	} else {
2613	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2614	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2615	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2616	664e0f19	bellard	}
2617	664e0f19	bellard	break;
2618	664e0f19	bellard	case 0x012: /* movlps */
2619	664e0f19	bellard	case 0x112: /* movlpd */
2620	664e0f19	bellard	if (mod != 3) {
2621	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2622	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2623	664e0f19	bellard	} else {
2624	664e0f19	bellard	/* movhlps */
2625	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2626	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2627	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2628	664e0f19	bellard	}
2629	664e0f19	bellard	break;
2630	664e0f19	bellard	case 0x016: /* movhps */
2631	664e0f19	bellard	case 0x116: /* movhpd */
2632	664e0f19	bellard	if (mod != 3) {
2633	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2634	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2635	664e0f19	bellard	} else {
2636	664e0f19	bellard	/* movlhps */
2637	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2638	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
2639	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2640	664e0f19	bellard	}
2641	664e0f19	bellard	break;
2642	664e0f19	bellard	case 0x216: /* movshdup */
2643	664e0f19	bellard	if (mod != 3) {
2644	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2645	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2646	664e0f19	bellard	} else {
2647	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2648	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
2649	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
2650	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
2651	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
2652	664e0f19	bellard	}
2653	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2654	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2655	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
2656	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2657	664e0f19	bellard	break;
2658	664e0f19	bellard	case 0x7e: /* movd ea, mm */
2659	664e0f19	bellard	gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2660	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2661	664e0f19	bellard	break;
2662	664e0f19	bellard	case 0x17e: /* movd ea, xmm */
2663	664e0f19	bellard	gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2664	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2665	664e0f19	bellard	break;
2666	664e0f19	bellard	case 0x27e: /* movq xmm, ea */
2667	664e0f19	bellard	if (mod != 3) {
2668	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2669	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2670	664e0f19	bellard	} else {
2671	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2672	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2673	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2674	664e0f19	bellard	}
2675	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2676	664e0f19	bellard	break;
2677	664e0f19	bellard	case 0x7f: /* movq ea, mm */
2678	664e0f19	bellard	if (mod != 3) {
2679	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2680	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2681	664e0f19	bellard	} else {
2682	664e0f19	bellard	rm = (modrm & 7);
2683	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2684	664e0f19	bellard	offsetof(CPUX86State,fpregs[reg].mmx));
2685	664e0f19	bellard	}
2686	664e0f19	bellard	break;
2687	664e0f19	bellard	case 0x011: /* movups */
2688	664e0f19	bellard	case 0x111: /* movupd */
2689	664e0f19	bellard	case 0x029: /* movaps */
2690	664e0f19	bellard	case 0x129: /* movapd */
2691	664e0f19	bellard	case 0x17f: /* movdqa ea, xmm */
2692	664e0f19	bellard	case 0x27f: /* movdqu ea, xmm */
2693	664e0f19	bellard	if (mod != 3) {
2694	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2695	664e0f19	bellard	gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2696	664e0f19	bellard	} else {
2697	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2698	664e0f19	bellard	gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
2699	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg]));
2700	664e0f19	bellard	}
2701	664e0f19	bellard	break;
2702	664e0f19	bellard	case 0x211: /* movss ea, xmm */
2703	664e0f19	bellard	if (mod != 3) {
2704	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2705	664e0f19	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2706	664e0f19	bellard	gen_op_st_T0_A0[OT_LONG + s->mem_index]();
2707	664e0f19	bellard	} else {
2708	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2709	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
2710	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2711	664e0f19	bellard	}
2712	664e0f19	bellard	break;
2713	664e0f19	bellard	case 0x311: /* movsd ea, xmm */
2714	664e0f19	bellard	if (mod != 3) {
2715	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2716	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2717	664e0f19	bellard	} else {
2718	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2719	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2720	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2721	664e0f19	bellard	}
2722	664e0f19	bellard	break;
2723	664e0f19	bellard	case 0x013: /* movlps */
2724	664e0f19	bellard	case 0x113: /* movlpd */
2725	664e0f19	bellard	if (mod != 3) {
2726	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2727	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2728	664e0f19	bellard	} else {
2729	664e0f19	bellard	goto illegal_op;
2730	664e0f19	bellard	}
2731	664e0f19	bellard	break;
2732	664e0f19	bellard	case 0x017: /* movhps */
2733	664e0f19	bellard	case 0x117: /* movhpd */
2734	664e0f19	bellard	if (mod != 3) {
2735	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2736	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2737	664e0f19	bellard	} else {
2738	664e0f19	bellard	goto illegal_op;
2739	664e0f19	bellard	}
2740	664e0f19	bellard	break;
2741	664e0f19	bellard	case 0x71: /* shift mm, im */
2742	664e0f19	bellard	case 0x72:
2743	664e0f19	bellard	case 0x73:
2744	664e0f19	bellard	case 0x171: /* shift xmm, im */
2745	664e0f19	bellard	case 0x172:
2746	664e0f19	bellard	case 0x173:
2747	664e0f19	bellard	val = ldub_code(s->pc++);
2748	664e0f19	bellard	if (is_xmm) {
2749	664e0f19	bellard	gen_op_movl_T0_im(val);
2750	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2751	664e0f19	bellard	gen_op_movl_T0_0();
2752	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
2753	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_t0);
2754	664e0f19	bellard	} else {
2755	664e0f19	bellard	gen_op_movl_T0_im(val);
2756	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
2757	664e0f19	bellard	gen_op_movl_T0_0();
2758	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
2759	664e0f19	bellard	op1_offset = offsetof(CPUX86State,mmx_t0);
2760	664e0f19	bellard	}
2761	664e0f19	bellard	sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
2762	664e0f19	bellard	if (!sse_op2)
2763	664e0f19	bellard	goto illegal_op;
2764	664e0f19	bellard	if (is_xmm) {
2765	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2766	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2767	664e0f19	bellard	} else {
2768	664e0f19	bellard	rm = (modrm & 7);
2769	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2770	664e0f19	bellard	}
2771	664e0f19	bellard	sse_op2(op2_offset, op1_offset);
2772	664e0f19	bellard	break;
2773	664e0f19	bellard	case 0x050: /* movmskps */
2774	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2775	31313213	bellard	gen_op_movmskps(offsetof(CPUX86State,xmm_regs[rm]));
2776	31313213	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2777	664e0f19	bellard	break;
2778	664e0f19	bellard	case 0x150: /* movmskpd */
2779	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2780	31313213	bellard	gen_op_movmskpd(offsetof(CPUX86State,xmm_regs[rm]));
2781	31313213	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2782	664e0f19	bellard	break;
2783	664e0f19	bellard	case 0x02a: /* cvtpi2ps */
2784	664e0f19	bellard	case 0x12a: /* cvtpi2pd */
2785	664e0f19	bellard	gen_op_enter_mmx();
2786	664e0f19	bellard	if (mod != 3) {
2787	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2788	664e0f19	bellard	op2_offset = offsetof(CPUX86State,mmx_t0);
2789	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2790	664e0f19	bellard	} else {
2791	664e0f19	bellard	rm = (modrm & 7);
2792	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2793	664e0f19	bellard	}
2794	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2795	664e0f19	bellard	switch(b >> 8) {
2796	664e0f19	bellard	case 0x0:
2797	664e0f19	bellard	gen_op_cvtpi2ps(op1_offset, op2_offset);
2798	664e0f19	bellard	break;
2799	664e0f19	bellard	default:
2800	664e0f19	bellard	case 0x1:
2801	664e0f19	bellard	gen_op_cvtpi2pd(op1_offset, op2_offset);
2802	664e0f19	bellard	break;
2803	664e0f19	bellard	}
2804	664e0f19	bellard	break;
2805	664e0f19	bellard	case 0x22a: /* cvtsi2ss */
2806	664e0f19	bellard	case 0x32a: /* cvtsi2sd */
2807	664e0f19	bellard	ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2808	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2809	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2810	664e0f19	bellard	sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)](op1_offset);
2811	664e0f19	bellard	break;
2812	664e0f19	bellard	case 0x02c: /* cvttps2pi */
2813	664e0f19	bellard	case 0x12c: /* cvttpd2pi */
2814	664e0f19	bellard	case 0x02d: /* cvtps2pi */
2815	664e0f19	bellard	case 0x12d: /* cvtpd2pi */
2816	664e0f19	bellard	gen_op_enter_mmx();
2817	664e0f19	bellard	if (mod != 3) {
2818	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2819	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2820	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2821	664e0f19	bellard	} else {
2822	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2823	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2824	664e0f19	bellard	}
2825	664e0f19	bellard	op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
2826	664e0f19	bellard	switch(b) {
2827	664e0f19	bellard	case 0x02c:
2828	664e0f19	bellard	gen_op_cvttps2pi(op1_offset, op2_offset);
2829	664e0f19	bellard	break;
2830	664e0f19	bellard	case 0x12c:
2831	664e0f19	bellard	gen_op_cvttpd2pi(op1_offset, op2_offset);
2832	664e0f19	bellard	break;
2833	664e0f19	bellard	case 0x02d:
2834	664e0f19	bellard	gen_op_cvtps2pi(op1_offset, op2_offset);
2835	664e0f19	bellard	break;
2836	664e0f19	bellard	case 0x12d:
2837	664e0f19	bellard	gen_op_cvtpd2pi(op1_offset, op2_offset);
2838	664e0f19	bellard	break;
2839	664e0f19	bellard	}
2840	664e0f19	bellard	break;
2841	664e0f19	bellard	case 0x22c: /* cvttss2si */
2842	664e0f19	bellard	case 0x32c: /* cvttsd2si */
2843	664e0f19	bellard	case 0x22d: /* cvtss2si */
2844	664e0f19	bellard	case 0x32d: /* cvtsd2si */
2845	664e0f19	bellard	ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2846	31313213	bellard	if (mod != 3) {
2847	31313213	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2848	31313213	bellard	if ((b >> 8) & 1) {
2849	31313213	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
2850	31313213	bellard	} else {
2851	31313213	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2852	31313213	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2853	31313213	bellard	}
2854	31313213	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2855	31313213	bellard	} else {
2856	31313213	bellard	rm = (modrm & 7) \| REX_B(s);
2857	31313213	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2858	31313213	bellard	}
2859	664e0f19	bellard	sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
2860	31313213	bellard	(b & 1) * 4](op2_offset);
2861	31313213	bellard	gen_op_mov_reg_T0[ot][reg]();
2862	664e0f19	bellard	break;
2863	664e0f19	bellard	case 0xc4: /* pinsrw */
2864	664e0f19	bellard	case 0x1c4:
2865	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2866	664e0f19	bellard	val = ldub_code(s->pc++);
2867	664e0f19	bellard	if (b1) {
2868	664e0f19	bellard	val &= 7;
2869	664e0f19	bellard	gen_op_pinsrw_xmm(offsetof(CPUX86State,xmm_regs[reg]), val);
2870	664e0f19	bellard	} else {
2871	664e0f19	bellard	val &= 3;
2872	664e0f19	bellard	gen_op_pinsrw_mmx(offsetof(CPUX86State,fpregs[reg].mmx), val);
2873	664e0f19	bellard	}
2874	664e0f19	bellard	break;
2875	664e0f19	bellard	case 0xc5: /* pextrw */
2876	664e0f19	bellard	case 0x1c5:
2877	664e0f19	bellard	if (mod != 3)
2878	664e0f19	bellard	goto illegal_op;
2879	664e0f19	bellard	val = ldub_code(s->pc++);
2880	664e0f19	bellard	if (b1) {
2881	664e0f19	bellard	val &= 7;
2882	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2883	664e0f19	bellard	gen_op_pextrw_xmm(offsetof(CPUX86State,xmm_regs[rm]), val);
2884	664e0f19	bellard	} else {
2885	664e0f19	bellard	val &= 3;
2886	664e0f19	bellard	rm = (modrm & 7);
2887	664e0f19	bellard	gen_op_pextrw_mmx(offsetof(CPUX86State,fpregs[rm].mmx), val);
2888	664e0f19	bellard	}
2889	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
2890	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2891	664e0f19	bellard	break;
2892	664e0f19	bellard	case 0x1d6: /* movq ea, xmm */
2893	664e0f19	bellard	if (mod != 3) {
2894	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2895	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2896	664e0f19	bellard	} else {
2897	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2898	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2899	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2900	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2901	664e0f19	bellard	}
2902	664e0f19	bellard	break;
2903	664e0f19	bellard	case 0x2d6: /* movq2dq */
2904	664e0f19	bellard	gen_op_enter_mmx();
2905	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2906	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2907	664e0f19	bellard	offsetof(CPUX86State,fpregs[reg & 7].mmx));
2908	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2909	664e0f19	bellard	break;
2910	664e0f19	bellard	case 0x3d6: /* movdq2q */
2911	664e0f19	bellard	gen_op_enter_mmx();
2912	664e0f19	bellard	rm = (modrm & 7);
2913	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2914	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2915	664e0f19	bellard	break;
2916	664e0f19	bellard	case 0xd7: /* pmovmskb */
2917	664e0f19	bellard	case 0x1d7:
2918	664e0f19	bellard	if (mod != 3)
2919	664e0f19	bellard	goto illegal_op;
2920	664e0f19	bellard	if (b1) {
2921	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2922	664e0f19	bellard	gen_op_pmovmskb_xmm(offsetof(CPUX86State,xmm_regs[rm]));
2923	664e0f19	bellard	} else {
2924	664e0f19	bellard	rm = (modrm & 7);
2925	664e0f19	bellard	gen_op_pmovmskb_mmx(offsetof(CPUX86State,fpregs[rm].mmx));
2926	664e0f19	bellard	}
2927	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
2928	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2929	664e0f19	bellard	break;
2930	664e0f19	bellard	default:
2931	664e0f19	bellard	goto illegal_op;
2932	664e0f19	bellard	}
2933	664e0f19	bellard	} else {
2934	664e0f19	bellard	/* generic MMX or SSE operation */
2935	664e0f19	bellard	if (b == 0xf7) {
2936	664e0f19	bellard	/* maskmov : we must prepare A0 */
2937	664e0f19	bellard	if (mod != 3)
2938	664e0f19	bellard	goto illegal_op;
2939	664e0f19	bellard	#ifdef TARGET_X86_64
2940	8f091a59	bellard	if (s->aflag == 2) {
2941	664e0f19	bellard	gen_op_movq_A0_reg[R_EDI]();
2942	664e0f19	bellard	} else
2943	664e0f19	bellard	#endif
2944	664e0f19	bellard	{
2945	664e0f19	bellard	gen_op_movl_A0_reg[R_EDI]();
2946	664e0f19	bellard	if (s->aflag == 0)
2947	664e0f19	bellard	gen_op_andl_A0_ffff();
2948	664e0f19	bellard	}
2949	664e0f19	bellard	gen_add_A0_ds_seg(s);
2950	664e0f19	bellard	}
2951	664e0f19	bellard	if (is_xmm) {
2952	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2953	664e0f19	bellard	if (mod != 3) {
2954	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2955	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2956	664e0f19	bellard	if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f) \|\|
2957	664e0f19	bellard	b == 0xc2)) {
2958	664e0f19	bellard	/* specific case for SSE single instructions */
2959	664e0f19	bellard	if (b1 == 2) {
2960	664e0f19	bellard	/* 32 bit access */
2961	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2962	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2963	664e0f19	bellard	} else {
2964	664e0f19	bellard	/* 64 bit access */
2965	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_D(0)));
2966	664e0f19	bellard	}
2967	664e0f19	bellard	} else {
2968	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2969	664e0f19	bellard	}
2970	664e0f19	bellard	} else {
2971	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2972	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2973	664e0f19	bellard	}
2974	664e0f19	bellard	} else {
2975	664e0f19	bellard	op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
2976	664e0f19	bellard	if (mod != 3) {
2977	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2978	664e0f19	bellard	op2_offset = offsetof(CPUX86State,mmx_t0);
2979	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2980	664e0f19	bellard	} else {
2981	664e0f19	bellard	rm = (modrm & 7);
2982	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2983	664e0f19	bellard	}
2984	664e0f19	bellard	}
2985	664e0f19	bellard	switch(b) {
2986	664e0f19	bellard	case 0x70: /* pshufx insn */
2987	664e0f19	bellard	case 0xc6: /* pshufx insn */
2988	664e0f19	bellard	val = ldub_code(s->pc++);
2989	664e0f19	bellard	sse_op3 = (GenOpFunc3 *)sse_op2;
2990	664e0f19	bellard	sse_op3(op1_offset, op2_offset, val);
2991	664e0f19	bellard	break;
2992	664e0f19	bellard	case 0xc2:
2993	664e0f19	bellard	/* compare insns */
2994	664e0f19	bellard	val = ldub_code(s->pc++);
2995	664e0f19	bellard	if (val >= 8)
2996	664e0f19	bellard	goto illegal_op;
2997	664e0f19	bellard	sse_op2 = sse_op_table4[val][b1];
2998	664e0f19	bellard	sse_op2(op1_offset, op2_offset);
2999	664e0f19	bellard	break;
3000	664e0f19	bellard	default:
3001	664e0f19	bellard	sse_op2(op1_offset, op2_offset);
3002	664e0f19	bellard	break;
3003	664e0f19	bellard	}
3004	664e0f19	bellard	if (b == 0x2e \|\| b == 0x2f) {
3005	664e0f19	bellard	s->cc_op = CC_OP_EFLAGS;
3006	664e0f19	bellard	}
3007	664e0f19	bellard	}
3008	664e0f19	bellard	}
3009	664e0f19	bellard
3010	664e0f19	bellard
3011	2c0262af	bellard	/* convert one instruction. s->is_jmp is set if the translation must
3012	2c0262af	bellard	be stopped. Return the next pc value */
3013	14ce26e7	bellard	static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3014	2c0262af	bellard	{
3015	2c0262af	bellard	int b, prefixes, aflag, dflag;
3016	2c0262af	bellard	int shift, ot;
3017	2c0262af	bellard	int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3018	14ce26e7	bellard	target_ulong next_eip, tval;
3019	14ce26e7	bellard	int rex_w, rex_r;
3020	2c0262af	bellard
3021	2c0262af	bellard	s->pc = pc_start;
3022	2c0262af	bellard	prefixes = 0;
3023	2c0262af	bellard	aflag = s->code32;
3024	2c0262af	bellard	dflag = s->code32;
3025	2c0262af	bellard	s->override = -1;
3026	14ce26e7	bellard	rex_w = -1;
3027	14ce26e7	bellard	rex_r = 0;
3028	14ce26e7	bellard	#ifdef TARGET_X86_64
3029	14ce26e7	bellard	s->rex_x = 0;
3030	14ce26e7	bellard	s->rex_b = 0;
3031	14ce26e7	bellard	x86_64_hregs = 0;
3032	14ce26e7	bellard	#endif
3033	14ce26e7	bellard	s->rip_offset = 0; /* for relative ip address */
3034	2c0262af	bellard	next_byte:
3035	61382a50	bellard	b = ldub_code(s->pc);
3036	2c0262af	bellard	s->pc++;
3037	2c0262af	bellard	/* check prefixes */
3038	14ce26e7	bellard	#ifdef TARGET_X86_64
3039	14ce26e7	bellard	if (CODE64(s)) {
3040	14ce26e7	bellard	switch (b) {
3041	14ce26e7	bellard	case 0xf3:
3042	14ce26e7	bellard	prefixes \|= PREFIX_REPZ;
3043	14ce26e7	bellard	goto next_byte;
3044	14ce26e7	bellard	case 0xf2:
3045	14ce26e7	bellard	prefixes \|= PREFIX_REPNZ;
3046	14ce26e7	bellard	goto next_byte;
3047	14ce26e7	bellard	case 0xf0:
3048	14ce26e7	bellard	prefixes \|= PREFIX_LOCK;
3049	14ce26e7	bellard	goto next_byte;
3050	14ce26e7	bellard	case 0x2e:
3051	14ce26e7	bellard	s->override = R_CS;
3052	14ce26e7	bellard	goto next_byte;
3053	14ce26e7	bellard	case 0x36:
3054	14ce26e7	bellard	s->override = R_SS;
3055	14ce26e7	bellard	goto next_byte;
3056	14ce26e7	bellard	case 0x3e:
3057	14ce26e7	bellard	s->override = R_DS;
3058	14ce26e7	bellard	goto next_byte;
3059	14ce26e7	bellard	case 0x26:
3060	14ce26e7	bellard	s->override = R_ES;
3061	14ce26e7	bellard	goto next_byte;
3062	14ce26e7	bellard	case 0x64:
3063	14ce26e7	bellard	s->override = R_FS;
3064	14ce26e7	bellard	goto next_byte;
3065	14ce26e7	bellard	case 0x65:
3066	14ce26e7	bellard	s->override = R_GS;
3067	14ce26e7	bellard	goto next_byte;
3068	14ce26e7	bellard	case 0x66:
3069	14ce26e7	bellard	prefixes \|= PREFIX_DATA;
3070	14ce26e7	bellard	goto next_byte;
3071	14ce26e7	bellard	case 0x67:
3072	14ce26e7	bellard	prefixes \|= PREFIX_ADR;
3073	14ce26e7	bellard	goto next_byte;
3074	14ce26e7	bellard	case 0x40 ... 0x4f:
3075	14ce26e7	bellard	/* REX prefix */
3076	14ce26e7	bellard	rex_w = (b >> 3) & 1;
3077	14ce26e7	bellard	rex_r = (b & 0x4) << 1;
3078	14ce26e7	bellard	s->rex_x = (b & 0x2) << 2;
3079	14ce26e7	bellard	REX_B(s) = (b & 0x1) << 3;
3080	14ce26e7	bellard	x86_64_hregs = 1; /* select uniform byte register addressing */
3081	14ce26e7	bellard	goto next_byte;
3082	14ce26e7	bellard	}
3083	14ce26e7	bellard	if (rex_w == 1) {
3084	14ce26e7	bellard	/* 0x66 is ignored if rex.w is set */
3085	14ce26e7	bellard	dflag = 2;
3086	14ce26e7	bellard	} else {
3087	14ce26e7	bellard	if (prefixes & PREFIX_DATA)
3088	14ce26e7	bellard	dflag ^= 1;
3089	14ce26e7	bellard	}
3090	14ce26e7	bellard	if (!(prefixes & PREFIX_ADR))
3091	14ce26e7	bellard	aflag = 2;
3092	14ce26e7	bellard	} else
3093	14ce26e7	bellard	#endif
3094	14ce26e7	bellard	{
3095	14ce26e7	bellard	switch (b) {
3096	14ce26e7	bellard	case 0xf3:
3097	14ce26e7	bellard	prefixes \|= PREFIX_REPZ;
3098	14ce26e7	bellard	goto next_byte;
3099	14ce26e7	bellard	case 0xf2:
3100	14ce26e7	bellard	prefixes \|= PREFIX_REPNZ;
3101	14ce26e7	bellard	goto next_byte;
3102	14ce26e7	bellard	case 0xf0:
3103	14ce26e7	bellard	prefixes \|= PREFIX_LOCK;
3104	14ce26e7	bellard	goto next_byte;
3105	14ce26e7	bellard	case 0x2e:
3106	14ce26e7	bellard	s->override = R_CS;
3107	14ce26e7	bellard	goto next_byte;
3108	14ce26e7	bellard	case 0x36:
3109	14ce26e7	bellard	s->override = R_SS;
3110	14ce26e7	bellard	goto next_byte;
3111	14ce26e7	bellard	case 0x3e:
3112	14ce26e7	bellard	s->override = R_DS;
3113	14ce26e7	bellard	goto next_byte;
3114	14ce26e7	bellard	case 0x26:
3115	14ce26e7	bellard	s->override = R_ES;
3116	14ce26e7	bellard	goto next_byte;
3117	14ce26e7	bellard	case 0x64:
3118	14ce26e7	bellard	s->override = R_FS;
3119	14ce26e7	bellard	goto next_byte;
3120	14ce26e7	bellard	case 0x65:
3121	14ce26e7	bellard	s->override = R_GS;
3122	14ce26e7	bellard	goto next_byte;
3123	14ce26e7	bellard	case 0x66:
3124	14ce26e7	bellard	prefixes \|= PREFIX_DATA;
3125	14ce26e7	bellard	goto next_byte;
3126	14ce26e7	bellard	case 0x67:
3127	14ce26e7	bellard	prefixes \|= PREFIX_ADR;
3128	14ce26e7	bellard	goto next_byte;
3129	14ce26e7	bellard	}
3130	14ce26e7	bellard	if (prefixes & PREFIX_DATA)
3131	14ce26e7	bellard	dflag ^= 1;
3132	14ce26e7	bellard	if (prefixes & PREFIX_ADR)
3133	14ce26e7	bellard	aflag ^= 1;
3134	2c0262af	bellard	}
3135	2c0262af	bellard
3136	2c0262af	bellard	s->prefix = prefixes;
3137	2c0262af	bellard	s->aflag = aflag;
3138	2c0262af	bellard	s->dflag = dflag;
3139	2c0262af	bellard
3140	2c0262af	bellard	/* lock generation */
3141	2c0262af	bellard	if (prefixes & PREFIX_LOCK)
3142	2c0262af	bellard	gen_op_lock();
3143	2c0262af	bellard
3144	2c0262af	bellard	/* now check op code */
3145	2c0262af	bellard	reswitch:
3146	2c0262af	bellard	switch(b) {
3147	2c0262af	bellard	case 0x0f:
3148	2c0262af	bellard	/**************************/
3149	2c0262af	bellard	/* extended op code */
3150	61382a50	bellard	b = ldub_code(s->pc++) \| 0x100;
3151	2c0262af	bellard	goto reswitch;
3152	2c0262af	bellard
3153	2c0262af	bellard	/**************************/
3154	2c0262af	bellard	/* arith & logic */
3155	2c0262af	bellard	case 0x00 ... 0x05:
3156	2c0262af	bellard	case 0x08 ... 0x0d:
3157	2c0262af	bellard	case 0x10 ... 0x15:
3158	2c0262af	bellard	case 0x18 ... 0x1d:
3159	2c0262af	bellard	case 0x20 ... 0x25:
3160	2c0262af	bellard	case 0x28 ... 0x2d:
3161	2c0262af	bellard	case 0x30 ... 0x35:
3162	2c0262af	bellard	case 0x38 ... 0x3d:
3163	2c0262af	bellard	{
3164	2c0262af	bellard	int op, f, val;
3165	2c0262af	bellard	op = (b >> 3) & 7;
3166	2c0262af	bellard	f = (b >> 1) & 3;
3167	2c0262af	bellard
3168	2c0262af	bellard	if ((b & 1) == 0)
3169	2c0262af	bellard	ot = OT_BYTE;
3170	2c0262af	bellard	else
3171	14ce26e7	bellard	ot = dflag + OT_WORD;
3172	2c0262af	bellard
3173	2c0262af	bellard	switch(f) {
3174	2c0262af	bellard	case 0: /* OP Ev, Gv */
3175	61382a50	bellard	modrm = ldub_code(s->pc++);
3176	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3177	2c0262af	bellard	mod = (modrm >> 6) & 3;
3178	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3179	2c0262af	bellard	if (mod != 3) {
3180	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3181	2c0262af	bellard	opreg = OR_TMP0;
3182	2c0262af	bellard	} else if (op == OP_XORL && rm == reg) {
3183	2c0262af	bellard	xor_zero:
3184	2c0262af	bellard	/* xor reg, reg optimisation */
3185	2c0262af	bellard	gen_op_movl_T0_0();
3186	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3187	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3188	2c0262af	bellard	gen_op_update1_cc();
3189	2c0262af	bellard	break;
3190	2c0262af	bellard	} else {
3191	2c0262af	bellard	opreg = rm;
3192	2c0262af	bellard	}
3193	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3194	2c0262af	bellard	gen_op(s, op, ot, opreg);
3195	2c0262af	bellard	break;
3196	2c0262af	bellard	case 1: /* OP Gv, Ev */
3197	61382a50	bellard	modrm = ldub_code(s->pc++);
3198	2c0262af	bellard	mod = (modrm >> 6) & 3;
3199	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3200	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3201	2c0262af	bellard	if (mod != 3) {
3202	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3203	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3204	2c0262af	bellard	} else if (op == OP_XORL && rm == reg) {
3205	2c0262af	bellard	goto xor_zero;
3206	2c0262af	bellard	} else {
3207	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3208	2c0262af	bellard	}
3209	2c0262af	bellard	gen_op(s, op, ot, reg);
3210	2c0262af	bellard	break;
3211	2c0262af	bellard	case 2: /* OP A, Iv */
3212	2c0262af	bellard	val = insn_get(s, ot);
3213	2c0262af	bellard	gen_op_movl_T1_im(val);
3214	2c0262af	bellard	gen_op(s, op, ot, OR_EAX);
3215	2c0262af	bellard	break;
3216	2c0262af	bellard	}
3217	2c0262af	bellard	}
3218	2c0262af	bellard	break;
3219	2c0262af	bellard
3220	2c0262af	bellard	case 0x80: /* GRP1 */
3221	2c0262af	bellard	case 0x81:
3222	d64477af	bellard	case 0x82:
3223	2c0262af	bellard	case 0x83:
3224	2c0262af	bellard	{
3225	2c0262af	bellard	int val;
3226	2c0262af	bellard
3227	2c0262af	bellard	if ((b & 1) == 0)
3228	2c0262af	bellard	ot = OT_BYTE;
3229	2c0262af	bellard	else
3230	14ce26e7	bellard	ot = dflag + OT_WORD;
3231	2c0262af	bellard
3232	61382a50	bellard	modrm = ldub_code(s->pc++);
3233	2c0262af	bellard	mod = (modrm >> 6) & 3;
3234	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3235	2c0262af	bellard	op = (modrm >> 3) & 7;
3236	2c0262af	bellard
3237	2c0262af	bellard	if (mod != 3) {
3238	14ce26e7	bellard	if (b == 0x83)
3239	14ce26e7	bellard	s->rip_offset = 1;
3240	14ce26e7	bellard	else
3241	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3242	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3243	2c0262af	bellard	opreg = OR_TMP0;
3244	2c0262af	bellard	} else {
3245	14ce26e7	bellard	opreg = rm;
3246	2c0262af	bellard	}
3247	2c0262af	bellard
3248	2c0262af	bellard	switch(b) {
3249	2c0262af	bellard	default:
3250	2c0262af	bellard	case 0x80:
3251	2c0262af	bellard	case 0x81:
3252	d64477af	bellard	case 0x82:
3253	2c0262af	bellard	val = insn_get(s, ot);
3254	2c0262af	bellard	break;
3255	2c0262af	bellard	case 0x83:
3256	2c0262af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3257	2c0262af	bellard	break;
3258	2c0262af	bellard	}
3259	2c0262af	bellard	gen_op_movl_T1_im(val);
3260	2c0262af	bellard	gen_op(s, op, ot, opreg);
3261	2c0262af	bellard	}
3262	2c0262af	bellard	break;
3263	2c0262af	bellard
3264	2c0262af	bellard	/**************************/
3265	2c0262af	bellard	/* inc, dec, and other misc arith */
3266	2c0262af	bellard	case 0x40 ... 0x47: /* inc Gv */
3267	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
3268	2c0262af	bellard	gen_inc(s, ot, OR_EAX + (b & 7), 1);
3269	2c0262af	bellard	break;
3270	2c0262af	bellard	case 0x48 ... 0x4f: /* dec Gv */
3271	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
3272	2c0262af	bellard	gen_inc(s, ot, OR_EAX + (b & 7), -1);
3273	2c0262af	bellard	break;
3274	2c0262af	bellard	case 0xf6: /* GRP3 */
3275	2c0262af	bellard	case 0xf7:
3276	2c0262af	bellard	if ((b & 1) == 0)
3277	2c0262af	bellard	ot = OT_BYTE;
3278	2c0262af	bellard	else
3279	14ce26e7	bellard	ot = dflag + OT_WORD;
3280	2c0262af	bellard
3281	61382a50	bellard	modrm = ldub_code(s->pc++);
3282	2c0262af	bellard	mod = (modrm >> 6) & 3;
3283	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3284	2c0262af	bellard	op = (modrm >> 3) & 7;
3285	2c0262af	bellard	if (mod != 3) {
3286	14ce26e7	bellard	if (op == 0)
3287	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3288	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3289	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3290	2c0262af	bellard	} else {
3291	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3292	2c0262af	bellard	}
3293	2c0262af	bellard
3294	2c0262af	bellard	switch(op) {
3295	2c0262af	bellard	case 0: /* test */
3296	2c0262af	bellard	val = insn_get(s, ot);
3297	2c0262af	bellard	gen_op_movl_T1_im(val);
3298	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3299	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3300	2c0262af	bellard	break;
3301	2c0262af	bellard	case 2: /* not */
3302	2c0262af	bellard	gen_op_notl_T0();
3303	2c0262af	bellard	if (mod != 3) {
3304	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3305	2c0262af	bellard	} else {
3306	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3307	2c0262af	bellard	}
3308	2c0262af	bellard	break;
3309	2c0262af	bellard	case 3: /* neg */
3310	2c0262af	bellard	gen_op_negl_T0();
3311	2c0262af	bellard	if (mod != 3) {
3312	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3313	2c0262af	bellard	} else {
3314	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3315	2c0262af	bellard	}
3316	2c0262af	bellard	gen_op_update_neg_cc();
3317	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
3318	2c0262af	bellard	break;
3319	2c0262af	bellard	case 4: /* mul */
3320	2c0262af	bellard	switch(ot) {
3321	2c0262af	bellard	case OT_BYTE:
3322	2c0262af	bellard	gen_op_mulb_AL_T0();
3323	d36cd60e	bellard	s->cc_op = CC_OP_MULB;
3324	2c0262af	bellard	break;
3325	2c0262af	bellard	case OT_WORD:
3326	2c0262af	bellard	gen_op_mulw_AX_T0();
3327	d36cd60e	bellard	s->cc_op = CC_OP_MULW;
3328	2c0262af	bellard	break;
3329	2c0262af	bellard	default:
3330	2c0262af	bellard	case OT_LONG:
3331	2c0262af	bellard	gen_op_mull_EAX_T0();
3332	d36cd60e	bellard	s->cc_op = CC_OP_MULL;
3333	2c0262af	bellard	break;
3334	14ce26e7	bellard	#ifdef TARGET_X86_64
3335	14ce26e7	bellard	case OT_QUAD:
3336	14ce26e7	bellard	gen_op_mulq_EAX_T0();
3337	14ce26e7	bellard	s->cc_op = CC_OP_MULQ;
3338	14ce26e7	bellard	break;
3339	14ce26e7	bellard	#endif
3340	2c0262af	bellard	}
3341	2c0262af	bellard	break;
3342	2c0262af	bellard	case 5: /* imul */
3343	2c0262af	bellard	switch(ot) {
3344	2c0262af	bellard	case OT_BYTE:
3345	2c0262af	bellard	gen_op_imulb_AL_T0();
3346	d36cd60e	bellard	s->cc_op = CC_OP_MULB;
3347	2c0262af	bellard	break;
3348	2c0262af	bellard	case OT_WORD:
3349	2c0262af	bellard	gen_op_imulw_AX_T0();
3350	d36cd60e	bellard	s->cc_op = CC_OP_MULW;
3351	2c0262af	bellard	break;
3352	2c0262af	bellard	default:
3353	2c0262af	bellard	case OT_LONG:
3354	2c0262af	bellard	gen_op_imull_EAX_T0();
3355	d36cd60e	bellard	s->cc_op = CC_OP_MULL;
3356	2c0262af	bellard	break;
3357	14ce26e7	bellard	#ifdef TARGET_X86_64
3358	14ce26e7	bellard	case OT_QUAD:
3359	14ce26e7	bellard	gen_op_imulq_EAX_T0();
3360	14ce26e7	bellard	s->cc_op = CC_OP_MULQ;
3361	14ce26e7	bellard	break;
3362	14ce26e7	bellard	#endif
3363	2c0262af	bellard	}
3364	2c0262af	bellard	break;
3365	2c0262af	bellard	case 6: /* div */
3366	2c0262af	bellard	switch(ot) {
3367	2c0262af	bellard	case OT_BYTE:
3368	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3369	14ce26e7	bellard	gen_op_divb_AL_T0();
3370	2c0262af	bellard	break;
3371	2c0262af	bellard	case OT_WORD:
3372	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3373	14ce26e7	bellard	gen_op_divw_AX_T0();
3374	2c0262af	bellard	break;
3375	2c0262af	bellard	default:
3376	2c0262af	bellard	case OT_LONG:
3377	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3378	14ce26e7	bellard	gen_op_divl_EAX_T0();
3379	14ce26e7	bellard	break;
3380	14ce26e7	bellard	#ifdef TARGET_X86_64
3381	14ce26e7	bellard	case OT_QUAD:
3382	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3383	14ce26e7	bellard	gen_op_divq_EAX_T0();
3384	2c0262af	bellard	break;
3385	14ce26e7	bellard	#endif
3386	2c0262af	bellard	}
3387	2c0262af	bellard	break;
3388	2c0262af	bellard	case 7: /* idiv */
3389	2c0262af	bellard	switch(ot) {
3390	2c0262af	bellard	case OT_BYTE:
3391	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3392	14ce26e7	bellard	gen_op_idivb_AL_T0();
3393	2c0262af	bellard	break;
3394	2c0262af	bellard	case OT_WORD:
3395	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3396	14ce26e7	bellard	gen_op_idivw_AX_T0();
3397	2c0262af	bellard	break;
3398	2c0262af	bellard	default:
3399	2c0262af	bellard	case OT_LONG:
3400	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3401	14ce26e7	bellard	gen_op_idivl_EAX_T0();
3402	14ce26e7	bellard	break;
3403	14ce26e7	bellard	#ifdef TARGET_X86_64
3404	14ce26e7	bellard	case OT_QUAD:
3405	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3406	14ce26e7	bellard	gen_op_idivq_EAX_T0();
3407	2c0262af	bellard	break;
3408	14ce26e7	bellard	#endif
3409	2c0262af	bellard	}
3410	2c0262af	bellard	break;
3411	2c0262af	bellard	default:
3412	2c0262af	bellard	goto illegal_op;
3413	2c0262af	bellard	}
3414	2c0262af	bellard	break;
3415	2c0262af	bellard
3416	2c0262af	bellard	case 0xfe: /* GRP4 */
3417	2c0262af	bellard	case 0xff: /* GRP5 */
3418	2c0262af	bellard	if ((b & 1) == 0)
3419	2c0262af	bellard	ot = OT_BYTE;
3420	2c0262af	bellard	else
3421	14ce26e7	bellard	ot = dflag + OT_WORD;
3422	2c0262af	bellard
3423	61382a50	bellard	modrm = ldub_code(s->pc++);
3424	2c0262af	bellard	mod = (modrm >> 6) & 3;
3425	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3426	2c0262af	bellard	op = (modrm >> 3) & 7;
3427	2c0262af	bellard	if (op >= 2 && b == 0xfe) {
3428	2c0262af	bellard	goto illegal_op;
3429	2c0262af	bellard	}
3430	14ce26e7	bellard	if (CODE64(s)) {
3431	aba9d61e	bellard	if (op == 2 \|\| op == 4) {
3432	14ce26e7	bellard	/* operand size for jumps is 64 bit */
3433	14ce26e7	bellard	ot = OT_QUAD;
3434	aba9d61e	bellard	} else if (op == 3 \|\| op == 5) {
3435	aba9d61e	bellard	/* for call calls, the operand is 16 or 32 bit, even
3436	aba9d61e	bellard	in long mode */
3437	aba9d61e	bellard	ot = dflag ? OT_LONG : OT_WORD;
3438	14ce26e7	bellard	} else if (op == 6) {
3439	14ce26e7	bellard	/* default push size is 64 bit */
3440	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3441	14ce26e7	bellard	}
3442	14ce26e7	bellard	}
3443	2c0262af	bellard	if (mod != 3) {
3444	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3445	2c0262af	bellard	if (op >= 2 && op != 3 && op != 5)
3446	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3447	2c0262af	bellard	} else {
3448	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3449	2c0262af	bellard	}
3450	2c0262af	bellard
3451	2c0262af	bellard	switch(op) {
3452	2c0262af	bellard	case 0: /* inc Ev */
3453	2c0262af	bellard	if (mod != 3)
3454	2c0262af	bellard	opreg = OR_TMP0;
3455	2c0262af	bellard	else
3456	2c0262af	bellard	opreg = rm;
3457	2c0262af	bellard	gen_inc(s, ot, opreg, 1);
3458	2c0262af	bellard	break;
3459	2c0262af	bellard	case 1: /* dec Ev */
3460	2c0262af	bellard	if (mod != 3)
3461	2c0262af	bellard	opreg = OR_TMP0;
3462	2c0262af	bellard	else
3463	2c0262af	bellard	opreg = rm;
3464	2c0262af	bellard	gen_inc(s, ot, opreg, -1);
3465	2c0262af	bellard	break;
3466	2c0262af	bellard	case 2: /* call Ev */
3467	4f31916f	bellard	/* XXX: optimize if memory (no 'and' is necessary) */
3468	2c0262af	bellard	if (s->dflag == 0)
3469	2c0262af	bellard	gen_op_andl_T0_ffff();
3470	2c0262af	bellard	next_eip = s->pc - s->cs_base;
3471	1ef38687	bellard	gen_movtl_T1_im(next_eip);
3472	4f31916f	bellard	gen_push_T1(s);
3473	4f31916f	bellard	gen_op_jmp_T0();
3474	2c0262af	bellard	gen_eob(s);
3475	2c0262af	bellard	break;
3476	61382a50	bellard	case 3: /* lcall Ev */
3477	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3478	aba9d61e	bellard	gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
3479	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3480	2c0262af	bellard	do_lcall:
3481	2c0262af	bellard	if (s->pe && !s->vm86) {
3482	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3483	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3484	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3485	aba9d61e	bellard	gen_op_lcall_protected_T0_T1(dflag, s->pc - pc_start);
3486	2c0262af	bellard	} else {
3487	2c0262af	bellard	gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
3488	2c0262af	bellard	}
3489	2c0262af	bellard	gen_eob(s);
3490	2c0262af	bellard	break;
3491	2c0262af	bellard	case 4: /* jmp Ev */
3492	2c0262af	bellard	if (s->dflag == 0)
3493	2c0262af	bellard	gen_op_andl_T0_ffff();
3494	2c0262af	bellard	gen_op_jmp_T0();
3495	2c0262af	bellard	gen_eob(s);
3496	2c0262af	bellard	break;
3497	2c0262af	bellard	case 5: /* ljmp Ev */
3498	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3499	aba9d61e	bellard	gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
3500	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3501	2c0262af	bellard	do_ljmp:
3502	2c0262af	bellard	if (s->pe && !s->vm86) {
3503	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3504	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3505	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3506	aba9d61e	bellard	gen_op_ljmp_protected_T0_T1(s->pc - pc_start);
3507	2c0262af	bellard	} else {
3508	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3509	2c0262af	bellard	gen_op_movl_T0_T1();
3510	2c0262af	bellard	gen_op_jmp_T0();
3511	2c0262af	bellard	}
3512	2c0262af	bellard	gen_eob(s);
3513	2c0262af	bellard	break;
3514	2c0262af	bellard	case 6: /* push Ev */
3515	2c0262af	bellard	gen_push_T0(s);
3516	2c0262af	bellard	break;
3517	2c0262af	bellard	default:
3518	2c0262af	bellard	goto illegal_op;
3519	2c0262af	bellard	}
3520	2c0262af	bellard	break;
3521	2c0262af	bellard
3522	2c0262af	bellard	case 0x84: /* test Ev, Gv */
3523	2c0262af	bellard	case 0x85:
3524	2c0262af	bellard	if ((b & 1) == 0)
3525	2c0262af	bellard	ot = OT_BYTE;
3526	2c0262af	bellard	else
3527	14ce26e7	bellard	ot = dflag + OT_WORD;
3528	2c0262af	bellard
3529	61382a50	bellard	modrm = ldub_code(s->pc++);
3530	2c0262af	bellard	mod = (modrm >> 6) & 3;
3531	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3532	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3533	2c0262af	bellard
3534	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3535	14ce26e7	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3536	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3537	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3538	2c0262af	bellard	break;
3539	2c0262af	bellard
3540	2c0262af	bellard	case 0xa8: /* test eAX, Iv */
3541	2c0262af	bellard	case 0xa9:
3542	2c0262af	bellard	if ((b & 1) == 0)
3543	2c0262af	bellard	ot = OT_BYTE;
3544	2c0262af	bellard	else
3545	14ce26e7	bellard	ot = dflag + OT_WORD;
3546	2c0262af	bellard	val = insn_get(s, ot);
3547	2c0262af	bellard
3548	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][OR_EAX]();
3549	2c0262af	bellard	gen_op_movl_T1_im(val);
3550	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3551	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3552	2c0262af	bellard	break;
3553	2c0262af	bellard
3554	2c0262af	bellard	case 0x98: /* CWDE/CBW */
3555	14ce26e7	bellard	#ifdef TARGET_X86_64
3556	14ce26e7	bellard	if (dflag == 2) {
3557	14ce26e7	bellard	gen_op_movslq_RAX_EAX();
3558	14ce26e7	bellard	} else
3559	14ce26e7	bellard	#endif
3560	14ce26e7	bellard	if (dflag == 1)
3561	2c0262af	bellard	gen_op_movswl_EAX_AX();
3562	2c0262af	bellard	else
3563	2c0262af	bellard	gen_op_movsbw_AX_AL();
3564	2c0262af	bellard	break;
3565	2c0262af	bellard	case 0x99: /* CDQ/CWD */
3566	14ce26e7	bellard	#ifdef TARGET_X86_64
3567	14ce26e7	bellard	if (dflag == 2) {
3568	14ce26e7	bellard	gen_op_movsqo_RDX_RAX();
3569	14ce26e7	bellard	} else
3570	14ce26e7	bellard	#endif
3571	14ce26e7	bellard	if (dflag == 1)
3572	2c0262af	bellard	gen_op_movslq_EDX_EAX();
3573	2c0262af	bellard	else
3574	2c0262af	bellard	gen_op_movswl_DX_AX();
3575	2c0262af	bellard	break;
3576	2c0262af	bellard	case 0x1af: /* imul Gv, Ev */
3577	2c0262af	bellard	case 0x69: /* imul Gv, Ev, I */
3578	2c0262af	bellard	case 0x6b:
3579	14ce26e7	bellard	ot = dflag + OT_WORD;
3580	61382a50	bellard	modrm = ldub_code(s->pc++);
3581	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3582	14ce26e7	bellard	if (b == 0x69)
3583	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3584	14ce26e7	bellard	else if (b == 0x6b)
3585	14ce26e7	bellard	s->rip_offset = 1;
3586	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3587	2c0262af	bellard	if (b == 0x69) {
3588	2c0262af	bellard	val = insn_get(s, ot);
3589	2c0262af	bellard	gen_op_movl_T1_im(val);
3590	2c0262af	bellard	} else if (b == 0x6b) {
3591	d64477af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3592	2c0262af	bellard	gen_op_movl_T1_im(val);
3593	2c0262af	bellard	} else {
3594	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3595	2c0262af	bellard	}
3596	2c0262af	bellard
3597	14ce26e7	bellard	#ifdef TARGET_X86_64
3598	14ce26e7	bellard	if (ot == OT_QUAD) {
3599	14ce26e7	bellard	gen_op_imulq_T0_T1();
3600	14ce26e7	bellard	} else
3601	14ce26e7	bellard	#endif
3602	2c0262af	bellard	if (ot == OT_LONG) {
3603	2c0262af	bellard	gen_op_imull_T0_T1();
3604	2c0262af	bellard	} else {
3605	2c0262af	bellard	gen_op_imulw_T0_T1();
3606	2c0262af	bellard	}
3607	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3608	d36cd60e	bellard	s->cc_op = CC_OP_MULB + ot;
3609	2c0262af	bellard	break;
3610	2c0262af	bellard	case 0x1c0:
3611	2c0262af	bellard	case 0x1c1: /* xadd Ev, Gv */
3612	2c0262af	bellard	if ((b & 1) == 0)
3613	2c0262af	bellard	ot = OT_BYTE;
3614	2c0262af	bellard	else
3615	14ce26e7	bellard	ot = dflag + OT_WORD;
3616	61382a50	bellard	modrm = ldub_code(s->pc++);
3617	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3618	2c0262af	bellard	mod = (modrm >> 6) & 3;
3619	2c0262af	bellard	if (mod == 3) {
3620	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3621	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3622	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3623	2c0262af	bellard	gen_op_addl_T0_T1();
3624	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3625	5a1388b6	bellard	gen_op_mov_reg_T0[ot][rm]();
3626	2c0262af	bellard	} else {
3627	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3628	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3629	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3630	2c0262af	bellard	gen_op_addl_T0_T1();
3631	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3632	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3633	2c0262af	bellard	}
3634	2c0262af	bellard	gen_op_update2_cc();
3635	2c0262af	bellard	s->cc_op = CC_OP_ADDB + ot;
3636	2c0262af	bellard	break;
3637	2c0262af	bellard	case 0x1b0:
3638	2c0262af	bellard	case 0x1b1: /* cmpxchg Ev, Gv */
3639	2c0262af	bellard	if ((b & 1) == 0)
3640	2c0262af	bellard	ot = OT_BYTE;
3641	2c0262af	bellard	else
3642	14ce26e7	bellard	ot = dflag + OT_WORD;
3643	61382a50	bellard	modrm = ldub_code(s->pc++);
3644	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3645	2c0262af	bellard	mod = (modrm >> 6) & 3;
3646	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3647	2c0262af	bellard	if (mod == 3) {
3648	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3649	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3650	2c0262af	bellard	gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
3651	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3652	2c0262af	bellard	} else {
3653	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3654	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3655	4f31916f	bellard	gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
3656	2c0262af	bellard	}
3657	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
3658	2c0262af	bellard	break;
3659	2c0262af	bellard	case 0x1c7: /* cmpxchg8b */
3660	61382a50	bellard	modrm = ldub_code(s->pc++);
3661	2c0262af	bellard	mod = (modrm >> 6) & 3;
3662	2c0262af	bellard	if (mod == 3)
3663	2c0262af	bellard	goto illegal_op;
3664	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3665	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3666	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3667	2c0262af	bellard	gen_op_cmpxchg8b();
3668	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
3669	2c0262af	bellard	break;
3670	2c0262af	bellard
3671	2c0262af	bellard	/**************************/
3672	2c0262af	bellard	/* push/pop */
3673	2c0262af	bellard	case 0x50 ... 0x57: /* push */
3674	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][(b & 7) \| REX_B(s)]();
3675	2c0262af	bellard	gen_push_T0(s);
3676	2c0262af	bellard	break;
3677	2c0262af	bellard	case 0x58 ... 0x5f: /* pop */
3678	14ce26e7	bellard	if (CODE64(s)) {
3679	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3680	14ce26e7	bellard	} else {
3681	14ce26e7	bellard	ot = dflag + OT_WORD;
3682	14ce26e7	bellard	}
3683	2c0262af	bellard	gen_pop_T0(s);
3684	77729c24	bellard	/* NOTE: order is important for pop %sp */
3685	2c0262af	bellard	gen_pop_update(s);
3686	14ce26e7	bellard	gen_op_mov_reg_T0[ot][(b & 7) \| REX_B(s)]();
3687	2c0262af	bellard	break;
3688	2c0262af	bellard	case 0x60: /* pusha */
3689	14ce26e7	bellard	if (CODE64(s))
3690	14ce26e7	bellard	goto illegal_op;
3691	2c0262af	bellard	gen_pusha(s);
3692	2c0262af	bellard	break;
3693	2c0262af	bellard	case 0x61: /* popa */
3694	14ce26e7	bellard	if (CODE64(s))
3695	14ce26e7	bellard	goto illegal_op;
3696	2c0262af	bellard	gen_popa(s);
3697	2c0262af	bellard	break;
3698	2c0262af	bellard	case 0x68: /* push Iv */
3699	2c0262af	bellard	case 0x6a:
3700	14ce26e7	bellard	if (CODE64(s)) {
3701	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3702	14ce26e7	bellard	} else {
3703	14ce26e7	bellard	ot = dflag + OT_WORD;
3704	14ce26e7	bellard	}
3705	2c0262af	bellard	if (b == 0x68)
3706	2c0262af	bellard	val = insn_get(s, ot);
3707	2c0262af	bellard	else
3708	2c0262af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3709	2c0262af	bellard	gen_op_movl_T0_im(val);
3710	2c0262af	bellard	gen_push_T0(s);
3711	2c0262af	bellard	break;
3712	2c0262af	bellard	case 0x8f: /* pop Ev */
3713	14ce26e7	bellard	if (CODE64(s)) {
3714	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3715	14ce26e7	bellard	} else {
3716	14ce26e7	bellard	ot = dflag + OT_WORD;
3717	14ce26e7	bellard	}
3718	61382a50	bellard	modrm = ldub_code(s->pc++);
3719	77729c24	bellard	mod = (modrm >> 6) & 3;
3720	2c0262af	bellard	gen_pop_T0(s);
3721	77729c24	bellard	if (mod == 3) {
3722	77729c24	bellard	/* NOTE: order is important for pop %sp */
3723	77729c24	bellard	gen_pop_update(s);
3724	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3725	77729c24	bellard	gen_op_mov_reg_T0[ot][rm]();
3726	77729c24	bellard	} else {
3727	77729c24	bellard	/* NOTE: order is important too for MMU exceptions */
3728	14ce26e7	bellard	s->popl_esp_hack = 1 << ot;
3729	77729c24	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3730	77729c24	bellard	s->popl_esp_hack = 0;
3731	77729c24	bellard	gen_pop_update(s);
3732	77729c24	bellard	}
3733	2c0262af	bellard	break;
3734	2c0262af	bellard	case 0xc8: /* enter */
3735	2c0262af	bellard	{
3736	2c0262af	bellard	int level;
3737	61382a50	bellard	val = lduw_code(s->pc);
3738	2c0262af	bellard	s->pc += 2;
3739	61382a50	bellard	level = ldub_code(s->pc++);
3740	2c0262af	bellard	gen_enter(s, val, level);
3741	2c0262af	bellard	}
3742	2c0262af	bellard	break;
3743	2c0262af	bellard	case 0xc9: /* leave */
3744	2c0262af	bellard	/* XXX: exception not precise (ESP is updated before potential exception) */
3745	14ce26e7	bellard	if (CODE64(s)) {
3746	14ce26e7	bellard	gen_op_mov_TN_reg[OT_QUAD][0][R_EBP]();
3747	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][R_ESP]();
3748	14ce26e7	bellard	} else if (s->ss32) {
3749	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
3750	2c0262af	bellard	gen_op_mov_reg_T0[OT_LONG][R_ESP]();
3751	2c0262af	bellard	} else {
3752	2c0262af	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
3753	2c0262af	bellard	gen_op_mov_reg_T0[OT_WORD][R_ESP]();
3754	2c0262af	bellard	}
3755	2c0262af	bellard	gen_pop_T0(s);
3756	14ce26e7	bellard	if (CODE64(s)) {
3757	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3758	14ce26e7	bellard	} else {
3759	14ce26e7	bellard	ot = dflag + OT_WORD;
3760	14ce26e7	bellard	}
3761	2c0262af	bellard	gen_op_mov_reg_T0[ot][R_EBP]();
3762	2c0262af	bellard	gen_pop_update(s);
3763	2c0262af	bellard	break;
3764	2c0262af	bellard	case 0x06: /* push es */
3765	2c0262af	bellard	case 0x0e: /* push cs */
3766	2c0262af	bellard	case 0x16: /* push ss */
3767	2c0262af	bellard	case 0x1e: /* push ds */
3768	14ce26e7	bellard	if (CODE64(s))
3769	14ce26e7	bellard	goto illegal_op;
3770	2c0262af	bellard	gen_op_movl_T0_seg(b >> 3);
3771	2c0262af	bellard	gen_push_T0(s);
3772	2c0262af	bellard	break;
3773	2c0262af	bellard	case 0x1a0: /* push fs */
3774	2c0262af	bellard	case 0x1a8: /* push gs */
3775	2c0262af	bellard	gen_op_movl_T0_seg((b >> 3) & 7);
3776	2c0262af	bellard	gen_push_T0(s);
3777	2c0262af	bellard	break;
3778	2c0262af	bellard	case 0x07: /* pop es */
3779	2c0262af	bellard	case 0x17: /* pop ss */
3780	2c0262af	bellard	case 0x1f: /* pop ds */
3781	14ce26e7	bellard	if (CODE64(s))
3782	14ce26e7	bellard	goto illegal_op;
3783	2c0262af	bellard	reg = b >> 3;
3784	2c0262af	bellard	gen_pop_T0(s);
3785	2c0262af	bellard	gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3786	2c0262af	bellard	gen_pop_update(s);
3787	2c0262af	bellard	if (reg == R_SS) {
3788	a2cc3b24	bellard	/* if reg == SS, inhibit interrupts/trace. */
3789	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
3790	a2cc3b24	bellard	_first_ does it */
3791	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3792	a2cc3b24	bellard	gen_op_set_inhibit_irq();
3793	2c0262af	bellard	s->tf = 0;
3794	2c0262af	bellard	}
3795	2c0262af	bellard	if (s->is_jmp) {
3796	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3797	2c0262af	bellard	gen_eob(s);
3798	2c0262af	bellard	}
3799	2c0262af	bellard	break;
3800	2c0262af	bellard	case 0x1a1: /* pop fs */
3801	2c0262af	bellard	case 0x1a9: /* pop gs */
3802	2c0262af	bellard	gen_pop_T0(s);
3803	2c0262af	bellard	gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
3804	2c0262af	bellard	gen_pop_update(s);
3805	2c0262af	bellard	if (s->is_jmp) {
3806	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3807	2c0262af	bellard	gen_eob(s);
3808	2c0262af	bellard	}
3809	2c0262af	bellard	break;
3810	2c0262af	bellard
3811	2c0262af	bellard	/**************************/
3812	2c0262af	bellard	/* mov */
3813	2c0262af	bellard	case 0x88:
3814	2c0262af	bellard	case 0x89: /* mov Gv, Ev */
3815	2c0262af	bellard	if ((b & 1) == 0)
3816	2c0262af	bellard	ot = OT_BYTE;
3817	2c0262af	bellard	else
3818	14ce26e7	bellard	ot = dflag + OT_WORD;
3819	61382a50	bellard	modrm = ldub_code(s->pc++);
3820	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3821	2c0262af	bellard
3822	2c0262af	bellard	/* generate a generic store */
3823	14ce26e7	bellard	gen_ldst_modrm(s, modrm, ot, reg, 1);
3824	2c0262af	bellard	break;
3825	2c0262af	bellard	case 0xc6:
3826	2c0262af	bellard	case 0xc7: /* mov Ev, Iv */
3827	2c0262af	bellard	if ((b & 1) == 0)
3828	2c0262af	bellard	ot = OT_BYTE;
3829	2c0262af	bellard	else
3830	14ce26e7	bellard	ot = dflag + OT_WORD;
3831	61382a50	bellard	modrm = ldub_code(s->pc++);
3832	2c0262af	bellard	mod = (modrm >> 6) & 3;
3833	14ce26e7	bellard	if (mod != 3) {
3834	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3835	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3836	14ce26e7	bellard	}
3837	2c0262af	bellard	val = insn_get(s, ot);
3838	2c0262af	bellard	gen_op_movl_T0_im(val);
3839	2c0262af	bellard	if (mod != 3)
3840	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3841	2c0262af	bellard	else
3842	14ce26e7	bellard	gen_op_mov_reg_T0[ot][(modrm & 7) \| REX_B(s)]();
3843	2c0262af	bellard	break;
3844	2c0262af	bellard	case 0x8a:
3845	2c0262af	bellard	case 0x8b: /* mov Ev, Gv */
3846	2c0262af	bellard	if ((b & 1) == 0)
3847	2c0262af	bellard	ot = OT_BYTE;
3848	2c0262af	bellard	else
3849	14ce26e7	bellard	ot = OT_WORD + dflag;
3850	61382a50	bellard	modrm = ldub_code(s->pc++);
3851	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3852	2c0262af	bellard
3853	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3854	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3855	2c0262af	bellard	break;
3856	2c0262af	bellard	case 0x8e: /* mov seg, Gv */
3857	61382a50	bellard	modrm = ldub_code(s->pc++);
3858	2c0262af	bellard	reg = (modrm >> 3) & 7;
3859	2c0262af	bellard	if (reg >= 6 \|\| reg == R_CS)
3860	2c0262af	bellard	goto illegal_op;
3861	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3862	2c0262af	bellard	gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3863	2c0262af	bellard	if (reg == R_SS) {
3864	2c0262af	bellard	/* if reg == SS, inhibit interrupts/trace */
3865	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
3866	a2cc3b24	bellard	_first_ does it */
3867	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3868	a2cc3b24	bellard	gen_op_set_inhibit_irq();
3869	2c0262af	bellard	s->tf = 0;
3870	2c0262af	bellard	}
3871	2c0262af	bellard	if (s->is_jmp) {
3872	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3873	2c0262af	bellard	gen_eob(s);
3874	2c0262af	bellard	}
3875	2c0262af	bellard	break;
3876	2c0262af	bellard	case 0x8c: /* mov Gv, seg */
3877	61382a50	bellard	modrm = ldub_code(s->pc++);
3878	2c0262af	bellard	reg = (modrm >> 3) & 7;
3879	2c0262af	bellard	mod = (modrm >> 6) & 3;
3880	2c0262af	bellard	if (reg >= 6)
3881	2c0262af	bellard	goto illegal_op;
3882	2c0262af	bellard	gen_op_movl_T0_seg(reg);
3883	14ce26e7	bellard	if (mod == 3)
3884	14ce26e7	bellard	ot = OT_WORD + dflag;
3885	14ce26e7	bellard	else
3886	14ce26e7	bellard	ot = OT_WORD;
3887	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3888	2c0262af	bellard	break;
3889	2c0262af	bellard
3890	2c0262af	bellard	case 0x1b6: /* movzbS Gv, Eb */
3891	2c0262af	bellard	case 0x1b7: /* movzwS Gv, Eb */
3892	2c0262af	bellard	case 0x1be: /* movsbS Gv, Eb */
3893	2c0262af	bellard	case 0x1bf: /* movswS Gv, Eb */
3894	2c0262af	bellard	{
3895	2c0262af	bellard	int d_ot;
3896	2c0262af	bellard	/* d_ot is the size of destination */
3897	2c0262af	bellard	d_ot = dflag + OT_WORD;
3898	2c0262af	bellard	/* ot is the size of source */
3899	2c0262af	bellard	ot = (b & 1) + OT_BYTE;
3900	61382a50	bellard	modrm = ldub_code(s->pc++);
3901	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3902	2c0262af	bellard	mod = (modrm >> 6) & 3;
3903	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3904	2c0262af	bellard
3905	2c0262af	bellard	if (mod == 3) {
3906	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3907	2c0262af	bellard	switch(ot \| (b & 8)) {
3908	2c0262af	bellard	case OT_BYTE:
3909	2c0262af	bellard	gen_op_movzbl_T0_T0();
3910	2c0262af	bellard	break;
3911	2c0262af	bellard	case OT_BYTE \| 8:
3912	2c0262af	bellard	gen_op_movsbl_T0_T0();
3913	2c0262af	bellard	break;
3914	2c0262af	bellard	case OT_WORD:
3915	2c0262af	bellard	gen_op_movzwl_T0_T0();
3916	2c0262af	bellard	break;
3917	2c0262af	bellard	default:
3918	2c0262af	bellard	case OT_WORD \| 8:
3919	2c0262af	bellard	gen_op_movswl_T0_T0();
3920	2c0262af	bellard	break;
3921	2c0262af	bellard	}
3922	2c0262af	bellard	gen_op_mov_reg_T0[d_ot][reg]();
3923	2c0262af	bellard	} else {
3924	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3925	2c0262af	bellard	if (b & 8) {
3926	2c0262af	bellard	gen_op_lds_T0_A0[ot + s->mem_index]();
3927	2c0262af	bellard	} else {
3928	2c0262af	bellard	gen_op_ldu_T0_A0[ot + s->mem_index]();
3929	2c0262af	bellard	}
3930	2c0262af	bellard	gen_op_mov_reg_T0[d_ot][reg]();
3931	2c0262af	bellard	}
3932	2c0262af	bellard	}
3933	2c0262af	bellard	break;
3934	2c0262af	bellard
3935	2c0262af	bellard	case 0x8d: /* lea */
3936	14ce26e7	bellard	ot = dflag + OT_WORD;
3937	61382a50	bellard	modrm = ldub_code(s->pc++);
3938	3a1d9b8b	bellard	mod = (modrm >> 6) & 3;
3939	3a1d9b8b	bellard	if (mod == 3)
3940	3a1d9b8b	bellard	goto illegal_op;
3941	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3942	2c0262af	bellard	/* we must ensure that no segment is added */
3943	2c0262af	bellard	s->override = -1;
3944	2c0262af	bellard	val = s->addseg;
3945	2c0262af	bellard	s->addseg = 0;
3946	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3947	2c0262af	bellard	s->addseg = val;
3948	2c0262af	bellard	gen_op_mov_reg_A0[ot - OT_WORD][reg]();
3949	2c0262af	bellard	break;
3950	2c0262af	bellard
3951	2c0262af	bellard	case 0xa0: /* mov EAX, Ov */
3952	2c0262af	bellard	case 0xa1:
3953	2c0262af	bellard	case 0xa2: /* mov Ov, EAX */
3954	2c0262af	bellard	case 0xa3:
3955	2c0262af	bellard	{
3956	14ce26e7	bellard	target_ulong offset_addr;
3957	14ce26e7	bellard
3958	14ce26e7	bellard	if ((b & 1) == 0)
3959	14ce26e7	bellard	ot = OT_BYTE;
3960	14ce26e7	bellard	else
3961	14ce26e7	bellard	ot = dflag + OT_WORD;
3962	14ce26e7	bellard	#ifdef TARGET_X86_64
3963	8f091a59	bellard	if (s->aflag == 2) {
3964	14ce26e7	bellard	offset_addr = ldq_code(s->pc);
3965	14ce26e7	bellard	s->pc += 8;
3966	14ce26e7	bellard	if (offset_addr == (int32_t)offset_addr)
3967	14ce26e7	bellard	gen_op_movq_A0_im(offset_addr);
3968	14ce26e7	bellard	else
3969	14ce26e7	bellard	gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
3970	14ce26e7	bellard	} else
3971	14ce26e7	bellard	#endif
3972	14ce26e7	bellard	{
3973	14ce26e7	bellard	if (s->aflag) {
3974	14ce26e7	bellard	offset_addr = insn_get(s, OT_LONG);
3975	14ce26e7	bellard	} else {
3976	14ce26e7	bellard	offset_addr = insn_get(s, OT_WORD);
3977	14ce26e7	bellard	}
3978	14ce26e7	bellard	gen_op_movl_A0_im(offset_addr);
3979	14ce26e7	bellard	}
3980	664e0f19	bellard	gen_add_A0_ds_seg(s);
3981	14ce26e7	bellard	if ((b & 2) == 0) {
3982	14ce26e7	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3983	14ce26e7	bellard	gen_op_mov_reg_T0[ot][R_EAX]();
3984	14ce26e7	bellard	} else {
3985	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][R_EAX]();
3986	14ce26e7	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3987	2c0262af	bellard	}
3988	2c0262af	bellard	}
3989	2c0262af	bellard	break;
3990	2c0262af	bellard	case 0xd7: /* xlat */
3991	14ce26e7	bellard	#ifdef TARGET_X86_64
3992	8f091a59	bellard	if (s->aflag == 2) {
3993	14ce26e7	bellard	gen_op_movq_A0_reg[R_EBX]();
3994	14ce26e7	bellard	gen_op_addq_A0_AL();
3995	14ce26e7	bellard	} else
3996	14ce26e7	bellard	#endif
3997	14ce26e7	bellard	{
3998	14ce26e7	bellard	gen_op_movl_A0_reg[R_EBX]();
3999	14ce26e7	bellard	gen_op_addl_A0_AL();
4000	14ce26e7	bellard	if (s->aflag == 0)
4001	14ce26e7	bellard	gen_op_andl_A0_ffff();
4002	14ce26e7	bellard	}
4003	664e0f19	bellard	gen_add_A0_ds_seg(s);
4004	2c0262af	bellard	gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
4005	2c0262af	bellard	gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
4006	2c0262af	bellard	break;
4007	2c0262af	bellard	case 0xb0 ... 0xb7: /* mov R, Ib */
4008	2c0262af	bellard	val = insn_get(s, OT_BYTE);
4009	2c0262af	bellard	gen_op_movl_T0_im(val);
4010	14ce26e7	bellard	gen_op_mov_reg_T0[OT_BYTE][(b & 7) \| REX_B(s)]();
4011	2c0262af	bellard	break;
4012	2c0262af	bellard	case 0xb8 ... 0xbf: /* mov R, Iv */
4013	14ce26e7	bellard	#ifdef TARGET_X86_64
4014	14ce26e7	bellard	if (dflag == 2) {
4015	14ce26e7	bellard	uint64_t tmp;
4016	14ce26e7	bellard	/* 64 bit case */
4017	14ce26e7	bellard	tmp = ldq_code(s->pc);
4018	14ce26e7	bellard	s->pc += 8;
4019	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
4020	14ce26e7	bellard	gen_movtl_T0_im(tmp);
4021	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][reg]();
4022	14ce26e7	bellard	} else
4023	14ce26e7	bellard	#endif
4024	14ce26e7	bellard	{
4025	14ce26e7	bellard	ot = dflag ? OT_LONG : OT_WORD;
4026	14ce26e7	bellard	val = insn_get(s, ot);
4027	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
4028	14ce26e7	bellard	gen_op_movl_T0_im(val);
4029	14ce26e7	bellard	gen_op_mov_reg_T0[ot][reg]();
4030	14ce26e7	bellard	}
4031	2c0262af	bellard	break;
4032	2c0262af	bellard
4033	2c0262af	bellard	case 0x91 ... 0x97: /* xchg R, EAX */
4034	14ce26e7	bellard	ot = dflag + OT_WORD;
4035	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
4036	2c0262af	bellard	rm = R_EAX;
4037	2c0262af	bellard	goto do_xchg_reg;
4038	2c0262af	bellard	case 0x86:
4039	2c0262af	bellard	case 0x87: /* xchg Ev, Gv */
4040	2c0262af	bellard	if ((b & 1) == 0)
4041	2c0262af	bellard	ot = OT_BYTE;
4042	2c0262af	bellard	else
4043	14ce26e7	bellard	ot = dflag + OT_WORD;
4044	61382a50	bellard	modrm = ldub_code(s->pc++);
4045	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4046	2c0262af	bellard	mod = (modrm >> 6) & 3;
4047	2c0262af	bellard	if (mod == 3) {
4048	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4049	2c0262af	bellard	do_xchg_reg:
4050	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
4051	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
4052	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
4053	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4054	2c0262af	bellard	} else {
4055	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4056	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
4057	2c0262af	bellard	/* for xchg, lock is implicit */
4058	2c0262af	bellard	if (!(prefixes & PREFIX_LOCK))
4059	2c0262af	bellard	gen_op_lock();
4060	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4061	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
4062	2c0262af	bellard	if (!(prefixes & PREFIX_LOCK))
4063	2c0262af	bellard	gen_op_unlock();
4064	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4065	2c0262af	bellard	}
4066	2c0262af	bellard	break;
4067	2c0262af	bellard	case 0xc4: /* les Gv */
4068	14ce26e7	bellard	if (CODE64(s))
4069	14ce26e7	bellard	goto illegal_op;
4070	2c0262af	bellard	op = R_ES;
4071	2c0262af	bellard	goto do_lxx;
4072	2c0262af	bellard	case 0xc5: /* lds Gv */
4073	14ce26e7	bellard	if (CODE64(s))
4074	14ce26e7	bellard	goto illegal_op;
4075	2c0262af	bellard	op = R_DS;
4076	2c0262af	bellard	goto do_lxx;
4077	2c0262af	bellard	case 0x1b2: /* lss Gv */
4078	2c0262af	bellard	op = R_SS;
4079	2c0262af	bellard	goto do_lxx;
4080	2c0262af	bellard	case 0x1b4: /* lfs Gv */
4081	2c0262af	bellard	op = R_FS;
4082	2c0262af	bellard	goto do_lxx;
4083	2c0262af	bellard	case 0x1b5: /* lgs Gv */
4084	2c0262af	bellard	op = R_GS;
4085	2c0262af	bellard	do_lxx:
4086	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4087	61382a50	bellard	modrm = ldub_code(s->pc++);
4088	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4089	2c0262af	bellard	mod = (modrm >> 6) & 3;
4090	2c0262af	bellard	if (mod == 3)
4091	2c0262af	bellard	goto illegal_op;
4092	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4093	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4094	aba9d61e	bellard	gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4095	2c0262af	bellard	/* load the segment first to handle exceptions properly */
4096	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
4097	2c0262af	bellard	gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4098	2c0262af	bellard	/* then put the data */
4099	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4100	2c0262af	bellard	if (s->is_jmp) {
4101	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
4102	2c0262af	bellard	gen_eob(s);
4103	2c0262af	bellard	}
4104	2c0262af	bellard	break;
4105	2c0262af	bellard
4106	2c0262af	bellard	/************************/
4107	2c0262af	bellard	/* shifts */
4108	2c0262af	bellard	case 0xc0:
4109	2c0262af	bellard	case 0xc1:
4110	2c0262af	bellard	/* shift Ev,Ib */
4111	2c0262af	bellard	shift = 2;
4112	2c0262af	bellard	grp2:
4113	2c0262af	bellard	{
4114	2c0262af	bellard	if ((b & 1) == 0)
4115	2c0262af	bellard	ot = OT_BYTE;
4116	2c0262af	bellard	else
4117	14ce26e7	bellard	ot = dflag + OT_WORD;
4118	2c0262af	bellard
4119	61382a50	bellard	modrm = ldub_code(s->pc++);
4120	2c0262af	bellard	mod = (modrm >> 6) & 3;
4121	2c0262af	bellard	op = (modrm >> 3) & 7;
4122	2c0262af	bellard
4123	2c0262af	bellard	if (mod != 3) {
4124	14ce26e7	bellard	if (shift == 2) {
4125	14ce26e7	bellard	s->rip_offset = 1;
4126	14ce26e7	bellard	}
4127	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4128	2c0262af	bellard	opreg = OR_TMP0;
4129	2c0262af	bellard	} else {
4130	14ce26e7	bellard	opreg = (modrm & 7) \| REX_B(s);
4131	2c0262af	bellard	}
4132	2c0262af	bellard
4133	2c0262af	bellard	/* simpler op */
4134	2c0262af	bellard	if (shift == 0) {
4135	2c0262af	bellard	gen_shift(s, op, ot, opreg, OR_ECX);
4136	2c0262af	bellard	} else {
4137	2c0262af	bellard	if (shift == 2) {
4138	61382a50	bellard	shift = ldub_code(s->pc++);
4139	2c0262af	bellard	}
4140	2c0262af	bellard	gen_shifti(s, op, ot, opreg, shift);
4141	2c0262af	bellard	}
4142	2c0262af	bellard	}
4143	2c0262af	bellard	break;
4144	2c0262af	bellard	case 0xd0:
4145	2c0262af	bellard	case 0xd1:
4146	2c0262af	bellard	/* shift Ev,1 */
4147	2c0262af	bellard	shift = 1;
4148	2c0262af	bellard	goto grp2;
4149	2c0262af	bellard	case 0xd2:
4150	2c0262af	bellard	case 0xd3:
4151	2c0262af	bellard	/* shift Ev,cl */
4152	2c0262af	bellard	shift = 0;
4153	2c0262af	bellard	goto grp2;
4154	2c0262af	bellard
4155	2c0262af	bellard	case 0x1a4: /* shld imm */
4156	2c0262af	bellard	op = 0;
4157	2c0262af	bellard	shift = 1;
4158	2c0262af	bellard	goto do_shiftd;
4159	2c0262af	bellard	case 0x1a5: /* shld cl */
4160	2c0262af	bellard	op = 0;
4161	2c0262af	bellard	shift = 0;
4162	2c0262af	bellard	goto do_shiftd;
4163	2c0262af	bellard	case 0x1ac: /* shrd imm */
4164	2c0262af	bellard	op = 1;
4165	2c0262af	bellard	shift = 1;
4166	2c0262af	bellard	goto do_shiftd;
4167	2c0262af	bellard	case 0x1ad: /* shrd cl */
4168	2c0262af	bellard	op = 1;
4169	2c0262af	bellard	shift = 0;
4170	2c0262af	bellard	do_shiftd:
4171	14ce26e7	bellard	ot = dflag + OT_WORD;
4172	61382a50	bellard	modrm = ldub_code(s->pc++);
4173	2c0262af	bellard	mod = (modrm >> 6) & 3;
4174	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4175	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4176	2c0262af	bellard
4177	2c0262af	bellard	if (mod != 3) {
4178	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4179	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
4180	2c0262af	bellard	} else {
4181	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
4182	2c0262af	bellard	}
4183	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
4184	2c0262af	bellard
4185	2c0262af	bellard	if (shift) {
4186	61382a50	bellard	val = ldub_code(s->pc++);
4187	14ce26e7	bellard	if (ot == OT_QUAD)
4188	14ce26e7	bellard	val &= 0x3f;
4189	14ce26e7	bellard	else
4190	14ce26e7	bellard	val &= 0x1f;
4191	2c0262af	bellard	if (val) {
4192	2c0262af	bellard	if (mod == 3)
4193	4f31916f	bellard	gen_op_shiftd_T0_T1_im_cc[ot][op](val);
4194	2c0262af	bellard	else
4195	4f31916f	bellard	gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
4196	2c0262af	bellard	if (op == 0 && ot != OT_WORD)
4197	2c0262af	bellard	s->cc_op = CC_OP_SHLB + ot;
4198	2c0262af	bellard	else
4199	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
4200	2c0262af	bellard	}
4201	2c0262af	bellard	} else {
4202	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4203	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4204	2c0262af	bellard	if (mod == 3)
4205	4f31916f	bellard	gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
4206	2c0262af	bellard	else
4207	4f31916f	bellard	gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
4208	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
4209	2c0262af	bellard	}
4210	2c0262af	bellard	if (mod == 3) {
4211	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
4212	2c0262af	bellard	}
4213	2c0262af	bellard	break;
4214	2c0262af	bellard
4215	2c0262af	bellard	/************************/
4216	2c0262af	bellard	/* floats */
4217	2c0262af	bellard	case 0xd8 ... 0xdf:
4218	7eee2a50	bellard	if (s->flags & (HF_EM_MASK \| HF_TS_MASK)) {
4219	7eee2a50	bellard	/* if CR0.EM or CR0.TS are set, generate an FPU exception */
4220	7eee2a50	bellard	/* XXX: what to do if illegal op ? */
4221	7eee2a50	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4222	7eee2a50	bellard	break;
4223	7eee2a50	bellard	}
4224	61382a50	bellard	modrm = ldub_code(s->pc++);
4225	2c0262af	bellard	mod = (modrm >> 6) & 3;
4226	2c0262af	bellard	rm = modrm & 7;
4227	2c0262af	bellard	op = ((b & 7) << 3) \| ((modrm >> 3) & 7);
4228	2c0262af	bellard	if (mod != 3) {
4229	2c0262af	bellard	/* memory op */
4230	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4231	2c0262af	bellard	switch(op) {
4232	2c0262af	bellard	case 0x00 ... 0x07: /* fxxxs */
4233	2c0262af	bellard	case 0x10 ... 0x17: /* fixxxl */
4234	2c0262af	bellard	case 0x20 ... 0x27: /* fxxxl */
4235	2c0262af	bellard	case 0x30 ... 0x37: /* fixxx */
4236	2c0262af	bellard	{
4237	2c0262af	bellard	int op1;
4238	2c0262af	bellard	op1 = op & 7;
4239	2c0262af	bellard
4240	2c0262af	bellard	switch(op >> 4) {
4241	2c0262af	bellard	case 0:
4242	2c0262af	bellard	gen_op_flds_FT0_A0();
4243	2c0262af	bellard	break;
4244	2c0262af	bellard	case 1:
4245	2c0262af	bellard	gen_op_fildl_FT0_A0();
4246	2c0262af	bellard	break;
4247	2c0262af	bellard	case 2:
4248	2c0262af	bellard	gen_op_fldl_FT0_A0();
4249	2c0262af	bellard	break;
4250	2c0262af	bellard	case 3:
4251	2c0262af	bellard	default:
4252	2c0262af	bellard	gen_op_fild_FT0_A0();
4253	2c0262af	bellard	break;
4254	2c0262af	bellard	}
4255	2c0262af	bellard
4256	2c0262af	bellard	gen_op_fp_arith_ST0_FT0[op1]();
4257	2c0262af	bellard	if (op1 == 3) {
4258	2c0262af	bellard	/* fcomp needs pop */
4259	2c0262af	bellard	gen_op_fpop();
4260	2c0262af	bellard	}
4261	2c0262af	bellard	}
4262	2c0262af	bellard	break;
4263	2c0262af	bellard	case 0x08: /* flds */
4264	2c0262af	bellard	case 0x0a: /* fsts */
4265	2c0262af	bellard	case 0x0b: /* fstps */
4266	2c0262af	bellard	case 0x18: /* fildl */
4267	2c0262af	bellard	case 0x1a: /* fistl */
4268	2c0262af	bellard	case 0x1b: /* fistpl */
4269	2c0262af	bellard	case 0x28: /* fldl */
4270	2c0262af	bellard	case 0x2a: /* fstl */
4271	2c0262af	bellard	case 0x2b: /* fstpl */
4272	2c0262af	bellard	case 0x38: /* filds */
4273	2c0262af	bellard	case 0x3a: /* fists */
4274	2c0262af	bellard	case 0x3b: /* fistps */
4275	2c0262af	bellard
4276	2c0262af	bellard	switch(op & 7) {
4277	2c0262af	bellard	case 0:
4278	2c0262af	bellard	switch(op >> 4) {
4279	2c0262af	bellard	case 0:
4280	2c0262af	bellard	gen_op_flds_ST0_A0();
4281	2c0262af	bellard	break;
4282	2c0262af	bellard	case 1:
4283	2c0262af	bellard	gen_op_fildl_ST0_A0();
4284	2c0262af	bellard	break;
4285	2c0262af	bellard	case 2:
4286	2c0262af	bellard	gen_op_fldl_ST0_A0();
4287	2c0262af	bellard	break;
4288	2c0262af	bellard	case 3:
4289	2c0262af	bellard	default:
4290	2c0262af	bellard	gen_op_fild_ST0_A0();
4291	2c0262af	bellard	break;
4292	2c0262af	bellard	}
4293	2c0262af	bellard	break;
4294	2c0262af	bellard	default:
4295	2c0262af	bellard	switch(op >> 4) {
4296	2c0262af	bellard	case 0:
4297	2c0262af	bellard	gen_op_fsts_ST0_A0();
4298	2c0262af	bellard	break;
4299	2c0262af	bellard	case 1:
4300	2c0262af	bellard	gen_op_fistl_ST0_A0();
4301	2c0262af	bellard	break;
4302	2c0262af	bellard	case 2:
4303	2c0262af	bellard	gen_op_fstl_ST0_A0();
4304	2c0262af	bellard	break;
4305	2c0262af	bellard	case 3:
4306	2c0262af	bellard	default:
4307	2c0262af	bellard	gen_op_fist_ST0_A0();
4308	2c0262af	bellard	break;
4309	2c0262af	bellard	}
4310	2c0262af	bellard	if ((op & 7) == 3)
4311	2c0262af	bellard	gen_op_fpop();
4312	2c0262af	bellard	break;
4313	2c0262af	bellard	}
4314	2c0262af	bellard	break;
4315	2c0262af	bellard	case 0x0c: /* fldenv mem */
4316	2c0262af	bellard	gen_op_fldenv_A0(s->dflag);
4317	2c0262af	bellard	break;
4318	2c0262af	bellard	case 0x0d: /* fldcw mem */
4319	2c0262af	bellard	gen_op_fldcw_A0();
4320	2c0262af	bellard	break;
4321	2c0262af	bellard	case 0x0e: /* fnstenv mem */
4322	2c0262af	bellard	gen_op_fnstenv_A0(s->dflag);
4323	2c0262af	bellard	break;
4324	2c0262af	bellard	case 0x0f: /* fnstcw mem */
4325	2c0262af	bellard	gen_op_fnstcw_A0();
4326	2c0262af	bellard	break;
4327	2c0262af	bellard	case 0x1d: /* fldt mem */
4328	2c0262af	bellard	gen_op_fldt_ST0_A0();
4329	2c0262af	bellard	break;
4330	2c0262af	bellard	case 0x1f: /* fstpt mem */
4331	2c0262af	bellard	gen_op_fstt_ST0_A0();
4332	2c0262af	bellard	gen_op_fpop();
4333	2c0262af	bellard	break;
4334	2c0262af	bellard	case 0x2c: /* frstor mem */
4335	2c0262af	bellard	gen_op_frstor_A0(s->dflag);
4336	2c0262af	bellard	break;
4337	2c0262af	bellard	case 0x2e: /* fnsave mem */
4338	2c0262af	bellard	gen_op_fnsave_A0(s->dflag);
4339	2c0262af	bellard	break;
4340	2c0262af	bellard	case 0x2f: /* fnstsw mem */
4341	2c0262af	bellard	gen_op_fnstsw_A0();
4342	2c0262af	bellard	break;
4343	2c0262af	bellard	case 0x3c: /* fbld */
4344	2c0262af	bellard	gen_op_fbld_ST0_A0();
4345	2c0262af	bellard	break;
4346	2c0262af	bellard	case 0x3e: /* fbstp */
4347	2c0262af	bellard	gen_op_fbst_ST0_A0();
4348	2c0262af	bellard	gen_op_fpop();
4349	2c0262af	bellard	break;
4350	2c0262af	bellard	case 0x3d: /* fildll */
4351	2c0262af	bellard	gen_op_fildll_ST0_A0();
4352	2c0262af	bellard	break;
4353	2c0262af	bellard	case 0x3f: /* fistpll */
4354	2c0262af	bellard	gen_op_fistll_ST0_A0();
4355	2c0262af	bellard	gen_op_fpop();
4356	2c0262af	bellard	break;
4357	2c0262af	bellard	default:
4358	2c0262af	bellard	goto illegal_op;
4359	2c0262af	bellard	}
4360	2c0262af	bellard	} else {
4361	2c0262af	bellard	/* register float ops */
4362	2c0262af	bellard	opreg = rm;
4363	2c0262af	bellard
4364	2c0262af	bellard	switch(op) {
4365	2c0262af	bellard	case 0x08: /* fld sti */
4366	2c0262af	bellard	gen_op_fpush();
4367	2c0262af	bellard	gen_op_fmov_ST0_STN((opreg + 1) & 7);
4368	2c0262af	bellard	break;
4369	2c0262af	bellard	case 0x09: /* fxchg sti */
4370	c169c906	bellard	case 0x29: /* fxchg4 sti, undocumented op */
4371	c169c906	bellard	case 0x39: /* fxchg7 sti, undocumented op */
4372	2c0262af	bellard	gen_op_fxchg_ST0_STN(opreg);
4373	2c0262af	bellard	break;
4374	2c0262af	bellard	case 0x0a: /* grp d9/2 */
4375	2c0262af	bellard	switch(rm) {
4376	2c0262af	bellard	case 0: /* fnop */
4377	023fe10d	bellard	/* check exceptions (FreeBSD FPU probe) */
4378	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4379	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
4380	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4381	023fe10d	bellard	gen_op_fwait();
4382	2c0262af	bellard	break;
4383	2c0262af	bellard	default:
4384	2c0262af	bellard	goto illegal_op;
4385	2c0262af	bellard	}
4386	2c0262af	bellard	break;
4387	2c0262af	bellard	case 0x0c: /* grp d9/4 */
4388	2c0262af	bellard	switch(rm) {
4389	2c0262af	bellard	case 0: /* fchs */
4390	2c0262af	bellard	gen_op_fchs_ST0();
4391	2c0262af	bellard	break;
4392	2c0262af	bellard	case 1: /* fabs */
4393	2c0262af	bellard	gen_op_fabs_ST0();
4394	2c0262af	bellard	break;
4395	2c0262af	bellard	case 4: /* ftst */
4396	2c0262af	bellard	gen_op_fldz_FT0();
4397	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4398	2c0262af	bellard	break;
4399	2c0262af	bellard	case 5: /* fxam */
4400	2c0262af	bellard	gen_op_fxam_ST0();
4401	2c0262af	bellard	break;
4402	2c0262af	bellard	default:
4403	2c0262af	bellard	goto illegal_op;
4404	2c0262af	bellard	}
4405	2c0262af	bellard	break;
4406	2c0262af	bellard	case 0x0d: /* grp d9/5 */
4407	2c0262af	bellard	{
4408	2c0262af	bellard	switch(rm) {
4409	2c0262af	bellard	case 0:
4410	2c0262af	bellard	gen_op_fpush();
4411	2c0262af	bellard	gen_op_fld1_ST0();
4412	2c0262af	bellard	break;
4413	2c0262af	bellard	case 1:
4414	2c0262af	bellard	gen_op_fpush();
4415	2c0262af	bellard	gen_op_fldl2t_ST0();
4416	2c0262af	bellard	break;
4417	2c0262af	bellard	case 2:
4418	2c0262af	bellard	gen_op_fpush();
4419	2c0262af	bellard	gen_op_fldl2e_ST0();
4420	2c0262af	bellard	break;
4421	2c0262af	bellard	case 3:
4422	2c0262af	bellard	gen_op_fpush();
4423	2c0262af	bellard	gen_op_fldpi_ST0();
4424	2c0262af	bellard	break;
4425	2c0262af	bellard	case 4:
4426	2c0262af	bellard	gen_op_fpush();
4427	2c0262af	bellard	gen_op_fldlg2_ST0();
4428	2c0262af	bellard	break;
4429	2c0262af	bellard	case 5:
4430	2c0262af	bellard	gen_op_fpush();
4431	2c0262af	bellard	gen_op_fldln2_ST0();
4432	2c0262af	bellard	break;
4433	2c0262af	bellard	case 6:
4434	2c0262af	bellard	gen_op_fpush();
4435	2c0262af	bellard	gen_op_fldz_ST0();
4436	2c0262af	bellard	break;
4437	2c0262af	bellard	default:
4438	2c0262af	bellard	goto illegal_op;
4439	2c0262af	bellard	}
4440	2c0262af	bellard	}
4441	2c0262af	bellard	break;
4442	2c0262af	bellard	case 0x0e: /* grp d9/6 */
4443	2c0262af	bellard	switch(rm) {
4444	2c0262af	bellard	case 0: /* f2xm1 */
4445	2c0262af	bellard	gen_op_f2xm1();
4446	2c0262af	bellard	break;
4447	2c0262af	bellard	case 1: /* fyl2x */
4448	2c0262af	bellard	gen_op_fyl2x();
4449	2c0262af	bellard	break;
4450	2c0262af	bellard	case 2: /* fptan */
4451	2c0262af	bellard	gen_op_fptan();
4452	2c0262af	bellard	break;
4453	2c0262af	bellard	case 3: /* fpatan */
4454	2c0262af	bellard	gen_op_fpatan();
4455	2c0262af	bellard	break;
4456	2c0262af	bellard	case 4: /* fxtract */
4457	2c0262af	bellard	gen_op_fxtract();
4458	2c0262af	bellard	break;
4459	2c0262af	bellard	case 5: /* fprem1 */
4460	2c0262af	bellard	gen_op_fprem1();
4461	2c0262af	bellard	break;
4462	2c0262af	bellard	case 6: /* fdecstp */
4463	2c0262af	bellard	gen_op_fdecstp();
4464	2c0262af	bellard	break;
4465	2c0262af	bellard	default:
4466	2c0262af	bellard	case 7: /* fincstp */
4467	2c0262af	bellard	gen_op_fincstp();
4468	2c0262af	bellard	break;
4469	2c0262af	bellard	}
4470	2c0262af	bellard	break;
4471	2c0262af	bellard	case 0x0f: /* grp d9/7 */
4472	2c0262af	bellard	switch(rm) {
4473	2c0262af	bellard	case 0: /* fprem */
4474	2c0262af	bellard	gen_op_fprem();
4475	2c0262af	bellard	break;
4476	2c0262af	bellard	case 1: /* fyl2xp1 */
4477	2c0262af	bellard	gen_op_fyl2xp1();
4478	2c0262af	bellard	break;
4479	2c0262af	bellard	case 2: /* fsqrt */
4480	2c0262af	bellard	gen_op_fsqrt();
4481	2c0262af	bellard	break;
4482	2c0262af	bellard	case 3: /* fsincos */
4483	2c0262af	bellard	gen_op_fsincos();
4484	2c0262af	bellard	break;
4485	2c0262af	bellard	case 5: /* fscale */
4486	2c0262af	bellard	gen_op_fscale();
4487	2c0262af	bellard	break;
4488	2c0262af	bellard	case 4: /* frndint */
4489	2c0262af	bellard	gen_op_frndint();
4490	2c0262af	bellard	break;
4491	2c0262af	bellard	case 6: /* fsin */
4492	2c0262af	bellard	gen_op_fsin();
4493	2c0262af	bellard	break;
4494	2c0262af	bellard	default:
4495	2c0262af	bellard	case 7: /* fcos */
4496	2c0262af	bellard	gen_op_fcos();
4497	2c0262af	bellard	break;
4498	2c0262af	bellard	}
4499	2c0262af	bellard	break;
4500	2c0262af	bellard	case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
4501	2c0262af	bellard	case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
4502	2c0262af	bellard	case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
4503	2c0262af	bellard	{
4504	2c0262af	bellard	int op1;
4505	2c0262af	bellard
4506	2c0262af	bellard	op1 = op & 7;
4507	2c0262af	bellard	if (op >= 0x20) {
4508	2c0262af	bellard	gen_op_fp_arith_STN_ST0[op1](opreg);
4509	2c0262af	bellard	if (op >= 0x30)
4510	2c0262af	bellard	gen_op_fpop();
4511	2c0262af	bellard	} else {
4512	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4513	2c0262af	bellard	gen_op_fp_arith_ST0_FT0[op1]();
4514	2c0262af	bellard	}
4515	2c0262af	bellard	}
4516	2c0262af	bellard	break;
4517	2c0262af	bellard	case 0x02: /* fcom */
4518	c169c906	bellard	case 0x22: /* fcom2, undocumented op */
4519	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4520	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4521	2c0262af	bellard	break;
4522	2c0262af	bellard	case 0x03: /* fcomp */
4523	c169c906	bellard	case 0x23: /* fcomp3, undocumented op */
4524	c169c906	bellard	case 0x32: /* fcomp5, undocumented op */
4525	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4526	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4527	2c0262af	bellard	gen_op_fpop();
4528	2c0262af	bellard	break;
4529	2c0262af	bellard	case 0x15: /* da/5 */
4530	2c0262af	bellard	switch(rm) {
4531	2c0262af	bellard	case 1: /* fucompp */
4532	2c0262af	bellard	gen_op_fmov_FT0_STN(1);
4533	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4534	2c0262af	bellard	gen_op_fpop();
4535	2c0262af	bellard	gen_op_fpop();
4536	2c0262af	bellard	break;
4537	2c0262af	bellard	default:
4538	2c0262af	bellard	goto illegal_op;
4539	2c0262af	bellard	}
4540	2c0262af	bellard	break;
4541	2c0262af	bellard	case 0x1c:
4542	2c0262af	bellard	switch(rm) {
4543	2c0262af	bellard	case 0: /* feni (287 only, just do nop here) */
4544	2c0262af	bellard	break;
4545	2c0262af	bellard	case 1: /* fdisi (287 only, just do nop here) */
4546	2c0262af	bellard	break;
4547	2c0262af	bellard	case 2: /* fclex */
4548	2c0262af	bellard	gen_op_fclex();
4549	2c0262af	bellard	break;
4550	2c0262af	bellard	case 3: /* fninit */
4551	2c0262af	bellard	gen_op_fninit();
4552	2c0262af	bellard	break;
4553	2c0262af	bellard	case 4: /* fsetpm (287 only, just do nop here) */
4554	2c0262af	bellard	break;
4555	2c0262af	bellard	default:
4556	2c0262af	bellard	goto illegal_op;
4557	2c0262af	bellard	}
4558	2c0262af	bellard	break;
4559	2c0262af	bellard	case 0x1d: /* fucomi */
4560	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4561	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4562	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4563	2c0262af	bellard	gen_op_fucomi_ST0_FT0();
4564	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4565	2c0262af	bellard	break;
4566	2c0262af	bellard	case 0x1e: /* fcomi */
4567	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4568	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4569	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4570	2c0262af	bellard	gen_op_fcomi_ST0_FT0();
4571	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4572	2c0262af	bellard	break;
4573	658c8bda	bellard	case 0x28: /* ffree sti */
4574	658c8bda	bellard	gen_op_ffree_STN(opreg);
4575	658c8bda	bellard	break;
4576	2c0262af	bellard	case 0x2a: /* fst sti */
4577	2c0262af	bellard	gen_op_fmov_STN_ST0(opreg);
4578	2c0262af	bellard	break;
4579	2c0262af	bellard	case 0x2b: /* fstp sti */
4580	c169c906	bellard	case 0x0b: /* fstp1 sti, undocumented op */
4581	c169c906	bellard	case 0x3a: /* fstp8 sti, undocumented op */
4582	c169c906	bellard	case 0x3b: /* fstp9 sti, undocumented op */
4583	2c0262af	bellard	gen_op_fmov_STN_ST0(opreg);
4584	2c0262af	bellard	gen_op_fpop();
4585	2c0262af	bellard	break;
4586	2c0262af	bellard	case 0x2c: /* fucom st(i) */
4587	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4588	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4589	2c0262af	bellard	break;
4590	2c0262af	bellard	case 0x2d: /* fucomp st(i) */
4591	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4592	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4593	2c0262af	bellard	gen_op_fpop();
4594	2c0262af	bellard	break;
4595	2c0262af	bellard	case 0x33: /* de/3 */
4596	2c0262af	bellard	switch(rm) {
4597	2c0262af	bellard	case 1: /* fcompp */
4598	2c0262af	bellard	gen_op_fmov_FT0_STN(1);
4599	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4600	2c0262af	bellard	gen_op_fpop();
4601	2c0262af	bellard	gen_op_fpop();
4602	2c0262af	bellard	break;
4603	2c0262af	bellard	default:
4604	2c0262af	bellard	goto illegal_op;
4605	2c0262af	bellard	}
4606	2c0262af	bellard	break;
4607	c169c906	bellard	case 0x38: /* ffreep sti, undocumented op */
4608	c169c906	bellard	gen_op_ffree_STN(opreg);
4609	c169c906	bellard	gen_op_fpop();
4610	c169c906	bellard	break;
4611	2c0262af	bellard	case 0x3c: /* df/4 */
4612	2c0262af	bellard	switch(rm) {
4613	2c0262af	bellard	case 0:
4614	2c0262af	bellard	gen_op_fnstsw_EAX();
4615	2c0262af	bellard	break;
4616	2c0262af	bellard	default:
4617	2c0262af	bellard	goto illegal_op;
4618	2c0262af	bellard	}
4619	2c0262af	bellard	break;
4620	2c0262af	bellard	case 0x3d: /* fucomip */
4621	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4622	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4623	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4624	2c0262af	bellard	gen_op_fucomi_ST0_FT0();
4625	2c0262af	bellard	gen_op_fpop();
4626	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4627	2c0262af	bellard	break;
4628	2c0262af	bellard	case 0x3e: /* fcomip */
4629	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4630	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4631	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4632	2c0262af	bellard	gen_op_fcomi_ST0_FT0();
4633	2c0262af	bellard	gen_op_fpop();
4634	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4635	2c0262af	bellard	break;
4636	a2cc3b24	bellard	case 0x10 ... 0x13: /* fcmovxx */
4637	a2cc3b24	bellard	case 0x18 ... 0x1b:
4638	a2cc3b24	bellard	{
4639	a2cc3b24	bellard	int op1;
4640	a2cc3b24	bellard	const static uint8_t fcmov_cc[8] = {
4641	a2cc3b24	bellard	(JCC_B << 1),
4642	a2cc3b24	bellard	(JCC_Z << 1),
4643	a2cc3b24	bellard	(JCC_BE << 1),
4644	a2cc3b24	bellard	(JCC_P << 1),
4645	a2cc3b24	bellard	};
4646	a2cc3b24	bellard	op1 = fcmov_cc[op & 3] \| ((op >> 3) & 1);
4647	a2cc3b24	bellard	gen_setcc(s, op1);
4648	a2cc3b24	bellard	gen_op_fcmov_ST0_STN_T0(opreg);
4649	a2cc3b24	bellard	}
4650	a2cc3b24	bellard	break;
4651	2c0262af	bellard	default:
4652	2c0262af	bellard	goto illegal_op;
4653	2c0262af	bellard	}
4654	2c0262af	bellard	}
4655	7eee2a50	bellard	#ifdef USE_CODE_COPY
4656	7eee2a50	bellard	s->tb->cflags \|= CF_TB_FP_USED;
4657	7eee2a50	bellard	#endif
4658	2c0262af	bellard	break;
4659	2c0262af	bellard	/************************/
4660	2c0262af	bellard	/* string ops */
4661	2c0262af	bellard
4662	2c0262af	bellard	case 0xa4: /* movsS */
4663	2c0262af	bellard	case 0xa5:
4664	2c0262af	bellard	if ((b & 1) == 0)
4665	2c0262af	bellard	ot = OT_BYTE;
4666	2c0262af	bellard	else
4667	14ce26e7	bellard	ot = dflag + OT_WORD;
4668	2c0262af	bellard
4669	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4670	2c0262af	bellard	gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4671	2c0262af	bellard	} else {
4672	2c0262af	bellard	gen_movs(s, ot);
4673	2c0262af	bellard	}
4674	2c0262af	bellard	break;
4675	2c0262af	bellard
4676	2c0262af	bellard	case 0xaa: /* stosS */
4677	2c0262af	bellard	case 0xab:
4678	2c0262af	bellard	if ((b & 1) == 0)
4679	2c0262af	bellard	ot = OT_BYTE;
4680	2c0262af	bellard	else
4681	14ce26e7	bellard	ot = dflag + OT_WORD;
4682	2c0262af	bellard
4683	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4684	2c0262af	bellard	gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4685	2c0262af	bellard	} else {
4686	2c0262af	bellard	gen_stos(s, ot);
4687	2c0262af	bellard	}
4688	2c0262af	bellard	break;
4689	2c0262af	bellard	case 0xac: /* lodsS */
4690	2c0262af	bellard	case 0xad:
4691	2c0262af	bellard	if ((b & 1) == 0)
4692	2c0262af	bellard	ot = OT_BYTE;
4693	2c0262af	bellard	else
4694	14ce26e7	bellard	ot = dflag + OT_WORD;
4695	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4696	2c0262af	bellard	gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4697	2c0262af	bellard	} else {
4698	2c0262af	bellard	gen_lods(s, ot);
4699	2c0262af	bellard	}
4700	2c0262af	bellard	break;
4701	2c0262af	bellard	case 0xae: /* scasS */
4702	2c0262af	bellard	case 0xaf:
4703	2c0262af	bellard	if ((b & 1) == 0)
4704	2c0262af	bellard	ot = OT_BYTE;
4705	2c0262af	bellard	else
4706	14ce26e7	bellard	ot = dflag + OT_WORD;
4707	2c0262af	bellard	if (prefixes & PREFIX_REPNZ) {
4708	2c0262af	bellard	gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4709	2c0262af	bellard	} else if (prefixes & PREFIX_REPZ) {
4710	2c0262af	bellard	gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4711	2c0262af	bellard	} else {
4712	2c0262af	bellard	gen_scas(s, ot);
4713	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
4714	2c0262af	bellard	}
4715	2c0262af	bellard	break;
4716	2c0262af	bellard
4717	2c0262af	bellard	case 0xa6: /* cmpsS */
4718	2c0262af	bellard	case 0xa7:
4719	2c0262af	bellard	if ((b & 1) == 0)
4720	2c0262af	bellard	ot = OT_BYTE;
4721	2c0262af	bellard	else
4722	14ce26e7	bellard	ot = dflag + OT_WORD;
4723	2c0262af	bellard	if (prefixes & PREFIX_REPNZ) {
4724	2c0262af	bellard	gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4725	2c0262af	bellard	} else if (prefixes & PREFIX_REPZ) {
4726	2c0262af	bellard	gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4727	2c0262af	bellard	} else {
4728	2c0262af	bellard	gen_cmps(s, ot);
4729	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
4730	2c0262af	bellard	}
4731	2c0262af	bellard	break;
4732	2c0262af	bellard	case 0x6c: /* insS */
4733	2c0262af	bellard	case 0x6d:
4734	f115e911	bellard	if ((b & 1) == 0)
4735	f115e911	bellard	ot = OT_BYTE;
4736	f115e911	bellard	else
4737	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4738	f115e911	bellard	gen_check_io(s, ot, 1, pc_start - s->cs_base);
4739	f115e911	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4740	f115e911	bellard	gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4741	2c0262af	bellard	} else {
4742	f115e911	bellard	gen_ins(s, ot);
4743	2c0262af	bellard	}
4744	2c0262af	bellard	break;
4745	2c0262af	bellard	case 0x6e: /* outsS */
4746	2c0262af	bellard	case 0x6f:
4747	f115e911	bellard	if ((b & 1) == 0)
4748	f115e911	bellard	ot = OT_BYTE;
4749	f115e911	bellard	else
4750	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4751	f115e911	bellard	gen_check_io(s, ot, 1, pc_start - s->cs_base);
4752	f115e911	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4753	f115e911	bellard	gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4754	2c0262af	bellard	} else {
4755	f115e911	bellard	gen_outs(s, ot);
4756	2c0262af	bellard	}
4757	2c0262af	bellard	break;
4758	2c0262af	bellard
4759	2c0262af	bellard	/************************/
4760	2c0262af	bellard	/* port I/O */
4761	2c0262af	bellard	case 0xe4:
4762	2c0262af	bellard	case 0xe5:
4763	f115e911	bellard	if ((b & 1) == 0)
4764	f115e911	bellard	ot = OT_BYTE;
4765	f115e911	bellard	else
4766	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4767	f115e911	bellard	val = ldub_code(s->pc++);
4768	f115e911	bellard	gen_op_movl_T0_im(val);
4769	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4770	f115e911	bellard	gen_op_in[ot]();
4771	f115e911	bellard	gen_op_mov_reg_T1[ot][R_EAX]();
4772	2c0262af	bellard	break;
4773	2c0262af	bellard	case 0xe6:
4774	2c0262af	bellard	case 0xe7:
4775	f115e911	bellard	if ((b & 1) == 0)
4776	f115e911	bellard	ot = OT_BYTE;
4777	f115e911	bellard	else
4778	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4779	f115e911	bellard	val = ldub_code(s->pc++);
4780	f115e911	bellard	gen_op_movl_T0_im(val);
4781	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4782	f115e911	bellard	gen_op_mov_TN_reg[ot][1][R_EAX]();
4783	f115e911	bellard	gen_op_out[ot]();
4784	2c0262af	bellard	break;
4785	2c0262af	bellard	case 0xec:
4786	2c0262af	bellard	case 0xed:
4787	f115e911	bellard	if ((b & 1) == 0)
4788	f115e911	bellard	ot = OT_BYTE;
4789	f115e911	bellard	else
4790	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4791	f115e911	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4792	4f31916f	bellard	gen_op_andl_T0_ffff();
4793	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4794	f115e911	bellard	gen_op_in[ot]();
4795	f115e911	bellard	gen_op_mov_reg_T1[ot][R_EAX]();
4796	2c0262af	bellard	break;
4797	2c0262af	bellard	case 0xee:
4798	2c0262af	bellard	case 0xef:
4799	f115e911	bellard	if ((b & 1) == 0)
4800	f115e911	bellard	ot = OT_BYTE;
4801	f115e911	bellard	else
4802	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4803	f115e911	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4804	4f31916f	bellard	gen_op_andl_T0_ffff();
4805	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4806	f115e911	bellard	gen_op_mov_TN_reg[ot][1][R_EAX]();
4807	f115e911	bellard	gen_op_out[ot]();
4808	2c0262af	bellard	break;
4809	2c0262af	bellard
4810	2c0262af	bellard	/************************/
4811	2c0262af	bellard	/* control */
4812	2c0262af	bellard	case 0xc2: /* ret im */
4813	61382a50	bellard	val = ldsw_code(s->pc);
4814	2c0262af	bellard	s->pc += 2;
4815	2c0262af	bellard	gen_pop_T0(s);
4816	8f091a59	bellard	if (CODE64(s) && s->dflag)
4817	8f091a59	bellard	s->dflag = 2;
4818	2c0262af	bellard	gen_stack_update(s, val + (2 << s->dflag));
4819	2c0262af	bellard	if (s->dflag == 0)
4820	2c0262af	bellard	gen_op_andl_T0_ffff();
4821	2c0262af	bellard	gen_op_jmp_T0();
4822	2c0262af	bellard	gen_eob(s);
4823	2c0262af	bellard	break;
4824	2c0262af	bellard	case 0xc3: /* ret */
4825	2c0262af	bellard	gen_pop_T0(s);
4826	2c0262af	bellard	gen_pop_update(s);
4827	2c0262af	bellard	if (s->dflag == 0)
4828	2c0262af	bellard	gen_op_andl_T0_ffff();
4829	2c0262af	bellard	gen_op_jmp_T0();
4830	2c0262af	bellard	gen_eob(s);
4831	2c0262af	bellard	break;
4832	2c0262af	bellard	case 0xca: /* lret im */
4833	61382a50	bellard	val = ldsw_code(s->pc);
4834	2c0262af	bellard	s->pc += 2;
4835	2c0262af	bellard	do_lret:
4836	2c0262af	bellard	if (s->pe && !s->vm86) {
4837	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4838	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4839	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4840	2c0262af	bellard	gen_op_lret_protected(s->dflag, val);
4841	2c0262af	bellard	} else {
4842	2c0262af	bellard	gen_stack_A0(s);
4843	2c0262af	bellard	/* pop offset */
4844	2c0262af	bellard	gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4845	2c0262af	bellard	if (s->dflag == 0)
4846	2c0262af	bellard	gen_op_andl_T0_ffff();
4847	2c0262af	bellard	/* NOTE: keeping EIP updated is not a problem in case of
4848	2c0262af	bellard	exception */
4849	2c0262af	bellard	gen_op_jmp_T0();
4850	2c0262af	bellard	/* pop selector */
4851	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
4852	2c0262af	bellard	gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4853	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
4854	2c0262af	bellard	/* add stack offset */
4855	2c0262af	bellard	gen_stack_update(s, val + (4 << s->dflag));
4856	2c0262af	bellard	}
4857	2c0262af	bellard	gen_eob(s);
4858	2c0262af	bellard	break;
4859	2c0262af	bellard	case 0xcb: /* lret */
4860	2c0262af	bellard	val = 0;
4861	2c0262af	bellard	goto do_lret;
4862	2c0262af	bellard	case 0xcf: /* iret */
4863	2c0262af	bellard	if (!s->pe) {
4864	2c0262af	bellard	/* real mode */
4865	2c0262af	bellard	gen_op_iret_real(s->dflag);
4866	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4867	f115e911	bellard	} else if (s->vm86) {
4868	f115e911	bellard	if (s->iopl != 3) {
4869	f115e911	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4870	f115e911	bellard	} else {
4871	f115e911	bellard	gen_op_iret_real(s->dflag);
4872	f115e911	bellard	s->cc_op = CC_OP_EFLAGS;
4873	f115e911	bellard	}
4874	2c0262af	bellard	} else {
4875	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4876	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4877	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4878	08cea4ee	bellard	gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
4879	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4880	2c0262af	bellard	}
4881	2c0262af	bellard	gen_eob(s);
4882	2c0262af	bellard	break;
4883	2c0262af	bellard	case 0xe8: /* call im */
4884	2c0262af	bellard	{
4885	14ce26e7	bellard	if (dflag)
4886	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4887	14ce26e7	bellard	else
4888	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4889	2c0262af	bellard	next_eip = s->pc - s->cs_base;
4890	14ce26e7	bellard	tval += next_eip;
4891	2c0262af	bellard	if (s->dflag == 0)
4892	14ce26e7	bellard	tval &= 0xffff;
4893	14ce26e7	bellard	gen_movtl_T0_im(next_eip);
4894	2c0262af	bellard	gen_push_T0(s);
4895	14ce26e7	bellard	gen_jmp(s, tval);
4896	2c0262af	bellard	}
4897	2c0262af	bellard	break;
4898	2c0262af	bellard	case 0x9a: /* lcall im */
4899	2c0262af	bellard	{
4900	2c0262af	bellard	unsigned int selector, offset;
4901	14ce26e7	bellard
4902	14ce26e7	bellard	if (CODE64(s))
4903	14ce26e7	bellard	goto illegal_op;
4904	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4905	2c0262af	bellard	offset = insn_get(s, ot);
4906	2c0262af	bellard	selector = insn_get(s, OT_WORD);
4907	2c0262af	bellard
4908	2c0262af	bellard	gen_op_movl_T0_im(selector);
4909	14ce26e7	bellard	gen_op_movl_T1_imu(offset);
4910	2c0262af	bellard	}
4911	2c0262af	bellard	goto do_lcall;
4912	2c0262af	bellard	case 0xe9: /* jmp */
4913	14ce26e7	bellard	if (dflag)
4914	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4915	14ce26e7	bellard	else
4916	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4917	14ce26e7	bellard	tval += s->pc - s->cs_base;
4918	2c0262af	bellard	if (s->dflag == 0)
4919	14ce26e7	bellard	tval &= 0xffff;
4920	14ce26e7	bellard	gen_jmp(s, tval);
4921	2c0262af	bellard	break;
4922	2c0262af	bellard	case 0xea: /* ljmp im */
4923	2c0262af	bellard	{
4924	2c0262af	bellard	unsigned int selector, offset;
4925	2c0262af	bellard
4926	14ce26e7	bellard	if (CODE64(s))
4927	14ce26e7	bellard	goto illegal_op;
4928	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4929	2c0262af	bellard	offset = insn_get(s, ot);
4930	2c0262af	bellard	selector = insn_get(s, OT_WORD);
4931	2c0262af	bellard
4932	2c0262af	bellard	gen_op_movl_T0_im(selector);
4933	14ce26e7	bellard	gen_op_movl_T1_imu(offset);
4934	2c0262af	bellard	}
4935	2c0262af	bellard	goto do_ljmp;
4936	2c0262af	bellard	case 0xeb: /* jmp Jb */
4937	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
4938	14ce26e7	bellard	tval += s->pc - s->cs_base;
4939	2c0262af	bellard	if (s->dflag == 0)
4940	14ce26e7	bellard	tval &= 0xffff;
4941	14ce26e7	bellard	gen_jmp(s, tval);
4942	2c0262af	bellard	break;
4943	2c0262af	bellard	case 0x70 ... 0x7f: /* jcc Jb */
4944	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
4945	2c0262af	bellard	goto do_jcc;
4946	2c0262af	bellard	case 0x180 ... 0x18f: /* jcc Jv */
4947	2c0262af	bellard	if (dflag) {
4948	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4949	2c0262af	bellard	} else {
4950	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4951	2c0262af	bellard	}
4952	2c0262af	bellard	do_jcc:
4953	2c0262af	bellard	next_eip = s->pc - s->cs_base;
4954	14ce26e7	bellard	tval += next_eip;
4955	2c0262af	bellard	if (s->dflag == 0)
4956	14ce26e7	bellard	tval &= 0xffff;
4957	14ce26e7	bellard	gen_jcc(s, b, tval, next_eip);
4958	2c0262af	bellard	break;
4959	2c0262af	bellard
4960	2c0262af	bellard	case 0x190 ... 0x19f: /* setcc Gv */
4961	61382a50	bellard	modrm = ldub_code(s->pc++);
4962	2c0262af	bellard	gen_setcc(s, b);
4963	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
4964	2c0262af	bellard	break;
4965	2c0262af	bellard	case 0x140 ... 0x14f: /* cmov Gv, Ev */
4966	14ce26e7	bellard	ot = dflag + OT_WORD;
4967	61382a50	bellard	modrm = ldub_code(s->pc++);
4968	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4969	2c0262af	bellard	mod = (modrm >> 6) & 3;
4970	2c0262af	bellard	gen_setcc(s, b);
4971	2c0262af	bellard	if (mod != 3) {
4972	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4973	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4974	2c0262af	bellard	} else {
4975	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4976	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
4977	2c0262af	bellard	}
4978	2c0262af	bellard	gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
4979	2c0262af	bellard	break;
4980	2c0262af	bellard
4981	2c0262af	bellard	/************************/
4982	2c0262af	bellard	/* flags */
4983	2c0262af	bellard	case 0x9c: /* pushf */
4984	2c0262af	bellard	if (s->vm86 && s->iopl != 3) {
4985	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4986	2c0262af	bellard	} else {
4987	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4988	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4989	2c0262af	bellard	gen_op_movl_T0_eflags();
4990	2c0262af	bellard	gen_push_T0(s);
4991	2c0262af	bellard	}
4992	2c0262af	bellard	break;
4993	2c0262af	bellard	case 0x9d: /* popf */
4994	2c0262af	bellard	if (s->vm86 && s->iopl != 3) {
4995	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4996	2c0262af	bellard	} else {
4997	2c0262af	bellard	gen_pop_T0(s);
4998	2c0262af	bellard	if (s->cpl == 0) {
4999	2c0262af	bellard	if (s->dflag) {
5000	2c0262af	bellard	gen_op_movl_eflags_T0_cpl0();
5001	2c0262af	bellard	} else {
5002	2c0262af	bellard	gen_op_movw_eflags_T0_cpl0();
5003	2c0262af	bellard	}
5004	2c0262af	bellard	} else {
5005	4136f33c	bellard	if (s->cpl <= s->iopl) {
5006	4136f33c	bellard	if (s->dflag) {
5007	4136f33c	bellard	gen_op_movl_eflags_T0_io();
5008	4136f33c	bellard	} else {
5009	4136f33c	bellard	gen_op_movw_eflags_T0_io();
5010	4136f33c	bellard	}
5011	2c0262af	bellard	} else {
5012	4136f33c	bellard	if (s->dflag) {
5013	4136f33c	bellard	gen_op_movl_eflags_T0();
5014	4136f33c	bellard	} else {
5015	4136f33c	bellard	gen_op_movw_eflags_T0();
5016	4136f33c	bellard	}
5017	2c0262af	bellard	}
5018	2c0262af	bellard	}
5019	2c0262af	bellard	gen_pop_update(s);
5020	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5021	2c0262af	bellard	/* abort translation because TF flag may change */
5022	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5023	2c0262af	bellard	gen_eob(s);
5024	2c0262af	bellard	}
5025	2c0262af	bellard	break;
5026	2c0262af	bellard	case 0x9e: /* sahf */
5027	14ce26e7	bellard	if (CODE64(s))
5028	14ce26e7	bellard	goto illegal_op;
5029	2c0262af	bellard	gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
5030	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5031	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5032	2c0262af	bellard	gen_op_movb_eflags_T0();
5033	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5034	2c0262af	bellard	break;
5035	2c0262af	bellard	case 0x9f: /* lahf */
5036	14ce26e7	bellard	if (CODE64(s))
5037	14ce26e7	bellard	goto illegal_op;
5038	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5039	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5040	2c0262af	bellard	gen_op_movl_T0_eflags();
5041	2c0262af	bellard	gen_op_mov_reg_T0[OT_BYTE][R_AH]();
5042	2c0262af	bellard	break;
5043	2c0262af	bellard	case 0xf5: /* cmc */
5044	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5045	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5046	2c0262af	bellard	gen_op_cmc();
5047	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5048	2c0262af	bellard	break;
5049	2c0262af	bellard	case 0xf8: /* clc */
5050	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5051	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5052	2c0262af	bellard	gen_op_clc();
5053	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5054	2c0262af	bellard	break;
5055	2c0262af	bellard	case 0xf9: /* stc */
5056	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5057	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5058	2c0262af	bellard	gen_op_stc();
5059	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5060	2c0262af	bellard	break;
5061	2c0262af	bellard	case 0xfc: /* cld */
5062	2c0262af	bellard	gen_op_cld();
5063	2c0262af	bellard	break;
5064	2c0262af	bellard	case 0xfd: /* std */
5065	2c0262af	bellard	gen_op_std();
5066	2c0262af	bellard	break;
5067	2c0262af	bellard
5068	2c0262af	bellard	/************************/
5069	2c0262af	bellard	/* bit operations */
5070	2c0262af	bellard	case 0x1ba: /* bt/bts/btr/btc Gv, im */
5071	14ce26e7	bellard	ot = dflag + OT_WORD;
5072	61382a50	bellard	modrm = ldub_code(s->pc++);
5073	14ce26e7	bellard	op = ((modrm >> 3) & 7) \| rex_r;
5074	2c0262af	bellard	mod = (modrm >> 6) & 3;
5075	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5076	2c0262af	bellard	if (mod != 3) {
5077	14ce26e7	bellard	s->rip_offset = 1;
5078	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5079	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5080	2c0262af	bellard	} else {
5081	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5082	2c0262af	bellard	}
5083	2c0262af	bellard	/* load shift */
5084	61382a50	bellard	val = ldub_code(s->pc++);
5085	2c0262af	bellard	gen_op_movl_T1_im(val);
5086	2c0262af	bellard	if (op < 4)
5087	2c0262af	bellard	goto illegal_op;
5088	2c0262af	bellard	op -= 4;
5089	2c0262af	bellard	gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5090	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
5091	2c0262af	bellard	if (op != 0) {
5092	2c0262af	bellard	if (mod != 3)
5093	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5094	2c0262af	bellard	else
5095	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
5096	2c0262af	bellard	gen_op_update_bt_cc();
5097	2c0262af	bellard	}
5098	2c0262af	bellard	break;
5099	2c0262af	bellard	case 0x1a3: /* bt Gv, Ev */
5100	2c0262af	bellard	op = 0;
5101	2c0262af	bellard	goto do_btx;
5102	2c0262af	bellard	case 0x1ab: /* bts */
5103	2c0262af	bellard	op = 1;
5104	2c0262af	bellard	goto do_btx;
5105	2c0262af	bellard	case 0x1b3: /* btr */
5106	2c0262af	bellard	op = 2;
5107	2c0262af	bellard	goto do_btx;
5108	2c0262af	bellard	case 0x1bb: /* btc */
5109	2c0262af	bellard	op = 3;
5110	2c0262af	bellard	do_btx:
5111	14ce26e7	bellard	ot = dflag + OT_WORD;
5112	61382a50	bellard	modrm = ldub_code(s->pc++);
5113	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5114	2c0262af	bellard	mod = (modrm >> 6) & 3;
5115	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5116	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][1][reg]();
5117	2c0262af	bellard	if (mod != 3) {
5118	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5119	2c0262af	bellard	/* specific case: we need to add a displacement */
5120	14ce26e7	bellard	gen_op_add_bit_A0_T1[ot - OT_WORD]();
5121	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5122	2c0262af	bellard	} else {
5123	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5124	2c0262af	bellard	}
5125	2c0262af	bellard	gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5126	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
5127	2c0262af	bellard	if (op != 0) {
5128	2c0262af	bellard	if (mod != 3)
5129	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5130	2c0262af	bellard	else
5131	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
5132	2c0262af	bellard	gen_op_update_bt_cc();
5133	2c0262af	bellard	}
5134	2c0262af	bellard	break;
5135	2c0262af	bellard	case 0x1bc: /* bsf */
5136	2c0262af	bellard	case 0x1bd: /* bsr */
5137	14ce26e7	bellard	ot = dflag + OT_WORD;
5138	61382a50	bellard	modrm = ldub_code(s->pc++);
5139	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5140	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5141	686f3f26	bellard	/* NOTE: in order to handle the 0 case, we must load the
5142	686f3f26	bellard	result. It could be optimized with a generated jump */
5143	686f3f26	bellard	gen_op_mov_TN_reg[ot][1][reg]();
5144	2c0262af	bellard	gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
5145	686f3f26	bellard	gen_op_mov_reg_T1[ot][reg]();
5146	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
5147	2c0262af	bellard	break;
5148	2c0262af	bellard	/************************/
5149	2c0262af	bellard	/* bcd */
5150	2c0262af	bellard	case 0x27: /* daa */
5151	14ce26e7	bellard	if (CODE64(s))
5152	14ce26e7	bellard	goto illegal_op;
5153	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5154	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5155	2c0262af	bellard	gen_op_daa();
5156	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5157	2c0262af	bellard	break;
5158	2c0262af	bellard	case 0x2f: /* das */
5159	14ce26e7	bellard	if (CODE64(s))
5160	14ce26e7	bellard	goto illegal_op;
5161	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5162	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5163	2c0262af	bellard	gen_op_das();
5164	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5165	2c0262af	bellard	break;
5166	2c0262af	bellard	case 0x37: /* aaa */
5167	14ce26e7	bellard	if (CODE64(s))
5168	14ce26e7	bellard	goto illegal_op;
5169	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5170	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5171	2c0262af	bellard	gen_op_aaa();
5172	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5173	2c0262af	bellard	break;
5174	2c0262af	bellard	case 0x3f: /* aas */
5175	14ce26e7	bellard	if (CODE64(s))
5176	14ce26e7	bellard	goto illegal_op;
5177	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5178	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5179	2c0262af	bellard	gen_op_aas();
5180	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5181	2c0262af	bellard	break;
5182	2c0262af	bellard	case 0xd4: /* aam */
5183	14ce26e7	bellard	if (CODE64(s))
5184	14ce26e7	bellard	goto illegal_op;
5185	61382a50	bellard	val = ldub_code(s->pc++);
5186	2c0262af	bellard	gen_op_aam(val);
5187	2c0262af	bellard	s->cc_op = CC_OP_LOGICB;
5188	2c0262af	bellard	break;
5189	2c0262af	bellard	case 0xd5: /* aad */
5190	14ce26e7	bellard	if (CODE64(s))
5191	14ce26e7	bellard	goto illegal_op;
5192	61382a50	bellard	val = ldub_code(s->pc++);
5193	2c0262af	bellard	gen_op_aad(val);
5194	2c0262af	bellard	s->cc_op = CC_OP_LOGICB;
5195	2c0262af	bellard	break;
5196	2c0262af	bellard	/************************/
5197	2c0262af	bellard	/* misc */
5198	2c0262af	bellard	case 0x90: /* nop */
5199	14ce26e7	bellard	/* XXX: xchg + rex handling */
5200	ab1f142b	bellard	/* XXX: correct lock test for all insn */
5201	ab1f142b	bellard	if (prefixes & PREFIX_LOCK)
5202	ab1f142b	bellard	goto illegal_op;
5203	2c0262af	bellard	break;
5204	2c0262af	bellard	case 0x9b: /* fwait */
5205	7eee2a50	bellard	if ((s->flags & (HF_MP_MASK \| HF_TS_MASK)) ==
5206	7eee2a50	bellard	(HF_MP_MASK \| HF_TS_MASK)) {
5207	7eee2a50	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5208	2ee73ac3	bellard	} else {
5209	2ee73ac3	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5210	2ee73ac3	bellard	gen_op_set_cc_op(s->cc_op);
5211	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5212	2ee73ac3	bellard	gen_op_fwait();
5213	7eee2a50	bellard	}
5214	2c0262af	bellard	break;
5215	2c0262af	bellard	case 0xcc: /* int3 */
5216	2c0262af	bellard	gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
5217	2c0262af	bellard	break;
5218	2c0262af	bellard	case 0xcd: /* int N */
5219	61382a50	bellard	val = ldub_code(s->pc++);
5220	f115e911	bellard	if (s->vm86 && s->iopl != 3) {
5221	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5222	f115e911	bellard	} else {
5223	f115e911	bellard	gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
5224	f115e911	bellard	}
5225	2c0262af	bellard	break;
5226	2c0262af	bellard	case 0xce: /* into */
5227	14ce26e7	bellard	if (CODE64(s))
5228	14ce26e7	bellard	goto illegal_op;
5229	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5230	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5231	a8ede8ba	bellard	gen_jmp_im(pc_start - s->cs_base);
5232	a8ede8ba	bellard	gen_op_into(s->pc - pc_start);
5233	2c0262af	bellard	break;
5234	2c0262af	bellard	case 0xf1: /* icebp (undocumented, exits to external debugger) */
5235	aba9d61e	bellard	#if 1
5236	2c0262af	bellard	gen_debug(s, pc_start - s->cs_base);
5237	aba9d61e	bellard	#else
5238	aba9d61e	bellard	/* start debug */
5239	aba9d61e	bellard	tb_flush(cpu_single_env);
5240	aba9d61e	bellard	cpu_set_log(CPU_LOG_INT \| CPU_LOG_TB_IN_ASM);
5241	aba9d61e	bellard	#endif
5242	2c0262af	bellard	break;
5243	2c0262af	bellard	case 0xfa: /* cli */
5244	2c0262af	bellard	if (!s->vm86) {
5245	2c0262af	bellard	if (s->cpl <= s->iopl) {
5246	2c0262af	bellard	gen_op_cli();
5247	2c0262af	bellard	} else {
5248	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5249	2c0262af	bellard	}
5250	2c0262af	bellard	} else {
5251	2c0262af	bellard	if (s->iopl == 3) {
5252	2c0262af	bellard	gen_op_cli();
5253	2c0262af	bellard	} else {
5254	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5255	2c0262af	bellard	}
5256	2c0262af	bellard	}
5257	2c0262af	bellard	break;
5258	2c0262af	bellard	case 0xfb: /* sti */
5259	2c0262af	bellard	if (!s->vm86) {
5260	2c0262af	bellard	if (s->cpl <= s->iopl) {
5261	2c0262af	bellard	gen_sti:
5262	2c0262af	bellard	gen_op_sti();
5263	2c0262af	bellard	/* interruptions are enabled only the first insn after sti */
5264	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
5265	a2cc3b24	bellard	_first_ does it */
5266	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5267	a2cc3b24	bellard	gen_op_set_inhibit_irq();
5268	2c0262af	bellard	/* give a chance to handle pending irqs */
5269	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5270	2c0262af	bellard	gen_eob(s);
5271	2c0262af	bellard	} else {
5272	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5273	2c0262af	bellard	}
5274	2c0262af	bellard	} else {
5275	2c0262af	bellard	if (s->iopl == 3) {
5276	2c0262af	bellard	goto gen_sti;
5277	2c0262af	bellard	} else {
5278	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5279	2c0262af	bellard	}
5280	2c0262af	bellard	}
5281	2c0262af	bellard	break;
5282	2c0262af	bellard	case 0x62: /* bound */
5283	14ce26e7	bellard	if (CODE64(s))
5284	14ce26e7	bellard	goto illegal_op;
5285	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
5286	61382a50	bellard	modrm = ldub_code(s->pc++);
5287	2c0262af	bellard	reg = (modrm >> 3) & 7;
5288	2c0262af	bellard	mod = (modrm >> 6) & 3;
5289	2c0262af	bellard	if (mod == 3)
5290	2c0262af	bellard	goto illegal_op;
5291	cabf23c3	bellard	gen_op_mov_TN_reg[ot][0][reg]();
5292	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5293	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5294	2c0262af	bellard	if (ot == OT_WORD)
5295	14ce26e7	bellard	gen_op_boundw();
5296	2c0262af	bellard	else
5297	14ce26e7	bellard	gen_op_boundl();
5298	2c0262af	bellard	break;
5299	2c0262af	bellard	case 0x1c8 ... 0x1cf: /* bswap reg */
5300	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
5301	14ce26e7	bellard	#ifdef TARGET_X86_64
5302	14ce26e7	bellard	if (dflag == 2) {
5303	14ce26e7	bellard	gen_op_mov_TN_reg[OT_QUAD][0][reg]();
5304	14ce26e7	bellard	gen_op_bswapq_T0();
5305	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][reg]();
5306	14ce26e7	bellard	} else
5307	14ce26e7	bellard	#endif
5308	14ce26e7	bellard	{
5309	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][reg]();
5310	14ce26e7	bellard	gen_op_bswapl_T0();
5311	14ce26e7	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
5312	14ce26e7	bellard	}
5313	2c0262af	bellard	break;
5314	2c0262af	bellard	case 0xd6: /* salc */
5315	14ce26e7	bellard	if (CODE64(s))
5316	14ce26e7	bellard	goto illegal_op;
5317	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5318	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5319	2c0262af	bellard	gen_op_salc();
5320	2c0262af	bellard	break;
5321	2c0262af	bellard	case 0xe0: /* loopnz */
5322	2c0262af	bellard	case 0xe1: /* loopz */
5323	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5324	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5325	2c0262af	bellard	/* FALL THRU */
5326	2c0262af	bellard	case 0xe2: /* loop */
5327	2c0262af	bellard	case 0xe3: /* jecxz */
5328	14ce26e7	bellard	{
5329	14ce26e7	bellard	int l1, l2;
5330	14ce26e7	bellard
5331	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
5332	14ce26e7	bellard	next_eip = s->pc - s->cs_base;
5333	14ce26e7	bellard	tval += next_eip;
5334	14ce26e7	bellard	if (s->dflag == 0)
5335	14ce26e7	bellard	tval &= 0xffff;
5336	14ce26e7	bellard
5337	14ce26e7	bellard	l1 = gen_new_label();
5338	14ce26e7	bellard	l2 = gen_new_label();
5339	14ce26e7	bellard	b &= 3;
5340	14ce26e7	bellard	if (b == 3) {
5341	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l1);
5342	14ce26e7	bellard	} else {
5343	14ce26e7	bellard	gen_op_dec_ECX[s->aflag]();
5344	0b9dc5e4	bellard	if (b <= 1)
5345	0b9dc5e4	bellard	gen_op_mov_T0_cc();
5346	14ce26e7	bellard	gen_op_loop[s->aflag][b](l1);
5347	14ce26e7	bellard	}
5348	14ce26e7	bellard
5349	14ce26e7	bellard	gen_jmp_im(next_eip);
5350	14ce26e7	bellard	gen_op_jmp_label(l2);
5351	14ce26e7	bellard	gen_set_label(l1);
5352	14ce26e7	bellard	gen_jmp_im(tval);
5353	14ce26e7	bellard	gen_set_label(l2);
5354	14ce26e7	bellard	gen_eob(s);
5355	14ce26e7	bellard	}
5356	2c0262af	bellard	break;
5357	2c0262af	bellard	case 0x130: /* wrmsr */
5358	2c0262af	bellard	case 0x132: /* rdmsr */
5359	2c0262af	bellard	if (s->cpl != 0) {
5360	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5361	2c0262af	bellard	} else {
5362	2c0262af	bellard	if (b & 2)
5363	2c0262af	bellard	gen_op_rdmsr();
5364	2c0262af	bellard	else
5365	2c0262af	bellard	gen_op_wrmsr();
5366	2c0262af	bellard	}
5367	2c0262af	bellard	break;
5368	2c0262af	bellard	case 0x131: /* rdtsc */
5369	2c0262af	bellard	gen_op_rdtsc();
5370	2c0262af	bellard	break;
5371	023fe10d	bellard	case 0x134: /* sysenter */
5372	14ce26e7	bellard	if (CODE64(s))
5373	14ce26e7	bellard	goto illegal_op;
5374	023fe10d	bellard	if (!s->pe) {
5375	023fe10d	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5376	023fe10d	bellard	} else {
5377	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5378	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
5379	023fe10d	bellard	s->cc_op = CC_OP_DYNAMIC;
5380	023fe10d	bellard	}
5381	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5382	023fe10d	bellard	gen_op_sysenter();
5383	023fe10d	bellard	gen_eob(s);
5384	023fe10d	bellard	}
5385	023fe10d	bellard	break;
5386	023fe10d	bellard	case 0x135: /* sysexit */
5387	14ce26e7	bellard	if (CODE64(s))
5388	14ce26e7	bellard	goto illegal_op;
5389	023fe10d	bellard	if (!s->pe) {
5390	023fe10d	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5391	023fe10d	bellard	} else {
5392	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5393	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
5394	023fe10d	bellard	s->cc_op = CC_OP_DYNAMIC;
5395	023fe10d	bellard	}
5396	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5397	023fe10d	bellard	gen_op_sysexit();
5398	023fe10d	bellard	gen_eob(s);
5399	023fe10d	bellard	}
5400	023fe10d	bellard	break;
5401	14ce26e7	bellard	#ifdef TARGET_X86_64
5402	14ce26e7	bellard	case 0x105: /* syscall */
5403	14ce26e7	bellard	/* XXX: is it usable in real mode ? */
5404	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5405	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5406	14ce26e7	bellard	s->cc_op = CC_OP_DYNAMIC;
5407	14ce26e7	bellard	}
5408	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5409	06c2f506	bellard	gen_op_syscall(s->pc - pc_start);
5410	14ce26e7	bellard	gen_eob(s);
5411	14ce26e7	bellard	break;
5412	14ce26e7	bellard	case 0x107: /* sysret */
5413	14ce26e7	bellard	if (!s->pe) {
5414	14ce26e7	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5415	14ce26e7	bellard	} else {
5416	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5417	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5418	14ce26e7	bellard	s->cc_op = CC_OP_DYNAMIC;
5419	14ce26e7	bellard	}
5420	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5421	14ce26e7	bellard	gen_op_sysret(s->dflag);
5422	aba9d61e	bellard	/* condition codes are modified only in long mode */
5423	aba9d61e	bellard	if (s->lma)
5424	aba9d61e	bellard	s->cc_op = CC_OP_EFLAGS;
5425	14ce26e7	bellard	gen_eob(s);
5426	14ce26e7	bellard	}
5427	14ce26e7	bellard	break;
5428	14ce26e7	bellard	#endif
5429	2c0262af	bellard	case 0x1a2: /* cpuid */
5430	2c0262af	bellard	gen_op_cpuid();
5431	2c0262af	bellard	break;
5432	2c0262af	bellard	case 0xf4: /* hlt */
5433	2c0262af	bellard	if (s->cpl != 0) {
5434	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5435	2c0262af	bellard	} else {
5436	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5437	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5438	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5439	2c0262af	bellard	gen_op_hlt();
5440	2c0262af	bellard	s->is_jmp = 3;
5441	2c0262af	bellard	}
5442	2c0262af	bellard	break;
5443	2c0262af	bellard	case 0x100:
5444	61382a50	bellard	modrm = ldub_code(s->pc++);
5445	2c0262af	bellard	mod = (modrm >> 6) & 3;
5446	2c0262af	bellard	op = (modrm >> 3) & 7;
5447	2c0262af	bellard	switch(op) {
5448	2c0262af	bellard	case 0: /* sldt */
5449	f115e911	bellard	if (!s->pe \|\| s->vm86)
5450	f115e911	bellard	goto illegal_op;
5451	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
5452	2c0262af	bellard	ot = OT_WORD;
5453	2c0262af	bellard	if (mod == 3)
5454	2c0262af	bellard	ot += s->dflag;
5455	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5456	2c0262af	bellard	break;
5457	2c0262af	bellard	case 2: /* lldt */
5458	f115e911	bellard	if (!s->pe \|\| s->vm86)
5459	f115e911	bellard	goto illegal_op;
5460	2c0262af	bellard	if (s->cpl != 0) {
5461	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5462	2c0262af	bellard	} else {
5463	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5464	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5465	2c0262af	bellard	gen_op_lldt_T0();
5466	2c0262af	bellard	}
5467	2c0262af	bellard	break;
5468	2c0262af	bellard	case 1: /* str */
5469	f115e911	bellard	if (!s->pe \|\| s->vm86)
5470	f115e911	bellard	goto illegal_op;
5471	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
5472	2c0262af	bellard	ot = OT_WORD;
5473	2c0262af	bellard	if (mod == 3)
5474	2c0262af	bellard	ot += s->dflag;
5475	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5476	2c0262af	bellard	break;
5477	2c0262af	bellard	case 3: /* ltr */
5478	f115e911	bellard	if (!s->pe \|\| s->vm86)
5479	f115e911	bellard	goto illegal_op;
5480	2c0262af	bellard	if (s->cpl != 0) {
5481	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5482	2c0262af	bellard	} else {
5483	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5484	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5485	2c0262af	bellard	gen_op_ltr_T0();
5486	2c0262af	bellard	}
5487	2c0262af	bellard	break;
5488	2c0262af	bellard	case 4: /* verr */
5489	2c0262af	bellard	case 5: /* verw */
5490	f115e911	bellard	if (!s->pe \|\| s->vm86)
5491	f115e911	bellard	goto illegal_op;
5492	f115e911	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5493	f115e911	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5494	f115e911	bellard	gen_op_set_cc_op(s->cc_op);
5495	f115e911	bellard	if (op == 4)
5496	f115e911	bellard	gen_op_verr();
5497	f115e911	bellard	else
5498	f115e911	bellard	gen_op_verw();
5499	f115e911	bellard	s->cc_op = CC_OP_EFLAGS;
5500	f115e911	bellard	break;
5501	2c0262af	bellard	default:
5502	2c0262af	bellard	goto illegal_op;
5503	2c0262af	bellard	}
5504	2c0262af	bellard	break;
5505	2c0262af	bellard	case 0x101:
5506	61382a50	bellard	modrm = ldub_code(s->pc++);
5507	2c0262af	bellard	mod = (modrm >> 6) & 3;
5508	2c0262af	bellard	op = (modrm >> 3) & 7;
5509	2c0262af	bellard	switch(op) {
5510	2c0262af	bellard	case 0: /* sgdt */
5511	2c0262af	bellard	case 1: /* sidt */
5512	2c0262af	bellard	if (mod == 3)
5513	2c0262af	bellard	goto illegal_op;
5514	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5515	2c0262af	bellard	if (op == 0)
5516	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
5517	2c0262af	bellard	else
5518	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
5519	2c0262af	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
5520	aba9d61e	bellard	gen_add_A0_im(s, 2);
5521	2c0262af	bellard	if (op == 0)
5522	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,gdt.base));
5523	2c0262af	bellard	else
5524	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,idt.base));
5525	2c0262af	bellard	if (!s->dflag)
5526	2c0262af	bellard	gen_op_andl_T0_im(0xffffff);
5527	14ce26e7	bellard	gen_op_st_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5528	2c0262af	bellard	break;
5529	2c0262af	bellard	case 2: /* lgdt */
5530	2c0262af	bellard	case 3: /* lidt */
5531	2c0262af	bellard	if (mod == 3)
5532	2c0262af	bellard	goto illegal_op;
5533	2c0262af	bellard	if (s->cpl != 0) {
5534	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5535	2c0262af	bellard	} else {
5536	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5537	2c0262af	bellard	gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
5538	aba9d61e	bellard	gen_add_A0_im(s, 2);
5539	14ce26e7	bellard	gen_op_ld_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5540	2c0262af	bellard	if (!s->dflag)
5541	2c0262af	bellard	gen_op_andl_T0_im(0xffffff);
5542	2c0262af	bellard	if (op == 2) {
5543	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base));
5544	2c0262af	bellard	gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
5545	2c0262af	bellard	} else {
5546	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base));
5547	2c0262af	bellard	gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
5548	2c0262af	bellard	}
5549	2c0262af	bellard	}
5550	2c0262af	bellard	break;
5551	2c0262af	bellard	case 4: /* smsw */
5552	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
5553	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
5554	2c0262af	bellard	break;
5555	2c0262af	bellard	case 6: /* lmsw */
5556	2c0262af	bellard	if (s->cpl != 0) {
5557	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5558	2c0262af	bellard	} else {
5559	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5560	2c0262af	bellard	gen_op_lmsw_T0();
5561	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5562	d71b9a8b	bellard	gen_eob(s);
5563	2c0262af	bellard	}
5564	2c0262af	bellard	break;
5565	2c0262af	bellard	case 7: /* invlpg */
5566	2c0262af	bellard	if (s->cpl != 0) {
5567	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5568	2c0262af	bellard	} else {
5569	14ce26e7	bellard	if (mod == 3) {
5570	14ce26e7	bellard	#ifdef TARGET_X86_64
5571	14ce26e7	bellard	if (CODE64(s) && (modrm & 7) == 0) {
5572	14ce26e7	bellard	/* swapgs */
5573	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base));
5574	14ce26e7	bellard	gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
5575	14ce26e7	bellard	gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
5576	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
5577	14ce26e7	bellard	} else
5578	14ce26e7	bellard	#endif
5579	14ce26e7	bellard	{
5580	14ce26e7	bellard	goto illegal_op;
5581	14ce26e7	bellard	}
5582	14ce26e7	bellard	} else {
5583	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5584	14ce26e7	bellard	gen_op_invlpg_A0();
5585	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5586	14ce26e7	bellard	gen_eob(s);
5587	14ce26e7	bellard	}
5588	2c0262af	bellard	}
5589	2c0262af	bellard	break;
5590	2c0262af	bellard	default:
5591	2c0262af	bellard	goto illegal_op;
5592	2c0262af	bellard	}
5593	2c0262af	bellard	break;
5594	3415a4dd	bellard	case 0x108: /* invd */
5595	3415a4dd	bellard	case 0x109: /* wbinvd */
5596	3415a4dd	bellard	if (s->cpl != 0) {
5597	3415a4dd	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5598	3415a4dd	bellard	} else {
5599	3415a4dd	bellard	/* nothing to do */
5600	3415a4dd	bellard	}
5601	3415a4dd	bellard	break;
5602	14ce26e7	bellard	case 0x63: /* arpl or movslS (x86_64) */
5603	14ce26e7	bellard	#ifdef TARGET_X86_64
5604	14ce26e7	bellard	if (CODE64(s)) {
5605	14ce26e7	bellard	int d_ot;
5606	14ce26e7	bellard	/* d_ot is the size of destination */
5607	14ce26e7	bellard	d_ot = dflag + OT_WORD;
5608	14ce26e7	bellard
5609	14ce26e7	bellard	modrm = ldub_code(s->pc++);
5610	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5611	14ce26e7	bellard	mod = (modrm >> 6) & 3;
5612	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5613	14ce26e7	bellard
5614	14ce26e7	bellard	if (mod == 3) {
5615	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][rm]();
5616	14ce26e7	bellard	/* sign extend */
5617	14ce26e7	bellard	if (d_ot == OT_QUAD)
5618	14ce26e7	bellard	gen_op_movslq_T0_T0();
5619	14ce26e7	bellard	gen_op_mov_reg_T0[d_ot][reg]();
5620	14ce26e7	bellard	} else {
5621	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5622	14ce26e7	bellard	if (d_ot == OT_QUAD) {
5623	14ce26e7	bellard	gen_op_lds_T0_A0[OT_LONG + s->mem_index]();
5624	14ce26e7	bellard	} else {
5625	14ce26e7	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5626	14ce26e7	bellard	}
5627	14ce26e7	bellard	gen_op_mov_reg_T0[d_ot][reg]();
5628	14ce26e7	bellard	}
5629	14ce26e7	bellard	} else
5630	14ce26e7	bellard	#endif
5631	14ce26e7	bellard	{
5632	14ce26e7	bellard	if (!s->pe \|\| s->vm86)
5633	14ce26e7	bellard	goto illegal_op;
5634	14ce26e7	bellard	ot = dflag ? OT_LONG : OT_WORD;
5635	14ce26e7	bellard	modrm = ldub_code(s->pc++);
5636	14ce26e7	bellard	reg = (modrm >> 3) & 7;
5637	14ce26e7	bellard	mod = (modrm >> 6) & 3;
5638	14ce26e7	bellard	rm = modrm & 7;
5639	14ce26e7	bellard	if (mod != 3) {
5640	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5641	14ce26e7	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5642	14ce26e7	bellard	} else {
5643	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5644	14ce26e7	bellard	}
5645	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5646	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5647	14ce26e7	bellard	gen_op_arpl();
5648	14ce26e7	bellard	s->cc_op = CC_OP_EFLAGS;
5649	14ce26e7	bellard	if (mod != 3) {
5650	14ce26e7	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5651	14ce26e7	bellard	} else {
5652	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5653	14ce26e7	bellard	}
5654	14ce26e7	bellard	gen_op_arpl_update();
5655	f115e911	bellard	}
5656	f115e911	bellard	break;
5657	2c0262af	bellard	case 0x102: /* lar */
5658	2c0262af	bellard	case 0x103: /* lsl */
5659	2c0262af	bellard	if (!s->pe \|\| s->vm86)
5660	2c0262af	bellard	goto illegal_op;
5661	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
5662	61382a50	bellard	modrm = ldub_code(s->pc++);
5663	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5664	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5665	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
5666	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5667	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5668	2c0262af	bellard	if (b == 0x102)
5669	2c0262af	bellard	gen_op_lar();
5670	2c0262af	bellard	else
5671	2c0262af	bellard	gen_op_lsl();
5672	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5673	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
5674	2c0262af	bellard	break;
5675	2c0262af	bellard	case 0x118:
5676	61382a50	bellard	modrm = ldub_code(s->pc++);
5677	2c0262af	bellard	mod = (modrm >> 6) & 3;
5678	2c0262af	bellard	op = (modrm >> 3) & 7;
5679	2c0262af	bellard	switch(op) {
5680	2c0262af	bellard	case 0: /* prefetchnta */
5681	2c0262af	bellard	case 1: /* prefetchnt0 */
5682	2c0262af	bellard	case 2: /* prefetchnt0 */
5683	2c0262af	bellard	case 3: /* prefetchnt0 */
5684	2c0262af	bellard	if (mod == 3)
5685	2c0262af	bellard	goto illegal_op;
5686	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5687	2c0262af	bellard	/* nothing more to do */
5688	2c0262af	bellard	break;
5689	2c0262af	bellard	default:
5690	2c0262af	bellard	goto illegal_op;
5691	2c0262af	bellard	}
5692	2c0262af	bellard	break;
5693	2c0262af	bellard	case 0x120: /* mov reg, crN */
5694	2c0262af	bellard	case 0x122: /* mov crN, reg */
5695	2c0262af	bellard	if (s->cpl != 0) {
5696	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5697	2c0262af	bellard	} else {
5698	61382a50	bellard	modrm = ldub_code(s->pc++);
5699	2c0262af	bellard	if ((modrm & 0xc0) != 0xc0)
5700	2c0262af	bellard	goto illegal_op;
5701	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5702	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5703	14ce26e7	bellard	if (CODE64(s))
5704	14ce26e7	bellard	ot = OT_QUAD;
5705	14ce26e7	bellard	else
5706	14ce26e7	bellard	ot = OT_LONG;
5707	2c0262af	bellard	switch(reg) {
5708	2c0262af	bellard	case 0:
5709	2c0262af	bellard	case 2:
5710	2c0262af	bellard	case 3:
5711	2c0262af	bellard	case 4:
5712	9230e66e	bellard	case 8:
5713	2c0262af	bellard	if (b & 2) {
5714	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5715	2c0262af	bellard	gen_op_movl_crN_T0(reg);
5716	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5717	2c0262af	bellard	gen_eob(s);
5718	2c0262af	bellard	} else {
5719	82e41634	bellard	#if !defined(CONFIG_USER_ONLY)
5720	9230e66e	bellard	if (reg == 8)
5721	9230e66e	bellard	gen_op_movtl_T0_cr8();
5722	9230e66e	bellard	else
5723	82e41634	bellard	#endif
5724	9230e66e	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
5725	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5726	2c0262af	bellard	}
5727	2c0262af	bellard	break;
5728	2c0262af	bellard	default:
5729	2c0262af	bellard	goto illegal_op;
5730	2c0262af	bellard	}
5731	2c0262af	bellard	}
5732	2c0262af	bellard	break;
5733	2c0262af	bellard	case 0x121: /* mov reg, drN */
5734	2c0262af	bellard	case 0x123: /* mov drN, reg */
5735	2c0262af	bellard	if (s->cpl != 0) {
5736	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5737	2c0262af	bellard	} else {
5738	61382a50	bellard	modrm = ldub_code(s->pc++);
5739	2c0262af	bellard	if ((modrm & 0xc0) != 0xc0)
5740	2c0262af	bellard	goto illegal_op;
5741	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5742	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5743	14ce26e7	bellard	if (CODE64(s))
5744	14ce26e7	bellard	ot = OT_QUAD;
5745	14ce26e7	bellard	else
5746	14ce26e7	bellard	ot = OT_LONG;
5747	2c0262af	bellard	/* XXX: do it dynamically with CR4.DE bit */
5748	14ce26e7	bellard	if (reg == 4 \|\| reg == 5 \|\| reg >= 8)
5749	2c0262af	bellard	goto illegal_op;
5750	2c0262af	bellard	if (b & 2) {
5751	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5752	2c0262af	bellard	gen_op_movl_drN_T0(reg);
5753	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5754	2c0262af	bellard	gen_eob(s);
5755	2c0262af	bellard	} else {
5756	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg]));
5757	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5758	2c0262af	bellard	}
5759	2c0262af	bellard	}
5760	2c0262af	bellard	break;
5761	2c0262af	bellard	case 0x106: /* clts */
5762	2c0262af	bellard	if (s->cpl != 0) {
5763	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5764	2c0262af	bellard	} else {
5765	2c0262af	bellard	gen_op_clts();
5766	7eee2a50	bellard	/* abort block because static cpu state changed */
5767	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5768	7eee2a50	bellard	gen_eob(s);
5769	2c0262af	bellard	}
5770	2c0262af	bellard	break;
5771	664e0f19	bellard	/* MMX/SSE/SSE2/PNI support */
5772	664e0f19	bellard	case 0x1c3: /* MOVNTI reg, mem */
5773	664e0f19	bellard	if (!(s->cpuid_features & CPUID_SSE2))
5774	14ce26e7	bellard	goto illegal_op;
5775	664e0f19	bellard	ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
5776	664e0f19	bellard	modrm = ldub_code(s->pc++);
5777	664e0f19	bellard	mod = (modrm >> 6) & 3;
5778	664e0f19	bellard	if (mod == 3)
5779	664e0f19	bellard	goto illegal_op;
5780	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5781	664e0f19	bellard	/* generate a generic store */
5782	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, reg, 1);
5783	14ce26e7	bellard	break;
5784	664e0f19	bellard	case 0x1ae:
5785	664e0f19	bellard	modrm = ldub_code(s->pc++);
5786	664e0f19	bellard	mod = (modrm >> 6) & 3;
5787	664e0f19	bellard	op = (modrm >> 3) & 7;
5788	664e0f19	bellard	switch(op) {
5789	664e0f19	bellard	case 0: /* fxsave */
5790	664e0f19	bellard	if (mod == 3 \|\| !(s->cpuid_features & CPUID_FXSR))
5791	14ce26e7	bellard	goto illegal_op;
5792	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5793	664e0f19	bellard	gen_op_fxsave_A0((s->dflag == 2));
5794	664e0f19	bellard	break;
5795	664e0f19	bellard	case 1: /* fxrstor */
5796	664e0f19	bellard	if (mod == 3 \|\| !(s->cpuid_features & CPUID_FXSR))
5797	14ce26e7	bellard	goto illegal_op;
5798	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5799	664e0f19	bellard	gen_op_fxrstor_A0((s->dflag == 2));
5800	664e0f19	bellard	break;
5801	664e0f19	bellard	case 2: /* ldmxcsr */
5802	664e0f19	bellard	case 3: /* stmxcsr */
5803	664e0f19	bellard	if (s->flags & HF_TS_MASK) {
5804	664e0f19	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5805	664e0f19	bellard	break;
5806	14ce26e7	bellard	}
5807	664e0f19	bellard	if ((s->flags & HF_EM_MASK) \|\| !(s->flags & HF_OSFXSR_MASK) \|\|
5808	664e0f19	bellard	mod == 3)
5809	14ce26e7	bellard	goto illegal_op;
5810	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5811	664e0f19	bellard	if (op == 2) {
5812	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5813	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr));
5814	14ce26e7	bellard	} else {
5815	664e0f19	bellard	gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr));
5816	664e0f19	bellard	gen_op_st_T0_A0[OT_LONG + s->mem_index]();
5817	14ce26e7	bellard	}
5818	664e0f19	bellard	break;
5819	664e0f19	bellard	case 5: /* lfence */
5820	664e0f19	bellard	case 6: /* mfence */
5821	664e0f19	bellard	if ((modrm & 0xc7) != 0xc0 \|\| !(s->cpuid_features & CPUID_SSE))
5822	664e0f19	bellard	goto illegal_op;
5823	664e0f19	bellard	break;
5824	8f091a59	bellard	case 7: /* sfence / clflush */
5825	8f091a59	bellard	if ((modrm & 0xc7) == 0xc0) {
5826	8f091a59	bellard	/* sfence */
5827	8f091a59	bellard	if (!(s->cpuid_features & CPUID_SSE))
5828	8f091a59	bellard	goto illegal_op;
5829	8f091a59	bellard	} else {
5830	8f091a59	bellard	/* clflush */
5831	8f091a59	bellard	if (!(s->cpuid_features & CPUID_CLFLUSH))
5832	8f091a59	bellard	goto illegal_op;
5833	8f091a59	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5834	8f091a59	bellard	}
5835	8f091a59	bellard	break;
5836	664e0f19	bellard	default:
5837	14ce26e7	bellard	goto illegal_op;
5838	14ce26e7	bellard	}
5839	14ce26e7	bellard	break;
5840	8f091a59	bellard	case 0x10d: /* prefetch */
5841	8f091a59	bellard	modrm = ldub_code(s->pc++);
5842	8f091a59	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5843	8f091a59	bellard	/* ignore for now */
5844	8f091a59	bellard	break;
5845	664e0f19	bellard	case 0x110 ... 0x117:
5846	664e0f19	bellard	case 0x128 ... 0x12f:
5847	664e0f19	bellard	case 0x150 ... 0x177:
5848	664e0f19	bellard	case 0x17c ... 0x17f:
5849	664e0f19	bellard	case 0x1c2:
5850	664e0f19	bellard	case 0x1c4 ... 0x1c6:
5851	664e0f19	bellard	case 0x1d0 ... 0x1fe:
5852	664e0f19	bellard	gen_sse(s, b, pc_start, rex_r);
5853	664e0f19	bellard	break;
5854	2c0262af	bellard	default:
5855	2c0262af	bellard	goto illegal_op;
5856	2c0262af	bellard	}
5857	2c0262af	bellard	/* lock generation */
5858	2c0262af	bellard	if (s->prefix & PREFIX_LOCK)
5859	2c0262af	bellard	gen_op_unlock();
5860	2c0262af	bellard	return s->pc;
5861	2c0262af	bellard	illegal_op:
5862	ab1f142b	bellard	if (s->prefix & PREFIX_LOCK)
5863	ab1f142b	bellard	gen_op_unlock();
5864	2c0262af	bellard	/* XXX: ensure that no lock was generated */
5865	2c0262af	bellard	gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
5866	2c0262af	bellard	return s->pc;
5867	2c0262af	bellard	}
5868	2c0262af	bellard
5869	2c0262af	bellard	#define CC_OSZAPC (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C)
5870	2c0262af	bellard	#define CC_OSZAP (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P)
5871	2c0262af	bellard
5872	2c0262af	bellard	/* flags read by an operation */
5873	2c0262af	bellard	static uint16_t opc_read_flags[NB_OPS] = {
5874	2c0262af	bellard	[INDEX_op_aas] = CC_A,
5875	2c0262af	bellard	[INDEX_op_aaa] = CC_A,
5876	2c0262af	bellard	[INDEX_op_das] = CC_A \| CC_C,
5877	2c0262af	bellard	[INDEX_op_daa] = CC_A \| CC_C,
5878	2c0262af	bellard
5879	2c0262af	bellard	/* subtle: due to the incl/decl implementation, C is used */
5880	2c0262af	bellard	[INDEX_op_update_inc_cc] = CC_C,
5881	2c0262af	bellard
5882	2c0262af	bellard	[INDEX_op_into] = CC_O,
5883	2c0262af	bellard
5884	2c0262af	bellard	[INDEX_op_jb_subb] = CC_C,
5885	2c0262af	bellard	[INDEX_op_jb_subw] = CC_C,
5886	2c0262af	bellard	[INDEX_op_jb_subl] = CC_C,
5887	2c0262af	bellard
5888	2c0262af	bellard	[INDEX_op_jz_subb] = CC_Z,
5889	2c0262af	bellard	[INDEX_op_jz_subw] = CC_Z,
5890	2c0262af	bellard	[INDEX_op_jz_subl] = CC_Z,
5891	2c0262af	bellard
5892	2c0262af	bellard	[INDEX_op_jbe_subb] = CC_Z \| CC_C,
5893	2c0262af	bellard	[INDEX_op_jbe_subw] = CC_Z \| CC_C,
5894	2c0262af	bellard	[INDEX_op_jbe_subl] = CC_Z \| CC_C,
5895	2c0262af	bellard
5896	2c0262af	bellard	[INDEX_op_js_subb] = CC_S,
5897	2c0262af	bellard	[INDEX_op_js_subw] = CC_S,
5898	2c0262af	bellard	[INDEX_op_js_subl] = CC_S,
5899	2c0262af	bellard
5900	2c0262af	bellard	[INDEX_op_jl_subb] = CC_O \| CC_S,
5901	2c0262af	bellard	[INDEX_op_jl_subw] = CC_O \| CC_S,
5902	2c0262af	bellard	[INDEX_op_jl_subl] = CC_O \| CC_S,
5903	2c0262af	bellard
5904	2c0262af	bellard	[INDEX_op_jle_subb] = CC_O \| CC_S \| CC_Z,
5905	2c0262af	bellard	[INDEX_op_jle_subw] = CC_O \| CC_S \| CC_Z,
5906	2c0262af	bellard	[INDEX_op_jle_subl] = CC_O \| CC_S \| CC_Z,
5907	2c0262af	bellard
5908	2c0262af	bellard	[INDEX_op_loopnzw] = CC_Z,
5909	2c0262af	bellard	[INDEX_op_loopnzl] = CC_Z,
5910	2c0262af	bellard	[INDEX_op_loopzw] = CC_Z,
5911	2c0262af	bellard	[INDEX_op_loopzl] = CC_Z,
5912	2c0262af	bellard
5913	2c0262af	bellard	[INDEX_op_seto_T0_cc] = CC_O,
5914	2c0262af	bellard	[INDEX_op_setb_T0_cc] = CC_C,
5915	2c0262af	bellard	[INDEX_op_setz_T0_cc] = CC_Z,
5916	2c0262af	bellard	[INDEX_op_setbe_T0_cc] = CC_Z \| CC_C,
5917	2c0262af	bellard	[INDEX_op_sets_T0_cc] = CC_S,
5918	2c0262af	bellard	[INDEX_op_setp_T0_cc] = CC_P,
5919	2c0262af	bellard	[INDEX_op_setl_T0_cc] = CC_O \| CC_S,
5920	2c0262af	bellard	[INDEX_op_setle_T0_cc] = CC_O \| CC_S \| CC_Z,
5921	2c0262af	bellard
5922	2c0262af	bellard	[INDEX_op_setb_T0_subb] = CC_C,
5923	2c0262af	bellard	[INDEX_op_setb_T0_subw] = CC_C,
5924	2c0262af	bellard	[INDEX_op_setb_T0_subl] = CC_C,
5925	2c0262af	bellard
5926	2c0262af	bellard	[INDEX_op_setz_T0_subb] = CC_Z,
5927	2c0262af	bellard	[INDEX_op_setz_T0_subw] = CC_Z,
5928	2c0262af	bellard	[INDEX_op_setz_T0_subl] = CC_Z,
5929	2c0262af	bellard
5930	2c0262af	bellard	[INDEX_op_setbe_T0_subb] = CC_Z \| CC_C,
5931	2c0262af	bellard	[INDEX_op_setbe_T0_subw] = CC_Z \| CC_C,
5932	2c0262af	bellard	[INDEX_op_setbe_T0_subl] = CC_Z \| CC_C,
5933	2c0262af	bellard
5934	2c0262af	bellard	[INDEX_op_sets_T0_subb] = CC_S,
5935	2c0262af	bellard	[INDEX_op_sets_T0_subw] = CC_S,
5936	2c0262af	bellard	[INDEX_op_sets_T0_subl] = CC_S,
5937	2c0262af	bellard
5938	2c0262af	bellard	[INDEX_op_setl_T0_subb] = CC_O \| CC_S,
5939	2c0262af	bellard	[INDEX_op_setl_T0_subw] = CC_O \| CC_S,
5940	2c0262af	bellard	[INDEX_op_setl_T0_subl] = CC_O \| CC_S,
5941	2c0262af	bellard
5942	2c0262af	bellard	[INDEX_op_setle_T0_subb] = CC_O \| CC_S \| CC_Z,
5943	2c0262af	bellard	[INDEX_op_setle_T0_subw] = CC_O \| CC_S \| CC_Z,
5944	2c0262af	bellard	[INDEX_op_setle_T0_subl] = CC_O \| CC_S \| CC_Z,
5945	2c0262af	bellard
5946	2c0262af	bellard	[INDEX_op_movl_T0_eflags] = CC_OSZAPC,
5947	2c0262af	bellard	[INDEX_op_cmc] = CC_C,
5948	2c0262af	bellard	[INDEX_op_salc] = CC_C,
5949	2c0262af	bellard
5950	7399c5a9	bellard	/* needed for correct flag optimisation before string ops */
5951	14ce26e7	bellard	[INDEX_op_jnz_ecxw] = CC_OSZAPC,
5952	14ce26e7	bellard	[INDEX_op_jnz_ecxl] = CC_OSZAPC,
5953	7399c5a9	bellard	[INDEX_op_jz_ecxw] = CC_OSZAPC,
5954	7399c5a9	bellard	[INDEX_op_jz_ecxl] = CC_OSZAPC,
5955	14ce26e7	bellard
5956	14ce26e7	bellard	#ifdef TARGET_X86_64
5957	14ce26e7	bellard	[INDEX_op_jb_subq] = CC_C,
5958	14ce26e7	bellard	[INDEX_op_jz_subq] = CC_Z,
5959	14ce26e7	bellard	[INDEX_op_jbe_subq] = CC_Z \| CC_C,
5960	14ce26e7	bellard	[INDEX_op_js_subq] = CC_S,
5961	14ce26e7	bellard	[INDEX_op_jl_subq] = CC_O \| CC_S,
5962	14ce26e7	bellard	[INDEX_op_jle_subq] = CC_O \| CC_S \| CC_Z,
5963	14ce26e7	bellard
5964	14ce26e7	bellard	[INDEX_op_loopnzq] = CC_Z,
5965	14ce26e7	bellard	[INDEX_op_loopzq] = CC_Z,
5966	14ce26e7	bellard
5967	14ce26e7	bellard	[INDEX_op_setb_T0_subq] = CC_C,
5968	14ce26e7	bellard	[INDEX_op_setz_T0_subq] = CC_Z,
5969	14ce26e7	bellard	[INDEX_op_setbe_T0_subq] = CC_Z \| CC_C,
5970	14ce26e7	bellard	[INDEX_op_sets_T0_subq] = CC_S,
5971	14ce26e7	bellard	[INDEX_op_setl_T0_subq] = CC_O \| CC_S,
5972	14ce26e7	bellard	[INDEX_op_setle_T0_subq] = CC_O \| CC_S \| CC_Z,
5973	14ce26e7	bellard
5974	14ce26e7	bellard	[INDEX_op_jnz_ecxq] = CC_OSZAPC,
5975	14ce26e7	bellard	[INDEX_op_jz_ecxq] = CC_OSZAPC,
5976	14ce26e7	bellard	#endif
5977	7399c5a9	bellard
5978	4f31916f	bellard	#define DEF_READF(SUFFIX)\
5979	4f31916f	bellard	[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5980	4f31916f	bellard	[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5981	4f31916f	bellard	[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5982	14ce26e7	bellard	X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5983	4f31916f	bellard	[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5984	4f31916f	bellard	[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5985	4f31916f	bellard	[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5986	14ce26e7	bellard	X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5987	4f31916f	bellard	\
5988	4f31916f	bellard	[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5989	4f31916f	bellard	[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5990	4f31916f	bellard	[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
5991	14ce26e7	bellard	X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5992	4f31916f	bellard	[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5993	4f31916f	bellard	[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5994	14ce26e7	bellard	[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5995	14ce26e7	bellard	X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_C,)
5996	4f31916f	bellard
5997	4bb2fcc7	bellard	DEF_READF( )
5998	4f31916f	bellard	DEF_READF(_raw)
5999	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6000	4f31916f	bellard	DEF_READF(_kernel)
6001	4f31916f	bellard	DEF_READF(_user)
6002	4f31916f	bellard	#endif
6003	2c0262af	bellard	};
6004	2c0262af	bellard
6005	2c0262af	bellard	/* flags written by an operation */
6006	2c0262af	bellard	static uint16_t opc_write_flags[NB_OPS] = {
6007	2c0262af	bellard	[INDEX_op_update2_cc] = CC_OSZAPC,
6008	2c0262af	bellard	[INDEX_op_update1_cc] = CC_OSZAPC,
6009	2c0262af	bellard	[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
6010	2c0262af	bellard	[INDEX_op_update_neg_cc] = CC_OSZAPC,
6011	2c0262af	bellard	/* subtle: due to the incl/decl implementation, C is used */
6012	2c0262af	bellard	[INDEX_op_update_inc_cc] = CC_OSZAPC,
6013	2c0262af	bellard	[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
6014	2c0262af	bellard
6015	2c0262af	bellard	[INDEX_op_mulb_AL_T0] = CC_OSZAPC,
6016	2c0262af	bellard	[INDEX_op_mulw_AX_T0] = CC_OSZAPC,
6017	2c0262af	bellard	[INDEX_op_mull_EAX_T0] = CC_OSZAPC,
6018	14ce26e7	bellard	X86_64_DEF([INDEX_op_mulq_EAX_T0] = CC_OSZAPC,)
6019	14ce26e7	bellard	[INDEX_op_imulb_AL_T0] = CC_OSZAPC,
6020	14ce26e7	bellard	[INDEX_op_imulw_AX_T0] = CC_OSZAPC,
6021	2c0262af	bellard	[INDEX_op_imull_EAX_T0] = CC_OSZAPC,
6022	14ce26e7	bellard	X86_64_DEF([INDEX_op_imulq_EAX_T0] = CC_OSZAPC,)
6023	2c0262af	bellard	[INDEX_op_imulw_T0_T1] = CC_OSZAPC,
6024	2c0262af	bellard	[INDEX_op_imull_T0_T1] = CC_OSZAPC,
6025	14ce26e7	bellard	X86_64_DEF([INDEX_op_imulq_T0_T1] = CC_OSZAPC,)
6026	14ce26e7	bellard
6027	664e0f19	bellard	/* sse */
6028	664e0f19	bellard	[INDEX_op_ucomiss] = CC_OSZAPC,
6029	664e0f19	bellard	[INDEX_op_ucomisd] = CC_OSZAPC,
6030	664e0f19	bellard	[INDEX_op_comiss] = CC_OSZAPC,
6031	664e0f19	bellard	[INDEX_op_comisd] = CC_OSZAPC,
6032	664e0f19	bellard
6033	2c0262af	bellard	/* bcd */
6034	2c0262af	bellard	[INDEX_op_aam] = CC_OSZAPC,
6035	2c0262af	bellard	[INDEX_op_aad] = CC_OSZAPC,
6036	2c0262af	bellard	[INDEX_op_aas] = CC_OSZAPC,
6037	2c0262af	bellard	[INDEX_op_aaa] = CC_OSZAPC,
6038	2c0262af	bellard	[INDEX_op_das] = CC_OSZAPC,
6039	2c0262af	bellard	[INDEX_op_daa] = CC_OSZAPC,
6040	2c0262af	bellard
6041	2c0262af	bellard	[INDEX_op_movb_eflags_T0] = CC_S \| CC_Z \| CC_A \| CC_P \| CC_C,
6042	2c0262af	bellard	[INDEX_op_movw_eflags_T0] = CC_OSZAPC,
6043	2c0262af	bellard	[INDEX_op_movl_eflags_T0] = CC_OSZAPC,
6044	4136f33c	bellard	[INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
6045	4136f33c	bellard	[INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
6046	4136f33c	bellard	[INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
6047	4136f33c	bellard	[INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
6048	2c0262af	bellard	[INDEX_op_clc] = CC_C,
6049	2c0262af	bellard	[INDEX_op_stc] = CC_C,
6050	2c0262af	bellard	[INDEX_op_cmc] = CC_C,
6051	2c0262af	bellard
6052	2c0262af	bellard	[INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
6053	2c0262af	bellard	[INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
6054	14ce26e7	bellard	X86_64_DEF([INDEX_op_btq_T0_T1_cc] = CC_OSZAPC,)
6055	2c0262af	bellard	[INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
6056	2c0262af	bellard	[INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
6057	14ce26e7	bellard	X86_64_DEF([INDEX_op_btsq_T0_T1_cc] = CC_OSZAPC,)
6058	2c0262af	bellard	[INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
6059	2c0262af	bellard	[INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
6060	14ce26e7	bellard	X86_64_DEF([INDEX_op_btrq_T0_T1_cc] = CC_OSZAPC,)
6061	2c0262af	bellard	[INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
6062	2c0262af	bellard	[INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
6063	14ce26e7	bellard	X86_64_DEF([INDEX_op_btcq_T0_T1_cc] = CC_OSZAPC,)
6064	2c0262af	bellard
6065	2c0262af	bellard	[INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
6066	2c0262af	bellard	[INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
6067	14ce26e7	bellard	X86_64_DEF([INDEX_op_bsfq_T0_cc] = CC_OSZAPC,)
6068	2c0262af	bellard	[INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
6069	2c0262af	bellard	[INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
6070	14ce26e7	bellard	X86_64_DEF([INDEX_op_bsrq_T0_cc] = CC_OSZAPC,)
6071	2c0262af	bellard
6072	2c0262af	bellard	[INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
6073	2c0262af	bellard	[INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
6074	2c0262af	bellard	[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
6075	14ce26e7	bellard	X86_64_DEF([INDEX_op_cmpxchgq_T0_T1_EAX_cc] = CC_OSZAPC,)
6076	2c0262af	bellard
6077	2c0262af	bellard	[INDEX_op_cmpxchg8b] = CC_Z,
6078	2c0262af	bellard	[INDEX_op_lar] = CC_Z,
6079	2c0262af	bellard	[INDEX_op_lsl] = CC_Z,
6080	cc6f538b	bellard	[INDEX_op_verr] = CC_Z,
6081	cc6f538b	bellard	[INDEX_op_verw] = CC_Z,
6082	2c0262af	bellard	[INDEX_op_fcomi_ST0_FT0] = CC_Z \| CC_P \| CC_C,
6083	2c0262af	bellard	[INDEX_op_fucomi_ST0_FT0] = CC_Z \| CC_P \| CC_C,
6084	4f31916f	bellard
6085	4f31916f	bellard	#define DEF_WRITEF(SUFFIX)\
6086	4f31916f	bellard	[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6087	4f31916f	bellard	[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6088	4f31916f	bellard	[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6089	14ce26e7	bellard	X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6090	4f31916f	bellard	[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6091	4f31916f	bellard	[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6092	4f31916f	bellard	[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6093	14ce26e7	bellard	X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6094	4f31916f	bellard	\
6095	4f31916f	bellard	[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6096	4f31916f	bellard	[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6097	4f31916f	bellard	[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6098	14ce26e7	bellard	X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6099	4f31916f	bellard	[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6100	4f31916f	bellard	[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6101	4f31916f	bellard	[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6102	14ce26e7	bellard	X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6103	4f31916f	bellard	\
6104	4f31916f	bellard	[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6105	4f31916f	bellard	[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6106	4f31916f	bellard	[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6107	14ce26e7	bellard	X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6108	4f31916f	bellard	[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6109	4f31916f	bellard	[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6110	4f31916f	bellard	[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6111	14ce26e7	bellard	X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6112	4f31916f	bellard	\
6113	4f31916f	bellard	[INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6114	4f31916f	bellard	[INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6115	4f31916f	bellard	[INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6116	14ce26e7	bellard	X86_64_DEF([INDEX_op_shlq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6117	4f31916f	bellard	\
6118	4f31916f	bellard	[INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6119	4f31916f	bellard	[INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6120	4f31916f	bellard	[INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6121	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6122	4f31916f	bellard	\
6123	4f31916f	bellard	[INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6124	4f31916f	bellard	[INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6125	4f31916f	bellard	[INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6126	14ce26e7	bellard	X86_64_DEF([INDEX_op_sarq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6127	4f31916f	bellard	\
6128	4f31916f	bellard	[INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6129	4f31916f	bellard	[INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6130	14ce26e7	bellard	X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6131	4f31916f	bellard	[INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6132	4f31916f	bellard	[INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6133	14ce26e7	bellard	X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6134	4f31916f	bellard	\
6135	4f31916f	bellard	[INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6136	4f31916f	bellard	[INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6137	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6138	4f31916f	bellard	[INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6139	4f31916f	bellard	[INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6140	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6141	4f31916f	bellard	\
6142	4f31916f	bellard	[INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6143	4f31916f	bellard	[INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6144	14ce26e7	bellard	[INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6145	14ce26e7	bellard	X86_64_DEF([INDEX_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,)
6146	4f31916f	bellard
6147	4f31916f	bellard
6148	4bb2fcc7	bellard	DEF_WRITEF( )
6149	4f31916f	bellard	DEF_WRITEF(_raw)
6150	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6151	4f31916f	bellard	DEF_WRITEF(_kernel)
6152	4f31916f	bellard	DEF_WRITEF(_user)
6153	4f31916f	bellard	#endif
6154	2c0262af	bellard	};
6155	2c0262af	bellard
6156	2c0262af	bellard	/* simpler form of an operation if no flags need to be generated */
6157	2c0262af	bellard	static uint16_t opc_simpler[NB_OPS] = {
6158	2c0262af	bellard	[INDEX_op_update2_cc] = INDEX_op_nop,
6159	2c0262af	bellard	[INDEX_op_update1_cc] = INDEX_op_nop,
6160	2c0262af	bellard	[INDEX_op_update_neg_cc] = INDEX_op_nop,
6161	2c0262af	bellard	#if 0
6162	2c0262af	bellard	/* broken: CC_OP logic must be rewritten */
6163	2c0262af	bellard	[INDEX_op_update_inc_cc] = INDEX_op_nop,
6164	2c0262af	bellard	#endif
6165	2c0262af	bellard
6166	2c0262af	bellard	[INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
6167	2c0262af	bellard	[INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
6168	2c0262af	bellard	[INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
6169	14ce26e7	bellard	X86_64_DEF([INDEX_op_shlq_T0_T1_cc] = INDEX_op_shlq_T0_T1,)
6170	2c0262af	bellard
6171	2c0262af	bellard	[INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
6172	2c0262af	bellard	[INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
6173	2c0262af	bellard	[INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
6174	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrq_T0_T1_cc] = INDEX_op_shrq_T0_T1,)
6175	2c0262af	bellard
6176	2c0262af	bellard	[INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
6177	2c0262af	bellard	[INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
6178	2c0262af	bellard	[INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
6179	14ce26e7	bellard	X86_64_DEF([INDEX_op_sarq_T0_T1_cc] = INDEX_op_sarq_T0_T1,)
6180	4f31916f	bellard
6181	4f31916f	bellard	#define DEF_SIMPLER(SUFFIX)\
6182	4f31916f	bellard	[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
6183	4f31916f	bellard	[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
6184	4f31916f	bellard	[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
6185	14ce26e7	bellard	X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolq ## SUFFIX ## _T0_T1,)\
6186	4f31916f	bellard	\
6187	4f31916f	bellard	[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
6188	4f31916f	bellard	[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
6189	14ce26e7	bellard	[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,\
6190	14ce26e7	bellard	X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorq ## SUFFIX ## _T0_T1,)
6191	4f31916f	bellard
6192	4bb2fcc7	bellard	DEF_SIMPLER( )
6193	4f31916f	bellard	DEF_SIMPLER(_raw)
6194	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6195	4f31916f	bellard	DEF_SIMPLER(_kernel)
6196	4f31916f	bellard	DEF_SIMPLER(_user)
6197	4f31916f	bellard	#endif
6198	2c0262af	bellard	};
6199	2c0262af	bellard
6200	2c0262af	bellard	void optimize_flags_init(void)
6201	2c0262af	bellard	{
6202	2c0262af	bellard	int i;
6203	2c0262af	bellard	/* put default values in arrays */
6204	2c0262af	bellard	for(i = 0; i < NB_OPS; i++) {
6205	2c0262af	bellard	if (opc_simpler[i] == 0)
6206	2c0262af	bellard	opc_simpler[i] = i;
6207	2c0262af	bellard	}
6208	2c0262af	bellard	}
6209	2c0262af	bellard
6210	2c0262af	bellard	/* CPU flags computation optimization: we move backward thru the
6211	2c0262af	bellard	generated code to see which flags are needed. The operation is
6212	2c0262af	bellard	modified if suitable */
6213	2c0262af	bellard	static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
6214	2c0262af	bellard	{
6215	2c0262af	bellard	uint16_t *opc_ptr;
6216	2c0262af	bellard	int live_flags, write_flags, op;
6217	2c0262af	bellard
6218	2c0262af	bellard	opc_ptr = opc_buf + opc_buf_len;
6219	2c0262af	bellard	/* live_flags contains the flags needed by the next instructions
6220	2c0262af	bellard	in the code. At the end of the bloc, we consider that all the
6221	2c0262af	bellard	flags are live. */
6222	2c0262af	bellard	live_flags = CC_OSZAPC;
6223	2c0262af	bellard	while (opc_ptr > opc_buf) {
6224	2c0262af	bellard	op = *--opc_ptr;
6225	2c0262af	bellard	/* if none of the flags written by the instruction is used,
6226	2c0262af	bellard	then we can try to find a simpler instruction */
6227	2c0262af	bellard	write_flags = opc_write_flags[op];
6228	2c0262af	bellard	if ((live_flags & write_flags) == 0) {
6229	2c0262af	bellard	*opc_ptr = opc_simpler[op];
6230	2c0262af	bellard	}
6231	2c0262af	bellard	/* compute the live flags before the instruction */
6232	2c0262af	bellard	live_flags &= ~write_flags;
6233	2c0262af	bellard	live_flags \|= opc_read_flags[op];
6234	2c0262af	bellard	}
6235	2c0262af	bellard	}
6236	2c0262af	bellard
6237	2c0262af	bellard	/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
6238	2c0262af	bellard	basic block 'tb'. If search_pc is TRUE, also generate PC
6239	2c0262af	bellard	information for each intermediate instruction. */
6240	2c0262af	bellard	static inline int gen_intermediate_code_internal(CPUState *env,
6241	2c0262af	bellard	TranslationBlock *tb,
6242	2c0262af	bellard	int search_pc)
6243	2c0262af	bellard	{
6244	2c0262af	bellard	DisasContext dc1, *dc = &dc1;
6245	14ce26e7	bellard	target_ulong pc_ptr;
6246	2c0262af	bellard	uint16_t *gen_opc_end;
6247	d720b93d	bellard	int flags, j, lj, cflags;
6248	14ce26e7	bellard	target_ulong pc_start;
6249	14ce26e7	bellard	target_ulong cs_base;
6250	2c0262af	bellard
6251	2c0262af	bellard	/* generate intermediate code */
6252	14ce26e7	bellard	pc_start = tb->pc;
6253	14ce26e7	bellard	cs_base = tb->cs_base;
6254	2c0262af	bellard	flags = tb->flags;
6255	d720b93d	bellard	cflags = tb->cflags;
6256	3a1d9b8b	bellard
6257	4f31916f	bellard	dc->pe = (flags >> HF_PE_SHIFT) & 1;
6258	2c0262af	bellard	dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
6259	2c0262af	bellard	dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
6260	2c0262af	bellard	dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
6261	2c0262af	bellard	dc->f_st = 0;
6262	2c0262af	bellard	dc->vm86 = (flags >> VM_SHIFT) & 1;
6263	2c0262af	bellard	dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
6264	2c0262af	bellard	dc->iopl = (flags >> IOPL_SHIFT) & 3;
6265	2c0262af	bellard	dc->tf = (flags >> TF_SHIFT) & 1;
6266	34865134	bellard	dc->singlestep_enabled = env->singlestep_enabled;
6267	2c0262af	bellard	dc->cc_op = CC_OP_DYNAMIC;
6268	2c0262af	bellard	dc->cs_base = cs_base;
6269	2c0262af	bellard	dc->tb = tb;
6270	2c0262af	bellard	dc->popl_esp_hack = 0;
6271	2c0262af	bellard	/* select memory access functions */
6272	2c0262af	bellard	dc->mem_index = 0;
6273	2c0262af	bellard	if (flags & HF_SOFTMMU_MASK) {
6274	2c0262af	bellard	if (dc->cpl == 3)
6275	14ce26e7	bellard	dc->mem_index = 2 * 4;
6276	2c0262af	bellard	else
6277	14ce26e7	bellard	dc->mem_index = 1 * 4;
6278	2c0262af	bellard	}
6279	14ce26e7	bellard	dc->cpuid_features = env->cpuid_features;
6280	14ce26e7	bellard	#ifdef TARGET_X86_64
6281	14ce26e7	bellard	dc->lma = (flags >> HF_LMA_SHIFT) & 1;
6282	14ce26e7	bellard	dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
6283	14ce26e7	bellard	#endif
6284	7eee2a50	bellard	dc->flags = flags;
6285	a2cc3b24	bellard	dc->jmp_opt = !(dc->tf \|\| env->singlestep_enabled \|\|
6286	a2cc3b24	bellard	(flags & HF_INHIBIT_IRQ_MASK)
6287	415fa2ea	bellard	#ifndef CONFIG_SOFTMMU
6288	2c0262af	bellard	\|\| (flags & HF_SOFTMMU_MASK)
6289	2c0262af	bellard	#endif
6290	2c0262af	bellard	);
6291	4f31916f	bellard	#if 0
6292	4f31916f	bellard	/* check addseg logic */
6293	dc196a57	bellard	if (!dc->addseg && (dc->vm86 \|\| !dc->pe \|\| !dc->code32))
6294	4f31916f	bellard	printf("ERROR addseg\n");
6295	4f31916f	bellard	#endif
6296	4f31916f	bellard
6297	2c0262af	bellard	gen_opc_ptr = gen_opc_buf;
6298	2c0262af	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6299	2c0262af	bellard	gen_opparam_ptr = gen_opparam_buf;
6300	14ce26e7	bellard	nb_gen_labels = 0;
6301	2c0262af	bellard
6302	2c0262af	bellard	dc->is_jmp = DISAS_NEXT;
6303	2c0262af	bellard	pc_ptr = pc_start;
6304	2c0262af	bellard	lj = -1;
6305	2c0262af	bellard
6306	2c0262af	bellard	for(;;) {
6307	2c0262af	bellard	if (env->nb_breakpoints > 0) {
6308	2c0262af	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
6309	14ce26e7	bellard	if (env->breakpoints[j] == pc_ptr) {
6310	2c0262af	bellard	gen_debug(dc, pc_ptr - dc->cs_base);
6311	2c0262af	bellard	break;
6312	2c0262af	bellard	}
6313	2c0262af	bellard	}
6314	2c0262af	bellard	}
6315	2c0262af	bellard	if (search_pc) {
6316	2c0262af	bellard	j = gen_opc_ptr - gen_opc_buf;
6317	2c0262af	bellard	if (lj < j) {
6318	2c0262af	bellard	lj++;
6319	2c0262af	bellard	while (lj < j)
6320	2c0262af	bellard	gen_opc_instr_start[lj++] = 0;
6321	2c0262af	bellard	}
6322	14ce26e7	bellard	gen_opc_pc[lj] = pc_ptr;
6323	2c0262af	bellard	gen_opc_cc_op[lj] = dc->cc_op;
6324	2c0262af	bellard	gen_opc_instr_start[lj] = 1;
6325	2c0262af	bellard	}
6326	2c0262af	bellard	pc_ptr = disas_insn(dc, pc_ptr);
6327	2c0262af	bellard	/* stop translation if indicated */
6328	2c0262af	bellard	if (dc->is_jmp)
6329	2c0262af	bellard	break;
6330	2c0262af	bellard	/* if single step mode, we generate only one instruction and
6331	2c0262af	bellard	generate an exception */
6332	a2cc3b24	bellard	/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
6333	a2cc3b24	bellard	the flag and abort the translation to give the irqs a
6334	a2cc3b24	bellard	change to be happen */
6335	a2cc3b24	bellard	if (dc->tf \|\| dc->singlestep_enabled \|\|
6336	d720b93d	bellard	(flags & HF_INHIBIT_IRQ_MASK) \|\|
6337	d720b93d	bellard	(cflags & CF_SINGLE_INSN)) {
6338	14ce26e7	bellard	gen_jmp_im(pc_ptr - dc->cs_base);
6339	2c0262af	bellard	gen_eob(dc);
6340	2c0262af	bellard	break;
6341	2c0262af	bellard	}
6342	2c0262af	bellard	/* if too long translation, stop generation too */
6343	2c0262af	bellard	if (gen_opc_ptr >= gen_opc_end \|\|
6344	2c0262af	bellard	(pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
6345	14ce26e7	bellard	gen_jmp_im(pc_ptr - dc->cs_base);
6346	2c0262af	bellard	gen_eob(dc);
6347	2c0262af	bellard	break;
6348	2c0262af	bellard	}
6349	2c0262af	bellard	}
6350	2c0262af	bellard	*gen_opc_ptr = INDEX_op_end;
6351	2c0262af	bellard	/* we don't forget to fill the last values */
6352	2c0262af	bellard	if (search_pc) {
6353	2c0262af	bellard	j = gen_opc_ptr - gen_opc_buf;
6354	2c0262af	bellard	lj++;
6355	2c0262af	bellard	while (lj <= j)
6356	2c0262af	bellard	gen_opc_instr_start[lj++] = 0;
6357	2c0262af	bellard	}
6358	2c0262af	bellard
6359	2c0262af	bellard	#ifdef DEBUG_DISAS
6360	658c8bda	bellard	if (loglevel & CPU_LOG_TB_CPU) {
6361	7fe48483	bellard	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
6362	658c8bda	bellard	}
6363	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
6364	14ce26e7	bellard	int disas_flags;
6365	2c0262af	bellard	fprintf(logfile, "----------------\n");
6366	2c0262af	bellard	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6367	14ce26e7	bellard	#ifdef TARGET_X86_64
6368	14ce26e7	bellard	if (dc->code64)
6369	14ce26e7	bellard	disas_flags = 2;
6370	14ce26e7	bellard	else
6371	14ce26e7	bellard	#endif
6372	14ce26e7	bellard	disas_flags = !dc->code32;
6373	14ce26e7	bellard	target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
6374	2c0262af	bellard	fprintf(logfile, "\n");
6375	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP) {
6376	e19e89a5	bellard	fprintf(logfile, "OP:\n");
6377	e19e89a5	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
6378	e19e89a5	bellard	fprintf(logfile, "\n");
6379	e19e89a5	bellard	}
6380	2c0262af	bellard	}
6381	2c0262af	bellard	#endif
6382	2c0262af	bellard
6383	2c0262af	bellard	/* optimize flag computations */
6384	2c0262af	bellard	optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
6385	2c0262af	bellard
6386	2c0262af	bellard	#ifdef DEBUG_DISAS
6387	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP_OPT) {
6388	2c0262af	bellard	fprintf(logfile, "AFTER FLAGS OPT:\n");
6389	2c0262af	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
6390	2c0262af	bellard	fprintf(logfile, "\n");
6391	2c0262af	bellard	}
6392	2c0262af	bellard	#endif
6393	2c0262af	bellard	if (!search_pc)
6394	2c0262af	bellard	tb->size = pc_ptr - pc_start;
6395	2c0262af	bellard	return 0;
6396	2c0262af	bellard	}
6397	2c0262af	bellard
6398	2c0262af	bellard	int gen_intermediate_code(CPUState env, TranslationBlock tb)
6399	2c0262af	bellard	{
6400	2c0262af	bellard	return gen_intermediate_code_internal(env, tb, 0);
6401	2c0262af	bellard	}
6402	2c0262af	bellard
6403	2c0262af	bellard	int gen_intermediate_code_pc(CPUState env, TranslationBlock tb)
6404	2c0262af	bellard	{
6405	2c0262af	bellard	return gen_intermediate_code_internal(env, tb, 1);
6406	2c0262af	bellard	}

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