root / hw / arm / pxa2xx_pic.c @ 2c9b15ca
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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA Programmable Interrupt Controller.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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7 | c1713132 | balrog | *
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8 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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9 | c1713132 | balrog | */
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10 | c1713132 | balrog | |
11 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
12 | 0d09e41a | Paolo Bonzini | #include "hw/arm/pxa.h" |
13 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
14 | c1713132 | balrog | |
15 | c1713132 | balrog | #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ |
16 | c1713132 | balrog | #define ICMR 0x04 /* Interrupt Controller Mask register */ |
17 | c1713132 | balrog | #define ICLR 0x08 /* Interrupt Controller Level register */ |
18 | c1713132 | balrog | #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */ |
19 | c1713132 | balrog | #define ICPR 0x10 /* Interrupt Controller Pending register */ |
20 | c1713132 | balrog | #define ICCR 0x14 /* Interrupt Controller Control register */ |
21 | c1713132 | balrog | #define ICHP 0x18 /* Interrupt Controller Highest Priority register */ |
22 | c1713132 | balrog | #define IPR0 0x1c /* Interrupt Controller Priority register 0 */ |
23 | c1713132 | balrog | #define IPR31 0x98 /* Interrupt Controller Priority register 31 */ |
24 | c1713132 | balrog | #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */ |
25 | c1713132 | balrog | #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */ |
26 | c1713132 | balrog | #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */ |
27 | c1713132 | balrog | #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */ |
28 | c1713132 | balrog | #define ICPR2 0xac /* Interrupt Controller Pending register 2 */ |
29 | c1713132 | balrog | #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ |
30 | c1713132 | balrog | #define IPR39 0xcc /* Interrupt Controller Priority register 39 */ |
31 | c1713132 | balrog | |
32 | c1713132 | balrog | #define PXA2XX_PIC_SRCS 40 |
33 | c1713132 | balrog | |
34 | bc24a225 | Paul Brook | typedef struct { |
35 | e1f8c729 | Dmitry Eremin-Solenikov | SysBusDevice busdev; |
36 | 90e8e5a3 | Benoît Canet | MemoryRegion iomem; |
37 | e9d872cf | Andreas Färber | ARMCPU *cpu; |
38 | c1713132 | balrog | uint32_t int_enabled[2];
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39 | c1713132 | balrog | uint32_t int_pending[2];
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40 | c1713132 | balrog | uint32_t is_fiq[2];
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41 | c1713132 | balrog | uint32_t int_idle; |
42 | c1713132 | balrog | uint32_t priority[PXA2XX_PIC_SRCS]; |
43 | bc24a225 | Paul Brook | } PXA2xxPICState; |
44 | c1713132 | balrog | |
45 | c1713132 | balrog | static void pxa2xx_pic_update(void *opaque) |
46 | c1713132 | balrog | { |
47 | c1713132 | balrog | uint32_t mask[2];
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48 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
49 | 259186a7 | Andreas Färber | CPUState *cpu = CPU(s->cpu); |
50 | c1713132 | balrog | |
51 | 259186a7 | Andreas Färber | if (cpu->halted) {
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52 | c1713132 | balrog | mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle); |
53 | c1713132 | balrog | mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle); |
54 | e9d872cf | Andreas Färber | if (mask[0] || mask[1]) { |
55 | c3affe56 | Andreas Färber | cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); |
56 | e9d872cf | Andreas Färber | } |
57 | c1713132 | balrog | } |
58 | c1713132 | balrog | |
59 | c1713132 | balrog | mask[0] = s->int_pending[0] & s->int_enabled[0]; |
60 | c1713132 | balrog | mask[1] = s->int_pending[1] & s->int_enabled[1]; |
61 | c1713132 | balrog | |
62 | e9d872cf | Andreas Färber | if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) { |
63 | c3affe56 | Andreas Färber | cpu_interrupt(cpu, CPU_INTERRUPT_FIQ); |
64 | e9d872cf | Andreas Färber | } else {
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65 | d8ed887b | Andreas Färber | cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ); |
66 | e9d872cf | Andreas Färber | } |
67 | c1713132 | balrog | |
68 | e9d872cf | Andreas Färber | if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) { |
69 | c3affe56 | Andreas Färber | cpu_interrupt(cpu, CPU_INTERRUPT_HARD); |
70 | e9d872cf | Andreas Färber | } else {
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71 | d8ed887b | Andreas Färber | cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); |
72 | e9d872cf | Andreas Färber | } |
73 | c1713132 | balrog | } |
74 | c1713132 | balrog | |
75 | c1713132 | balrog | /* Note: Here level means state of the signal on a pin, not
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76 | c1713132 | balrog | * IRQ/FIQ distinction as in PXA Developer Manual. */
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77 | c1713132 | balrog | static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) |
78 | c1713132 | balrog | { |
79 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
80 | c1713132 | balrog | int int_set = (irq >= 32); |
81 | c1713132 | balrog | irq &= 31;
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82 | c1713132 | balrog | |
83 | c1713132 | balrog | if (level)
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84 | c1713132 | balrog | s->int_pending[int_set] |= 1 << irq;
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85 | c1713132 | balrog | else
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86 | c1713132 | balrog | s->int_pending[int_set] &= ~(1 << irq);
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87 | c1713132 | balrog | |
88 | c1713132 | balrog | pxa2xx_pic_update(opaque); |
89 | c1713132 | balrog | } |
90 | c1713132 | balrog | |
91 | bc24a225 | Paul Brook | static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { |
92 | c1713132 | balrog | int i, int_set, irq;
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93 | c1713132 | balrog | uint32_t bit, mask[2];
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94 | c1713132 | balrog | uint32_t ichp = 0x003f003f; /* Both IDs invalid */ |
95 | c1713132 | balrog | |
96 | c1713132 | balrog | mask[0] = s->int_pending[0] & s->int_enabled[0]; |
97 | c1713132 | balrog | mask[1] = s->int_pending[1] & s->int_enabled[1]; |
98 | c1713132 | balrog | |
99 | c1713132 | balrog | for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) { |
100 | c1713132 | balrog | irq = s->priority[i] & 0x3f;
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101 | c1713132 | balrog | if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) { |
102 | c1713132 | balrog | /* Source peripheral ID is valid. */
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103 | c1713132 | balrog | bit = 1 << (irq & 31); |
104 | c1713132 | balrog | int_set = (irq >= 32);
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105 | c1713132 | balrog | |
106 | c1713132 | balrog | if (mask[int_set] & bit & s->is_fiq[int_set]) {
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107 | c1713132 | balrog | /* FIQ asserted */
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108 | c1713132 | balrog | ichp &= 0xffff0000;
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109 | c1713132 | balrog | ichp |= (1 << 15) | irq; |
110 | c1713132 | balrog | } |
111 | c1713132 | balrog | |
112 | c1713132 | balrog | if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
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113 | c1713132 | balrog | /* IRQ asserted */
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114 | c1713132 | balrog | ichp &= 0x0000ffff;
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115 | c1713132 | balrog | ichp |= (1 << 31) | (irq << 16); |
116 | c1713132 | balrog | } |
117 | c1713132 | balrog | } |
118 | c1713132 | balrog | } |
119 | c1713132 | balrog | |
120 | c1713132 | balrog | return ichp;
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121 | c1713132 | balrog | } |
122 | c1713132 | balrog | |
123 | a8170e5e | Avi Kivity | static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset, |
124 | 90e8e5a3 | Benoît Canet | unsigned size)
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125 | c1713132 | balrog | { |
126 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
127 | c1713132 | balrog | |
128 | c1713132 | balrog | switch (offset) {
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129 | c1713132 | balrog | case ICIP: /* IRQ Pending register */ |
130 | c1713132 | balrog | return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0]; |
131 | c1713132 | balrog | case ICIP2: /* IRQ Pending register 2 */ |
132 | c1713132 | balrog | return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1]; |
133 | c1713132 | balrog | case ICMR: /* Mask register */ |
134 | c1713132 | balrog | return s->int_enabled[0]; |
135 | c1713132 | balrog | case ICMR2: /* Mask register 2 */ |
136 | c1713132 | balrog | return s->int_enabled[1]; |
137 | c1713132 | balrog | case ICLR: /* Level register */ |
138 | c1713132 | balrog | return s->is_fiq[0]; |
139 | c1713132 | balrog | case ICLR2: /* Level register 2 */ |
140 | c1713132 | balrog | return s->is_fiq[1]; |
141 | c1713132 | balrog | case ICCR: /* Idle mask */ |
142 | c1713132 | balrog | return (s->int_idle == 0); |
143 | c1713132 | balrog | case ICFP: /* FIQ Pending register */ |
144 | c1713132 | balrog | return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0]; |
145 | c1713132 | balrog | case ICFP2: /* FIQ Pending register 2 */ |
146 | c1713132 | balrog | return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1]; |
147 | c1713132 | balrog | case ICPR: /* Pending register */ |
148 | c1713132 | balrog | return s->int_pending[0]; |
149 | c1713132 | balrog | case ICPR2: /* Pending register 2 */ |
150 | c1713132 | balrog | return s->int_pending[1]; |
151 | c1713132 | balrog | case IPR0 ... IPR31:
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152 | c1713132 | balrog | return s->priority[0 + ((offset - IPR0 ) >> 2)]; |
153 | c1713132 | balrog | case IPR32 ... IPR39:
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154 | c1713132 | balrog | return s->priority[32 + ((offset - IPR32) >> 2)]; |
155 | c1713132 | balrog | case ICHP: /* Highest Priority register */ |
156 | c1713132 | balrog | return pxa2xx_pic_highest(s);
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157 | c1713132 | balrog | default:
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158 | c1713132 | balrog | printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); |
159 | c1713132 | balrog | return 0; |
160 | c1713132 | balrog | } |
161 | c1713132 | balrog | } |
162 | c1713132 | balrog | |
163 | a8170e5e | Avi Kivity | static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset, |
164 | 90e8e5a3 | Benoît Canet | uint64_t value, unsigned size)
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165 | c1713132 | balrog | { |
166 | bc24a225 | Paul Brook | PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
167 | c1713132 | balrog | |
168 | c1713132 | balrog | switch (offset) {
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169 | c1713132 | balrog | case ICMR: /* Mask register */ |
170 | c1713132 | balrog | s->int_enabled[0] = value;
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171 | c1713132 | balrog | break;
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172 | c1713132 | balrog | case ICMR2: /* Mask register 2 */ |
173 | c1713132 | balrog | s->int_enabled[1] = value;
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174 | c1713132 | balrog | break;
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175 | c1713132 | balrog | case ICLR: /* Level register */ |
176 | c1713132 | balrog | s->is_fiq[0] = value;
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177 | c1713132 | balrog | break;
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178 | c1713132 | balrog | case ICLR2: /* Level register 2 */ |
179 | c1713132 | balrog | s->is_fiq[1] = value;
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180 | c1713132 | balrog | break;
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181 | c1713132 | balrog | case ICCR: /* Idle mask */ |
182 | c1713132 | balrog | s->int_idle = (value & 1) ? 0 : ~0; |
183 | c1713132 | balrog | break;
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184 | c1713132 | balrog | case IPR0 ... IPR31:
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185 | c1713132 | balrog | s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f; |
186 | c1713132 | balrog | break;
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187 | c1713132 | balrog | case IPR32 ... IPR39:
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188 | c1713132 | balrog | s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; |
189 | c1713132 | balrog | break;
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190 | c1713132 | balrog | default:
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191 | c1713132 | balrog | printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); |
192 | c1713132 | balrog | return;
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193 | c1713132 | balrog | } |
194 | c1713132 | balrog | pxa2xx_pic_update(opaque); |
195 | c1713132 | balrog | } |
196 | c1713132 | balrog | |
197 | c1713132 | balrog | /* Interrupt Controller Coprocessor Space Register Mapping */
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198 | c1713132 | balrog | static const int pxa2xx_cp_reg_map[0x10] = { |
199 | c1713132 | balrog | [0x0 ... 0xf] = -1, |
200 | c1713132 | balrog | [0x0] = ICIP,
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201 | c1713132 | balrog | [0x1] = ICMR,
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202 | c1713132 | balrog | [0x2] = ICLR,
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203 | c1713132 | balrog | [0x3] = ICFP,
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204 | c1713132 | balrog | [0x4] = ICPR,
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205 | c1713132 | balrog | [0x5] = ICHP,
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206 | c1713132 | balrog | [0x6] = ICIP2,
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207 | c1713132 | balrog | [0x7] = ICMR2,
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208 | c1713132 | balrog | [0x8] = ICLR2,
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209 | c1713132 | balrog | [0x9] = ICFP2,
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210 | c1713132 | balrog | [0xa] = ICPR2,
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211 | c1713132 | balrog | }; |
212 | c1713132 | balrog | |
213 | 9ee703b0 | Peter Maydell | static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri, |
214 | 9ee703b0 | Peter Maydell | uint64_t *value) |
215 | c1713132 | balrog | { |
216 | 9ee703b0 | Peter Maydell | int offset = pxa2xx_cp_reg_map[ri->crn];
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217 | 9ee703b0 | Peter Maydell | *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
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218 | 9ee703b0 | Peter Maydell | return 0; |
219 | c1713132 | balrog | } |
220 | c1713132 | balrog | |
221 | 9ee703b0 | Peter Maydell | static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, |
222 | 9ee703b0 | Peter Maydell | uint64_t value) |
223 | c1713132 | balrog | { |
224 | 9ee703b0 | Peter Maydell | int offset = pxa2xx_cp_reg_map[ri->crn];
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225 | 9ee703b0 | Peter Maydell | pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
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226 | 9ee703b0 | Peter Maydell | return 0; |
227 | c1713132 | balrog | } |
228 | c1713132 | balrog | |
229 | 9ee703b0 | Peter Maydell | #define REGINFO_FOR_PIC_CP(NAME, CRN) \
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230 | 9ee703b0 | Peter Maydell | { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \ |
231 | 9ee703b0 | Peter Maydell | .access = PL1_RW, \ |
232 | 9ee703b0 | Peter Maydell | .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write } |
233 | 9ee703b0 | Peter Maydell | |
234 | 9ee703b0 | Peter Maydell | static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { |
235 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICIP", 0), |
236 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICMR", 1), |
237 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICLR", 2), |
238 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICFP", 3), |
239 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICPR", 4), |
240 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICHP", 5), |
241 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICIP2", 6), |
242 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICMR2", 7), |
243 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICLR2", 8), |
244 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICFP2", 9), |
245 | 9ee703b0 | Peter Maydell | REGINFO_FOR_PIC_CP("ICPR2", 0xa), |
246 | 9ee703b0 | Peter Maydell | REGINFO_SENTINEL |
247 | 9ee703b0 | Peter Maydell | }; |
248 | 9ee703b0 | Peter Maydell | |
249 | 90e8e5a3 | Benoît Canet | static const MemoryRegionOps pxa2xx_pic_ops = { |
250 | 90e8e5a3 | Benoît Canet | .read = pxa2xx_pic_mem_read, |
251 | 90e8e5a3 | Benoît Canet | .write = pxa2xx_pic_mem_write, |
252 | 90e8e5a3 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
253 | c1713132 | balrog | }; |
254 | c1713132 | balrog | |
255 | e1f8c729 | Dmitry Eremin-Solenikov | static int pxa2xx_pic_post_load(void *opaque, int version_id) |
256 | aa941b94 | balrog | { |
257 | aa941b94 | balrog | pxa2xx_pic_update(opaque); |
258 | aa941b94 | balrog | return 0; |
259 | aa941b94 | balrog | } |
260 | aa941b94 | balrog | |
261 | a8170e5e | Avi Kivity | DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) |
262 | c1713132 | balrog | { |
263 | f161bcd0 | Andreas Färber | CPUARMState *env = &cpu->env; |
264 | e1f8c729 | Dmitry Eremin-Solenikov | DeviceState *dev = qdev_create(NULL, "pxa2xx_pic"); |
265 | 1356b98d | Andreas Färber | PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, SYS_BUS_DEVICE(dev)); |
266 | c1713132 | balrog | |
267 | e9d872cf | Andreas Färber | s->cpu = cpu; |
268 | c1713132 | balrog | |
269 | c1713132 | balrog | s->int_pending[0] = 0; |
270 | c1713132 | balrog | s->int_pending[1] = 0; |
271 | c1713132 | balrog | s->int_enabled[0] = 0; |
272 | c1713132 | balrog | s->int_enabled[1] = 0; |
273 | c1713132 | balrog | s->is_fiq[0] = 0; |
274 | c1713132 | balrog | s->is_fiq[1] = 0; |
275 | c1713132 | balrog | |
276 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_init_nofail(dev); |
277 | e1f8c729 | Dmitry Eremin-Solenikov | |
278 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); |
279 | c1713132 | balrog | |
280 | c1713132 | balrog | /* Enable IC memory-mapped registers access. */
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281 | 2c9b15ca | Paolo Bonzini | memory_region_init_io(&s->iomem, NULL, &pxa2xx_pic_ops, s,
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282 | 90e8e5a3 | Benoît Canet | "pxa2xx-pic", 0x00100000); |
283 | 1356b98d | Andreas Färber | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
284 | 1356b98d | Andreas Färber | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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285 | c1713132 | balrog | |
286 | c1713132 | balrog | /* Enable IC coprocessor access. */
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287 | 9ee703b0 | Peter Maydell | define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s); |
288 | c1713132 | balrog | |
289 | e1f8c729 | Dmitry Eremin-Solenikov | return dev;
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290 | e1f8c729 | Dmitry Eremin-Solenikov | } |
291 | e1f8c729 | Dmitry Eremin-Solenikov | |
292 | e1f8c729 | Dmitry Eremin-Solenikov | static VMStateDescription vmstate_pxa2xx_pic_regs = {
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293 | e1f8c729 | Dmitry Eremin-Solenikov | .name = "pxa2xx_pic",
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294 | e1f8c729 | Dmitry Eremin-Solenikov | .version_id = 0,
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295 | e1f8c729 | Dmitry Eremin-Solenikov | .minimum_version_id = 0,
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296 | e1f8c729 | Dmitry Eremin-Solenikov | .minimum_version_id_old = 0,
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297 | e1f8c729 | Dmitry Eremin-Solenikov | .post_load = pxa2xx_pic_post_load, |
298 | e1f8c729 | Dmitry Eremin-Solenikov | .fields = (VMStateField[]) { |
299 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
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300 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
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301 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
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302 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(int_idle, PXA2xxPICState), |
303 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS), |
304 | e1f8c729 | Dmitry Eremin-Solenikov | VMSTATE_END_OF_LIST(), |
305 | e1f8c729 | Dmitry Eremin-Solenikov | }, |
306 | e1f8c729 | Dmitry Eremin-Solenikov | }; |
307 | aa941b94 | balrog | |
308 | e1f8c729 | Dmitry Eremin-Solenikov | static int pxa2xx_pic_initfn(SysBusDevice *dev) |
309 | e1f8c729 | Dmitry Eremin-Solenikov | { |
310 | e1f8c729 | Dmitry Eremin-Solenikov | return 0; |
311 | e1f8c729 | Dmitry Eremin-Solenikov | } |
312 | e1f8c729 | Dmitry Eremin-Solenikov | |
313 | 999e12bb | Anthony Liguori | static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) |
314 | 999e12bb | Anthony Liguori | { |
315 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
316 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
317 | 999e12bb | Anthony Liguori | |
318 | 999e12bb | Anthony Liguori | k->init = pxa2xx_pic_initfn; |
319 | 39bffca2 | Anthony Liguori | dc->desc = "PXA2xx PIC";
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320 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pxa2xx_pic_regs; |
321 | 999e12bb | Anthony Liguori | } |
322 | 999e12bb | Anthony Liguori | |
323 | 8c43a6f0 | Andreas Färber | static const TypeInfo pxa2xx_pic_info = { |
324 | 39bffca2 | Anthony Liguori | .name = "pxa2xx_pic",
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325 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
326 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PXA2xxPICState),
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327 | 39bffca2 | Anthony Liguori | .class_init = pxa2xx_pic_class_init, |
328 | e1f8c729 | Dmitry Eremin-Solenikov | }; |
329 | e1f8c729 | Dmitry Eremin-Solenikov | |
330 | 83f7d43a | Andreas Färber | static void pxa2xx_pic_register_types(void) |
331 | e1f8c729 | Dmitry Eremin-Solenikov | { |
332 | 39bffca2 | Anthony Liguori | type_register_static(&pxa2xx_pic_info); |
333 | c1713132 | balrog | } |
334 | 83f7d43a | Andreas Färber | |
335 | 83f7d43a | Andreas Färber | type_init(pxa2xx_pic_register_types) |