Revision 2c9b15ca hw/alpha/typhoon.c
| b/hw/alpha/typhoon.c | ||
|---|---|---|
| 741 | 741 |
|
| 742 | 742 |
/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, |
| 743 | 743 |
but the address space hole reserved at this point is 8TB. */ |
| 744 |
memory_region_init_ram(&s->ram_region, "ram", ram_size); |
|
| 744 |
memory_region_init_ram(&s->ram_region, NULL, "ram", ram_size);
|
|
| 745 | 745 |
vmstate_register_ram_global(&s->ram_region); |
| 746 | 746 |
memory_region_add_subregion(addr_space, 0, &s->ram_region); |
| 747 | 747 |
|
| ... | ... | |
| 750 | 750 |
the flash ROM. I'm not sure that we need to implement it at all. */ |
| 751 | 751 |
|
| 752 | 752 |
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */ |
| 753 |
memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB); |
|
| 753 |
memory_region_init_io(&s->pchip.region, NULL, &pchip_ops, s, "pchip0", 256*MB);
|
|
| 754 | 754 |
memory_region_add_subregion(addr_space, 0x80180000000ULL, |
| 755 | 755 |
&s->pchip.region); |
| 756 | 756 |
|
| 757 | 757 |
/* Cchip CSRs, 0x801.A000.0000, 256MB. */ |
| 758 |
memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB); |
|
| 758 |
memory_region_init_io(&s->cchip.region, NULL, &cchip_ops, s, "cchip0", 256*MB);
|
|
| 759 | 759 |
memory_region_add_subregion(addr_space, 0x801a0000000ULL, |
| 760 | 760 |
&s->cchip.region); |
| 761 | 761 |
|
| 762 | 762 |
/* Dchip CSRs, 0x801.B000.0000, 256MB. */ |
| 763 |
memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB); |
|
| 763 |
memory_region_init_io(&s->dchip_region, NULL, &dchip_ops, s, "dchip0", 256*MB);
|
|
| 764 | 764 |
memory_region_add_subregion(addr_space, 0x801b0000000ULL, |
| 765 | 765 |
&s->dchip_region); |
| 766 | 766 |
|
| 767 | 767 |
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */ |
| 768 |
memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB); |
|
| 768 |
memory_region_init(&s->pchip.reg_mem, NULL, "pci0-mem", 4*GB);
|
|
| 769 | 769 |
memory_region_add_subregion(addr_space, 0x80000000000ULL, |
| 770 | 770 |
&s->pchip.reg_mem); |
| 771 | 771 |
|
| ... | ... | |
| 773 | 773 |
/* ??? Ideally we drop the "system" i/o space on the floor and give the |
| 774 | 774 |
PCI subsystem the full address space reserved by the chipset. |
| 775 | 775 |
We can't do that until the MEM and IO paths in memory.c are unified. */ |
| 776 |
memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL, |
|
| 776 |
memory_region_init_io(&s->pchip.reg_io, NULL, &alpha_pci_bw_io_ops, NULL,
|
|
| 777 | 777 |
"pci0-io", 32*MB); |
| 778 | 778 |
memory_region_add_subregion(addr_space, 0x801fc000000ULL, |
| 779 | 779 |
&s->pchip.reg_io); |
| ... | ... | |
| 784 | 784 |
phb->bus = b; |
| 785 | 785 |
|
| 786 | 786 |
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ |
| 787 |
memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b, |
|
| 787 |
memory_region_init_io(&s->pchip.reg_iack, NULL, &alpha_pci_iack_ops, b,
|
|
| 788 | 788 |
"pci0-iack", 64*MB); |
| 789 | 789 |
memory_region_add_subregion(addr_space, 0x801f8000000ULL, |
| 790 | 790 |
&s->pchip.reg_iack); |
| 791 | 791 |
|
| 792 | 792 |
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ |
| 793 |
memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b, |
|
| 793 |
memory_region_init_io(&s->pchip.reg_conf, NULL, &alpha_pci_conf1_ops, b,
|
|
| 794 | 794 |
"pci0-conf", 16*MB); |
| 795 | 795 |
memory_region_add_subregion(addr_space, 0x801fe000000ULL, |
| 796 | 796 |
&s->pchip.reg_conf); |
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