root / hw / display / tcx.c @ 2c9b15ca
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/*
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* QEMU TCX Frame buffer
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu-common.h" |
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#include "ui/console.h" |
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#include "ui/pixel_ops.h" |
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#include "hw/sysbus.h" |
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|
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#define MAXX 1024 |
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#define MAXY 768 |
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#define TCX_DAC_NREGS 16 |
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#define TCX_THC_NREGS_8 0x081c |
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#define TCX_THC_NREGS_24 0x1000 |
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#define TCX_TEC_NREGS 0x1000 |
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typedef struct TCXState { |
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SysBusDevice busdev; |
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QemuConsole *con; |
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uint8_t *vram; |
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uint32_t *vram24, *cplane; |
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MemoryRegion vram_mem; |
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MemoryRegion vram_8bit; |
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MemoryRegion vram_24bit; |
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MemoryRegion vram_cplane; |
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MemoryRegion dac; |
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MemoryRegion tec; |
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MemoryRegion thc24; |
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MemoryRegion thc8; |
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ram_addr_t vram24_offset, cplane_offset; |
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uint32_t vram_size; |
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uint32_t palette[256];
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uint8_t r[256], g[256], b[256]; |
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uint16_t width, height, depth; |
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uint8_t dac_index, dac_state; |
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} TCXState; |
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static void tcx_set_dirty(TCXState *s) |
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{ |
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memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
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} |
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static void tcx24_set_dirty(TCXState *s) |
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{ |
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memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
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memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
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} |
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static void update_palette_entries(TCXState *s, int start, int end) |
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{ |
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DisplaySurface *surface = qemu_console_surface(s->con); |
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int i;
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for (i = start; i < end; i++) {
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switch (surface_bits_per_pixel(surface)) {
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default:
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case 8: |
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s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
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break;
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case 15: |
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s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
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break;
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case 16: |
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s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
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break;
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case 32: |
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if (is_surface_bgr(surface)) {
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s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
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} else {
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s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
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} |
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break;
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} |
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} |
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if (s->depth == 24) { |
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tcx24_set_dirty(s); |
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} else {
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tcx_set_dirty(s); |
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} |
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} |
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static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint32_t *p = (uint32_t *)d; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint16_t *p = (uint16_t *)d; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*d++ = s1->palette[val]; |
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} |
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} |
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/*
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XXX Could be much more optimal:
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* detect if line/page/whole screen is in 24 bit mode
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* if destination is also BGR, use memcpy
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*/
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static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width, |
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const uint32_t *cplane,
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const uint32_t *s24)
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{ |
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DisplaySurface *surface = qemu_console_surface(s1->con); |
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int x, bgr, r, g, b;
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uint8_t val, *p8; |
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uint32_t *p = (uint32_t *)d; |
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uint32_t dval; |
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bgr = is_surface_bgr(surface); |
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for(x = 0; x < width; x++, s++, s24++) { |
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if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
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// 24-bit direct, BGR order
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p8 = (uint8_t *)s24; |
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p8++; |
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b = *p8++; |
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g = *p8++; |
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r = *p8; |
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if (bgr)
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dval = rgb_to_pixel32bgr(r, g, b); |
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else
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dval = rgb_to_pixel32(r, g, b); |
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} else {
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val = *s; |
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dval = s1->palette[val]; |
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} |
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*p++ = dval; |
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} |
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} |
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static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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int ret;
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ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE, |
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DIRTY_MEMORY_VGA); |
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ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
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DIRTY_MEMORY_VGA); |
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ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
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DIRTY_MEMORY_VGA); |
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return ret;
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} |
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static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
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ram_addr_t page_max, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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memory_region_reset_dirty(&ts->vram_mem, |
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page_min, |
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(page_max - page_min) + TARGET_PAGE_SIZE, |
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DIRTY_MEMORY_VGA); |
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memory_region_reset_dirty(&ts->vram_mem, |
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page24 + page_min * 4,
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(page_max - page_min) * 4 + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA); |
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memory_region_reset_dirty(&ts->vram_mem, |
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cpage + page_min * 4,
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(page_max - page_min) * 4 + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA); |
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} |
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/* Fixed line length 1024 allows us to do nice tricks not possible on
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VGA... */
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static void tcx_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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DisplaySurface *surface = qemu_console_surface(ts->con); |
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ram_addr_t page, page_min, page_max; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
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if (surface_bits_per_pixel(surface) == 0) { |
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return;
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} |
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page = 0;
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y_start = -1;
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page_min = -1;
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page_max = 0;
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d = surface_data(surface); |
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s = ts->vram; |
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dd = surface_stride(surface); |
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ds = 1024;
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switch (surface_bits_per_pixel(surface)) {
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case 32: |
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f = tcx_draw_line32; |
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break;
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case 15: |
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case 16: |
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f = tcx_draw_line16; |
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break;
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default:
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case 8: |
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f = tcx_draw_line8; |
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break;
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case 0: |
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return;
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} |
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
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if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA)) { |
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_gfx_update(ts->con, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
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d += dd * 4;
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s += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
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/* flush to display */
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dpy_gfx_update(ts->con, 0, y_start,
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ts->width, y - y_start); |
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} |
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/* reset modified pages */
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if (page_max >= page_min) {
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memory_region_reset_dirty(&ts->vram_mem, |
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page_min, |
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(page_max - page_min) + TARGET_PAGE_SIZE, |
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DIRTY_MEMORY_VGA); |
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} |
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} |
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static void tcx24_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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DisplaySurface *surface = qemu_console_surface(ts->con); |
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ram_addr_t page, page_min, page_max, cpage, page24; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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uint32_t *cptr, *s24; |
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if (surface_bits_per_pixel(surface) != 32) { |
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return;
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} |
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page = 0;
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page24 = ts->vram24_offset; |
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cpage = ts->cplane_offset; |
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y_start = -1;
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page_min = -1;
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page_max = 0;
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d = surface_data(surface); |
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s = ts->vram; |
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s24 = ts->vram24; |
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cptr = ts->cplane; |
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dd = surface_stride(surface); |
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ds = 1024;
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
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page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
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if (check_dirty(ts, page, page24, cpage)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_gfx_update(ts->con, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
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d += dd * 4;
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s += ds * 4;
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cptr += ds * 4;
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s24 += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
364 |
/* flush to display */
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dpy_gfx_update(ts->con, 0, y_start,
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ts->width, y - y_start); |
367 |
} |
368 |
/* reset modified pages */
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if (page_max >= page_min) {
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reset_dirty(ts, page_min, page_max, page24, cpage); |
371 |
} |
372 |
} |
373 |
|
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static void tcx_invalidate_display(void *opaque) |
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{ |
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TCXState *s = opaque; |
377 |
|
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tcx_set_dirty(s); |
379 |
qemu_console_resize(s->con, s->width, s->height); |
380 |
} |
381 |
|
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static void tcx24_invalidate_display(void *opaque) |
383 |
{ |
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TCXState *s = opaque; |
385 |
|
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tcx_set_dirty(s); |
387 |
tcx24_set_dirty(s); |
388 |
qemu_console_resize(s->con, s->width, s->height); |
389 |
} |
390 |
|
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static int vmstate_tcx_post_load(void *opaque, int version_id) |
392 |
{ |
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TCXState *s = opaque; |
394 |
|
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update_palette_entries(s, 0, 256); |
396 |
if (s->depth == 24) { |
397 |
tcx24_set_dirty(s); |
398 |
} else {
|
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tcx_set_dirty(s); |
400 |
} |
401 |
|
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return 0; |
403 |
} |
404 |
|
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static const VMStateDescription vmstate_tcx = { |
406 |
.name ="tcx",
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.version_id = 4,
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.minimum_version_id = 4,
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.minimum_version_id_old = 4,
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.post_load = vmstate_tcx_post_load, |
411 |
.fields = (VMStateField []) { |
412 |
VMSTATE_UINT16(height, TCXState), |
413 |
VMSTATE_UINT16(width, TCXState), |
414 |
VMSTATE_UINT16(depth, TCXState), |
415 |
VMSTATE_BUFFER(r, TCXState), |
416 |
VMSTATE_BUFFER(g, TCXState), |
417 |
VMSTATE_BUFFER(b, TCXState), |
418 |
VMSTATE_UINT8(dac_index, TCXState), |
419 |
VMSTATE_UINT8(dac_state, TCXState), |
420 |
VMSTATE_END_OF_LIST() |
421 |
} |
422 |
}; |
423 |
|
424 |
static void tcx_reset(DeviceState *d) |
425 |
{ |
426 |
TCXState *s = container_of(d, TCXState, busdev.qdev); |
427 |
|
428 |
/* Initialize palette */
|
429 |
memset(s->r, 0, 256); |
430 |
memset(s->g, 0, 256); |
431 |
memset(s->b, 0, 256); |
432 |
s->r[255] = s->g[255] = s->b[255] = 255; |
433 |
update_palette_entries(s, 0, 256); |
434 |
memset(s->vram, 0, MAXX*MAXY);
|
435 |
memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), |
436 |
DIRTY_MEMORY_VGA); |
437 |
s->dac_index = 0;
|
438 |
s->dac_state = 0;
|
439 |
} |
440 |
|
441 |
static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, |
442 |
unsigned size)
|
443 |
{ |
444 |
return 0; |
445 |
} |
446 |
|
447 |
static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, |
448 |
unsigned size)
|
449 |
{ |
450 |
TCXState *s = opaque; |
451 |
|
452 |
switch (addr) {
|
453 |
case 0: |
454 |
s->dac_index = val >> 24;
|
455 |
s->dac_state = 0;
|
456 |
break;
|
457 |
case 4: |
458 |
switch (s->dac_state) {
|
459 |
case 0: |
460 |
s->r[s->dac_index] = val >> 24;
|
461 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
462 |
s->dac_state++; |
463 |
break;
|
464 |
case 1: |
465 |
s->g[s->dac_index] = val >> 24;
|
466 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
467 |
s->dac_state++; |
468 |
break;
|
469 |
case 2: |
470 |
s->b[s->dac_index] = val >> 24;
|
471 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
472 |
s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
473 |
default:
|
474 |
s->dac_state = 0;
|
475 |
break;
|
476 |
} |
477 |
break;
|
478 |
default:
|
479 |
break;
|
480 |
} |
481 |
} |
482 |
|
483 |
static const MemoryRegionOps tcx_dac_ops = { |
484 |
.read = tcx_dac_readl, |
485 |
.write = tcx_dac_writel, |
486 |
.endianness = DEVICE_NATIVE_ENDIAN, |
487 |
.valid = { |
488 |
.min_access_size = 4,
|
489 |
.max_access_size = 4,
|
490 |
}, |
491 |
}; |
492 |
|
493 |
static uint64_t dummy_readl(void *opaque, hwaddr addr, |
494 |
unsigned size)
|
495 |
{ |
496 |
return 0; |
497 |
} |
498 |
|
499 |
static void dummy_writel(void *opaque, hwaddr addr, |
500 |
uint64_t val, unsigned size)
|
501 |
{ |
502 |
} |
503 |
|
504 |
static const MemoryRegionOps dummy_ops = { |
505 |
.read = dummy_readl, |
506 |
.write = dummy_writel, |
507 |
.endianness = DEVICE_NATIVE_ENDIAN, |
508 |
.valid = { |
509 |
.min_access_size = 4,
|
510 |
.max_access_size = 4,
|
511 |
}, |
512 |
}; |
513 |
|
514 |
static const GraphicHwOps tcx_ops = { |
515 |
.invalidate = tcx_invalidate_display, |
516 |
.gfx_update = tcx_update_display, |
517 |
}; |
518 |
|
519 |
static const GraphicHwOps tcx24_ops = { |
520 |
.invalidate = tcx24_invalidate_display, |
521 |
.gfx_update = tcx24_update_display, |
522 |
}; |
523 |
|
524 |
static int tcx_init1(SysBusDevice *dev) |
525 |
{ |
526 |
TCXState *s = FROM_SYSBUS(TCXState, dev); |
527 |
ram_addr_t vram_offset = 0;
|
528 |
int size;
|
529 |
uint8_t *vram_base; |
530 |
|
531 |
memory_region_init_ram(&s->vram_mem, NULL, "tcx.vram", |
532 |
s->vram_size * (1 + 4 + 4)); |
533 |
vmstate_register_ram_global(&s->vram_mem); |
534 |
vram_base = memory_region_get_ram_ptr(&s->vram_mem); |
535 |
|
536 |
/* 8-bit plane */
|
537 |
s->vram = vram_base; |
538 |
size = s->vram_size; |
539 |
memory_region_init_alias(&s->vram_8bit, NULL, "tcx.vram.8bit", |
540 |
&s->vram_mem, vram_offset, size); |
541 |
sysbus_init_mmio(dev, &s->vram_8bit); |
542 |
vram_offset += size; |
543 |
vram_base += size; |
544 |
|
545 |
/* DAC */
|
546 |
memory_region_init_io(&s->dac, NULL, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS); |
547 |
sysbus_init_mmio(dev, &s->dac); |
548 |
|
549 |
/* TEC (dummy) */
|
550 |
memory_region_init_io(&s->tec, NULL, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS); |
551 |
sysbus_init_mmio(dev, &s->tec); |
552 |
/* THC: NetBSD writes here even with 8-bit display: dummy */
|
553 |
memory_region_init_io(&s->thc24, NULL, &dummy_ops, s, "tcx.thc24", |
554 |
TCX_THC_NREGS_24); |
555 |
sysbus_init_mmio(dev, &s->thc24); |
556 |
|
557 |
if (s->depth == 24) { |
558 |
/* 24-bit plane */
|
559 |
size = s->vram_size * 4;
|
560 |
s->vram24 = (uint32_t *)vram_base; |
561 |
s->vram24_offset = vram_offset; |
562 |
memory_region_init_alias(&s->vram_24bit, NULL, "tcx.vram.24bit", |
563 |
&s->vram_mem, vram_offset, size); |
564 |
sysbus_init_mmio(dev, &s->vram_24bit); |
565 |
vram_offset += size; |
566 |
vram_base += size; |
567 |
|
568 |
/* Control plane */
|
569 |
size = s->vram_size * 4;
|
570 |
s->cplane = (uint32_t *)vram_base; |
571 |
s->cplane_offset = vram_offset; |
572 |
memory_region_init_alias(&s->vram_cplane, NULL, "tcx.vram.cplane", |
573 |
&s->vram_mem, vram_offset, size); |
574 |
sysbus_init_mmio(dev, &s->vram_cplane); |
575 |
|
576 |
s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s); |
577 |
} else {
|
578 |
/* THC 8 bit (dummy) */
|
579 |
memory_region_init_io(&s->thc8, NULL, &dummy_ops, s, "tcx.thc8", |
580 |
TCX_THC_NREGS_8); |
581 |
sysbus_init_mmio(dev, &s->thc8); |
582 |
|
583 |
s->con = graphic_console_init(DEVICE(dev), &tcx_ops, s); |
584 |
} |
585 |
|
586 |
qemu_console_resize(s->con, s->width, s->height); |
587 |
return 0; |
588 |
} |
589 |
|
590 |
static Property tcx_properties[] = {
|
591 |
DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), |
592 |
DEFINE_PROP_UINT16("width", TCXState, width, -1), |
593 |
DEFINE_PROP_UINT16("height", TCXState, height, -1), |
594 |
DEFINE_PROP_UINT16("depth", TCXState, depth, -1), |
595 |
DEFINE_PROP_END_OF_LIST(), |
596 |
}; |
597 |
|
598 |
static void tcx_class_init(ObjectClass *klass, void *data) |
599 |
{ |
600 |
DeviceClass *dc = DEVICE_CLASS(klass); |
601 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
602 |
|
603 |
k->init = tcx_init1; |
604 |
dc->reset = tcx_reset; |
605 |
dc->vmsd = &vmstate_tcx; |
606 |
dc->props = tcx_properties; |
607 |
} |
608 |
|
609 |
static const TypeInfo tcx_info = { |
610 |
.name = "SUNW,tcx",
|
611 |
.parent = TYPE_SYS_BUS_DEVICE, |
612 |
.instance_size = sizeof(TCXState),
|
613 |
.class_init = tcx_class_init, |
614 |
}; |
615 |
|
616 |
static void tcx_register_types(void) |
617 |
{ |
618 |
type_register_static(&tcx_info); |
619 |
} |
620 |
|
621 |
type_init(tcx_register_types) |