Archipelago » qemu

/*

 * QEMU VMWARE VMXNET3 paravirtual NIC

 *

 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)

 *

 * Developed by Daynix Computing LTD (http://www.daynix.com)

 *

 * Authors:

 * Dmitry Fleytman <dmitry@daynix.com>

 * Tamir Shomer <tamirs@daynix.com>

 * Yan Vugenfirer <yan@daynix.com>

 *

 * This work is licensed under the terms of the GNU GPL, version 2.

 * See the COPYING file in the top-level directory.

 *

 */

#include "hw/hw.h"

#include "hw/pci/pci.h"

#include "net/net.h"

#include "net/tap.h"

#include "net/checksum.h"

#include "sysemu/sysemu.h"

#include "qemu-common.h"

#include "qemu/bswap.h"

#include "hw/pci/msix.h"

#include "hw/pci/msi.h"

#include "vmxnet3.h"

#include "vmxnet_debug.h"

#include "vmware_utils.h"

#include "vmxnet_tx_pkt.h"

#include "vmxnet_rx_pkt.h"

#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1

#define VMXNET3_MSIX_BAR_SIZE 0x2000

#define VMXNET3_BAR0_IDX      (0)

#define VMXNET3_BAR1_IDX      (1)

#define VMXNET3_MSIX_BAR_IDX  (2)

#define VMXNET3_OFF_MSIX_TABLE (0x000)

#define VMXNET3_OFF_MSIX_PBA   (0x800)

/* Link speed in Mbps should be shifted by 16 */

#define VMXNET3_LINK_SPEED      (1000 << 16)

/* Link status: 1 - up, 0 - down. */

#define VMXNET3_LINK_STATUS_UP  0x1

/* Least significant bit should be set for revision and version */

#define VMXNET3_DEVICE_VERSION    0x1

#define VMXNET3_DEVICE_REVISION   0x1

/* Macros for rings descriptors access */

#define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \

    (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))

#define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \

    (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))

#define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \

    (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))

#define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \

    (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))

#define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \

    (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))

#define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \

    (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))

#define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \

    (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))

#define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \

    (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))

#define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \

    (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))

#define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \

    (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))

/* Macros for guest driver shared area access */

#define VMXNET3_READ_DRV_SHARED64(shpa, field) \

    (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))

#define VMXNET3_READ_DRV_SHARED32(shpa, field) \

    (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))

#define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \

    (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))

#define VMXNET3_READ_DRV_SHARED16(shpa, field) \

    (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))

#define VMXNET3_READ_DRV_SHARED8(shpa, field) \

    (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))

#define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \

    (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))

#define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))

#define TYPE_VMXNET3 "vmxnet3"

#define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)

/* Cyclic ring abstraction */

typedef struct {

    hwaddr pa;

    size_t size;

    size_t cell_size;

    size_t next;

    uint8_t gen;

} Vmxnet3Ring;

static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,

                                     hwaddr pa,

                                     size_t size,

                                     size_t cell_size,

                                     bool zero_region)

{

    ring->pa = pa;

    ring->size = size;

    ring->cell_size = cell_size;

    ring->gen = VMXNET3_INIT_GEN;

    ring->next = 0;

    if (zero_region) {

        vmw_shmem_set(pa, 0, size * cell_size);

    }

}

#define VMXNET3_RING_DUMP(macro, ring_name, ridx, r)                         \

    macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu",  \

          (ring_name), (ridx),                                               \

          (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)

static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)

{

    if (++ring->next >= ring->size) {

        ring->next = 0;

        ring->gen ^= 1;

    }

}

static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)

{

    if (ring->next-- == 0) {

        ring->next = ring->size - 1;

        ring->gen ^= 1;

    }

}

static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)

{

    return ring->pa + ring->next * ring->cell_size;

}

static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)

{

    vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);

}

static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)

{

    vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);

}

static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)

{

    return ring->next;

}

static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)

{

    return ring->gen;

}

/* Debug trace-related functions */

static inline void

vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)

{

    VMW_PKPRN("TX DESCR: "

              "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "

              "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "

              "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",

              le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,

              descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,

              descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);

}

static inline void

vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)

{

    VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "

              "csum_start: %d, csum_offset: %d",

              vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,

              vhdr->csum_start, vhdr->csum_offset);

}

static inline void

vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)

{

    VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "

              "dtype: %d, ext1: %d, btype: %d",

              le64_to_cpu(descr->addr), descr->len, descr->gen,

              descr->rsvd, descr->dtype, descr->ext1, descr->btype);

}

/* Device state and helper functions */

#define VMXNET3_RX_RINGS_PER_QUEUE (2)

typedef struct {

    Vmxnet3Ring tx_ring;

    Vmxnet3Ring comp_ring;

    uint8_t intr_idx;

    hwaddr tx_stats_pa;

    struct UPT1_TxStats txq_stats;

} Vmxnet3TxqDescr;

typedef struct {

    Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];

    Vmxnet3Ring comp_ring;

    uint8_t intr_idx;

    hwaddr rx_stats_pa;

    struct UPT1_RxStats rxq_stats;

} Vmxnet3RxqDescr;

typedef struct {

    bool is_masked;

    bool is_pending;

    bool is_asserted;

} Vmxnet3IntState;

typedef struct {

        PCIDevice parent_obj;

        NICState *nic;

        NICConf conf;

        MemoryRegion bar0;

        MemoryRegion bar1;

        MemoryRegion msix_bar;

        Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];

        Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];

        /* Whether MSI-X support was installed successfully */

        bool msix_used;

        /* Whether MSI support was installed successfully */

        bool msi_used;

        hwaddr drv_shmem;

        hwaddr temp_shared_guest_driver_memory;

        uint8_t txq_num;

        /* This boolean tells whether RX packet being indicated has to */

        /* be split into head and body chunks from different RX rings  */

        bool rx_packets_compound;

        bool rx_vlan_stripping;

        bool lro_supported;

        uint8_t rxq_num;

        /* Network MTU */

        uint32_t mtu;

        /* Maximum number of fragments for indicated TX packets */

        uint32_t max_tx_frags;

        /* Maximum number of fragments for indicated RX packets */

        uint16_t max_rx_frags;

        /* Index for events interrupt */

        uint8_t event_int_idx;

        /* Whether automatic interrupts masking enabled */

        bool auto_int_masking;

        bool peer_has_vhdr;

        /* TX packets to QEMU interface */

        struct VmxnetTxPkt *tx_pkt;

        uint32_t offload_mode;

        uint32_t cso_or_gso_size;

        uint16_t tci;

        bool needs_vlan;

        struct VmxnetRxPkt *rx_pkt;

        bool tx_sop;

        bool skip_current_tx_pkt;

        uint32_t device_active;

        uint32_t last_command;

        uint32_t link_status_and_speed;

        Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];

        uint32_t temp_mac;   /* To store the low part first */

        MACAddr perm_mac;

        uint32_t vlan_table[VMXNET3_VFT_SIZE];

        uint32_t rx_mode;

        MACAddr *mcast_list;

        uint32_t mcast_list_len;

        uint32_t mcast_list_buff_size; /* needed for live migration. */

} VMXNET3State;

/* Interrupt management */

/*

 *This function returns sign whether interrupt line is in asserted state

 * This depends on the type of interrupt used. For INTX interrupt line will

 * be asserted until explicit deassertion, for MSI(X) interrupt line will

 * be deasserted automatically due to notification semantics of the MSI(X)

 * interrupts

 */

static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)

{

    PCIDevice *d = PCI_DEVICE(s);

    if (s->msix_used && msix_enabled(d)) {

        VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);

        msix_notify(d, int_idx);

        return false;

    }

    if (s->msi_used && msi_enabled(d)) {

        VMW_IRPRN("Sending MSI notification for vector %u", int_idx);

        msi_notify(d, int_idx);

        return false;

    }

    VMW_IRPRN("Asserting line for interrupt %u", int_idx);

    qemu_set_irq(d->irq[int_idx], 1);

    return true;

}

static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)

{

    PCIDevice *d = PCI_DEVICE(s);

    /*

     * This function should never be called for MSI(X) interrupts

     * because deassertion never required for message interrupts

     */

    assert(!s->msix_used || !msix_enabled(d));

    /*

     * This function should never be called for MSI(X) interrupts

     * because deassertion never required for message interrupts

     */

    assert(!s->msi_used || !msi_enabled(d));

    VMW_IRPRN("Deasserting line for interrupt %u", lidx);

    qemu_set_irq(d->irq[lidx], 0);

}

static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)

{

    if (!s->interrupt_states[lidx].is_pending &&

       s->interrupt_states[lidx].is_asserted) {

        VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);

        _vmxnet3_deassert_interrupt_line(s, lidx);

        s->interrupt_states[lidx].is_asserted = false;

        return;

    }

    if (s->interrupt_states[lidx].is_pending &&

       !s->interrupt_states[lidx].is_masked &&

       !s->interrupt_states[lidx].is_asserted) {

        VMW_IRPRN("New interrupt line state for index %d is UP", lidx);

        s->interrupt_states[lidx].is_asserted =

            _vmxnet3_assert_interrupt_line(s, lidx);

        s->interrupt_states[lidx].is_pending = false;

        return;

    }

}

static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)

{

    PCIDevice *d = PCI_DEVICE(s);

    s->interrupt_states[lidx].is_pending = true;

    vmxnet3_update_interrupt_line_state(s, lidx);

    if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {

        goto do_automask;

    }

    if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {

        goto do_automask;

    }

    return;

do_automask:

    s->interrupt_states[lidx].is_masked = true;

    vmxnet3_update_interrupt_line_state(s, lidx);

}

static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)

{

    return s->interrupt_states[lidx].is_asserted;

}

static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)

{

    s->interrupt_states[int_idx].is_pending = false;

    if (s->auto_int_masking) {

        s->interrupt_states[int_idx].is_masked = true;

    }

    vmxnet3_update_interrupt_line_state(s, int_idx);

}

static void

vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)

{

    s->interrupt_states[lidx].is_masked = is_masked;

    vmxnet3_update_interrupt_line_state(s, lidx);

}

static bool vmxnet3_verify_driver_magic(hwaddr dshmem)

{

    return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);

}

#define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)

#define VMXNET3_MAKE_BYTE(byte_num, val) \

    (((uint32_t)((val) & 0xFF)) << (byte_num)*8)

static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)

{

    s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l,  0);

    s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l,  1);

    s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l,  2);

    s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l,  3);

    s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);

    s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);

    VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));

    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);

}

static uint64_t vmxnet3_get_mac_low(MACAddr *addr)

{

    return VMXNET3_MAKE_BYTE(0, addr->a[0]) |

           VMXNET3_MAKE_BYTE(1, addr->a[1]) |

           VMXNET3_MAKE_BYTE(2, addr->a[2]) |

           VMXNET3_MAKE_BYTE(3, addr->a[3]);

}

static uint64_t vmxnet3_get_mac_high(MACAddr *addr)

{

    return VMXNET3_MAKE_BYTE(0, addr->a[4]) |

           VMXNET3_MAKE_BYTE(1, addr->a[5]);

}

static void

vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)

{

    vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);

}

static inline void

vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)

{

    vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);

}

static inline void

vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)

{

    vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);

}

static void

vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)

{

    vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);

}

static void

vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)

{

    vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);

}

static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32 tx_ridx)

{

    struct Vmxnet3_TxCompDesc txcq_descr;

    VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);

    txcq_descr.txdIdx = tx_ridx;

    txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);

    vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);

    /* Flush changes in TX descriptor before changing the counter value */

    smp_wmb();

    vmxnet3_inc_tx_completion_counter(s, qidx);

    vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);

}

static bool

vmxnet3_setup_tx_offloads(VMXNET3State *s)

{

    switch (s->offload_mode) {

    case VMXNET3_OM_NONE:

        vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);

        break;

    case VMXNET3_OM_CSUM:

        vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);

        VMW_PKPRN("L4 CSO requested\n");

        break;

    case VMXNET3_OM_TSO:

        vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,

            s->cso_or_gso_size);

        vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);

        VMW_PKPRN("GSO offload requested.");

        break;

    default:

        assert(false);

        return false;

    }

    return true;

}

static void

vmxnet3_tx_retrieve_metadata(VMXNET3State *s,

                             const struct Vmxnet3_TxDesc *txd)

{

    s->offload_mode = txd->om;

    s->cso_or_gso_size = txd->msscof;

    s->tci = txd->tci;

    s->needs_vlan = txd->ti;

}

typedef enum {

    VMXNET3_PKT_STATUS_OK,

    VMXNET3_PKT_STATUS_ERROR,

    VMXNET3_PKT_STATUS_DISCARD,/* only for tx */

    VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */

} Vmxnet3PktStatus;

static void

vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,

    Vmxnet3PktStatus status)

{

    size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);

    struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;

    switch (status) {

    case VMXNET3_PKT_STATUS_OK:

        switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {

        case ETH_PKT_BCAST:

            stats->bcastPktsTxOK++;

            stats->bcastBytesTxOK += tot_len;

            break;

        case ETH_PKT_MCAST:

            stats->mcastPktsTxOK++;

            stats->mcastBytesTxOK += tot_len;

            break;

        case ETH_PKT_UCAST:

            stats->ucastPktsTxOK++;

            stats->ucastBytesTxOK += tot_len;

            break;

        default:

            assert(false);

        }

        if (s->offload_mode == VMXNET3_OM_TSO) {

            /*

             * According to VMWARE headers this statistic is a number

             * of packets after segmentation but since we don't have

             * this information in QEMU model, the best we can do is to

             * provide number of non-segmented packets

             */

            stats->TSOPktsTxOK++;

            stats->TSOBytesTxOK += tot_len;

        }

        break;

    case VMXNET3_PKT_STATUS_DISCARD:

        stats->pktsTxDiscard++;

        break;

    case VMXNET3_PKT_STATUS_ERROR:

        stats->pktsTxError++;

        break;

    default:

        assert(false);

    }

}

static void

vmxnet3_on_rx_done_update_stats(VMXNET3State *s,

                                int qidx,

                                Vmxnet3PktStatus status)

{

    struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;

    size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);

    switch (status) {

    case VMXNET3_PKT_STATUS_OUT_OF_BUF:

        stats->pktsRxOutOfBuf++;

        break;

    case VMXNET3_PKT_STATUS_ERROR:

        stats->pktsRxError++;

        break;

    case VMXNET3_PKT_STATUS_OK:

        switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {

        case ETH_PKT_BCAST:

            stats->bcastPktsRxOK++;

            stats->bcastBytesRxOK += tot_len;

            break;

        case ETH_PKT_MCAST:

            stats->mcastPktsRxOK++;

            stats->mcastBytesRxOK += tot_len;

            break;

        case ETH_PKT_UCAST:

            stats->ucastPktsRxOK++;

            stats->ucastBytesRxOK += tot_len;

            break;

        default:

            assert(false);

        }

        if (tot_len > s->mtu) {

            stats->LROPktsRxOK++;

            stats->LROBytesRxOK += tot_len;

        }

        break;

    default:

        assert(false);

    }

}

static inline bool

vmxnet3_pop_next_tx_descr(VMXNET3State *s,

                          int qidx,

                          struct Vmxnet3_TxDesc *txd,

                          uint32_t *descr_idx)

{

    Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;

    vmxnet3_ring_read_curr_cell(ring, txd);

    if (txd->gen == vmxnet3_ring_curr_gen(ring)) {

        /* Only read after generation field verification */

        smp_rmb();

        /* Re-read to be sure we got the latest version */

        vmxnet3_ring_read_curr_cell(ring, txd);

        VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);

        *descr_idx = vmxnet3_ring_curr_cell_idx(ring);

        vmxnet3_inc_tx_consumption_counter(s, qidx);

        return true;

    }

    return false;

}

static bool

vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)

{

    Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;

    if (!vmxnet3_setup_tx_offloads(s)) {

        status = VMXNET3_PKT_STATUS_ERROR;

        goto func_exit;

    }

    /* debug prints */

    vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));

    vmxnet_tx_pkt_dump(s->tx_pkt);

    if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {

        status = VMXNET3_PKT_STATUS_DISCARD;

        goto func_exit;

    }

func_exit:

    vmxnet3_on_tx_done_update_stats(s, qidx, status);

    return (status == VMXNET3_PKT_STATUS_OK);

}

static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)

{

    struct Vmxnet3_TxDesc txd;

    uint32_t txd_idx;

    uint32_t data_len;

    hwaddr data_pa;

    for (;;) {

        if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {

            break;

        }

        vmxnet3_dump_tx_descr(&txd);

        if (!s->skip_current_tx_pkt) {

            data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;

            data_pa = le64_to_cpu(txd.addr);

            if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,

                                                data_pa,

                                                data_len)) {

                s->skip_current_tx_pkt = true;

            }

        }

        if (s->tx_sop) {

            vmxnet3_tx_retrieve_metadata(s, &txd);

            s->tx_sop = false;

        }

        if (txd.eop) {

            if (!s->skip_current_tx_pkt) {

                vmxnet_tx_pkt_parse(s->tx_pkt);

                if (s->needs_vlan) {

                    vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);

                }

                vmxnet3_send_packet(s, qidx);

            } else {

                vmxnet3_on_tx_done_update_stats(s, qidx,

                                                VMXNET3_PKT_STATUS_ERROR);

            }

            vmxnet3_complete_packet(s, qidx, txd_idx);

            s->tx_sop = true;

            s->skip_current_tx_pkt = false;

            vmxnet_tx_pkt_reset(s->tx_pkt);

        }

    }

}

static inline void

vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,

                           struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)

{

    Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];

    *didx = vmxnet3_ring_curr_cell_idx(ring);

    vmxnet3_ring_read_curr_cell(ring, dbuf);

}

static inline uint8_t

vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)

{

    return s->rxq_descr[qidx].rx_ring[ridx].gen;

}

static inline hwaddr

vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)

{

    uint8_t ring_gen;

    struct Vmxnet3_RxCompDesc rxcd;

    hwaddr daddr =

        vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);

    cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));

    ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);

    if (rxcd.gen != ring_gen) {

        *descr_gen = ring_gen;

        vmxnet3_inc_rx_completion_counter(s, qidx);

        return daddr;

    }

    return 0;

}

static inline void

vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)

{

    vmxnet3_dec_rx_completion_counter(s, qidx);

}

#define RXQ_IDX      (0)

#define RX_HEAD_BODY_RING (0)

#define RX_BODY_ONLY_RING (1)

static bool

vmxnet3_get_next_head_rx_descr(VMXNET3State *s,

                               struct Vmxnet3_RxDesc *descr_buf,

                               uint32_t *descr_idx,

                               uint32_t *ridx)

{

    for (;;) {

        uint32_t ring_gen;

        vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,

                                   descr_buf, descr_idx);

        /* If no more free descriptors - return */

        ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);

        if (descr_buf->gen != ring_gen) {

            return false;

        }

        /* Only read after generation field verification */

        smp_rmb();

        /* Re-read to be sure we got the latest version */

        vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,

                                   descr_buf, descr_idx);

        /* Mark current descriptor as used/skipped */

        vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);

        /* If this is what we are looking for - return */

        if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {

            *ridx = RX_HEAD_BODY_RING;

            return true;

        }

    }

}

static bool

vmxnet3_get_next_body_rx_descr(VMXNET3State *s,

                               struct Vmxnet3_RxDesc *d,

                               uint32_t *didx,

                               uint32_t *ridx)

{

    vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);

    /* Try to find corresponding descriptor in head/body ring */

    if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {

        /* Only read after generation field verification */

        smp_rmb();

        /* Re-read to be sure we got the latest version */

        vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);

        if (d->btype == VMXNET3_RXD_BTYPE_BODY) {

            vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);

            *ridx = RX_HEAD_BODY_RING;

            return true;

        }

    }

    /*

     * If there is no free descriptors on head/body ring or next free

     * descriptor is a head descriptor switch to body only ring

     */

    vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);

    /* If no more free descriptors - return */

    if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {

        /* Only read after generation field verification */

        smp_rmb();

        /* Re-read to be sure we got the latest version */

        vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);

        assert(d->btype == VMXNET3_RXD_BTYPE_BODY);

        *ridx = RX_BODY_ONLY_RING;

        vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);

        return true;

    }

    return false;

}

static inline bool

vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,

                          struct Vmxnet3_RxDesc *descr_buf,

                          uint32_t *descr_idx,

                          uint32_t *ridx)

{

    if (is_head || !s->rx_packets_compound) {

        return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);

    } else {

        return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);

    }

}

static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,

    struct Vmxnet3_RxCompDesc *rxcd)

{

    int csum_ok, is_gso;

    bool isip4, isip6, istcp, isudp;

    struct virtio_net_hdr *vhdr;

    uint8_t offload_type;

    if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {

        rxcd->ts = 1;

        rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);

    }

    if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {

        goto nocsum;

    }

    vhdr = vmxnet_rx_pkt_get_vhdr(pkt);

    /*

     * Checksum is valid when lower level tell so or when lower level

     * requires checksum offload telling that packet produced/bridged

     * locally and did travel over network after last checksum calculation

     * or production

     */

    csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||

              VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);

    offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;

    is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;

    if (!csum_ok && !is_gso) {

        goto nocsum;

    }

    vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);

    if ((!istcp && !isudp) || (!isip4 && !isip6)) {

        goto nocsum;

    }

    rxcd->cnc = 0;

    rxcd->v4 = isip4 ? 1 : 0;

    rxcd->v6 = isip6 ? 1 : 0;

    rxcd->tcp = istcp ? 1 : 0;

    rxcd->udp = isudp ? 1 : 0;

    rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;

    return;

nocsum:

    rxcd->cnc = 1;

    return;

}

static void

vmxnet3_physical_memory_writev(const struct iovec *iov,

                               size_t start_iov_off,

                               hwaddr target_addr,

                               size_t bytes_to_copy)

{

    size_t curr_off = 0;

    size_t copied = 0;

    while (bytes_to_copy) {

        if (start_iov_off < (curr_off + iov->iov_len)) {

            size_t chunk_len =

                MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);

            cpu_physical_memory_write(target_addr + copied,

                                      iov->iov_base + start_iov_off - curr_off,

                                      chunk_len);

            copied += chunk_len;

            start_iov_off += chunk_len;

            curr_off = start_iov_off;

            bytes_to_copy -= chunk_len;

        } else {

            curr_off += iov->iov_len;

        }

        iov++;

    }

}

static bool

vmxnet3_indicate_packet(VMXNET3State *s)

{

    struct Vmxnet3_RxDesc rxd;

    bool is_head = true;

    uint32_t rxd_idx;

    uint32_t rx_ridx = 0;

    struct Vmxnet3_RxCompDesc rxcd;

    uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;

    hwaddr new_rxcd_pa = 0;

    hwaddr ready_rxcd_pa = 0;

    struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);

    size_t bytes_copied = 0;

    size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);

    uint16_t num_frags = 0;

    size_t chunk_size;

    vmxnet_rx_pkt_dump(s->rx_pkt);

    while (bytes_left > 0) {

        /* cannot add more frags to packet */

        if (num_frags == s->max_rx_frags) {

            break;

        }

        new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);

        if (!new_rxcd_pa) {

            break;

        }

        if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {

            break;

        }

        chunk_size = MIN(bytes_left, rxd.len);

        vmxnet3_physical_memory_writev(data, bytes_copied,

                                       le64_to_cpu(rxd.addr), chunk_size);

        bytes_copied += chunk_size;

        bytes_left -= chunk_size;

        vmxnet3_dump_rx_descr(&rxd);

        if (0 != ready_rxcd_pa) {

            cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));

        }

        memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));

        rxcd.rxdIdx = rxd_idx;

        rxcd.len = chunk_size;

        rxcd.sop = is_head;

        rxcd.gen = new_rxcd_gen;

        rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;

        if (0 == bytes_left) {

            vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);

        }

        VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "

                  "sop %d csum_correct %lu",

                  (unsigned long) rx_ridx,

                  (unsigned long) rxcd.rxdIdx,

                  (unsigned long) rxcd.len,

                  (int) rxcd.sop,

                  (unsigned long) rxcd.tuc);

        is_head = false;

        ready_rxcd_pa = new_rxcd_pa;

        new_rxcd_pa = 0;

        num_frags++;

    }

    if (0 != ready_rxcd_pa) {

        rxcd.eop = 1;

        rxcd.err = (0 != bytes_left);

        cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));

        /* Flush RX descriptor changes */

        smp_wmb();

    }

    if (0 != new_rxcd_pa) {

        vmxnet3_revert_rxc_descr(s, RXQ_IDX);

    }

    vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);

    if (bytes_left == 0) {

        vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);

        return true;

    } else if (num_frags == s->max_rx_frags) {

        vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);

        return false;

    } else {

        vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,

                                        VMXNET3_PKT_STATUS_OUT_OF_BUF);

        return false;

    }

}

static void

vmxnet3_io_bar0_write(void *opaque, hwaddr addr,

                      uint64_t val, unsigned size)

{

    VMXNET3State *s = opaque;

    if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,

                        VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {

        int tx_queue_idx =

            VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,

                                     VMXNET3_REG_ALIGN);

        assert(tx_queue_idx <= s->txq_num);

        vmxnet3_process_tx_queue(s, tx_queue_idx);

        return;

    }

    if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,

                        VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {

        int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,

                                         VMXNET3_REG_ALIGN);

        VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);

        vmxnet3_on_interrupt_mask_changed(s, l, val);

        return;

    }

    if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,

                        VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||

       VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,

                        VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {

        return;

    }

    VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",

              (uint64_t) addr, val, size);

}

static uint64_t

vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)

{

    if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,

                        VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {

        assert(false);

    }

    VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);

    return 0;

}

static void vmxnet3_reset_interrupt_states(VMXNET3State *s)

{

    int i;

    for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {

        s->interrupt_states[i].is_asserted = false;

        s->interrupt_states[i].is_pending = false;

        s->interrupt_states[i].is_masked = true;

    }

}

static void vmxnet3_reset_mac(VMXNET3State *s)

{

    memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));

    VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));

}

static void vmxnet3_deactivate_device(VMXNET3State *s)

{

    VMW_CBPRN("Deactivating vmxnet3...");

    s->device_active = false;

}

static void vmxnet3_reset(VMXNET3State *s)

{

    VMW_CBPRN("Resetting vmxnet3...");

    vmxnet3_deactivate_device(s);

    vmxnet3_reset_interrupt_states(s);

    vmxnet_tx_pkt_reset(s->tx_pkt);

    s->drv_shmem = 0;

    s->tx_sop = true;

    s->skip_current_tx_pkt = false;

}

static void vmxnet3_update_rx_mode(VMXNET3State *s)

{

    s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,

                                           devRead.rxFilterConf.rxMode);

    VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);

}

static void vmxnet3_update_vlan_filters(VMXNET3State *s)

{

    int i;

    /* Copy configuration from shared memory */

    VMXNET3_READ_DRV_SHARED(s->drv_shmem,

                            devRead.rxFilterConf.vfTable,

                            s->vlan_table,

                            sizeof(s->vlan_table));

    /* Invert byte order when needed */

    for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {

        s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);

    }

    /* Dump configuration for debugging purposes */

    VMW_CFPRN("Configured VLANs:");

    for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {

        if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {

            VMW_CFPRN("\tVLAN %d is present", i);

        }

    }

}

static void vmxnet3_update_mcast_filters(VMXNET3State *s)

{

    uint16_t list_bytes =

        VMXNET3_READ_DRV_SHARED16(s->drv_shmem,

                                  devRead.rxFilterConf.mfTableLen);

    s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);

    s->mcast_list = g_realloc(s->mcast_list, list_bytes);

    if (NULL == s->mcast_list) {

        if (0 == s->mcast_list_len) {

            VMW_CFPRN("Current multicast list is empty");

        } else {

            VMW_ERPRN("Failed to allocate multicast list of %d elements",

                      s->mcast_list_len);

        }

        s->mcast_list_len = 0;

    } else {

        int i;

        hwaddr mcast_list_pa =

            VMXNET3_READ_DRV_SHARED64(s->drv_shmem,

                                      devRead.rxFilterConf.mfTablePA);

        cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);

        VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);

        for (i = 0; i < s->mcast_list_len; i++) {

            VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));

        }

    }

}

static void vmxnet3_setup_rx_filtering(VMXNET3State *s)

{

    vmxnet3_update_rx_mode(s);

    vmxnet3_update_vlan_filters(s);

    vmxnet3_update_mcast_filters(s);

}

static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)

{

    uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);

    VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);

    return interrupt_mode;

}

static void vmxnet3_fill_stats(VMXNET3State *s)

{

    int i;

    for (i = 0; i < s->txq_num; i++) {

        cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,

                                  &s->txq_descr[i].txq_stats,

                                  sizeof(s->txq_descr[i].txq_stats));

    }

    for (i = 0; i < s->rxq_num; i++) {

        cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,

                                  &s->rxq_descr[i].rxq_stats,

                                  sizeof(s->rxq_descr[i].rxq_stats));

    }

}

static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)

{

    struct Vmxnet3_GOSInfo gos;

    VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,

                            &gos, sizeof(gos));

    s->rx_packets_compound =

        (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;

    VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);

}

static void

vmxnet3_dump_conf_descr(const char *name,

                        struct Vmxnet3_VariableLenConfDesc *pm_descr)

{

    VMW_CFPRN("%s descriptor dump: Version %u, Length %u",

              name, pm_descr->confVer, pm_descr->confLen);

};

static void vmxnet3_update_pm_state(VMXNET3State *s)

{

    struct Vmxnet3_VariableLenConfDesc pm_descr;

    pm_descr.confLen =

        VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);

    pm_descr.confVer =

        VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);

    pm_descr.confPA =

        VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);

    vmxnet3_dump_conf_descr("PM State", &pm_descr);

}

static void vmxnet3_update_features(VMXNET3State *s)

{

    uint32_t guest_features;

    int rxcso_supported;

    guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,

                                               devRead.misc.uptFeatures);

    rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);

    s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);

    s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);

    VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",

              s->lro_supported, rxcso_supported,

              s->rx_vlan_stripping);

    if (s->peer_has_vhdr) {

        tap_set_offload(qemu_get_queue(s->nic)->peer,

                        rxcso_supported,

                        s->lro_supported,

                        s->lro_supported,

                        0,

                        0);

    }

}

static void vmxnet3_activate_device(VMXNET3State *s)

{

    int i;

    static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;

    hwaddr qdescr_table_pa;

    uint64_t pa;

    uint32_t size;

    /* Verify configuration consistency */

    if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {

        VMW_ERPRN("Device configuration received from driver is invalid");

        return;

    }

    vmxnet3_adjust_by_guest_type(s);

    vmxnet3_update_features(s);

    vmxnet3_update_pm_state(s);

    vmxnet3_setup_rx_filtering(s);

    /* Cache fields from shared memory */

    s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);

    VMW_CFPRN("MTU is %u", s->mtu);

    s->max_rx_frags =

        VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);

    if (s->max_rx_frags == 0) {

        s->max_rx_frags = 1;

    }

    VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);

    s->event_int_idx =

        VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);

    VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);

    s->auto_int_masking =

        VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);

    VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);

    s->txq_num =

        VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);

    s->rxq_num =

        VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);

    VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);

    assert(s->txq_num <= VMXNET3_DEVICE_MAX_TX_QUEUES);

    qdescr_table_pa =

        VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);

    VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);

    /*

     * Worst-case scenario is a packet that holds all TX rings space so

     * we calculate total size of all TX rings for max TX fragments number

     */

    s->max_tx_frags = 0;

    /* TX queues */

    for (i = 0; i < s->txq_num; i++) {

        hwaddr qdescr_pa =

            qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);

        /* Read interrupt number for this TX queue */

        s->txq_descr[i].intr_idx =

            VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);

        VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);

        /* Read rings memory locations for TX queues */

        pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);

        size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);

        vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,

                          sizeof(struct Vmxnet3_TxDesc), false);

        VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);

        s->max_tx_frags += size;

        /* TXC ring */

        pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);

        size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);

        vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,

                          sizeof(struct Vmxnet3_TxCompDesc), true);

        VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);