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/*
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* QEMU i440FX/PIIX3 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/i386/pc.h" |
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#include "hw/pci/pci.h" |
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#include "hw/pci/pci_host.h" |
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#include "hw/isa/isa.h" |
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#include "hw/sysbus.h" |
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#include "qemu/range.h" |
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#include "hw/xen/xen.h" |
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#include "hw/pci-host/pam.h" |
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#include "sysemu/sysemu.h" |
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/*
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* I440FX chipset data sheet.
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* http://download.intel.com/design/chipsets/datashts/29054901.pdf
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*/
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typedef struct I440FXState { |
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PCIHostState parent_obj; |
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} I440FXState; |
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#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
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#define XEN_PIIX_NUM_PIRQS 128ULL |
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#define PIIX_PIRQC 0x60 |
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/*
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* Reset Control Register: PCI-accessible ISA-Compatible Register at address
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* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
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*/
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#define RCR_IOPORT 0xcf9 |
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typedef struct PIIX3State { |
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PCIDevice dev; |
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/*
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* bitmap to track pic levels.
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* The pic level is the logical OR of all the PCI irqs mapped to it
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* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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*
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* PIRQ is mapped to PIC pins, we track it by
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* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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* pic_irq * PIIX_NUM_PIRQS + pirq
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*/
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#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 |
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#error "unable to encode pic state in 64bit in pic_levels." |
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#endif
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uint64_t pic_levels; |
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qemu_irq *pic; |
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/* This member isn't used. Just for save/load compatibility */
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; |
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/* Reset Control Register contents */
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uint8_t rcr; |
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/* IO memory region for Reset Control Register (RCR_IOPORT) */
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MemoryRegion rcr_mem; |
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} PIIX3State; |
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#define TYPE_I440FX_PCI_DEVICE "i440FX" |
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#define I440FX_PCI_DEVICE(obj) \
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OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) |
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struct PCII440FXState {
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PCIDevice dev; |
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MemoryRegion *system_memory; |
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MemoryRegion *pci_address_space; |
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MemoryRegion *ram_memory; |
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MemoryRegion pci_hole; |
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MemoryRegion pci_hole_64bit; |
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PAMMemoryRegion pam_regions[13];
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MemoryRegion smram_region; |
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uint8_t smm_enabled; |
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}; |
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#define I440FX_PAM 0x59 |
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#define I440FX_PAM_SIZE 7 |
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#define I440FX_SMRAM 0x72 |
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static void piix3_set_irq(void *opaque, int pirq, int level); |
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static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
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static void piix3_write_config_xen(PCIDevice *dev, |
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uint32_t address, uint32_t val, int len);
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/* return the global irq number corresponding to a given device irq
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pin. We could also use the bus number to have a more precise
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mapping. */
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static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
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{ |
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int slot_addend;
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slot_addend = (pci_dev->devfn >> 3) - 1; |
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return (pci_intx + slot_addend) & 3; |
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} |
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static void i440fx_update_memory_mappings(PCII440FXState *d) |
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{ |
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int i;
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memory_region_transaction_begin(); |
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for (i = 0; i < 13; i++) { |
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pam_update(&d->pam_regions[i], i, |
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d->dev.config[I440FX_PAM + ((i + 1) / 2)]); |
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} |
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smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled); |
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memory_region_transaction_commit(); |
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} |
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static void i440fx_set_smm(int val, void *arg) |
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{ |
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PCII440FXState *d = arg; |
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memory_region_transaction_begin(); |
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smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM], |
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&d->smram_region); |
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memory_region_transaction_commit(); |
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} |
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static void i440fx_write_config(PCIDevice *dev, |
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uint32_t address, uint32_t val, int len)
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{ |
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PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(dev, address, val, len); |
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if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
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range_covers_byte(address, len, I440FX_SMRAM)) { |
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i440fx_update_memory_mappings(d); |
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} |
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} |
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static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
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{ |
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PCII440FXState *d = opaque; |
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int ret, i;
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ret = pci_device_load(&d->dev, f); |
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if (ret < 0) |
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return ret;
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i440fx_update_memory_mappings(d); |
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qemu_get_8s(f, &d->smm_enabled); |
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if (version_id == 2) { |
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for (i = 0; i < PIIX_NUM_PIRQS; i++) { |
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qemu_get_be32(f); /* dummy load for compatibility */
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} |
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} |
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return 0; |
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} |
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static int i440fx_post_load(void *opaque, int version_id) |
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{ |
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PCII440FXState *d = opaque; |
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i440fx_update_memory_mappings(d); |
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return 0; |
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} |
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static const VMStateDescription vmstate_i440fx = { |
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.name = "I440FX",
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 1,
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.load_state_old = i440fx_load_old, |
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.post_load = i440fx_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, PCII440FXState), |
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VMSTATE_UINT8(smm_enabled, PCII440FXState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int i440fx_pcihost_initfn(SysBusDevice *dev) |
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{ |
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PCIHostState *s = PCI_HOST_BRIDGE(dev); |
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memory_region_init_io(&s->conf_mem, NULL, &pci_host_conf_le_ops, s,
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"pci-conf-idx", 4); |
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sysbus_add_io(dev, 0xcf8, &s->conf_mem);
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sysbus_init_ioports(&s->busdev, 0xcf8, 4); |
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memory_region_init_io(&s->data_mem, NULL, &pci_host_data_le_ops, s,
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"pci-conf-data", 4); |
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sysbus_add_io(dev, 0xcfc, &s->data_mem);
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sysbus_init_ioports(&s->busdev, 0xcfc, 4); |
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return 0; |
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} |
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static int i440fx_initfn(PCIDevice *dev) |
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{ |
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PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
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d->dev.config[I440FX_SMRAM] = 0x02;
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cpu_smm_register(&i440fx_set_smm, d); |
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return 0; |
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} |
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static PCIBus *i440fx_common_init(const char *device_name, |
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PCII440FXState **pi440fx_state, |
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int *piix3_devfn,
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ISABus **isa_bus, qemu_irq *pic, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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ram_addr_t ram_size, |
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hwaddr pci_hole_start, |
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hwaddr pci_hole_size, |
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hwaddr pci_hole64_start, |
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hwaddr pci_hole64_size, |
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MemoryRegion *pci_address_space, |
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MemoryRegion *ram_memory) |
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{ |
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DeviceState *dev; |
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PCIBus *b; |
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PCIDevice *d; |
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PCIHostState *s; |
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PIIX3State *piix3; |
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PCII440FXState *f; |
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unsigned i;
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dev = qdev_create(NULL, "i440FX-pcihost"); |
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s = PCI_HOST_BRIDGE(dev); |
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b = pci_bus_new(dev, NULL, pci_address_space,
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address_space_io, 0, TYPE_PCI_BUS);
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s->bus = b; |
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object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
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qdev_init_nofail(dev); |
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d = pci_create_simple(b, 0, device_name);
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*pi440fx_state = I440FX_PCI_DEVICE(d); |
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f = *pi440fx_state; |
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f->system_memory = address_space_mem; |
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f->pci_address_space = pci_address_space; |
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f->ram_memory = ram_memory; |
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memory_region_init_alias(&f->pci_hole, NULL, "pci-hole", f->pci_address_space, |
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pci_hole_start, pci_hole_size); |
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memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); |
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memory_region_init_alias(&f->pci_hole_64bit, NULL, "pci-hole64", |
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f->pci_address_space, |
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pci_hole64_start, pci_hole64_size); |
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if (pci_hole64_size) {
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memory_region_add_subregion(f->system_memory, pci_hole64_start, |
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&f->pci_hole_64bit); |
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} |
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memory_region_init_alias(&f->smram_region, NULL, "smram-region", |
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f->pci_address_space, 0xa0000, 0x20000); |
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memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
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&f->smram_region, 1);
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memory_region_set_enabled(&f->smram_region, false);
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init_pam(f->ram_memory, f->system_memory, f->pci_address_space, |
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&f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
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for (i = 0; i < 12; ++i) { |
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init_pam(f->ram_memory, f->system_memory, f->pci_address_space, |
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&f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
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PAM_EXPAN_SIZE); |
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} |
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/* Xen supports additional interrupt routes from the PCI devices to
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* the IOAPIC: the four pins of each PCI device on the bus are also
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* connected to the IOAPIC directly.
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* These additional routes can be discovered through ACPI. */
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if (xen_enabled()) {
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piix3 = DO_UPCAST(PIIX3State, dev, |
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pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); |
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pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, |
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piix3, XEN_PIIX_NUM_PIRQS); |
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} else {
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piix3 = DO_UPCAST(PIIX3State, dev, |
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pci_create_simple_multifunction(b, -1, true, "PIIX3")); |
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pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, |
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PIIX_NUM_PIRQS); |
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pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
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} |
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piix3->pic = pic; |
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*isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
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*piix3_devfn = piix3->dev.devfn; |
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ram_size = ram_size / 8 / 1024 / 1024; |
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if (ram_size > 255) |
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ram_size = 255;
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(*pi440fx_state)->dev.config[0x57]=ram_size;
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i440fx_update_memory_mappings(f); |
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return b;
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} |
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PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
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ISABus **isa_bus, qemu_irq *pic, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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ram_addr_t ram_size, |
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hwaddr pci_hole_start, |
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hwaddr pci_hole_size, |
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hwaddr pci_hole64_start, |
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hwaddr pci_hole64_size, |
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MemoryRegion *pci_memory, MemoryRegion *ram_memory) |
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|
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{ |
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PCIBus *b; |
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b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE, pi440fx_state, |
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piix3_devfn, isa_bus, pic, |
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address_space_mem, address_space_io, ram_size, |
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pci_hole_start, pci_hole_size, |
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pci_hole64_start, pci_hole64_size, |
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pci_memory, ram_memory); |
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return b;
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} |
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|
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/* PIIX3 PCI to ISA bridge */
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static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
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{ |
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qemu_set_irq(piix3->pic[pic_irq], |
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!!(piix3->pic_levels & |
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(((1ULL << PIIX_NUM_PIRQS) - 1) << |
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(pic_irq * PIIX_NUM_PIRQS)))); |
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} |
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|
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static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
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{ |
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int pic_irq;
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uint64_t mask; |
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pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; |
355 |
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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return;
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} |
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|
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mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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piix3->pic_levels &= ~mask; |
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piix3->pic_levels |= mask * !!level; |
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|
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piix3_set_irq_pic(piix3, pic_irq); |
364 |
} |
365 |
|
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static void piix3_set_irq(void *opaque, int pirq, int level) |
367 |
{ |
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PIIX3State *piix3 = opaque; |
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piix3_set_irq_level(piix3, pirq, level); |
370 |
} |
371 |
|
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static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
373 |
{ |
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PIIX3State *piix3 = opaque; |
375 |
int irq = piix3->dev.config[PIIX_PIRQC + pin];
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PCIINTxRoute route; |
377 |
|
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if (irq < PIIX_NUM_PIC_IRQS) {
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route.mode = PCI_INTX_ENABLED; |
380 |
route.irq = irq; |
381 |
} else {
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route.mode = PCI_INTX_DISABLED; |
383 |
route.irq = -1;
|
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} |
385 |
return route;
|
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} |
387 |
|
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/* irq routing is changed. so rebuild bitmap */
|
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static void piix3_update_irq_levels(PIIX3State *piix3) |
390 |
{ |
391 |
int pirq;
|
392 |
|
393 |
piix3->pic_levels = 0;
|
394 |
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { |
395 |
piix3_set_irq_level(piix3, pirq, |
396 |
pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
397 |
} |
398 |
} |
399 |
|
400 |
static void piix3_write_config(PCIDevice *dev, |
401 |
uint32_t address, uint32_t val, int len)
|
402 |
{ |
403 |
pci_default_write_config(dev, address, val, len); |
404 |
if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { |
405 |
PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); |
406 |
int pic_irq;
|
407 |
|
408 |
pci_bus_fire_intx_routing_notifier(piix3->dev.bus); |
409 |
piix3_update_irq_levels(piix3); |
410 |
for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { |
411 |
piix3_set_irq_pic(piix3, pic_irq); |
412 |
} |
413 |
} |
414 |
} |
415 |
|
416 |
static void piix3_write_config_xen(PCIDevice *dev, |
417 |
uint32_t address, uint32_t val, int len)
|
418 |
{ |
419 |
xen_piix_pci_write_config_client(address, val, len); |
420 |
piix3_write_config(dev, address, val, len); |
421 |
} |
422 |
|
423 |
static void piix3_reset(void *opaque) |
424 |
{ |
425 |
PIIX3State *d = opaque; |
426 |
uint8_t *pci_conf = d->dev.config; |
427 |
|
428 |
pci_conf[0x04] = 0x07; /* master, memory and I/O */ |
429 |
pci_conf[0x05] = 0x00; |
430 |
pci_conf[0x06] = 0x00; |
431 |
pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ |
432 |
pci_conf[0x4c] = 0x4d; |
433 |
pci_conf[0x4e] = 0x03; |
434 |
pci_conf[0x4f] = 0x00; |
435 |
pci_conf[0x60] = 0x80; |
436 |
pci_conf[0x61] = 0x80; |
437 |
pci_conf[0x62] = 0x80; |
438 |
pci_conf[0x63] = 0x80; |
439 |
pci_conf[0x69] = 0x02; |
440 |
pci_conf[0x70] = 0x80; |
441 |
pci_conf[0x76] = 0x0c; |
442 |
pci_conf[0x77] = 0x0c; |
443 |
pci_conf[0x78] = 0x02; |
444 |
pci_conf[0x79] = 0x00; |
445 |
pci_conf[0x80] = 0x00; |
446 |
pci_conf[0x82] = 0x00; |
447 |
pci_conf[0xa0] = 0x08; |
448 |
pci_conf[0xa2] = 0x00; |
449 |
pci_conf[0xa3] = 0x00; |
450 |
pci_conf[0xa4] = 0x00; |
451 |
pci_conf[0xa5] = 0x00; |
452 |
pci_conf[0xa6] = 0x00; |
453 |
pci_conf[0xa7] = 0x00; |
454 |
pci_conf[0xa8] = 0x0f; |
455 |
pci_conf[0xaa] = 0x00; |
456 |
pci_conf[0xab] = 0x00; |
457 |
pci_conf[0xac] = 0x00; |
458 |
pci_conf[0xae] = 0x00; |
459 |
|
460 |
d->pic_levels = 0;
|
461 |
d->rcr = 0;
|
462 |
} |
463 |
|
464 |
static int piix3_post_load(void *opaque, int version_id) |
465 |
{ |
466 |
PIIX3State *piix3 = opaque; |
467 |
piix3_update_irq_levels(piix3); |
468 |
return 0; |
469 |
} |
470 |
|
471 |
static void piix3_pre_save(void *opaque) |
472 |
{ |
473 |
int i;
|
474 |
PIIX3State *piix3 = opaque; |
475 |
|
476 |
for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { |
477 |
piix3->pci_irq_levels_vmstate[i] = |
478 |
pci_bus_get_irq_level(piix3->dev.bus, i); |
479 |
} |
480 |
} |
481 |
|
482 |
static bool piix3_rcr_needed(void *opaque) |
483 |
{ |
484 |
PIIX3State *piix3 = opaque; |
485 |
|
486 |
return (piix3->rcr != 0); |
487 |
} |
488 |
|
489 |
static const VMStateDescription vmstate_piix3_rcr = { |
490 |
.name = "PIIX3/rcr",
|
491 |
.version_id = 1,
|
492 |
.minimum_version_id = 1,
|
493 |
.fields = (VMStateField []) { |
494 |
VMSTATE_UINT8(rcr, PIIX3State), |
495 |
VMSTATE_END_OF_LIST() |
496 |
} |
497 |
}; |
498 |
|
499 |
static const VMStateDescription vmstate_piix3 = { |
500 |
.name = "PIIX3",
|
501 |
.version_id = 3,
|
502 |
.minimum_version_id = 2,
|
503 |
.minimum_version_id_old = 2,
|
504 |
.post_load = piix3_post_load, |
505 |
.pre_save = piix3_pre_save, |
506 |
.fields = (VMStateField[]) { |
507 |
VMSTATE_PCI_DEVICE(dev, PIIX3State), |
508 |
VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
509 |
PIIX_NUM_PIRQS, 3),
|
510 |
VMSTATE_END_OF_LIST() |
511 |
}, |
512 |
.subsections = (VMStateSubsection[]) { |
513 |
{ |
514 |
.vmsd = &vmstate_piix3_rcr, |
515 |
.needed = piix3_rcr_needed, |
516 |
}, |
517 |
{ 0 }
|
518 |
} |
519 |
}; |
520 |
|
521 |
|
522 |
static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) |
523 |
{ |
524 |
PIIX3State *d = opaque; |
525 |
|
526 |
if (val & 4) { |
527 |
qemu_system_reset_request(); |
528 |
return;
|
529 |
} |
530 |
d->rcr = val & 2; /* keep System Reset type only */ |
531 |
} |
532 |
|
533 |
static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) |
534 |
{ |
535 |
PIIX3State *d = opaque; |
536 |
|
537 |
return d->rcr;
|
538 |
} |
539 |
|
540 |
static const MemoryRegionOps rcr_ops = { |
541 |
.read = rcr_read, |
542 |
.write = rcr_write, |
543 |
.endianness = DEVICE_LITTLE_ENDIAN |
544 |
}; |
545 |
|
546 |
static int piix3_initfn(PCIDevice *dev) |
547 |
{ |
548 |
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
549 |
|
550 |
isa_bus_new(DEVICE(d), pci_address_space_io(dev)); |
551 |
|
552 |
memory_region_init_io(&d->rcr_mem, NULL, &rcr_ops, d, "piix3-reset-control", 1); |
553 |
memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, |
554 |
&d->rcr_mem, 1);
|
555 |
|
556 |
qemu_register_reset(piix3_reset, d); |
557 |
return 0; |
558 |
} |
559 |
|
560 |
static void piix3_class_init(ObjectClass *klass, void *data) |
561 |
{ |
562 |
DeviceClass *dc = DEVICE_CLASS(klass); |
563 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
564 |
|
565 |
dc->desc = "ISA bridge";
|
566 |
dc->vmsd = &vmstate_piix3; |
567 |
dc->no_user = 1,
|
568 |
k->no_hotplug = 1;
|
569 |
k->init = piix3_initfn; |
570 |
k->config_write = piix3_write_config; |
571 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
572 |
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
|
573 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; |
574 |
k->class_id = PCI_CLASS_BRIDGE_ISA; |
575 |
} |
576 |
|
577 |
static const TypeInfo piix3_info = { |
578 |
.name = "PIIX3",
|
579 |
.parent = TYPE_PCI_DEVICE, |
580 |
.instance_size = sizeof(PIIX3State),
|
581 |
.class_init = piix3_class_init, |
582 |
}; |
583 |
|
584 |
static void piix3_xen_class_init(ObjectClass *klass, void *data) |
585 |
{ |
586 |
DeviceClass *dc = DEVICE_CLASS(klass); |
587 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
588 |
|
589 |
dc->desc = "ISA bridge";
|
590 |
dc->vmsd = &vmstate_piix3; |
591 |
dc->no_user = 1;
|
592 |
k->no_hotplug = 1;
|
593 |
k->init = piix3_initfn; |
594 |
k->config_write = piix3_write_config_xen; |
595 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
596 |
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
|
597 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; |
598 |
k->class_id = PCI_CLASS_BRIDGE_ISA; |
599 |
}; |
600 |
|
601 |
static const TypeInfo piix3_xen_info = { |
602 |
.name = "PIIX3-xen",
|
603 |
.parent = TYPE_PCI_DEVICE, |
604 |
.instance_size = sizeof(PIIX3State),
|
605 |
.class_init = piix3_xen_class_init, |
606 |
}; |
607 |
|
608 |
static void i440fx_class_init(ObjectClass *klass, void *data) |
609 |
{ |
610 |
DeviceClass *dc = DEVICE_CLASS(klass); |
611 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
612 |
|
613 |
k->no_hotplug = 1;
|
614 |
k->init = i440fx_initfn; |
615 |
k->config_write = i440fx_write_config; |
616 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
617 |
k->device_id = PCI_DEVICE_ID_INTEL_82441; |
618 |
k->revision = 0x02;
|
619 |
k->class_id = PCI_CLASS_BRIDGE_HOST; |
620 |
dc->desc = "Host bridge";
|
621 |
dc->no_user = 1;
|
622 |
dc->vmsd = &vmstate_i440fx; |
623 |
} |
624 |
|
625 |
static const TypeInfo i440fx_info = { |
626 |
.name = TYPE_I440FX_PCI_DEVICE, |
627 |
.parent = TYPE_PCI_DEVICE, |
628 |
.instance_size = sizeof(PCII440FXState),
|
629 |
.class_init = i440fx_class_init, |
630 |
}; |
631 |
|
632 |
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
633 |
{ |
634 |
DeviceClass *dc = DEVICE_CLASS(klass); |
635 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
636 |
|
637 |
k->init = i440fx_pcihost_initfn; |
638 |
dc->fw_name = "pci";
|
639 |
dc->no_user = 1;
|
640 |
} |
641 |
|
642 |
static const TypeInfo i440fx_pcihost_info = { |
643 |
.name = "i440FX-pcihost",
|
644 |
.parent = TYPE_PCI_HOST_BRIDGE, |
645 |
.instance_size = sizeof(I440FXState),
|
646 |
.class_init = i440fx_pcihost_class_init, |
647 |
}; |
648 |
|
649 |
static void i440fx_register_types(void) |
650 |
{ |
651 |
type_register_static(&i440fx_info); |
652 |
type_register_static(&piix3_info); |
653 |
type_register_static(&piix3_xen_info); |
654 |
type_register_static(&i440fx_pcihost_info); |
655 |
} |
656 |
|
657 |
type_init(i440fx_register_types) |