root / hw / ssi / xilinx_spips.c @ 2c9b15ca
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/*
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* QEMU model of the Xilinx Zynq SPI controller
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*
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* Copyright (c) 2012 Peter A. G. Crosthwaite
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/ptimer.h" |
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#include "qemu/log.h" |
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#include "qemu/fifo8.h" |
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#include "hw/ssi.h" |
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#include "qemu/bitops.h" |
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#ifndef XILINX_SPIPS_ERR_DEBUG
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#define XILINX_SPIPS_ERR_DEBUG 0 |
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#endif
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#define DB_PRINT_L(level, ...) do { \ |
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if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \ |
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} \ |
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} while (0); |
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/* config register */
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#define R_CONFIG (0x00 / 4) |
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#define IFMODE (1 << 31) |
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#define ENDIAN (1 << 26) |
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#define MODEFAIL_GEN_EN (1 << 17) |
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#define MAN_START_COM (1 << 16) |
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#define MAN_START_EN (1 << 15) |
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#define MANUAL_CS (1 << 14) |
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#define CS (0xF << 10) |
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#define CS_SHIFT (10) |
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#define PERI_SEL (1 << 9) |
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#define REF_CLK (1 << 8) |
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#define FIFO_WIDTH (3 << 6) |
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#define BAUD_RATE_DIV (7 << 3) |
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#define CLK_PH (1 << 2) |
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#define CLK_POL (1 << 1) |
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#define MODE_SEL (1 << 0) |
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#define R_CONFIG_RSVD (0x7bf40000) |
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|
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/* interrupt mechanism */
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#define R_INTR_STATUS (0x04 / 4) |
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#define R_INTR_EN (0x08 / 4) |
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#define R_INTR_DIS (0x0C / 4) |
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#define R_INTR_MASK (0x10 / 4) |
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#define IXR_TX_FIFO_UNDERFLOW (1 << 6) |
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#define IXR_RX_FIFO_FULL (1 << 5) |
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#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) |
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#define IXR_TX_FIFO_FULL (1 << 3) |
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#define IXR_TX_FIFO_NOT_FULL (1 << 2) |
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#define IXR_TX_FIFO_MODE_FAIL (1 << 1) |
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#define IXR_RX_FIFO_OVERFLOW (1 << 0) |
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#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) |
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#define R_EN (0x14 / 4) |
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#define R_DELAY (0x18 / 4) |
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#define R_TX_DATA (0x1C / 4) |
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#define R_RX_DATA (0x20 / 4) |
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#define R_SLAVE_IDLE_COUNT (0x24 / 4) |
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#define R_TX_THRES (0x28 / 4) |
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#define R_RX_THRES (0x2C / 4) |
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#define R_TXD1 (0x80 / 4) |
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#define R_TXD2 (0x84 / 4) |
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#define R_TXD3 (0x88 / 4) |
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#define R_LQSPI_CFG (0xa0 / 4) |
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#define R_LQSPI_CFG_RESET 0x03A002EB |
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#define LQSPI_CFG_LQ_MODE (1 << 31) |
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#define LQSPI_CFG_TWO_MEM (1 << 30) |
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#define LQSPI_CFG_SEP_BUS (1 << 30) |
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#define LQSPI_CFG_U_PAGE (1 << 28) |
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#define LQSPI_CFG_MODE_EN (1 << 25) |
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#define LQSPI_CFG_MODE_WIDTH 8 |
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#define LQSPI_CFG_MODE_SHIFT 16 |
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#define LQSPI_CFG_DUMMY_WIDTH 3 |
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#define LQSPI_CFG_DUMMY_SHIFT 8 |
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#define LQSPI_CFG_INST_CODE 0xFF |
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#define R_LQSPI_STS (0xA4 / 4) |
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#define LQSPI_STS_WR_RECVD (1 << 1) |
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#define R_MOD_ID (0xFC / 4) |
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#define R_MAX (R_MOD_ID+1) |
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/* size of TXRX FIFOs */
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#define RXFF_A 32 |
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#define TXFF_A 32 |
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#define RXFF_A_Q (64 * 4) |
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#define TXFF_A_Q (64 * 4) |
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/* 16MB per linear region */
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#define LQSPI_ADDRESS_BITS 24 |
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/* Bite off 4k chunks at a time */
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#define LQSPI_CACHE_SIZE 1024 |
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#define SNOOP_CHECKING 0xFF |
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#define SNOOP_NONE 0xFE |
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#define SNOOP_STRIPING 0 |
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typedef enum { |
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READ = 0x3,
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FAST_READ = 0xb,
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DOR = 0x3b,
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QOR = 0x6b,
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DIOR = 0xbb,
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QIOR = 0xeb,
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PP = 0x2,
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DPP = 0xa2,
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QPP = 0x32,
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} FlashCMD; |
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typedef struct { |
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SysBusDevice parent_obj; |
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MemoryRegion iomem; |
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MemoryRegion mmlqspi; |
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qemu_irq irq; |
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int irqline;
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uint8_t num_cs; |
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uint8_t num_busses; |
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uint8_t snoop_state; |
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qemu_irq *cs_lines; |
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SSIBus **spi; |
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Fifo8 rx_fifo; |
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Fifo8 tx_fifo; |
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uint8_t num_txrx_bytes; |
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uint32_t regs[R_MAX]; |
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} XilinxSPIPS; |
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typedef struct { |
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XilinxSPIPS parent_obj; |
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uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; |
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hwaddr lqspi_cached_addr; |
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} XilinxQSPIPS; |
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typedef struct XilinxSPIPSClass { |
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SysBusDeviceClass parent_class; |
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const MemoryRegionOps *reg_ops;
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uint32_t rx_fifo_size; |
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uint32_t tx_fifo_size; |
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} XilinxSPIPSClass; |
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#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" |
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#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" |
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#define XILINX_SPIPS(obj) \
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OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) |
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#define XILINX_SPIPS_CLASS(klass) \
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OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) |
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#define XILINX_SPIPS_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) |
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#define XILINX_QSPIPS(obj) \
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OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) |
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static inline int num_effective_busses(XilinxSPIPS *s) |
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{ |
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return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
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s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
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} |
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static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) |
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{ |
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return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS |
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|| !fifo8_is_empty(&s->tx_fifo)); |
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} |
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static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) |
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{ |
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int i, j;
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bool found = false; |
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int field = s->regs[R_CONFIG] >> CS_SHIFT;
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for (i = 0; i < s->num_cs; i++) { |
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for (j = 0; j < num_effective_busses(s); j++) { |
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int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
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int cs_to_set = (j * s->num_cs + i + upage) %
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(s->num_cs * s->num_busses); |
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if (xilinx_spips_cs_is_set(s, i, field) && !found) {
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DB_PRINT_L(0, "selecting slave %d\n", i); |
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qemu_set_irq(s->cs_lines[cs_to_set], 0);
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} else {
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DB_PRINT_L(0, "deselecting slave %d\n", i); |
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qemu_set_irq(s->cs_lines[cs_to_set], 1);
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} |
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} |
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if (xilinx_spips_cs_is_set(s, i, field)) {
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found = true;
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} |
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} |
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if (!found) {
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s->snoop_state = SNOOP_CHECKING; |
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DB_PRINT_L(1, "moving to snoop check state\n"); |
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} |
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} |
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static void xilinx_spips_update_ixr(XilinxSPIPS *s) |
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{ |
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if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
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return;
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} |
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/* These are set/cleared as they occur */
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s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | |
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IXR_TX_FIFO_MODE_FAIL); |
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/* these are pure functions of fifo state, set them here */
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s->regs[R_INTR_STATUS] |= |
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(fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
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(s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
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(fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
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(s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
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/* drive external interrupt pin */
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int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
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IXR_ALL); |
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if (new_irqline != s->irqline) {
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s->irqline = new_irqline; |
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qemu_set_irq(s->irq, s->irqline); |
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} |
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} |
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static void xilinx_spips_reset(DeviceState *d) |
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{ |
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XilinxSPIPS *s = XILINX_SPIPS(d); |
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int i;
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for (i = 0; i < R_MAX; i++) { |
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s->regs[i] = 0;
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} |
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fifo8_reset(&s->rx_fifo); |
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fifo8_reset(&s->rx_fifo); |
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/* non zero resets */
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s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; |
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s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
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s->regs[R_TX_THRES] = 1;
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s->regs[R_RX_THRES] = 1;
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/* FIXME: move magic number definition somewhere sensible */
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s->regs[R_MOD_ID] = 0x01090106;
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s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; |
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s->snoop_state = SNOOP_CHECKING; |
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xilinx_spips_update_ixr(s); |
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xilinx_spips_update_cs_lines(s); |
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} |
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/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB)
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* column wise (from element 0 to N-1). num is the length of x, and dir
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* reverses the direction of the transform. Best illustrated by example:
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* Each digit in the below array is a single bit (num == 3):
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*
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* {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, }
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* { hgfedcba, } { GDAfc741, }
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* { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }}
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*/
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static inline void stripe8(uint8_t *x, int num, bool dir) |
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{ |
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uint8_t r[num]; |
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memset(r, 0, sizeof(uint8_t) * num); |
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int idx[2] = {0, 0}; |
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int bit[2] = {0, 0}; |
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int d = dir;
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for (idx[0] = 0; idx[0] < num; ++idx[0]) { |
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for (bit[0] = 0; bit[0] < 8; ++bit[0]) { |
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r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; |
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idx[1] = (idx[1] + 1) % num; |
301 |
if (!idx[1]) { |
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bit[1]++;
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} |
304 |
} |
305 |
} |
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memcpy(x, r, sizeof(uint8_t) * num);
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} |
308 |
|
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static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) |
310 |
{ |
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int debug_level = 0; |
312 |
|
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for (;;) {
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int i;
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uint8_t tx = 0;
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uint8_t tx_rx[num_effective_busses(s)]; |
317 |
|
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if (fifo8_is_empty(&s->tx_fifo)) {
|
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if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
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s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; |
321 |
} |
322 |
xilinx_spips_update_ixr(s); |
323 |
return;
|
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} else if (s->snoop_state == SNOOP_STRIPING) { |
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for (i = 0; i < num_effective_busses(s); ++i) { |
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tx_rx[i] = fifo8_pop(&s->tx_fifo); |
327 |
} |
328 |
stripe8(tx_rx, num_effective_busses(s), false);
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} else {
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tx = fifo8_pop(&s->tx_fifo); |
331 |
for (i = 0; i < num_effective_busses(s); ++i) { |
332 |
tx_rx[i] = tx; |
333 |
} |
334 |
} |
335 |
|
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for (i = 0; i < num_effective_busses(s); ++i) { |
337 |
DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
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tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); |
339 |
DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
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} |
341 |
|
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if (fifo8_is_full(&s->rx_fifo)) {
|
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s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; |
344 |
DB_PRINT_L(0, "rx FIFO overflow"); |
345 |
} else if (s->snoop_state == SNOOP_STRIPING) { |
346 |
stripe8(tx_rx, num_effective_busses(s), true);
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for (i = 0; i < num_effective_busses(s); ++i) { |
348 |
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); |
349 |
} |
350 |
} else {
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fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
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} |
353 |
|
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DB_PRINT_L(debug_level, "initial snoop state: %x\n",
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(unsigned)s->snoop_state);
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switch (s->snoop_state) {
|
357 |
case (SNOOP_CHECKING):
|
358 |
switch (tx) { /* new instruction code */ |
359 |
case READ: /* 3 address bytes, no dummy bytes/cycles */ |
360 |
case PP:
|
361 |
case DPP:
|
362 |
case QPP:
|
363 |
s->snoop_state = 3;
|
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break;
|
365 |
case FAST_READ: /* 3 address bytes, 1 dummy byte */ |
366 |
case DOR:
|
367 |
case QOR:
|
368 |
case DIOR: /* FIXME: these vary between vendor - set to spansion */ |
369 |
s->snoop_state = 4;
|
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break;
|
371 |
case QIOR: /* 3 address bytes, 2 dummy bytes */ |
372 |
s->snoop_state = 6;
|
373 |
break;
|
374 |
default:
|
375 |
s->snoop_state = SNOOP_NONE; |
376 |
} |
377 |
break;
|
378 |
case (SNOOP_STRIPING):
|
379 |
case (SNOOP_NONE):
|
380 |
/* Once we hit the boring stuff - squelch debug noise */
|
381 |
if (!debug_level) {
|
382 |
DB_PRINT_L(0, "squelching debug info ....\n"); |
383 |
debug_level = 1;
|
384 |
} |
385 |
break;
|
386 |
default:
|
387 |
s->snoop_state--; |
388 |
} |
389 |
DB_PRINT_L(debug_level, "final snoop state: %x\n",
|
390 |
(unsigned)s->snoop_state);
|
391 |
} |
392 |
} |
393 |
|
394 |
static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) |
395 |
{ |
396 |
int i;
|
397 |
|
398 |
for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { |
399 |
value[i] = fifo8_pop(&s->rx_fifo); |
400 |
} |
401 |
} |
402 |
|
403 |
static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, |
404 |
unsigned size)
|
405 |
{ |
406 |
XilinxSPIPS *s = opaque; |
407 |
uint32_t mask = ~0;
|
408 |
uint32_t ret; |
409 |
uint8_t rx_buf[4];
|
410 |
|
411 |
addr >>= 2;
|
412 |
switch (addr) {
|
413 |
case R_CONFIG:
|
414 |
mask = ~(R_CONFIG_RSVD | MAN_START_COM); |
415 |
break;
|
416 |
case R_INTR_STATUS:
|
417 |
ret = s->regs[addr] & IXR_ALL; |
418 |
s->regs[addr] = 0;
|
419 |
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); |
420 |
return ret;
|
421 |
case R_INTR_MASK:
|
422 |
mask = IXR_ALL; |
423 |
break;
|
424 |
case R_EN:
|
425 |
mask = 0x1;
|
426 |
break;
|
427 |
case R_SLAVE_IDLE_COUNT:
|
428 |
mask = 0xFF;
|
429 |
break;
|
430 |
case R_MOD_ID:
|
431 |
mask = 0x01FFFFFF;
|
432 |
break;
|
433 |
case R_INTR_EN:
|
434 |
case R_INTR_DIS:
|
435 |
case R_TX_DATA:
|
436 |
mask = 0;
|
437 |
break;
|
438 |
case R_RX_DATA:
|
439 |
memset(rx_buf, 0, sizeof(rx_buf)); |
440 |
rx_data_bytes(s, rx_buf, s->num_txrx_bytes); |
441 |
ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) |
442 |
: cpu_to_le32(*(uint32_t *)rx_buf); |
443 |
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); |
444 |
xilinx_spips_update_ixr(s); |
445 |
return ret;
|
446 |
} |
447 |
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, |
448 |
s->regs[addr] & mask); |
449 |
return s->regs[addr] & mask;
|
450 |
|
451 |
} |
452 |
|
453 |
static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) |
454 |
{ |
455 |
int i;
|
456 |
for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { |
457 |
if (s->regs[R_CONFIG] & ENDIAN) {
|
458 |
fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
|
459 |
value <<= 8;
|
460 |
} else {
|
461 |
fifo8_push(&s->tx_fifo, (uint8_t)value); |
462 |
value >>= 8;
|
463 |
} |
464 |
} |
465 |
} |
466 |
|
467 |
static void xilinx_spips_write(void *opaque, hwaddr addr, |
468 |
uint64_t value, unsigned size)
|
469 |
{ |
470 |
int mask = ~0; |
471 |
int man_start_com = 0; |
472 |
XilinxSPIPS *s = opaque; |
473 |
|
474 |
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); |
475 |
addr >>= 2;
|
476 |
switch (addr) {
|
477 |
case R_CONFIG:
|
478 |
mask = ~(R_CONFIG_RSVD | MAN_START_COM); |
479 |
if (value & MAN_START_COM) {
|
480 |
man_start_com = 1;
|
481 |
} |
482 |
break;
|
483 |
case R_INTR_STATUS:
|
484 |
mask = IXR_ALL; |
485 |
s->regs[R_INTR_STATUS] &= ~(mask & value); |
486 |
goto no_reg_update;
|
487 |
case R_INTR_DIS:
|
488 |
mask = IXR_ALL; |
489 |
s->regs[R_INTR_MASK] &= ~(mask & value); |
490 |
goto no_reg_update;
|
491 |
case R_INTR_EN:
|
492 |
mask = IXR_ALL; |
493 |
s->regs[R_INTR_MASK] |= mask & value; |
494 |
goto no_reg_update;
|
495 |
case R_EN:
|
496 |
mask = 0x1;
|
497 |
break;
|
498 |
case R_SLAVE_IDLE_COUNT:
|
499 |
mask = 0xFF;
|
500 |
break;
|
501 |
case R_RX_DATA:
|
502 |
case R_INTR_MASK:
|
503 |
case R_MOD_ID:
|
504 |
mask = 0;
|
505 |
break;
|
506 |
case R_TX_DATA:
|
507 |
tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); |
508 |
goto no_reg_update;
|
509 |
case R_TXD1:
|
510 |
tx_data_bytes(s, (uint32_t)value, 1);
|
511 |
goto no_reg_update;
|
512 |
case R_TXD2:
|
513 |
tx_data_bytes(s, (uint32_t)value, 2);
|
514 |
goto no_reg_update;
|
515 |
case R_TXD3:
|
516 |
tx_data_bytes(s, (uint32_t)value, 3);
|
517 |
goto no_reg_update;
|
518 |
} |
519 |
s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); |
520 |
no_reg_update:
|
521 |
xilinx_spips_update_cs_lines(s); |
522 |
if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
|
523 |
(fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { |
524 |
xilinx_spips_flush_txfifo(s); |
525 |
} |
526 |
xilinx_spips_update_cs_lines(s); |
527 |
xilinx_spips_update_ixr(s); |
528 |
} |
529 |
|
530 |
static const MemoryRegionOps spips_ops = { |
531 |
.read = xilinx_spips_read, |
532 |
.write = xilinx_spips_write, |
533 |
.endianness = DEVICE_LITTLE_ENDIAN, |
534 |
}; |
535 |
|
536 |
static void xilinx_qspips_write(void *opaque, hwaddr addr, |
537 |
uint64_t value, unsigned size)
|
538 |
{ |
539 |
XilinxQSPIPS *q = XILINX_QSPIPS(opaque); |
540 |
|
541 |
xilinx_spips_write(opaque, addr, value, size); |
542 |
addr >>= 2;
|
543 |
|
544 |
if (addr == R_LQSPI_CFG) {
|
545 |
q->lqspi_cached_addr = ~0ULL;
|
546 |
} |
547 |
} |
548 |
|
549 |
static const MemoryRegionOps qspips_ops = { |
550 |
.read = xilinx_spips_read, |
551 |
.write = xilinx_qspips_write, |
552 |
.endianness = DEVICE_LITTLE_ENDIAN, |
553 |
}; |
554 |
|
555 |
#define LQSPI_CACHE_SIZE 1024 |
556 |
|
557 |
static uint64_t
|
558 |
lqspi_read(void *opaque, hwaddr addr, unsigned int size) |
559 |
{ |
560 |
int i;
|
561 |
XilinxQSPIPS *q = opaque; |
562 |
XilinxSPIPS *s = opaque; |
563 |
uint32_t ret; |
564 |
|
565 |
if (addr >= q->lqspi_cached_addr &&
|
566 |
addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
|
567 |
uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; |
568 |
ret = cpu_to_le32(*(uint32_t *)retp); |
569 |
DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, |
570 |
(unsigned)ret);
|
571 |
return ret;
|
572 |
} else {
|
573 |
int flash_addr = (addr / num_effective_busses(s));
|
574 |
int slave = flash_addr >> LQSPI_ADDRESS_BITS;
|
575 |
int cache_entry = 0; |
576 |
uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; |
577 |
|
578 |
s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; |
579 |
s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
|
580 |
|
581 |
DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); |
582 |
|
583 |
fifo8_reset(&s->tx_fifo); |
584 |
fifo8_reset(&s->rx_fifo); |
585 |
|
586 |
/* instruction */
|
587 |
DB_PRINT_L(0, "pushing read instruction: %02x\n", |
588 |
(unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
|
589 |
LQSPI_CFG_INST_CODE)); |
590 |
fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); |
591 |
/* read address */
|
592 |
DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); |
593 |
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
|
594 |
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
|
595 |
fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); |
596 |
/* mode bits */
|
597 |
if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
|
598 |
fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], |
599 |
LQSPI_CFG_MODE_SHIFT, |
600 |
LQSPI_CFG_MODE_WIDTH)); |
601 |
} |
602 |
/* dummy bytes */
|
603 |
for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, |
604 |
LQSPI_CFG_DUMMY_WIDTH)); ++i) { |
605 |
DB_PRINT_L(0, "pushing dummy byte\n"); |
606 |
fifo8_push(&s->tx_fifo, 0);
|
607 |
} |
608 |
xilinx_spips_update_cs_lines(s); |
609 |
xilinx_spips_flush_txfifo(s); |
610 |
fifo8_reset(&s->rx_fifo); |
611 |
|
612 |
DB_PRINT_L(0, "starting QSPI data read\n"); |
613 |
|
614 |
while (cache_entry < LQSPI_CACHE_SIZE) {
|
615 |
for (i = 0; i < 64; ++i) { |
616 |
tx_data_bytes(s, 0, 1); |
617 |
} |
618 |
xilinx_spips_flush_txfifo(s); |
619 |
for (i = 0; i < 64; ++i) { |
620 |
rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1);
|
621 |
} |
622 |
} |
623 |
|
624 |
s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; |
625 |
s->regs[R_LQSPI_STS] |= u_page_save; |
626 |
xilinx_spips_update_cs_lines(s); |
627 |
|
628 |
q->lqspi_cached_addr = flash_addr * num_effective_busses(s); |
629 |
return lqspi_read(opaque, addr, size);
|
630 |
} |
631 |
} |
632 |
|
633 |
static const MemoryRegionOps lqspi_ops = { |
634 |
.read = lqspi_read, |
635 |
.endianness = DEVICE_NATIVE_ENDIAN, |
636 |
.valid = { |
637 |
.min_access_size = 1,
|
638 |
.max_access_size = 4
|
639 |
} |
640 |
}; |
641 |
|
642 |
static void xilinx_spips_realize(DeviceState *dev, Error **errp) |
643 |
{ |
644 |
XilinxSPIPS *s = XILINX_SPIPS(dev); |
645 |
SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
646 |
XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); |
647 |
int i;
|
648 |
|
649 |
DB_PRINT_L(0, "realized spips\n"); |
650 |
|
651 |
s->spi = g_new(SSIBus *, s->num_busses); |
652 |
for (i = 0; i < s->num_busses; ++i) { |
653 |
char bus_name[16]; |
654 |
snprintf(bus_name, 16, "spi%d", i); |
655 |
s->spi[i] = ssi_create_bus(dev, bus_name); |
656 |
} |
657 |
|
658 |
s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); |
659 |
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
|
660 |
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
|
661 |
sysbus_init_irq(sbd, &s->irq); |
662 |
for (i = 0; i < s->num_cs * s->num_busses; ++i) { |
663 |
sysbus_init_irq(sbd, &s->cs_lines[i]); |
664 |
} |
665 |
|
666 |
memory_region_init_io(&s->iomem, NULL, xsc->reg_ops, s, "spi", R_MAX*4); |
667 |
sysbus_init_mmio(sbd, &s->iomem); |
668 |
|
669 |
s->irqline = -1;
|
670 |
|
671 |
fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); |
672 |
fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); |
673 |
} |
674 |
|
675 |
static void xilinx_qspips_realize(DeviceState *dev, Error **errp) |
676 |
{ |
677 |
XilinxSPIPS *s = XILINX_SPIPS(dev); |
678 |
XilinxQSPIPS *q = XILINX_QSPIPS(dev); |
679 |
SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
680 |
|
681 |
DB_PRINT_L(0, "realized qspips\n"); |
682 |
|
683 |
s->num_busses = 2;
|
684 |
s->num_cs = 2;
|
685 |
s->num_txrx_bytes = 4;
|
686 |
|
687 |
xilinx_spips_realize(dev, errp); |
688 |
memory_region_init_io(&s->mmlqspi, NULL, &lqspi_ops, s, "lqspi", |
689 |
(1 << LQSPI_ADDRESS_BITS) * 2); |
690 |
sysbus_init_mmio(sbd, &s->mmlqspi); |
691 |
|
692 |
q->lqspi_cached_addr = ~0ULL;
|
693 |
} |
694 |
|
695 |
static int xilinx_spips_post_load(void *opaque, int version_id) |
696 |
{ |
697 |
xilinx_spips_update_ixr((XilinxSPIPS *)opaque); |
698 |
xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); |
699 |
return 0; |
700 |
} |
701 |
|
702 |
static const VMStateDescription vmstate_xilinx_spips = { |
703 |
.name = "xilinx_spips",
|
704 |
.version_id = 2,
|
705 |
.minimum_version_id = 2,
|
706 |
.minimum_version_id_old = 2,
|
707 |
.post_load = xilinx_spips_post_load, |
708 |
.fields = (VMStateField[]) { |
709 |
VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), |
710 |
VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), |
711 |
VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX), |
712 |
VMSTATE_UINT8(snoop_state, XilinxSPIPS), |
713 |
VMSTATE_END_OF_LIST() |
714 |
} |
715 |
}; |
716 |
|
717 |
static Property xilinx_spips_properties[] = {
|
718 |
DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), |
719 |
DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), |
720 |
DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), |
721 |
DEFINE_PROP_END_OF_LIST(), |
722 |
}; |
723 |
|
724 |
static void xilinx_qspips_class_init(ObjectClass *klass, void * data) |
725 |
{ |
726 |
DeviceClass *dc = DEVICE_CLASS(klass); |
727 |
XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); |
728 |
|
729 |
dc->realize = xilinx_qspips_realize; |
730 |
xsc->reg_ops = &qspips_ops; |
731 |
xsc->rx_fifo_size = RXFF_A_Q; |
732 |
xsc->tx_fifo_size = TXFF_A_Q; |
733 |
} |
734 |
|
735 |
static void xilinx_spips_class_init(ObjectClass *klass, void *data) |
736 |
{ |
737 |
DeviceClass *dc = DEVICE_CLASS(klass); |
738 |
XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); |
739 |
|
740 |
dc->realize = xilinx_spips_realize; |
741 |
dc->reset = xilinx_spips_reset; |
742 |
dc->props = xilinx_spips_properties; |
743 |
dc->vmsd = &vmstate_xilinx_spips; |
744 |
|
745 |
xsc->reg_ops = &spips_ops; |
746 |
xsc->rx_fifo_size = RXFF_A; |
747 |
xsc->tx_fifo_size = TXFF_A; |
748 |
} |
749 |
|
750 |
static const TypeInfo xilinx_spips_info = { |
751 |
.name = TYPE_XILINX_SPIPS, |
752 |
.parent = TYPE_SYS_BUS_DEVICE, |
753 |
.instance_size = sizeof(XilinxSPIPS),
|
754 |
.class_init = xilinx_spips_class_init, |
755 |
.class_size = sizeof(XilinxSPIPSClass),
|
756 |
}; |
757 |
|
758 |
static const TypeInfo xilinx_qspips_info = { |
759 |
.name = TYPE_XILINX_QSPIPS, |
760 |
.parent = TYPE_XILINX_SPIPS, |
761 |
.instance_size = sizeof(XilinxQSPIPS),
|
762 |
.class_init = xilinx_qspips_class_init, |
763 |
}; |
764 |
|
765 |
static void xilinx_spips_register_types(void) |
766 |
{ |
767 |
type_register_static(&xilinx_spips_info); |
768 |
type_register_static(&xilinx_qspips_info); |
769 |
} |
770 |
|
771 |
type_init(xilinx_spips_register_types) |