root / hw / usb / hcd-ehci.c @ 2c9b15ca
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/*
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* QEMU USB EHCI Emulation
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*
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* Copyright(c) 2008 Emutex Ltd. (address@hidden)
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* Copyright(c) 2011-2012 Red Hat, Inc.
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*
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* Red Hat Authors:
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* Gerd Hoffmann <kraxel@redhat.com>
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* Hans de Goede <hdegoede@redhat.com>
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*
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* EHCI project was started by Mark Burkley, with contributions by
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* Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
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* Jan Kiszka and Vincent Palatin contributed bugfixes.
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or(at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/usb/hcd-ehci.h" |
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/* Capability Registers Base Address - section 2.2 */
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#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ |
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#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ |
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#define HCSPARAMS 0x0004 /* 4-bytes, structural params */ |
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#define HCCPARAMS 0x0008 /* 4-bytes, capability params */ |
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#define EECP HCCPARAMS + 1 |
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#define HCSPPORTROUTE1 0x000c |
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#define HCSPPORTROUTE2 0x0010 |
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|
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#define USBCMD 0x0000 |
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#define USBCMD_RUNSTOP (1 << 0) // run / Stop |
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#define USBCMD_HCRESET (1 << 1) // HC Reset |
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#define USBCMD_FLS (3 << 2) // Frame List Size |
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#define USBCMD_FLS_SH 2 // Frame List Size Shift |
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#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable |
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#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable |
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#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell |
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#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset |
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#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count |
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#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable |
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#define USBCMD_ITC (0x7f << 16) // Int Threshold Control |
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#define USBCMD_ITC_SH 16 // Int Threshold Control Shift |
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|
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#define USBSTS 0x0004 |
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#define USBSTS_RO_MASK 0x0000003f |
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#define USBSTS_INT (1 << 0) // USB Interrupt |
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#define USBSTS_ERRINT (1 << 1) // Error Interrupt |
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#define USBSTS_PCD (1 << 2) // Port Change Detect |
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#define USBSTS_FLR (1 << 3) // Frame List Rollover |
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#define USBSTS_HSE (1 << 4) // Host System Error |
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#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance |
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#define USBSTS_HALT (1 << 12) // HC Halted |
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#define USBSTS_REC (1 << 13) // Reclamation |
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#define USBSTS_PSS (1 << 14) // Periodic Schedule Status |
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#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status |
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|
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/*
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* Interrupt enable bits correspond to the interrupt active bits in USBSTS
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* so no need to redefine here.
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*/
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#define USBINTR 0x0008 |
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#define USBINTR_MASK 0x0000003f |
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|
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#define FRINDEX 0x000c |
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#define CTRLDSSEGMENT 0x0010 |
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#define PERIODICLISTBASE 0x0014 |
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#define ASYNCLISTADDR 0x0018 |
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#define ASYNCLISTADDR_MASK 0xffffffe0 |
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|
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#define CONFIGFLAG 0x0040 |
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|
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/*
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* Bits that are reserved or are read-only are masked out of values
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* written to us by software
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*/
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#define PORTSC_RO_MASK 0x007001c0 |
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#define PORTSC_RWC_MASK 0x0000002a |
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#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable |
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#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable |
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#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable |
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#define PORTSC_PTC (15 << 16) // Port Test Control |
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#define PORTSC_PTC_SH 16 // Port Test Control shift |
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#define PORTSC_PIC (3 << 14) // Port Indicator Control |
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#define PORTSC_PIC_SH 14 // Port Indicator Control Shift |
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#define PORTSC_POWNER (1 << 13) // Port Owner |
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#define PORTSC_PPOWER (1 << 12) // Port Power |
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#define PORTSC_LINESTAT (3 << 10) // Port Line Status |
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#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift |
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#define PORTSC_PRESET (1 << 8) // Port Reset |
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#define PORTSC_SUSPEND (1 << 7) // Port Suspend |
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#define PORTSC_FPRES (1 << 6) // Force Port Resume |
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#define PORTSC_OCC (1 << 5) // Over Current Change |
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#define PORTSC_OCA (1 << 4) // Over Current Active |
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#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change |
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#define PORTSC_PED (1 << 2) // Port Enable/Disable |
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#define PORTSC_CSC (1 << 1) // Connect Status Change |
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#define PORTSC_CONNECT (1 << 0) // Current Connect Status |
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|
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#define FRAME_TIMER_FREQ 1000 |
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#define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
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#define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8) |
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|
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#define NB_MAXINTRATE 8 // Max rate at which controller issues ints |
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#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
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#define MAX_QH 100 // Max allowable queue heads in a chain |
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#define MIN_UFR_PER_TICK 24 /* Min frames to process when catching up */ |
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#define PERIODIC_ACTIVE 512 /* Micro-frames */ |
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|
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/* Internal periodic / asynchronous schedule state machine states
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*/
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typedef enum { |
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EST_INACTIVE = 1000,
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EST_ACTIVE, |
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EST_EXECUTING, |
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EST_SLEEPING, |
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/* The following states are internal to the state machine function
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*/
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EST_WAITLISTHEAD, |
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EST_FETCHENTRY, |
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EST_FETCHQH, |
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EST_FETCHITD, |
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EST_FETCHSITD, |
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EST_ADVANCEQUEUE, |
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EST_FETCHQTD, |
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EST_EXECUTE, |
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EST_WRITEBACK, |
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EST_HORIZONTALQH |
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} EHCI_STATES; |
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|
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/* macros for accessing fields within next link pointer entry */
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#define NLPTR_GET(x) ((x) & 0xffffffe0) |
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#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) |
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#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid |
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|
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/* link pointer types */
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#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor |
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#define NLPTR_TYPE_QH 1 // queue head |
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#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor |
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#define NLPTR_TYPE_FSTN 3 // frame span traversal node |
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|
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#define SET_LAST_RUN_CLOCK(s) \
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(s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
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|
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/* nifty macros from Arnon's EHCI version */
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#define get_field(data, field) \
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(((data) & field##_MASK) >> field##_SH) |
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#define set_field(data, newval, field) do { \ |
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uint32_t val = *data; \ |
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val &= ~ field##_MASK; \ |
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val |= ((newval) << field##_SH) & field##_MASK; \ |
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*data = val; \ |
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} while(0) |
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|
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static const char *ehci_state_names[] = { |
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[EST_INACTIVE] = "INACTIVE",
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[EST_ACTIVE] = "ACTIVE",
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[EST_EXECUTING] = "EXECUTING",
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[EST_SLEEPING] = "SLEEPING",
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[EST_WAITLISTHEAD] = "WAITLISTHEAD",
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[EST_FETCHENTRY] = "FETCH ENTRY",
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[EST_FETCHQH] = "FETCH QH",
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[EST_FETCHITD] = "FETCH ITD",
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[EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
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[EST_FETCHQTD] = "FETCH QTD",
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[EST_EXECUTE] = "EXECUTE",
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[EST_WRITEBACK] = "WRITEBACK",
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[EST_HORIZONTALQH] = "HORIZONTALQH",
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}; |
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static const char *ehci_mmio_names[] = { |
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[USBCMD] = "USBCMD",
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[USBSTS] = "USBSTS",
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[USBINTR] = "USBINTR",
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[FRINDEX] = "FRINDEX",
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[PERIODICLISTBASE] = "P-LIST BASE",
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[ASYNCLISTADDR] = "A-LIST ADDR",
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[CONFIGFLAG] = "CONFIGFLAG",
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}; |
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static int ehci_state_executing(EHCIQueue *q); |
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static int ehci_state_writeback(EHCIQueue *q); |
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static int ehci_state_advqueue(EHCIQueue *q); |
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static int ehci_fill_queue(EHCIPacket *p); |
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static void ehci_free_packet(EHCIPacket *p); |
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static const char *nr2str(const char **n, size_t len, uint32_t nr) |
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{
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if (nr < len && n[nr] != NULL) { |
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return n[nr];
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} else {
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return "unknown"; |
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} |
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} |
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static const char *state2str(uint32_t state) |
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{
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return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
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} |
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static const char *addr2str(hwaddr addr) |
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{
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return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
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} |
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static void ehci_trace_usbsts(uint32_t mask, int state) |
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{
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/* interrupts */
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if (mask & USBSTS_INT) {
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trace_usb_ehci_usbsts("INT", state);
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} |
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if (mask & USBSTS_ERRINT) {
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trace_usb_ehci_usbsts("ERRINT", state);
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} |
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if (mask & USBSTS_PCD) {
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trace_usb_ehci_usbsts("PCD", state);
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} |
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if (mask & USBSTS_FLR) {
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trace_usb_ehci_usbsts("FLR", state);
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} |
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if (mask & USBSTS_HSE) {
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trace_usb_ehci_usbsts("HSE", state);
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} |
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if (mask & USBSTS_IAA) {
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trace_usb_ehci_usbsts("IAA", state);
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} |
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|
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/* status */
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if (mask & USBSTS_HALT) {
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trace_usb_ehci_usbsts("HALT", state);
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} |
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if (mask & USBSTS_REC) {
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trace_usb_ehci_usbsts("REC", state);
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} |
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if (mask & USBSTS_PSS) {
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trace_usb_ehci_usbsts("PSS", state);
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} |
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if (mask & USBSTS_ASS) {
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trace_usb_ehci_usbsts("ASS", state);
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} |
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} |
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|
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static inline void ehci_set_usbsts(EHCIState *s, int mask) |
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{
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if ((s->usbsts & mask) == mask) {
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return;
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} |
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ehci_trace_usbsts(mask, 1);
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s->usbsts |= mask; |
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} |
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|
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static inline void ehci_clear_usbsts(EHCIState *s, int mask) |
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{
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if ((s->usbsts & mask) == 0) { |
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return;
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} |
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ehci_trace_usbsts(mask, 0);
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s->usbsts &= ~mask; |
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} |
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|
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/* update irq line */
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static inline void ehci_update_irq(EHCIState *s) |
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{
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int level = 0; |
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if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
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level = 1;
|
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} |
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|
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trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); |
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qemu_set_irq(s->irq, level); |
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} |
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|
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/* flag interrupt condition */
|
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static inline void ehci_raise_irq(EHCIState *s, int intr) |
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{
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if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
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s->usbsts |= intr; |
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ehci_update_irq(s); |
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} else {
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s->usbsts_pending |= intr; |
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} |
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} |
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|
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/*
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* Commit pending interrupts (added via ehci_raise_irq),
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* at the rate allowed by "Interrupt Threshold Control".
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*/
|
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static inline void ehci_commit_irq(EHCIState *s) |
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{
|
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uint32_t itc; |
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|
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if (!s->usbsts_pending) {
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return;
|
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} |
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if (s->usbsts_frindex > s->frindex) {
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return;
|
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} |
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|
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itc = (s->usbcmd >> 16) & 0xff; |
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s->usbsts |= s->usbsts_pending; |
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s->usbsts_pending = 0;
|
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s->usbsts_frindex = s->frindex + itc; |
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ehci_update_irq(s); |
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} |
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|
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static void ehci_update_halt(EHCIState *s) |
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{
|
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if (s->usbcmd & USBCMD_RUNSTOP) {
|
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ehci_clear_usbsts(s, USBSTS_HALT); |
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} else {
|
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if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
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ehci_set_usbsts(s, USBSTS_HALT); |
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} |
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} |
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} |
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|
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static void ehci_set_state(EHCIState *s, int async, int state) |
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{
|
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if (async) {
|
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trace_usb_ehci_state("async", state2str(state));
|
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s->astate = state; |
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if (s->astate == EST_INACTIVE) {
|
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ehci_clear_usbsts(s, USBSTS_ASS); |
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ehci_update_halt(s); |
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} else {
|
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ehci_set_usbsts(s, USBSTS_ASS); |
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} |
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} else {
|
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trace_usb_ehci_state("periodic", state2str(state));
|
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s->pstate = state; |
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if (s->pstate == EST_INACTIVE) {
|
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ehci_clear_usbsts(s, USBSTS_PSS); |
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ehci_update_halt(s); |
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} else {
|
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ehci_set_usbsts(s, USBSTS_PSS); |
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} |
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} |
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} |
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|
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static int ehci_get_state(EHCIState *s, int async) |
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{
|
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return async ? s->astate : s->pstate;
|
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} |
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|
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static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
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{
|
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if (async) {
|
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s->a_fetch_addr = addr; |
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} else {
|
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s->p_fetch_addr = addr; |
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} |
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} |
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|
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static int ehci_get_fetch_addr(EHCIState *s, int async) |
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{
|
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return async ? s->a_fetch_addr : s->p_fetch_addr;
|
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} |
| 370 |
|
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static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh) |
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{
|
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/* need three here due to argument count limits */
|
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trace_usb_ehci_qh_ptrs(q, addr, qh->next, |
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qh->current_qtd, qh->next_qtd, qh->altnext_qtd); |
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trace_usb_ehci_qh_fields(addr, |
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get_field(qh->epchar, QH_EPCHAR_RL), |
| 378 |
get_field(qh->epchar, QH_EPCHAR_MPLEN), |
| 379 |
get_field(qh->epchar, QH_EPCHAR_EPS), |
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get_field(qh->epchar, QH_EPCHAR_EP), |
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get_field(qh->epchar, QH_EPCHAR_DEVADDR)); |
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trace_usb_ehci_qh_bits(addr, |
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(bool)(qh->epchar & QH_EPCHAR_C),
|
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(bool)(qh->epchar & QH_EPCHAR_H),
|
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(bool)(qh->epchar & QH_EPCHAR_DTC),
|
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(bool)(qh->epchar & QH_EPCHAR_I));
|
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} |
| 388 |
|
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static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd) |
| 390 |
{
|
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/* need three here due to argument count limits */
|
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trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); |
| 393 |
trace_usb_ehci_qtd_fields(addr, |
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get_field(qtd->token, QTD_TOKEN_TBYTES), |
| 395 |
get_field(qtd->token, QTD_TOKEN_CPAGE), |
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get_field(qtd->token, QTD_TOKEN_CERR), |
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get_field(qtd->token, QTD_TOKEN_PID)); |
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trace_usb_ehci_qtd_bits(addr, |
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(bool)(qtd->token & QTD_TOKEN_IOC),
|
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(bool)(qtd->token & QTD_TOKEN_ACTIVE),
|
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(bool)(qtd->token & QTD_TOKEN_HALT),
|
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(bool)(qtd->token & QTD_TOKEN_BABBLE),
|
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(bool)(qtd->token & QTD_TOKEN_XACTERR));
|
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} |
| 405 |
|
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static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd) |
| 407 |
{
|
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trace_usb_ehci_itd(addr, itd->next, |
| 409 |
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
|
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get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
|
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get_field(itd->bufptr[0], ITD_BUFPTR_EP),
|
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get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
|
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} |
| 414 |
|
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static void ehci_trace_sitd(EHCIState *s, hwaddr addr, |
| 416 |
EHCIsitd *sitd) |
| 417 |
{
|
| 418 |
trace_usb_ehci_sitd(addr, sitd->next, |
| 419 |
(bool)(sitd->results & SITD_RESULTS_ACTIVE));
|
| 420 |
} |
| 421 |
|
| 422 |
static void ehci_trace_guest_bug(EHCIState *s, const char *message) |
| 423 |
{
|
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trace_usb_ehci_guest_bug(message); |
| 425 |
fprintf(stderr, "ehci warning: %s\n", message);
|
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} |
| 427 |
|
| 428 |
static inline bool ehci_enabled(EHCIState *s) |
| 429 |
{
|
| 430 |
return s->usbcmd & USBCMD_RUNSTOP;
|
| 431 |
} |
| 432 |
|
| 433 |
static inline bool ehci_async_enabled(EHCIState *s) |
| 434 |
{
|
| 435 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
|
| 436 |
} |
| 437 |
|
| 438 |
static inline bool ehci_periodic_enabled(EHCIState *s) |
| 439 |
{
|
| 440 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
|
| 441 |
} |
| 442 |
|
| 443 |
/* Get an array of dwords from main memory */
|
| 444 |
static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
| 445 |
uint32_t *buf, int num)
|
| 446 |
{
|
| 447 |
int i;
|
| 448 |
|
| 449 |
if (!ehci->as) {
|
| 450 |
ehci_raise_irq(ehci, USBSTS_HSE); |
| 451 |
ehci->usbcmd &= ~USBCMD_RUNSTOP; |
| 452 |
trace_usb_ehci_dma_error(); |
| 453 |
return -1; |
| 454 |
} |
| 455 |
|
| 456 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
| 457 |
dma_memory_read(ehci->as, addr, buf, sizeof(*buf));
|
| 458 |
*buf = le32_to_cpu(*buf); |
| 459 |
} |
| 460 |
|
| 461 |
return num;
|
| 462 |
} |
| 463 |
|
| 464 |
/* Put an array of dwords in to main memory */
|
| 465 |
static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
| 466 |
uint32_t *buf, int num)
|
| 467 |
{
|
| 468 |
int i;
|
| 469 |
|
| 470 |
if (!ehci->as) {
|
| 471 |
ehci_raise_irq(ehci, USBSTS_HSE); |
| 472 |
ehci->usbcmd &= ~USBCMD_RUNSTOP; |
| 473 |
trace_usb_ehci_dma_error(); |
| 474 |
return -1; |
| 475 |
} |
| 476 |
|
| 477 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
| 478 |
uint32_t tmp = cpu_to_le32(*buf); |
| 479 |
dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp));
|
| 480 |
} |
| 481 |
|
| 482 |
return num;
|
| 483 |
} |
| 484 |
|
| 485 |
static int ehci_get_pid(EHCIqtd *qtd) |
| 486 |
{
|
| 487 |
switch (get_field(qtd->token, QTD_TOKEN_PID)) {
|
| 488 |
case 0: |
| 489 |
return USB_TOKEN_OUT;
|
| 490 |
case 1: |
| 491 |
return USB_TOKEN_IN;
|
| 492 |
case 2: |
| 493 |
return USB_TOKEN_SETUP;
|
| 494 |
default:
|
| 495 |
fprintf(stderr, "bad token\n");
|
| 496 |
return 0; |
| 497 |
} |
| 498 |
} |
| 499 |
|
| 500 |
static bool ehci_verify_qh(EHCIQueue *q, EHCIqh *qh) |
| 501 |
{
|
| 502 |
uint32_t devaddr = get_field(qh->epchar, QH_EPCHAR_DEVADDR); |
| 503 |
uint32_t endp = get_field(qh->epchar, QH_EPCHAR_EP); |
| 504 |
if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
|
| 505 |
(endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || |
| 506 |
(qh->current_qtd != q->qh.current_qtd) || |
| 507 |
(q->async && qh->next_qtd != q->qh.next_qtd) || |
| 508 |
(memcmp(&qh->altnext_qtd, &q->qh.altnext_qtd, |
| 509 |
7 * sizeof(uint32_t)) != 0) || |
| 510 |
(q->dev != NULL && q->dev->addr != devaddr)) {
|
| 511 |
return false; |
| 512 |
} else {
|
| 513 |
return true; |
| 514 |
} |
| 515 |
} |
| 516 |
|
| 517 |
static bool ehci_verify_qtd(EHCIPacket *p, EHCIqtd *qtd) |
| 518 |
{
|
| 519 |
if (p->qtdaddr != p->queue->qtdaddr ||
|
| 520 |
(p->queue->async && !NLPTR_TBIT(p->qtd.next) && |
| 521 |
(p->qtd.next != qtd->next)) || |
| 522 |
(!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd->altnext)) || |
| 523 |
p->qtd.token != qtd->token || |
| 524 |
p->qtd.bufptr[0] != qtd->bufptr[0]) { |
| 525 |
return false; |
| 526 |
} else {
|
| 527 |
return true; |
| 528 |
} |
| 529 |
} |
| 530 |
|
| 531 |
static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd) |
| 532 |
{
|
| 533 |
int ep = get_field(q->qh.epchar, QH_EPCHAR_EP);
|
| 534 |
int pid = ehci_get_pid(qtd);
|
| 535 |
|
| 536 |
/* Note the pid changing is normal for ep 0 (the control ep) */
|
| 537 |
if (q->last_pid && ep != 0 && pid != q->last_pid) { |
| 538 |
return false; |
| 539 |
} else {
|
| 540 |
return true; |
| 541 |
} |
| 542 |
} |
| 543 |
|
| 544 |
/* Finish executing and writeback a packet outside of the regular
|
| 545 |
fetchqh -> fetchqtd -> execute -> writeback cycle */
|
| 546 |
static void ehci_writeback_async_complete_packet(EHCIPacket *p) |
| 547 |
{
|
| 548 |
EHCIQueue *q = p->queue; |
| 549 |
EHCIqtd qtd; |
| 550 |
EHCIqh qh; |
| 551 |
int state;
|
| 552 |
|
| 553 |
/* Verify the qh + qtd, like we do when going through fetchqh & fetchqtd */
|
| 554 |
get_dwords(q->ehci, NLPTR_GET(q->qhaddr), |
| 555 |
(uint32_t *) &qh, sizeof(EHCIqh) >> 2); |
| 556 |
get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), |
| 557 |
(uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); |
| 558 |
if (!ehci_verify_qh(q, &qh) || !ehci_verify_qtd(p, &qtd)) {
|
| 559 |
p->async = EHCI_ASYNC_INITIALIZED; |
| 560 |
ehci_free_packet(p); |
| 561 |
return;
|
| 562 |
} |
| 563 |
|
| 564 |
state = ehci_get_state(q->ehci, q->async); |
| 565 |
ehci_state_executing(q); |
| 566 |
ehci_state_writeback(q); /* Frees the packet! */
|
| 567 |
if (!(q->qh.token & QTD_TOKEN_HALT)) {
|
| 568 |
ehci_state_advqueue(q); |
| 569 |
} |
| 570 |
ehci_set_state(q->ehci, q->async, state); |
| 571 |
} |
| 572 |
|
| 573 |
/* packet management */
|
| 574 |
|
| 575 |
static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
|
| 576 |
{
|
| 577 |
EHCIPacket *p; |
| 578 |
|
| 579 |
p = g_new0(EHCIPacket, 1);
|
| 580 |
p->queue = q; |
| 581 |
usb_packet_init(&p->packet); |
| 582 |
QTAILQ_INSERT_TAIL(&q->packets, p, next); |
| 583 |
trace_usb_ehci_packet_action(p->queue, p, "alloc");
|
| 584 |
return p;
|
| 585 |
} |
| 586 |
|
| 587 |
static void ehci_free_packet(EHCIPacket *p) |
| 588 |
{
|
| 589 |
if (p->async == EHCI_ASYNC_FINISHED &&
|
| 590 |
!(p->queue->qh.token & QTD_TOKEN_HALT)) {
|
| 591 |
ehci_writeback_async_complete_packet(p); |
| 592 |
return;
|
| 593 |
} |
| 594 |
trace_usb_ehci_packet_action(p->queue, p, "free");
|
| 595 |
if (p->async == EHCI_ASYNC_INFLIGHT) {
|
| 596 |
usb_cancel_packet(&p->packet); |
| 597 |
} |
| 598 |
if (p->async == EHCI_ASYNC_FINISHED &&
|
| 599 |
p->packet.status == USB_RET_SUCCESS) {
|
| 600 |
fprintf(stderr, |
| 601 |
"EHCI: Dropping completed packet from halted %s ep %02X\n",
|
| 602 |
(p->pid == USB_TOKEN_IN) ? "in" : "out", |
| 603 |
get_field(p->queue->qh.epchar, QH_EPCHAR_EP)); |
| 604 |
} |
| 605 |
if (p->async != EHCI_ASYNC_NONE) {
|
| 606 |
usb_packet_unmap(&p->packet, &p->sgl); |
| 607 |
qemu_sglist_destroy(&p->sgl); |
| 608 |
} |
| 609 |
QTAILQ_REMOVE(&p->queue->packets, p, next); |
| 610 |
usb_packet_cleanup(&p->packet); |
| 611 |
g_free(p); |
| 612 |
} |
| 613 |
|
| 614 |
/* queue management */
|
| 615 |
|
| 616 |
static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
| 617 |
{
|
| 618 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
| 619 |
EHCIQueue *q; |
| 620 |
|
| 621 |
q = g_malloc0(sizeof(*q));
|
| 622 |
q->ehci = ehci; |
| 623 |
q->qhaddr = addr; |
| 624 |
q->async = async; |
| 625 |
QTAILQ_INIT(&q->packets); |
| 626 |
QTAILQ_INSERT_HEAD(head, q, next); |
| 627 |
trace_usb_ehci_queue_action(q, "alloc");
|
| 628 |
return q;
|
| 629 |
} |
| 630 |
|
| 631 |
static void ehci_queue_stopped(EHCIQueue *q) |
| 632 |
{
|
| 633 |
int endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
|
| 634 |
|
| 635 |
if (!q->last_pid || !q->dev) {
|
| 636 |
return;
|
| 637 |
} |
| 638 |
|
| 639 |
usb_device_ep_stopped(q->dev, usb_ep_get(q->dev, q->last_pid, endp)); |
| 640 |
} |
| 641 |
|
| 642 |
static int ehci_cancel_queue(EHCIQueue *q) |
| 643 |
{
|
| 644 |
EHCIPacket *p; |
| 645 |
int packets = 0; |
| 646 |
|
| 647 |
p = QTAILQ_FIRST(&q->packets); |
| 648 |
if (p == NULL) { |
| 649 |
goto leave;
|
| 650 |
} |
| 651 |
|
| 652 |
trace_usb_ehci_queue_action(q, "cancel");
|
| 653 |
do {
|
| 654 |
ehci_free_packet(p); |
| 655 |
packets++; |
| 656 |
} while ((p = QTAILQ_FIRST(&q->packets)) != NULL); |
| 657 |
|
| 658 |
leave:
|
| 659 |
ehci_queue_stopped(q); |
| 660 |
return packets;
|
| 661 |
} |
| 662 |
|
| 663 |
static int ehci_reset_queue(EHCIQueue *q) |
| 664 |
{
|
| 665 |
int packets;
|
| 666 |
|
| 667 |
trace_usb_ehci_queue_action(q, "reset");
|
| 668 |
packets = ehci_cancel_queue(q); |
| 669 |
q->dev = NULL;
|
| 670 |
q->qtdaddr = 0;
|
| 671 |
q->last_pid = 0;
|
| 672 |
return packets;
|
| 673 |
} |
| 674 |
|
| 675 |
static void ehci_free_queue(EHCIQueue *q, const char *warn) |
| 676 |
{
|
| 677 |
EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
| 678 |
int cancelled;
|
| 679 |
|
| 680 |
trace_usb_ehci_queue_action(q, "free");
|
| 681 |
cancelled = ehci_cancel_queue(q); |
| 682 |
if (warn && cancelled > 0) { |
| 683 |
ehci_trace_guest_bug(q->ehci, warn); |
| 684 |
} |
| 685 |
QTAILQ_REMOVE(head, q, next); |
| 686 |
g_free(q); |
| 687 |
} |
| 688 |
|
| 689 |
static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
|
| 690 |
int async)
|
| 691 |
{
|
| 692 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
| 693 |
EHCIQueue *q; |
| 694 |
|
| 695 |
QTAILQ_FOREACH(q, head, next) {
|
| 696 |
if (addr == q->qhaddr) {
|
| 697 |
return q;
|
| 698 |
} |
| 699 |
} |
| 700 |
return NULL; |
| 701 |
} |
| 702 |
|
| 703 |
static void ehci_queues_rip_unused(EHCIState *ehci, int async) |
| 704 |
{
|
| 705 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
| 706 |
const char *warn = async ? "guest unlinked busy QH" : NULL; |
| 707 |
uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
|
| 708 |
EHCIQueue *q, *tmp; |
| 709 |
|
| 710 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
|
| 711 |
if (q->seen) {
|
| 712 |
q->seen = 0;
|
| 713 |
q->ts = ehci->last_run_ns; |
| 714 |
continue;
|
| 715 |
} |
| 716 |
if (ehci->last_run_ns < q->ts + maxage) {
|
| 717 |
continue;
|
| 718 |
} |
| 719 |
ehci_free_queue(q, warn); |
| 720 |
} |
| 721 |
} |
| 722 |
|
| 723 |
static void ehci_queues_rip_unseen(EHCIState *ehci, int async) |
| 724 |
{
|
| 725 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
| 726 |
EHCIQueue *q, *tmp; |
| 727 |
|
| 728 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
|
| 729 |
if (!q->seen) {
|
| 730 |
ehci_free_queue(q, NULL);
|
| 731 |
} |
| 732 |
} |
| 733 |
} |
| 734 |
|
| 735 |
static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
| 736 |
{
|
| 737 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
| 738 |
EHCIQueue *q, *tmp; |
| 739 |
|
| 740 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
|
| 741 |
if (q->dev != dev) {
|
| 742 |
continue;
|
| 743 |
} |
| 744 |
ehci_free_queue(q, NULL);
|
| 745 |
} |
| 746 |
} |
| 747 |
|
| 748 |
static void ehci_queues_rip_all(EHCIState *ehci, int async) |
| 749 |
{
|
| 750 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
| 751 |
const char *warn = async ? "guest stopped busy async schedule" : NULL; |
| 752 |
EHCIQueue *q, *tmp; |
| 753 |
|
| 754 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
|
| 755 |
ehci_free_queue(q, warn); |
| 756 |
} |
| 757 |
} |
| 758 |
|
| 759 |
/* Attach or detach a device on root hub */
|
| 760 |
|
| 761 |
static void ehci_attach(USBPort *port) |
| 762 |
{
|
| 763 |
EHCIState *s = port->opaque; |
| 764 |
uint32_t *portsc = &s->portsc[port->index]; |
| 765 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
| 766 |
|
| 767 |
trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); |
| 768 |
|
| 769 |
if (*portsc & PORTSC_POWNER) {
|
| 770 |
USBPort *companion = s->companion_ports[port->index]; |
| 771 |
companion->dev = port->dev; |
| 772 |
companion->ops->attach(companion); |
| 773 |
return;
|
| 774 |
} |
| 775 |
|
| 776 |
*portsc |= PORTSC_CONNECT; |
| 777 |
*portsc |= PORTSC_CSC; |
| 778 |
|
| 779 |
ehci_raise_irq(s, USBSTS_PCD); |
| 780 |
} |
| 781 |
|
| 782 |
static void ehci_detach(USBPort *port) |
| 783 |
{
|
| 784 |
EHCIState *s = port->opaque; |
| 785 |
uint32_t *portsc = &s->portsc[port->index]; |
| 786 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
| 787 |
|
| 788 |
trace_usb_ehci_port_detach(port->index, owner); |
| 789 |
|
| 790 |
if (*portsc & PORTSC_POWNER) {
|
| 791 |
USBPort *companion = s->companion_ports[port->index]; |
| 792 |
companion->ops->detach(companion); |
| 793 |
companion->dev = NULL;
|
| 794 |
/*
|
| 795 |
* EHCI spec 4.2.2: "When a disconnect occurs... On the event,
|
| 796 |
* the port ownership is returned immediately to the EHCI controller."
|
| 797 |
*/
|
| 798 |
*portsc &= ~PORTSC_POWNER; |
| 799 |
return;
|
| 800 |
} |
| 801 |
|
| 802 |
ehci_queues_rip_device(s, port->dev, 0);
|
| 803 |
ehci_queues_rip_device(s, port->dev, 1);
|
| 804 |
|
| 805 |
*portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
| 806 |
*portsc |= PORTSC_CSC; |
| 807 |
|
| 808 |
ehci_raise_irq(s, USBSTS_PCD); |
| 809 |
} |
| 810 |
|
| 811 |
static void ehci_child_detach(USBPort *port, USBDevice *child) |
| 812 |
{
|
| 813 |
EHCIState *s = port->opaque; |
| 814 |
uint32_t portsc = s->portsc[port->index]; |
| 815 |
|
| 816 |
if (portsc & PORTSC_POWNER) {
|
| 817 |
USBPort *companion = s->companion_ports[port->index]; |
| 818 |
companion->ops->child_detach(companion, child); |
| 819 |
return;
|
| 820 |
} |
| 821 |
|
| 822 |
ehci_queues_rip_device(s, child, 0);
|
| 823 |
ehci_queues_rip_device(s, child, 1);
|
| 824 |
} |
| 825 |
|
| 826 |
static void ehci_wakeup(USBPort *port) |
| 827 |
{
|
| 828 |
EHCIState *s = port->opaque; |
| 829 |
uint32_t portsc = s->portsc[port->index]; |
| 830 |
|
| 831 |
if (portsc & PORTSC_POWNER) {
|
| 832 |
USBPort *companion = s->companion_ports[port->index]; |
| 833 |
if (companion->ops->wakeup) {
|
| 834 |
companion->ops->wakeup(companion); |
| 835 |
} |
| 836 |
return;
|
| 837 |
} |
| 838 |
|
| 839 |
qemu_bh_schedule(s->async_bh); |
| 840 |
} |
| 841 |
|
| 842 |
static int ehci_register_companion(USBBus *bus, USBPort *ports[], |
| 843 |
uint32_t portcount, uint32_t firstport) |
| 844 |
{
|
| 845 |
EHCIState *s = container_of(bus, EHCIState, bus); |
| 846 |
uint32_t i; |
| 847 |
|
| 848 |
if (firstport + portcount > NB_PORTS) {
|
| 849 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
|
| 850 |
"firstport on masterbus");
|
| 851 |
error_printf_unless_qmp( |
| 852 |
"firstport value of %u makes companion take ports %u - %u, which "
|
| 853 |
"is outside of the valid range of 0 - %u\n", firstport, firstport,
|
| 854 |
firstport + portcount - 1, NB_PORTS - 1); |
| 855 |
return -1; |
| 856 |
} |
| 857 |
|
| 858 |
for (i = 0; i < portcount; i++) { |
| 859 |
if (s->companion_ports[firstport + i]) {
|
| 860 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
|
| 861 |
"an USB masterbus");
|
| 862 |
error_printf_unless_qmp( |
| 863 |
"port %u on masterbus %s already has a companion assigned\n",
|
| 864 |
firstport + i, bus->qbus.name); |
| 865 |
return -1; |
| 866 |
} |
| 867 |
} |
| 868 |
|
| 869 |
for (i = 0; i < portcount; i++) { |
| 870 |
s->companion_ports[firstport + i] = ports[i]; |
| 871 |
s->ports[firstport + i].speedmask |= |
| 872 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; |
| 873 |
/* Ensure devs attached before the initial reset go to the companion */
|
| 874 |
s->portsc[firstport + i] = PORTSC_POWNER; |
| 875 |
} |
| 876 |
|
| 877 |
s->companion_count++; |
| 878 |
s->caps[0x05] = (s->companion_count << 4) | portcount; |
| 879 |
|
| 880 |
return 0; |
| 881 |
} |
| 882 |
|
| 883 |
static void ehci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, |
| 884 |
unsigned int stream) |
| 885 |
{
|
| 886 |
EHCIState *s = container_of(bus, EHCIState, bus); |
| 887 |
uint32_t portsc = s->portsc[ep->dev->port->index]; |
| 888 |
|
| 889 |
if (portsc & PORTSC_POWNER) {
|
| 890 |
return;
|
| 891 |
} |
| 892 |
|
| 893 |
s->periodic_sched_active = PERIODIC_ACTIVE; |
| 894 |
qemu_bh_schedule(s->async_bh); |
| 895 |
} |
| 896 |
|
| 897 |
static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
|
| 898 |
{
|
| 899 |
USBDevice *dev; |
| 900 |
USBPort *port; |
| 901 |
int i;
|
| 902 |
|
| 903 |
for (i = 0; i < NB_PORTS; i++) { |
| 904 |
port = &ehci->ports[i]; |
| 905 |
if (!(ehci->portsc[i] & PORTSC_PED)) {
|
| 906 |
DPRINTF("Port %d not enabled\n", i);
|
| 907 |
continue;
|
| 908 |
} |
| 909 |
dev = usb_find_device(port, addr); |
| 910 |
if (dev != NULL) { |
| 911 |
return dev;
|
| 912 |
} |
| 913 |
} |
| 914 |
return NULL; |
| 915 |
} |
| 916 |
|
| 917 |
/* 4.1 host controller initialization */
|
| 918 |
static void ehci_reset(void *opaque) |
| 919 |
{
|
| 920 |
EHCIState *s = opaque; |
| 921 |
int i;
|
| 922 |
USBDevice *devs[NB_PORTS]; |
| 923 |
|
| 924 |
trace_usb_ehci_reset(); |
| 925 |
|
| 926 |
/*
|
| 927 |
* Do the detach before touching portsc, so that it correctly gets send to
|
| 928 |
* us or to our companion based on PORTSC_POWNER before the reset.
|
| 929 |
*/
|
| 930 |
for(i = 0; i < NB_PORTS; i++) { |
| 931 |
devs[i] = s->ports[i].dev; |
| 932 |
if (devs[i] && devs[i]->attached) {
|
| 933 |
usb_detach(&s->ports[i]); |
| 934 |
} |
| 935 |
} |
| 936 |
|
| 937 |
memset(&s->opreg, 0x00, sizeof(s->opreg)); |
| 938 |
memset(&s->portsc, 0x00, sizeof(s->portsc)); |
| 939 |
|
| 940 |
s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; |
| 941 |
s->usbsts = USBSTS_HALT; |
| 942 |
s->usbsts_pending = 0;
|
| 943 |
s->usbsts_frindex = 0;
|
| 944 |
|
| 945 |
s->astate = EST_INACTIVE; |
| 946 |
s->pstate = EST_INACTIVE; |
| 947 |
|
| 948 |
for(i = 0; i < NB_PORTS; i++) { |
| 949 |
if (s->companion_ports[i]) {
|
| 950 |
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; |
| 951 |
} else {
|
| 952 |
s->portsc[i] = PORTSC_PPOWER; |
| 953 |
} |
| 954 |
if (devs[i] && devs[i]->attached) {
|
| 955 |
usb_attach(&s->ports[i]); |
| 956 |
usb_device_reset(devs[i]); |
| 957 |
} |
| 958 |
} |
| 959 |
ehci_queues_rip_all(s, 0);
|
| 960 |
ehci_queues_rip_all(s, 1);
|
| 961 |
qemu_del_timer(s->frame_timer); |
| 962 |
qemu_bh_cancel(s->async_bh); |
| 963 |
} |
| 964 |
|
| 965 |
static uint64_t ehci_caps_read(void *ptr, hwaddr addr, |
| 966 |
unsigned size)
|
| 967 |
{
|
| 968 |
EHCIState *s = ptr; |
| 969 |
return s->caps[addr];
|
| 970 |
} |
| 971 |
|
| 972 |
static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, |
| 973 |
unsigned size)
|
| 974 |
{
|
| 975 |
EHCIState *s = ptr; |
| 976 |
uint32_t val; |
| 977 |
|
| 978 |
switch (addr) {
|
| 979 |
case FRINDEX:
|
| 980 |
/* Round down to mult of 8, else it can go backwards on migration */
|
| 981 |
val = s->frindex & ~7;
|
| 982 |
break;
|
| 983 |
default:
|
| 984 |
val = s->opreg[addr >> 2];
|
| 985 |
} |
| 986 |
|
| 987 |
trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); |
| 988 |
return val;
|
| 989 |
} |
| 990 |
|
| 991 |
static uint64_t ehci_port_read(void *ptr, hwaddr addr, |
| 992 |
unsigned size)
|
| 993 |
{
|
| 994 |
EHCIState *s = ptr; |
| 995 |
uint32_t val; |
| 996 |
|
| 997 |
val = s->portsc[addr >> 2];
|
| 998 |
trace_usb_ehci_portsc_read(addr + s->portscbase, addr >> 2, val);
|
| 999 |
return val;
|
| 1000 |
} |
| 1001 |
|
| 1002 |
static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
| 1003 |
{
|
| 1004 |
USBDevice *dev = s->ports[port].dev; |
| 1005 |
uint32_t *portsc = &s->portsc[port]; |
| 1006 |
uint32_t orig; |
| 1007 |
|
| 1008 |
if (s->companion_ports[port] == NULL) |
| 1009 |
return;
|
| 1010 |
|
| 1011 |
owner = owner & PORTSC_POWNER; |
| 1012 |
orig = *portsc & PORTSC_POWNER; |
| 1013 |
|
| 1014 |
if (!(owner ^ orig)) {
|
| 1015 |
return;
|
| 1016 |
} |
| 1017 |
|
| 1018 |
if (dev && dev->attached) {
|
| 1019 |
usb_detach(&s->ports[port]); |
| 1020 |
} |
| 1021 |
|
| 1022 |
*portsc &= ~PORTSC_POWNER; |
| 1023 |
*portsc |= owner; |
| 1024 |
|
| 1025 |
if (dev && dev->attached) {
|
| 1026 |
usb_attach(&s->ports[port]); |
| 1027 |
} |
| 1028 |
} |
| 1029 |
|
| 1030 |
static void ehci_port_write(void *ptr, hwaddr addr, |
| 1031 |
uint64_t val, unsigned size)
|
| 1032 |
{
|
| 1033 |
EHCIState *s = ptr; |
| 1034 |
int port = addr >> 2; |
| 1035 |
uint32_t *portsc = &s->portsc[port]; |
| 1036 |
uint32_t old = *portsc; |
| 1037 |
USBDevice *dev = s->ports[port].dev; |
| 1038 |
|
| 1039 |
trace_usb_ehci_portsc_write(addr + s->portscbase, addr >> 2, val);
|
| 1040 |
|
| 1041 |
/* Clear rwc bits */
|
| 1042 |
*portsc &= ~(val & PORTSC_RWC_MASK); |
| 1043 |
/* The guest may clear, but not set the PED bit */
|
| 1044 |
*portsc &= val | ~PORTSC_PED; |
| 1045 |
/* POWNER is masked out by RO_MASK as it is RO when we've no companion */
|
| 1046 |
handle_port_owner_write(s, port, val); |
| 1047 |
/* And finally apply RO_MASK */
|
| 1048 |
val &= PORTSC_RO_MASK; |
| 1049 |
|
| 1050 |
if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
|
| 1051 |
trace_usb_ehci_port_reset(port, 1);
|
| 1052 |
} |
| 1053 |
|
| 1054 |
if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
|
| 1055 |
trace_usb_ehci_port_reset(port, 0);
|
| 1056 |
if (dev && dev->attached) {
|
| 1057 |
usb_port_reset(&s->ports[port]); |
| 1058 |
*portsc &= ~PORTSC_CSC; |
| 1059 |
} |
| 1060 |
|
| 1061 |
/*
|
| 1062 |
* Table 2.16 Set the enable bit(and enable bit change) to indicate
|
| 1063 |
* to SW that this port has a high speed device attached
|
| 1064 |
*/
|
| 1065 |
if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
|
| 1066 |
val |= PORTSC_PED; |
| 1067 |
} |
| 1068 |
} |
| 1069 |
|
| 1070 |
*portsc &= ~PORTSC_RO_MASK; |
| 1071 |
*portsc |= val; |
| 1072 |
trace_usb_ehci_portsc_change(addr + s->portscbase, addr >> 2, *portsc, old);
|
| 1073 |
} |
| 1074 |
|
| 1075 |
static void ehci_opreg_write(void *ptr, hwaddr addr, |
| 1076 |
uint64_t val, unsigned size)
|
| 1077 |
{
|
| 1078 |
EHCIState *s = ptr; |
| 1079 |
uint32_t *mmio = s->opreg + (addr >> 2);
|
| 1080 |
uint32_t old = *mmio; |
| 1081 |
int i;
|
| 1082 |
|
| 1083 |
trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); |
| 1084 |
|
| 1085 |
switch (addr) {
|
| 1086 |
case USBCMD:
|
| 1087 |
if (val & USBCMD_HCRESET) {
|
| 1088 |
ehci_reset(s); |
| 1089 |
val = s->usbcmd; |
| 1090 |
break;
|
| 1091 |
} |
| 1092 |
|
| 1093 |
/* not supporting dynamic frame list size at the moment */
|
| 1094 |
if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
|
| 1095 |
fprintf(stderr, "attempt to set frame list size -- value %d\n",
|
| 1096 |
(int)val & USBCMD_FLS);
|
| 1097 |
val &= ~USBCMD_FLS; |
| 1098 |
} |
| 1099 |
|
| 1100 |
if (val & USBCMD_IAAD) {
|
| 1101 |
/*
|
| 1102 |
* Process IAAD immediately, otherwise the Linux IAAD watchdog may
|
| 1103 |
* trigger and re-use a qh without us seeing the unlink.
|
| 1104 |
*/
|
| 1105 |
s->async_stepdown = 0;
|
| 1106 |
qemu_bh_schedule(s->async_bh); |
| 1107 |
trace_usb_ehci_doorbell_ring(); |
| 1108 |
} |
| 1109 |
|
| 1110 |
if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
|
| 1111 |
((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
|
| 1112 |
if (s->pstate == EST_INACTIVE) {
|
| 1113 |
SET_LAST_RUN_CLOCK(s); |
| 1114 |
} |
| 1115 |
s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
|
| 1116 |
ehci_update_halt(s); |
| 1117 |
s->async_stepdown = 0;
|
| 1118 |
qemu_bh_schedule(s->async_bh); |
| 1119 |
} |
| 1120 |
break;
|
| 1121 |
|
| 1122 |
case USBSTS:
|
| 1123 |
val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
|
| 1124 |
ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
|
| 1125 |
val = s->usbsts; |
| 1126 |
ehci_update_irq(s); |
| 1127 |
break;
|
| 1128 |
|
| 1129 |
case USBINTR:
|
| 1130 |
val &= USBINTR_MASK; |
| 1131 |
if (ehci_enabled(s) && (USBSTS_FLR & val)) {
|
| 1132 |
qemu_bh_schedule(s->async_bh); |
| 1133 |
} |
| 1134 |
break;
|
| 1135 |
|
| 1136 |
case FRINDEX:
|
| 1137 |
val &= 0x00003fff; /* frindex is 14bits */ |
| 1138 |
s->usbsts_frindex = val; |
| 1139 |
break;
|
| 1140 |
|
| 1141 |
case CONFIGFLAG:
|
| 1142 |
val &= 0x1;
|
| 1143 |
if (val) {
|
| 1144 |
for(i = 0; i < NB_PORTS; i++) |
| 1145 |
handle_port_owner_write(s, i, 0);
|
| 1146 |
} |
| 1147 |
break;
|
| 1148 |
|
| 1149 |
case PERIODICLISTBASE:
|
| 1150 |
if (ehci_periodic_enabled(s)) {
|
| 1151 |
fprintf(stderr, |
| 1152 |
"ehci: PERIODIC list base register set while periodic schedule\n"
|
| 1153 |
" is enabled and HC is enabled\n");
|
| 1154 |
} |
| 1155 |
break;
|
| 1156 |
|
| 1157 |
case ASYNCLISTADDR:
|
| 1158 |
if (ehci_async_enabled(s)) {
|
| 1159 |
fprintf(stderr, |
| 1160 |
"ehci: ASYNC list address register set while async schedule\n"
|
| 1161 |
" is enabled and HC is enabled\n");
|
| 1162 |
} |
| 1163 |
break;
|
| 1164 |
} |
| 1165 |
|
| 1166 |
*mmio = val; |
| 1167 |
trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), |
| 1168 |
*mmio, old); |
| 1169 |
} |
| 1170 |
|
| 1171 |
/*
|
| 1172 |
* Write the qh back to guest physical memory. This step isn't
|
| 1173 |
* in the EHCI spec but we need to do it since we don't share
|
| 1174 |
* physical memory with our guest VM.
|
| 1175 |
*
|
| 1176 |
* The first three dwords are read-only for the EHCI, so skip them
|
| 1177 |
* when writing back the qh.
|
| 1178 |
*/
|
| 1179 |
static void ehci_flush_qh(EHCIQueue *q) |
| 1180 |
{
|
| 1181 |
uint32_t *qh = (uint32_t *) &q->qh; |
| 1182 |
uint32_t dwords = sizeof(EHCIqh) >> 2; |
| 1183 |
uint32_t addr = NLPTR_GET(q->qhaddr); |
| 1184 |
|
| 1185 |
put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
| 1186 |
} |
| 1187 |
|
| 1188 |
// 4.10.2
|
| 1189 |
|
| 1190 |
static int ehci_qh_do_overlay(EHCIQueue *q) |
| 1191 |
{
|
| 1192 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
| 1193 |
int i;
|
| 1194 |
int dtoggle;
|
| 1195 |
int ping;
|
| 1196 |
int eps;
|
| 1197 |
int reload;
|
| 1198 |
|
| 1199 |
assert(p != NULL);
|
| 1200 |
assert(p->qtdaddr == q->qtdaddr); |
| 1201 |
|
| 1202 |
// remember values in fields to preserve in qh after overlay
|
| 1203 |
|
| 1204 |
dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
| 1205 |
ping = q->qh.token & QTD_TOKEN_PING; |
| 1206 |
|
| 1207 |
q->qh.current_qtd = p->qtdaddr; |
| 1208 |
q->qh.next_qtd = p->qtd.next; |
| 1209 |
q->qh.altnext_qtd = p->qtd.altnext; |
| 1210 |
q->qh.token = p->qtd.token; |
| 1211 |
|
| 1212 |
|
| 1213 |
eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
| 1214 |
if (eps == EHCI_QH_EPS_HIGH) {
|
| 1215 |
q->qh.token &= ~QTD_TOKEN_PING; |
| 1216 |
q->qh.token |= ping; |
| 1217 |
} |
| 1218 |
|
| 1219 |
reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
| 1220 |
set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
| 1221 |
|
| 1222 |
for (i = 0; i < 5; i++) { |
| 1223 |
q->qh.bufptr[i] = p->qtd.bufptr[i]; |
| 1224 |
} |
| 1225 |
|
| 1226 |
if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
|
| 1227 |
// preserve QH DT bit
|
| 1228 |
q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
| 1229 |
q->qh.token |= dtoggle; |
| 1230 |
} |
| 1231 |
|
| 1232 |
q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
|
| 1233 |
q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
|
| 1234 |
|
| 1235 |
ehci_flush_qh(q); |
| 1236 |
|
| 1237 |
return 0; |
| 1238 |
} |
| 1239 |
|
| 1240 |
static int ehci_init_transfer(EHCIPacket *p) |
| 1241 |
{
|
| 1242 |
uint32_t cpage, offset, bytes, plen; |
| 1243 |
dma_addr_t page; |
| 1244 |
USBBus *bus = &p->queue->ehci->bus; |
| 1245 |
BusState *qbus = BUS(bus); |
| 1246 |
|
| 1247 |
cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
| 1248 |
bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); |
| 1249 |
offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
|
| 1250 |
qemu_sglist_init(&p->sgl, qbus->parent, 5, p->queue->ehci->as);
|
| 1251 |
|
| 1252 |
while (bytes > 0) { |
| 1253 |
if (cpage > 4) { |
| 1254 |
fprintf(stderr, "cpage out of range (%d)\n", cpage);
|
| 1255 |
return -1; |
| 1256 |
} |
| 1257 |
|
| 1258 |
page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
| 1259 |
page += offset; |
| 1260 |
plen = bytes; |
| 1261 |
if (plen > 4096 - offset) { |
| 1262 |
plen = 4096 - offset;
|
| 1263 |
offset = 0;
|
| 1264 |
cpage++; |
| 1265 |
} |
| 1266 |
|
| 1267 |
qemu_sglist_add(&p->sgl, page, plen); |
| 1268 |
bytes -= plen; |
| 1269 |
} |
| 1270 |
return 0; |
| 1271 |
} |
| 1272 |
|
| 1273 |
static void ehci_finish_transfer(EHCIQueue *q, int len) |
| 1274 |
{
|
| 1275 |
uint32_t cpage, offset; |
| 1276 |
|
| 1277 |
if (len > 0) { |
| 1278 |
/* update cpage & offset */
|
| 1279 |
cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
| 1280 |
offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
|
| 1281 |
|
| 1282 |
offset += len; |
| 1283 |
cpage += offset >> QTD_BUFPTR_SH; |
| 1284 |
offset &= ~QTD_BUFPTR_MASK; |
| 1285 |
|
| 1286 |
set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
| 1287 |
q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
|
| 1288 |
q->qh.bufptr[0] |= offset;
|
| 1289 |
} |
| 1290 |
} |
| 1291 |
|
| 1292 |
static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
| 1293 |
{
|
| 1294 |
EHCIPacket *p; |
| 1295 |
EHCIState *s = port->opaque; |
| 1296 |
uint32_t portsc = s->portsc[port->index]; |
| 1297 |
|
| 1298 |
if (portsc & PORTSC_POWNER) {
|
| 1299 |
USBPort *companion = s->companion_ports[port->index]; |
| 1300 |
companion->ops->complete(companion, packet); |
| 1301 |
return;
|
| 1302 |
} |
| 1303 |
|
| 1304 |
p = container_of(packet, EHCIPacket, packet); |
| 1305 |
assert(p->async == EHCI_ASYNC_INFLIGHT); |
| 1306 |
|
| 1307 |
if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
|
| 1308 |
trace_usb_ehci_packet_action(p->queue, p, "remove");
|
| 1309 |
ehci_free_packet(p); |
| 1310 |
return;
|
| 1311 |
} |
| 1312 |
|
| 1313 |
trace_usb_ehci_packet_action(p->queue, p, "wakeup");
|
| 1314 |
p->async = EHCI_ASYNC_FINISHED; |
| 1315 |
|
| 1316 |
if (!p->queue->async) {
|
| 1317 |
s->periodic_sched_active = PERIODIC_ACTIVE; |
| 1318 |
} |
| 1319 |
qemu_bh_schedule(s->async_bh); |
| 1320 |
} |
| 1321 |
|
| 1322 |
static void ehci_execute_complete(EHCIQueue *q) |
| 1323 |
{
|
| 1324 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
| 1325 |
uint32_t tbytes; |
| 1326 |
|
| 1327 |
assert(p != NULL);
|
| 1328 |
assert(p->qtdaddr == q->qtdaddr); |
| 1329 |
assert(p->async == EHCI_ASYNC_INITIALIZED || |
| 1330 |
p->async == EHCI_ASYNC_FINISHED); |
| 1331 |
|
| 1332 |
DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, "
|
| 1333 |
"status %d, actual_length %d\n",
|
| 1334 |
q->qhaddr, q->qh.next, q->qtdaddr, |
| 1335 |
p->packet.status, p->packet.actual_length); |
| 1336 |
|
| 1337 |
switch (p->packet.status) {
|
| 1338 |
case USB_RET_SUCCESS:
|
| 1339 |
break;
|
| 1340 |
case USB_RET_IOERROR:
|
| 1341 |
case USB_RET_NODEV:
|
| 1342 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
| 1343 |
set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
|
| 1344 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
| 1345 |
break;
|
| 1346 |
case USB_RET_STALL:
|
| 1347 |
q->qh.token |= QTD_TOKEN_HALT; |
| 1348 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
| 1349 |
break;
|
| 1350 |
case USB_RET_NAK:
|
| 1351 |
set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
|
| 1352 |
return; /* We're not done yet with this transaction */ |
| 1353 |
case USB_RET_BABBLE:
|
| 1354 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
| 1355 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
| 1356 |
break;
|
| 1357 |
default:
|
| 1358 |
/* should not be triggerable */
|
| 1359 |
fprintf(stderr, "USB invalid response %d\n", p->packet.status);
|
| 1360 |
assert(0);
|
| 1361 |
break;
|
| 1362 |
} |
| 1363 |
|
| 1364 |
/* TODO check 4.12 for splits */
|
| 1365 |
tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); |
| 1366 |
if (tbytes && p->pid == USB_TOKEN_IN) {
|
| 1367 |
tbytes -= p->packet.actual_length; |
| 1368 |
if (tbytes) {
|
| 1369 |
/* 4.15.1.2 must raise int on a short input packet */
|
| 1370 |
ehci_raise_irq(q->ehci, USBSTS_INT); |
| 1371 |
if (q->async) {
|
| 1372 |
q->ehci->int_req_by_async = true;
|
| 1373 |
} |
| 1374 |
} |
| 1375 |
} else {
|
| 1376 |
tbytes = 0;
|
| 1377 |
} |
| 1378 |
DPRINTF("updating tbytes to %d\n", tbytes);
|
| 1379 |
set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES); |
| 1380 |
|
| 1381 |
ehci_finish_transfer(q, p->packet.actual_length); |
| 1382 |
usb_packet_unmap(&p->packet, &p->sgl); |
| 1383 |
qemu_sglist_destroy(&p->sgl); |
| 1384 |
p->async = EHCI_ASYNC_NONE; |
| 1385 |
|
| 1386 |
q->qh.token ^= QTD_TOKEN_DTOGGLE; |
| 1387 |
q->qh.token &= ~QTD_TOKEN_ACTIVE; |
| 1388 |
|
| 1389 |
if (q->qh.token & QTD_TOKEN_IOC) {
|
| 1390 |
ehci_raise_irq(q->ehci, USBSTS_INT); |
| 1391 |
if (q->async) {
|
| 1392 |
q->ehci->int_req_by_async = true;
|
| 1393 |
} |
| 1394 |
} |
| 1395 |
} |
| 1396 |
|
| 1397 |
/* 4.10.3 returns "again" */
|
| 1398 |
static int ehci_execute(EHCIPacket *p, const char *action) |
| 1399 |
{
|
| 1400 |
USBEndpoint *ep; |
| 1401 |
int endp;
|
| 1402 |
bool spd;
|
| 1403 |
|
| 1404 |
assert(p->async == EHCI_ASYNC_NONE || |
| 1405 |
p->async == EHCI_ASYNC_INITIALIZED); |
| 1406 |
|
| 1407 |
if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
|
| 1408 |
fprintf(stderr, "Attempting to execute inactive qtd\n");
|
| 1409 |
return -1; |
| 1410 |
} |
| 1411 |
|
| 1412 |
if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
|
| 1413 |
ehci_trace_guest_bug(p->queue->ehci, |
| 1414 |
"guest requested more bytes than allowed");
|
| 1415 |
return -1; |
| 1416 |
} |
| 1417 |
|
| 1418 |
if (!ehci_verify_pid(p->queue, &p->qtd)) {
|
| 1419 |
ehci_queue_stopped(p->queue); /* Mark the ep in the prev dir stopped */
|
| 1420 |
} |
| 1421 |
p->pid = ehci_get_pid(&p->qtd); |
| 1422 |
p->queue->last_pid = p->pid; |
| 1423 |
endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
| 1424 |
ep = usb_ep_get(p->queue->dev, p->pid, endp); |
| 1425 |
|
| 1426 |
if (p->async == EHCI_ASYNC_NONE) {
|
| 1427 |
if (ehci_init_transfer(p) != 0) { |
| 1428 |
return -1; |
| 1429 |
} |
| 1430 |
|
| 1431 |
spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
|
| 1432 |
usb_packet_setup(&p->packet, p->pid, ep, 0, p->qtdaddr, spd,
|
| 1433 |
(p->qtd.token & QTD_TOKEN_IOC) != 0);
|
| 1434 |
usb_packet_map(&p->packet, &p->sgl); |
| 1435 |
p->async = EHCI_ASYNC_INITIALIZED; |
| 1436 |
} |
| 1437 |
|
| 1438 |
trace_usb_ehci_packet_action(p->queue, p, action); |
| 1439 |
usb_handle_packet(p->queue->dev, &p->packet); |
| 1440 |
DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
|
| 1441 |
"status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next,
|
| 1442 |
p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status, |
| 1443 |
p->packet.actual_length); |
| 1444 |
|
| 1445 |
if (p->packet.actual_length > BUFF_SIZE) {
|
| 1446 |
fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
|
| 1447 |
return -1; |
| 1448 |
} |
| 1449 |
|
| 1450 |
return 1; |
| 1451 |
} |
| 1452 |
|
| 1453 |
/* 4.7.2
|
| 1454 |
*/
|
| 1455 |
|
| 1456 |
static int ehci_process_itd(EHCIState *ehci, |
| 1457 |
EHCIitd *itd, |
| 1458 |
uint32_t addr) |
| 1459 |
{
|
| 1460 |
USBDevice *dev; |
| 1461 |
USBEndpoint *ep; |
| 1462 |
uint32_t i, len, pid, dir, devaddr, endp; |
| 1463 |
uint32_t pg, off, ptr1, ptr2, max, mult; |
| 1464 |
|
| 1465 |
ehci->periodic_sched_active = PERIODIC_ACTIVE; |
| 1466 |
|
| 1467 |
dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
|
| 1468 |
devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
|
| 1469 |
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
|
| 1470 |
max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
|
| 1471 |
mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
|
| 1472 |
|
| 1473 |
for(i = 0; i < 8; i++) { |
| 1474 |
if (itd->transact[i] & ITD_XACT_ACTIVE) {
|
| 1475 |
pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
| 1476 |
off = itd->transact[i] & ITD_XACT_OFFSET_MASK; |
| 1477 |
ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); |
| 1478 |
ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
|
| 1479 |
len = get_field(itd->transact[i], ITD_XACT_LENGTH); |
| 1480 |
|
| 1481 |
if (len > max * mult) {
|
| 1482 |
len = max * mult; |
| 1483 |
} |
| 1484 |
|
| 1485 |
if (len > BUFF_SIZE) {
|
| 1486 |
return -1; |
| 1487 |
} |
| 1488 |
|
| 1489 |
qemu_sglist_init(&ehci->isgl, DEVICE(ehci), 2, ehci->as);
|
| 1490 |
if (off + len > 4096) { |
| 1491 |
/* transfer crosses page border */
|
| 1492 |
uint32_t len2 = off + len - 4096;
|
| 1493 |
uint32_t len1 = len - len2; |
| 1494 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); |
| 1495 |
qemu_sglist_add(&ehci->isgl, ptr2, len2); |
| 1496 |
} else {
|
| 1497 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
| 1498 |
} |
| 1499 |
|
| 1500 |
pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
| 1501 |
|
| 1502 |
dev = ehci_find_device(ehci, devaddr); |
| 1503 |
ep = usb_ep_get(dev, pid, endp); |
| 1504 |
if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
|
| 1505 |
usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false, |
| 1506 |
(itd->transact[i] & ITD_XACT_IOC) != 0);
|
| 1507 |
usb_packet_map(&ehci->ipacket, &ehci->isgl); |
| 1508 |
usb_handle_packet(dev, &ehci->ipacket); |
| 1509 |
usb_packet_unmap(&ehci->ipacket, &ehci->isgl); |
| 1510 |
} else {
|
| 1511 |
DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
|
| 1512 |
ehci->ipacket.status = USB_RET_NAK; |
| 1513 |
ehci->ipacket.actual_length = 0;
|
| 1514 |
} |
| 1515 |
qemu_sglist_destroy(&ehci->isgl); |
| 1516 |
|
| 1517 |
switch (ehci->ipacket.status) {
|
| 1518 |
case USB_RET_SUCCESS:
|
| 1519 |
break;
|
| 1520 |
default:
|
| 1521 |
fprintf(stderr, "Unexpected iso usb result: %d\n",
|
| 1522 |
ehci->ipacket.status); |
| 1523 |
/* Fall through */
|
| 1524 |
case USB_RET_IOERROR:
|
| 1525 |
case USB_RET_NODEV:
|
| 1526 |
/* 3.3.2: XACTERR is only allowed on IN transactions */
|
| 1527 |
if (dir) {
|
| 1528 |
itd->transact[i] |= ITD_XACT_XACTERR; |
| 1529 |
ehci_raise_irq(ehci, USBSTS_ERRINT); |
| 1530 |
} |
| 1531 |
break;
|
| 1532 |
case USB_RET_BABBLE:
|
| 1533 |
itd->transact[i] |= ITD_XACT_BABBLE; |
| 1534 |
ehci_raise_irq(ehci, USBSTS_ERRINT); |
| 1535 |
break;
|
| 1536 |
case USB_RET_NAK:
|
| 1537 |
/* no data for us, so do a zero-length transfer */
|
| 1538 |
ehci->ipacket.actual_length = 0;
|
| 1539 |
break;
|
| 1540 |
} |
| 1541 |
if (!dir) {
|
| 1542 |
set_field(&itd->transact[i], len - ehci->ipacket.actual_length, |
| 1543 |
ITD_XACT_LENGTH); /* OUT */
|
| 1544 |
} else {
|
| 1545 |
set_field(&itd->transact[i], ehci->ipacket.actual_length, |
| 1546 |
ITD_XACT_LENGTH); /* IN */
|
| 1547 |
} |
| 1548 |
if (itd->transact[i] & ITD_XACT_IOC) {
|
| 1549 |
ehci_raise_irq(ehci, USBSTS_INT); |
| 1550 |
} |
| 1551 |
itd->transact[i] &= ~ITD_XACT_ACTIVE; |
| 1552 |
} |
| 1553 |
} |
| 1554 |
return 0; |
| 1555 |
} |
| 1556 |
|
| 1557 |
|
| 1558 |
/* This state is the entry point for asynchronous schedule
|
| 1559 |
* processing. Entry here consitutes a EHCI start event state (4.8.5)
|
| 1560 |
*/
|
| 1561 |
static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
| 1562 |
{
|
| 1563 |
EHCIqh qh; |
| 1564 |
int i = 0; |
| 1565 |
int again = 0; |
| 1566 |
uint32_t entry = ehci->asynclistaddr; |
| 1567 |
|
| 1568 |
/* set reclamation flag at start event (4.8.6) */
|
| 1569 |
if (async) {
|
| 1570 |
ehci_set_usbsts(ehci, USBSTS_REC); |
| 1571 |
} |
| 1572 |
|
| 1573 |
ehci_queues_rip_unused(ehci, async); |
| 1574 |
|
| 1575 |
/* Find the head of the list (4.9.1.1) */
|
| 1576 |
for(i = 0; i < MAX_QH; i++) { |
| 1577 |
if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
|
| 1578 |
sizeof(EHCIqh) >> 2) < 0) { |
| 1579 |
return 0; |
| 1580 |
} |
| 1581 |
ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
|
| 1582 |
|
| 1583 |
if (qh.epchar & QH_EPCHAR_H) {
|
| 1584 |
if (async) {
|
| 1585 |
entry |= (NLPTR_TYPE_QH << 1);
|
| 1586 |
} |
| 1587 |
|
| 1588 |
ehci_set_fetch_addr(ehci, async, entry); |
| 1589 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
| 1590 |
again = 1;
|
| 1591 |
goto out;
|
| 1592 |
} |
| 1593 |
|
| 1594 |
entry = qh.next; |
| 1595 |
if (entry == ehci->asynclistaddr) {
|
| 1596 |
break;
|
| 1597 |
} |
| 1598 |
} |
| 1599 |
|
| 1600 |
/* no head found for list. */
|
| 1601 |
|
| 1602 |
ehci_set_state(ehci, async, EST_ACTIVE); |
| 1603 |
|
| 1604 |
out:
|
| 1605 |
return again;
|
| 1606 |
} |
| 1607 |
|
| 1608 |
|
| 1609 |
/* This state is the entry point for periodic schedule processing as
|
| 1610 |
* well as being a continuation state for async processing.
|
| 1611 |
*/
|
| 1612 |
static int ehci_state_fetchentry(EHCIState *ehci, int async) |
| 1613 |
{
|
| 1614 |
int again = 0; |
| 1615 |
uint32_t entry = ehci_get_fetch_addr(ehci, async); |
| 1616 |
|
| 1617 |
if (NLPTR_TBIT(entry)) {
|
| 1618 |
ehci_set_state(ehci, async, EST_ACTIVE); |
| 1619 |
goto out;
|
| 1620 |
} |
| 1621 |
|
| 1622 |
/* section 4.8, only QH in async schedule */
|
| 1623 |
if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
|
| 1624 |
fprintf(stderr, "non queue head request in async schedule\n");
|
| 1625 |
return -1; |
| 1626 |
} |
| 1627 |
|
| 1628 |
switch (NLPTR_TYPE_GET(entry)) {
|
| 1629 |
case NLPTR_TYPE_QH:
|
| 1630 |
ehci_set_state(ehci, async, EST_FETCHQH); |
| 1631 |
again = 1;
|
| 1632 |
break;
|
| 1633 |
|
| 1634 |
case NLPTR_TYPE_ITD:
|
| 1635 |
ehci_set_state(ehci, async, EST_FETCHITD); |
| 1636 |
again = 1;
|
| 1637 |
break;
|
| 1638 |
|
| 1639 |
case NLPTR_TYPE_STITD:
|
| 1640 |
ehci_set_state(ehci, async, EST_FETCHSITD); |
| 1641 |
again = 1;
|
| 1642 |
break;
|
| 1643 |
|
| 1644 |
default:
|
| 1645 |
/* TODO: handle FSTN type */
|
| 1646 |
fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
|
| 1647 |
"which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
|
| 1648 |
return -1; |
| 1649 |
} |
| 1650 |
|
| 1651 |
out:
|
| 1652 |
return again;
|
| 1653 |
} |
| 1654 |
|
| 1655 |
static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
| 1656 |
{
|
| 1657 |
uint32_t entry; |
| 1658 |
EHCIQueue *q; |
| 1659 |
EHCIqh qh; |
| 1660 |
|
| 1661 |
entry = ehci_get_fetch_addr(ehci, async); |
| 1662 |
q = ehci_find_queue_by_qh(ehci, entry, async); |
| 1663 |
if (NULL == q) { |
| 1664 |
q = ehci_alloc_queue(ehci, entry, async); |
| 1665 |
} |
| 1666 |
|
| 1667 |
q->seen++; |
| 1668 |
if (q->seen > 1) { |
| 1669 |
/* we are going in circles -- stop processing */
|
| 1670 |
ehci_set_state(ehci, async, EST_ACTIVE); |
| 1671 |
q = NULL;
|
| 1672 |
goto out;
|
| 1673 |
} |
| 1674 |
|
| 1675 |
if (get_dwords(ehci, NLPTR_GET(q->qhaddr),
|
| 1676 |
(uint32_t *) &qh, sizeof(EHCIqh) >> 2) < 0) { |
| 1677 |
q = NULL;
|
| 1678 |
goto out;
|
| 1679 |
} |
| 1680 |
ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); |
| 1681 |
|
| 1682 |
/*
|
| 1683 |
* The overlay area of the qh should never be changed by the guest,
|
| 1684 |
* except when idle, in which case the reset is a nop.
|
| 1685 |
*/
|
| 1686 |
if (!ehci_verify_qh(q, &qh)) {
|
| 1687 |
if (ehci_reset_queue(q) > 0) { |
| 1688 |
ehci_trace_guest_bug(ehci, "guest updated active QH");
|
| 1689 |
} |
| 1690 |
} |
| 1691 |
q->qh = qh; |
| 1692 |
|
| 1693 |
q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
| 1694 |
if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */ |
| 1695 |
q->transact_ctr = 4;
|
| 1696 |
} |
| 1697 |
|
| 1698 |
if (q->dev == NULL) { |
| 1699 |
q->dev = ehci_find_device(q->ehci, |
| 1700 |
get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)); |
| 1701 |
} |
| 1702 |
|
| 1703 |
if (async && (q->qh.epchar & QH_EPCHAR_H)) {
|
| 1704 |
|
| 1705 |
/* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
|
| 1706 |
if (ehci->usbsts & USBSTS_REC) {
|
| 1707 |
ehci_clear_usbsts(ehci, USBSTS_REC); |
| 1708 |
} else {
|
| 1709 |
DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
|
| 1710 |
" - done processing\n", q->qhaddr);
|
| 1711 |
ehci_set_state(ehci, async, EST_ACTIVE); |
| 1712 |
q = NULL;
|
| 1713 |
goto out;
|
| 1714 |
} |
| 1715 |
} |
| 1716 |
|
| 1717 |
#if EHCI_DEBUG
|
| 1718 |
if (q->qhaddr != q->qh.next) {
|
| 1719 |
DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
|
| 1720 |
q->qhaddr, |
| 1721 |
q->qh.epchar & QH_EPCHAR_H, |
| 1722 |
q->qh.token & QTD_TOKEN_HALT, |
| 1723 |
q->qh.token & QTD_TOKEN_ACTIVE, |
| 1724 |
q->qh.next); |
| 1725 |
} |
| 1726 |
#endif
|
| 1727 |
|
| 1728 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
| 1729 |
ehci_set_state(ehci, async, EST_HORIZONTALQH); |
| 1730 |
|
| 1731 |
} else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
| 1732 |
(NLPTR_TBIT(q->qh.current_qtd) == 0)) {
|
| 1733 |
q->qtdaddr = q->qh.current_qtd; |
| 1734 |
ehci_set_state(ehci, async, EST_FETCHQTD); |
| 1735 |
|
| 1736 |
} else {
|
| 1737 |
/* EHCI spec version 1.0 Section 4.10.2 */
|
| 1738 |
ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
| 1739 |
} |
| 1740 |
|
| 1741 |
out:
|
| 1742 |
return q;
|
| 1743 |
} |
| 1744 |
|
| 1745 |
static int ehci_state_fetchitd(EHCIState *ehci, int async) |
| 1746 |
{
|
| 1747 |
uint32_t entry; |
| 1748 |
EHCIitd itd; |
| 1749 |
|
| 1750 |
assert(!async); |
| 1751 |
entry = ehci_get_fetch_addr(ehci, async); |
| 1752 |
|
| 1753 |
if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
|
| 1754 |
sizeof(EHCIitd) >> 2) < 0) { |
| 1755 |
return -1; |
| 1756 |
} |
| 1757 |
ehci_trace_itd(ehci, entry, &itd); |
| 1758 |
|
| 1759 |
if (ehci_process_itd(ehci, &itd, entry) != 0) { |
| 1760 |
return -1; |
| 1761 |
} |
| 1762 |
|
| 1763 |
put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
| 1764 |
sizeof(EHCIitd) >> 2); |
| 1765 |
ehci_set_fetch_addr(ehci, async, itd.next); |
| 1766 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
| 1767 |
|
| 1768 |
return 1; |
| 1769 |
} |
| 1770 |
|
| 1771 |
static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
| 1772 |
{
|
| 1773 |
uint32_t entry; |
| 1774 |
EHCIsitd sitd; |
| 1775 |
|
| 1776 |
assert(!async); |
| 1777 |
entry = ehci_get_fetch_addr(ehci, async); |
| 1778 |
|
| 1779 |
if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
|
| 1780 |
sizeof(EHCIsitd) >> 2) < 0) { |
| 1781 |
return 0; |
| 1782 |
} |
| 1783 |
ehci_trace_sitd(ehci, entry, &sitd); |
| 1784 |
|
| 1785 |
if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
|
| 1786 |
/* siTD is not active, nothing to do */;
|
| 1787 |
} else {
|
| 1788 |
/* TODO: split transfers are not implemented */
|
| 1789 |
fprintf(stderr, "WARNING: Skipping active siTD\n");
|
| 1790 |
} |
| 1791 |
|
| 1792 |
ehci_set_fetch_addr(ehci, async, sitd.next); |
| 1793 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
| 1794 |
return 1; |
| 1795 |
} |
| 1796 |
|
| 1797 |
/* Section 4.10.2 - paragraph 3 */
|
| 1798 |
static int ehci_state_advqueue(EHCIQueue *q) |
| 1799 |
{
|
| 1800 |
#if 0
|
| 1801 |
/* TO-DO: 4.10.2 - paragraph 2
|
| 1802 |
* if I-bit is set to 1 and QH is not active
|
| 1803 |
* go to horizontal QH
|
| 1804 |
*/
|
| 1805 |
if (I-bit set) {
|
| 1806 |
ehci_set_state(ehci, async, EST_HORIZONTALQH);
|
| 1807 |
goto out;
|
| 1808 |
}
|
| 1809 |
#endif
|
| 1810 |
|
| 1811 |
/*
|
| 1812 |
* want data and alt-next qTD is valid
|
| 1813 |
*/
|
| 1814 |
if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
| 1815 |
(NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
|
| 1816 |
q->qtdaddr = q->qh.altnext_qtd; |
| 1817 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
| 1818 |
|
| 1819 |
/*
|
| 1820 |
* next qTD is valid
|
| 1821 |
*/
|
| 1822 |
} else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
| 1823 |
q->qtdaddr = q->qh.next_qtd; |
| 1824 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
| 1825 |
|
| 1826 |
/*
|
| 1827 |
* no valid qTD, try next QH
|
| 1828 |
*/
|
| 1829 |
} else {
|
| 1830 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 1831 |
} |
| 1832 |
|
| 1833 |
return 1; |
| 1834 |
} |
| 1835 |
|
| 1836 |
/* Section 4.10.2 - paragraph 4 */
|
| 1837 |
static int ehci_state_fetchqtd(EHCIQueue *q) |
| 1838 |
{
|
| 1839 |
EHCIqtd qtd; |
| 1840 |
EHCIPacket *p; |
| 1841 |
int again = 1; |
| 1842 |
|
| 1843 |
if (get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
|
| 1844 |
sizeof(EHCIqtd) >> 2) < 0) { |
| 1845 |
return 0; |
| 1846 |
} |
| 1847 |
ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
| 1848 |
|
| 1849 |
p = QTAILQ_FIRST(&q->packets); |
| 1850 |
if (p != NULL) { |
| 1851 |
if (!ehci_verify_qtd(p, &qtd)) {
|
| 1852 |
ehci_cancel_queue(q); |
| 1853 |
if (qtd.token & QTD_TOKEN_ACTIVE) {
|
| 1854 |
ehci_trace_guest_bug(q->ehci, "guest updated active qTD");
|
| 1855 |
} |
| 1856 |
p = NULL;
|
| 1857 |
} else {
|
| 1858 |
p->qtd = qtd; |
| 1859 |
ehci_qh_do_overlay(q); |
| 1860 |
} |
| 1861 |
} |
| 1862 |
|
| 1863 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
| 1864 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 1865 |
} else if (p != NULL) { |
| 1866 |
switch (p->async) {
|
| 1867 |
case EHCI_ASYNC_NONE:
|
| 1868 |
case EHCI_ASYNC_INITIALIZED:
|
| 1869 |
/* Not yet executed (MULT), or previously nacked (int) packet */
|
| 1870 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
| 1871 |
break;
|
| 1872 |
case EHCI_ASYNC_INFLIGHT:
|
| 1873 |
/* Check if the guest has added new tds to the queue */
|
| 1874 |
again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head)); |
| 1875 |
/* Unfinished async handled packet, go horizontal */
|
| 1876 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 1877 |
break;
|
| 1878 |
case EHCI_ASYNC_FINISHED:
|
| 1879 |
/* Complete executing of the packet */
|
| 1880 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
| 1881 |
break;
|
| 1882 |
} |
| 1883 |
} else {
|
| 1884 |
p = ehci_alloc_packet(q); |
| 1885 |
p->qtdaddr = q->qtdaddr; |
| 1886 |
p->qtd = qtd; |
| 1887 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
| 1888 |
} |
| 1889 |
|
| 1890 |
return again;
|
| 1891 |
} |
| 1892 |
|
| 1893 |
static int ehci_state_horizqh(EHCIQueue *q) |
| 1894 |
{
|
| 1895 |
int again = 0; |
| 1896 |
|
| 1897 |
if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
|
| 1898 |
ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); |
| 1899 |
ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); |
| 1900 |
again = 1;
|
| 1901 |
} else {
|
| 1902 |
ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
| 1903 |
} |
| 1904 |
|
| 1905 |
return again;
|
| 1906 |
} |
| 1907 |
|
| 1908 |
/* Returns "again" */
|
| 1909 |
static int ehci_fill_queue(EHCIPacket *p) |
| 1910 |
{
|
| 1911 |
USBEndpoint *ep = p->packet.ep; |
| 1912 |
EHCIQueue *q = p->queue; |
| 1913 |
EHCIqtd qtd = p->qtd; |
| 1914 |
uint32_t qtdaddr; |
| 1915 |
|
| 1916 |
for (;;) {
|
| 1917 |
if (NLPTR_TBIT(qtd.next) != 0) { |
| 1918 |
break;
|
| 1919 |
} |
| 1920 |
qtdaddr = qtd.next; |
| 1921 |
/*
|
| 1922 |
* Detect circular td lists, Windows creates these, counting on the
|
| 1923 |
* active bit going low after execution to make the queue stop.
|
| 1924 |
*/
|
| 1925 |
QTAILQ_FOREACH(p, &q->packets, next) {
|
| 1926 |
if (p->qtdaddr == qtdaddr) {
|
| 1927 |
goto leave;
|
| 1928 |
} |
| 1929 |
} |
| 1930 |
if (get_dwords(q->ehci, NLPTR_GET(qtdaddr),
|
| 1931 |
(uint32_t *) &qtd, sizeof(EHCIqtd) >> 2) < 0) { |
| 1932 |
return -1; |
| 1933 |
} |
| 1934 |
ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); |
| 1935 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
| 1936 |
break;
|
| 1937 |
} |
| 1938 |
if (!ehci_verify_pid(q, &qtd)) {
|
| 1939 |
ehci_trace_guest_bug(q->ehci, "guest queued token with wrong pid");
|
| 1940 |
break;
|
| 1941 |
} |
| 1942 |
p = ehci_alloc_packet(q); |
| 1943 |
p->qtdaddr = qtdaddr; |
| 1944 |
p->qtd = qtd; |
| 1945 |
if (ehci_execute(p, "queue") == -1) { |
| 1946 |
return -1; |
| 1947 |
} |
| 1948 |
assert(p->packet.status == USB_RET_ASYNC); |
| 1949 |
p->async = EHCI_ASYNC_INFLIGHT; |
| 1950 |
} |
| 1951 |
leave:
|
| 1952 |
usb_device_flush_ep_queue(ep->dev, ep); |
| 1953 |
return 1; |
| 1954 |
} |
| 1955 |
|
| 1956 |
static int ehci_state_execute(EHCIQueue *q) |
| 1957 |
{
|
| 1958 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
| 1959 |
int again = 0; |
| 1960 |
|
| 1961 |
assert(p != NULL);
|
| 1962 |
assert(p->qtdaddr == q->qtdaddr); |
| 1963 |
|
| 1964 |
if (ehci_qh_do_overlay(q) != 0) { |
| 1965 |
return -1; |
| 1966 |
} |
| 1967 |
|
| 1968 |
// TODO verify enough time remains in the uframe as in 4.4.1.1
|
| 1969 |
// TODO write back ptr to async list when done or out of time
|
| 1970 |
|
| 1971 |
/* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
|
| 1972 |
if (!q->async && q->transact_ctr == 0) { |
| 1973 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 1974 |
again = 1;
|
| 1975 |
goto out;
|
| 1976 |
} |
| 1977 |
|
| 1978 |
if (q->async) {
|
| 1979 |
ehci_set_usbsts(q->ehci, USBSTS_REC); |
| 1980 |
} |
| 1981 |
|
| 1982 |
again = ehci_execute(p, "process");
|
| 1983 |
if (again == -1) { |
| 1984 |
goto out;
|
| 1985 |
} |
| 1986 |
if (p->packet.status == USB_RET_ASYNC) {
|
| 1987 |
ehci_flush_qh(q); |
| 1988 |
trace_usb_ehci_packet_action(p->queue, p, "async");
|
| 1989 |
p->async = EHCI_ASYNC_INFLIGHT; |
| 1990 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 1991 |
if (q->async) {
|
| 1992 |
again = ehci_fill_queue(p); |
| 1993 |
} else {
|
| 1994 |
again = 1;
|
| 1995 |
} |
| 1996 |
goto out;
|
| 1997 |
} |
| 1998 |
|
| 1999 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
| 2000 |
again = 1;
|
| 2001 |
|
| 2002 |
out:
|
| 2003 |
return again;
|
| 2004 |
} |
| 2005 |
|
| 2006 |
static int ehci_state_executing(EHCIQueue *q) |
| 2007 |
{
|
| 2008 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
| 2009 |
|
| 2010 |
assert(p != NULL);
|
| 2011 |
assert(p->qtdaddr == q->qtdaddr); |
| 2012 |
|
| 2013 |
ehci_execute_complete(q); |
| 2014 |
|
| 2015 |
/* 4.10.3 */
|
| 2016 |
if (!q->async && q->transact_ctr > 0) { |
| 2017 |
q->transact_ctr--; |
| 2018 |
} |
| 2019 |
|
| 2020 |
/* 4.10.5 */
|
| 2021 |
if (p->packet.status == USB_RET_NAK) {
|
| 2022 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 2023 |
} else {
|
| 2024 |
ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
| 2025 |
} |
| 2026 |
|
| 2027 |
ehci_flush_qh(q); |
| 2028 |
return 1; |
| 2029 |
} |
| 2030 |
|
| 2031 |
|
| 2032 |
static int ehci_state_writeback(EHCIQueue *q) |
| 2033 |
{
|
| 2034 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
| 2035 |
uint32_t *qtd, addr; |
| 2036 |
int again = 0; |
| 2037 |
|
| 2038 |
/* Write back the QTD from the QH area */
|
| 2039 |
assert(p != NULL);
|
| 2040 |
assert(p->qtdaddr == q->qtdaddr); |
| 2041 |
|
| 2042 |
ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); |
| 2043 |
qtd = (uint32_t *) &q->qh.next_qtd; |
| 2044 |
addr = NLPTR_GET(p->qtdaddr); |
| 2045 |
put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); |
| 2046 |
ehci_free_packet(p); |
| 2047 |
|
| 2048 |
/*
|
| 2049 |
* EHCI specs say go horizontal here.
|
| 2050 |
*
|
| 2051 |
* We can also advance the queue here for performance reasons. We
|
| 2052 |
* need to take care to only take that shortcut in case we've
|
| 2053 |
* processed the qtd just written back without errors, i.e. halt
|
| 2054 |
* bit is clear.
|
| 2055 |
*/
|
| 2056 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
| 2057 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
| 2058 |
again = 1;
|
| 2059 |
} else {
|
| 2060 |
ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
| 2061 |
again = 1;
|
| 2062 |
} |
| 2063 |
return again;
|
| 2064 |
} |
| 2065 |
|
| 2066 |
/*
|
| 2067 |
* This is the state machine that is common to both async and periodic
|
| 2068 |
*/
|
| 2069 |
|
| 2070 |
static void ehci_advance_state(EHCIState *ehci, int async) |
| 2071 |
{
|
| 2072 |
EHCIQueue *q = NULL;
|
| 2073 |
int again;
|
| 2074 |
|
| 2075 |
do {
|
| 2076 |
switch(ehci_get_state(ehci, async)) {
|
| 2077 |
case EST_WAITLISTHEAD:
|
| 2078 |
again = ehci_state_waitlisthead(ehci, async); |
| 2079 |
break;
|
| 2080 |
|
| 2081 |
case EST_FETCHENTRY:
|
| 2082 |
again = ehci_state_fetchentry(ehci, async); |
| 2083 |
break;
|
| 2084 |
|
| 2085 |
case EST_FETCHQH:
|
| 2086 |
q = ehci_state_fetchqh(ehci, async); |
| 2087 |
if (q != NULL) { |
| 2088 |
assert(q->async == async); |
| 2089 |
again = 1;
|
| 2090 |
} else {
|
| 2091 |
again = 0;
|
| 2092 |
} |
| 2093 |
break;
|
| 2094 |
|
| 2095 |
case EST_FETCHITD:
|
| 2096 |
again = ehci_state_fetchitd(ehci, async); |
| 2097 |
break;
|
| 2098 |
|
| 2099 |
case EST_FETCHSITD:
|
| 2100 |
again = ehci_state_fetchsitd(ehci, async); |
| 2101 |
break;
|
| 2102 |
|
| 2103 |
case EST_ADVANCEQUEUE:
|
| 2104 |
assert(q != NULL);
|
| 2105 |
again = ehci_state_advqueue(q); |
| 2106 |
break;
|
| 2107 |
|
| 2108 |
case EST_FETCHQTD:
|
| 2109 |
assert(q != NULL);
|
| 2110 |
again = ehci_state_fetchqtd(q); |
| 2111 |
break;
|
| 2112 |
|
| 2113 |
case EST_HORIZONTALQH:
|
| 2114 |
assert(q != NULL);
|
| 2115 |
again = ehci_state_horizqh(q); |
| 2116 |
break;
|
| 2117 |
|
| 2118 |
case EST_EXECUTE:
|
| 2119 |
assert(q != NULL);
|
| 2120 |
again = ehci_state_execute(q); |
| 2121 |
if (async) {
|
| 2122 |
ehci->async_stepdown = 0;
|
| 2123 |
} |
| 2124 |
break;
|
| 2125 |
|
| 2126 |
case EST_EXECUTING:
|
| 2127 |
assert(q != NULL);
|
| 2128 |
if (async) {
|
| 2129 |
ehci->async_stepdown = 0;
|
| 2130 |
} |
| 2131 |
again = ehci_state_executing(q); |
| 2132 |
break;
|
| 2133 |
|
| 2134 |
case EST_WRITEBACK:
|
| 2135 |
assert(q != NULL);
|
| 2136 |
again = ehci_state_writeback(q); |
| 2137 |
if (!async) {
|
| 2138 |
ehci->periodic_sched_active = PERIODIC_ACTIVE; |
| 2139 |
} |
| 2140 |
break;
|
| 2141 |
|
| 2142 |
default:
|
| 2143 |
fprintf(stderr, "Bad state!\n");
|
| 2144 |
again = -1;
|
| 2145 |
assert(0);
|
| 2146 |
break;
|
| 2147 |
} |
| 2148 |
|
| 2149 |
if (again < 0) { |
| 2150 |
fprintf(stderr, "processing error - resetting ehci HC\n");
|
| 2151 |
ehci_reset(ehci); |
| 2152 |
again = 0;
|
| 2153 |
} |
| 2154 |
} |
| 2155 |
while (again);
|
| 2156 |
} |
| 2157 |
|
| 2158 |
static void ehci_advance_async_state(EHCIState *ehci) |
| 2159 |
{
|
| 2160 |
const int async = 1; |
| 2161 |
|
| 2162 |
switch(ehci_get_state(ehci, async)) {
|
| 2163 |
case EST_INACTIVE:
|
| 2164 |
if (!ehci_async_enabled(ehci)) {
|
| 2165 |
break;
|
| 2166 |
} |
| 2167 |
ehci_set_state(ehci, async, EST_ACTIVE); |
| 2168 |
// No break, fall through to ACTIVE
|
| 2169 |
|
| 2170 |
case EST_ACTIVE:
|
| 2171 |
if (!ehci_async_enabled(ehci)) {
|
| 2172 |
ehci_queues_rip_all(ehci, async); |
| 2173 |
ehci_set_state(ehci, async, EST_INACTIVE); |
| 2174 |
break;
|
| 2175 |
} |
| 2176 |
|
| 2177 |
/* make sure guest has acknowledged the doorbell interrupt */
|
| 2178 |
/* TO-DO: is this really needed? */
|
| 2179 |
if (ehci->usbsts & USBSTS_IAA) {
|
| 2180 |
DPRINTF("IAA status bit still set.\n");
|
| 2181 |
break;
|
| 2182 |
} |
| 2183 |
|
| 2184 |
/* check that address register has been set */
|
| 2185 |
if (ehci->asynclistaddr == 0) { |
| 2186 |
break;
|
| 2187 |
} |
| 2188 |
|
| 2189 |
ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
| 2190 |
ehci_advance_state(ehci, async); |
| 2191 |
|
| 2192 |
/* If the doorbell is set, the guest wants to make a change to the
|
| 2193 |
* schedule. The host controller needs to release cached data.
|
| 2194 |
* (section 4.8.2)
|
| 2195 |
*/
|
| 2196 |
if (ehci->usbcmd & USBCMD_IAAD) {
|
| 2197 |
/* Remove all unseen qhs from the async qhs queue */
|
| 2198 |
ehci_queues_rip_unseen(ehci, async); |
| 2199 |
trace_usb_ehci_doorbell_ack(); |
| 2200 |
ehci->usbcmd &= ~USBCMD_IAAD; |
| 2201 |
ehci_raise_irq(ehci, USBSTS_IAA); |
| 2202 |
} |
| 2203 |
break;
|
| 2204 |
|
| 2205 |
default:
|
| 2206 |
/* this should only be due to a developer mistake */
|
| 2207 |
fprintf(stderr, "ehci: Bad asynchronous state %d. "
|
| 2208 |
"Resetting to active\n", ehci->astate);
|
| 2209 |
assert(0);
|
| 2210 |
} |
| 2211 |
} |
| 2212 |
|
| 2213 |
static void ehci_advance_periodic_state(EHCIState *ehci) |
| 2214 |
{
|
| 2215 |
uint32_t entry; |
| 2216 |
uint32_t list; |
| 2217 |
const int async = 0; |
| 2218 |
|
| 2219 |
// 4.6
|
| 2220 |
|
| 2221 |
switch(ehci_get_state(ehci, async)) {
|
| 2222 |
case EST_INACTIVE:
|
| 2223 |
if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
| 2224 |
ehci_set_state(ehci, async, EST_ACTIVE); |
| 2225 |
// No break, fall through to ACTIVE
|
| 2226 |
} else
|
| 2227 |
break;
|
| 2228 |
|
| 2229 |
case EST_ACTIVE:
|
| 2230 |
if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
| 2231 |
ehci_queues_rip_all(ehci, async); |
| 2232 |
ehci_set_state(ehci, async, EST_INACTIVE); |
| 2233 |
break;
|
| 2234 |
} |
| 2235 |
|
| 2236 |
list = ehci->periodiclistbase & 0xfffff000;
|
| 2237 |
/* check that register has been set */
|
| 2238 |
if (list == 0) { |
| 2239 |
break;
|
| 2240 |
} |
| 2241 |
list |= ((ehci->frindex & 0x1ff8) >> 1); |
| 2242 |
|
| 2243 |
if (get_dwords(ehci, list, &entry, 1) < 0) { |
| 2244 |
break;
|
| 2245 |
} |
| 2246 |
|
| 2247 |
DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
|
| 2248 |
ehci->frindex / 8, list, entry);
|
| 2249 |
ehci_set_fetch_addr(ehci, async,entry); |
| 2250 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
| 2251 |
ehci_advance_state(ehci, async); |
| 2252 |
ehci_queues_rip_unused(ehci, async); |
| 2253 |
break;
|
| 2254 |
|
| 2255 |
default:
|
| 2256 |
/* this should only be due to a developer mistake */
|
| 2257 |
fprintf(stderr, "ehci: Bad periodic state %d. "
|
| 2258 |
"Resetting to active\n", ehci->pstate);
|
| 2259 |
assert(0);
|
| 2260 |
} |
| 2261 |
} |
| 2262 |
|
| 2263 |
static void ehci_update_frindex(EHCIState *ehci, int uframes) |
| 2264 |
{
|
| 2265 |
int i;
|
| 2266 |
|
| 2267 |
if (!ehci_enabled(ehci) && ehci->pstate == EST_INACTIVE) {
|
| 2268 |
return;
|
| 2269 |
} |
| 2270 |
|
| 2271 |
for (i = 0; i < uframes; i++) { |
| 2272 |
ehci->frindex++; |
| 2273 |
|
| 2274 |
if (ehci->frindex == 0x00002000) { |
| 2275 |
ehci_raise_irq(ehci, USBSTS_FLR); |
| 2276 |
} |
| 2277 |
|
| 2278 |
if (ehci->frindex == 0x00004000) { |
| 2279 |
ehci_raise_irq(ehci, USBSTS_FLR); |
| 2280 |
ehci->frindex = 0;
|
| 2281 |
if (ehci->usbsts_frindex >= 0x00004000) { |
| 2282 |
ehci->usbsts_frindex -= 0x00004000;
|
| 2283 |
} else {
|
| 2284 |
ehci->usbsts_frindex = 0;
|
| 2285 |
} |
| 2286 |
} |
| 2287 |
} |
| 2288 |
} |
| 2289 |
|
| 2290 |
static void ehci_frame_timer(void *opaque) |
| 2291 |
{
|
| 2292 |
EHCIState *ehci = opaque; |
| 2293 |
int need_timer = 0; |
| 2294 |
int64_t expire_time, t_now; |
| 2295 |
uint64_t ns_elapsed; |
| 2296 |
int uframes, skipped_uframes;
|
| 2297 |
int i;
|
| 2298 |
|
| 2299 |
t_now = qemu_get_clock_ns(vm_clock); |
| 2300 |
ns_elapsed = t_now - ehci->last_run_ns; |
| 2301 |
uframes = ns_elapsed / UFRAME_TIMER_NS; |
| 2302 |
|
| 2303 |
if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
|
| 2304 |
need_timer++; |
| 2305 |
|
| 2306 |
if (uframes > (ehci->maxframes * 8)) { |
| 2307 |
skipped_uframes = uframes - (ehci->maxframes * 8);
|
| 2308 |
ehci_update_frindex(ehci, skipped_uframes); |
| 2309 |
ehci->last_run_ns += UFRAME_TIMER_NS * skipped_uframes; |
| 2310 |
uframes -= skipped_uframes; |
| 2311 |
DPRINTF("WARNING - EHCI skipped %d uframes\n", skipped_uframes);
|
| 2312 |
} |
| 2313 |
|
| 2314 |
for (i = 0; i < uframes; i++) { |
| 2315 |
/*
|
| 2316 |
* If we're running behind schedule, we should not catch up
|
| 2317 |
* too fast, as that will make some guests unhappy:
|
| 2318 |
* 1) We must process a minimum of MIN_UFR_PER_TICK frames,
|
| 2319 |
* otherwise we will never catch up
|
| 2320 |
* 2) Process frames until the guest has requested an irq (IOC)
|
| 2321 |
*/
|
| 2322 |
if (i >= MIN_UFR_PER_TICK) {
|
| 2323 |
ehci_commit_irq(ehci); |
| 2324 |
if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
|
| 2325 |
break;
|
| 2326 |
} |
| 2327 |
} |
| 2328 |
if (ehci->periodic_sched_active) {
|
| 2329 |
ehci->periodic_sched_active--; |
| 2330 |
} |
| 2331 |
ehci_update_frindex(ehci, 1);
|
| 2332 |
if ((ehci->frindex & 7) == 0) { |
| 2333 |
ehci_advance_periodic_state(ehci); |
| 2334 |
} |
| 2335 |
ehci->last_run_ns += UFRAME_TIMER_NS; |
| 2336 |
} |
| 2337 |
} else {
|
| 2338 |
ehci->periodic_sched_active = 0;
|
| 2339 |
ehci_update_frindex(ehci, uframes); |
| 2340 |
ehci->last_run_ns += UFRAME_TIMER_NS * uframes; |
| 2341 |
} |
| 2342 |
|
| 2343 |
if (ehci->periodic_sched_active) {
|
| 2344 |
ehci->async_stepdown = 0;
|
| 2345 |
} else if (ehci->async_stepdown < ehci->maxframes / 2) { |
| 2346 |
ehci->async_stepdown++; |
| 2347 |
} |
| 2348 |
|
| 2349 |
/* Async is not inside loop since it executes everything it can once
|
| 2350 |
* called
|
| 2351 |
*/
|
| 2352 |
if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
|
| 2353 |
need_timer++; |
| 2354 |
ehci_advance_async_state(ehci); |
| 2355 |
} |
| 2356 |
|
| 2357 |
ehci_commit_irq(ehci); |
| 2358 |
if (ehci->usbsts_pending) {
|
| 2359 |
need_timer++; |
| 2360 |
ehci->async_stepdown = 0;
|
| 2361 |
} |
| 2362 |
|
| 2363 |
if (ehci_enabled(ehci) && (ehci->usbintr & USBSTS_FLR)) {
|
| 2364 |
need_timer++; |
| 2365 |
} |
| 2366 |
|
| 2367 |
if (need_timer) {
|
| 2368 |
/* If we've raised int, we speed up the timer, so that we quickly
|
| 2369 |
* notice any new packets queued up in response */
|
| 2370 |
if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
|
| 2371 |
expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 4);
|
| 2372 |
ehci->int_req_by_async = false;
|
| 2373 |
} else {
|
| 2374 |
expire_time = t_now + (get_ticks_per_sec() |
| 2375 |
* (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
|
| 2376 |
} |
| 2377 |
qemu_mod_timer(ehci->frame_timer, expire_time); |
| 2378 |
} |
| 2379 |
} |
| 2380 |
|
| 2381 |
static const MemoryRegionOps ehci_mmio_caps_ops = { |
| 2382 |
.read = ehci_caps_read, |
| 2383 |
.valid.min_access_size = 1,
|
| 2384 |
.valid.max_access_size = 4,
|
| 2385 |
.impl.min_access_size = 1,
|
| 2386 |
.impl.max_access_size = 1,
|
| 2387 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2388 |
}; |
| 2389 |
|
| 2390 |
static const MemoryRegionOps ehci_mmio_opreg_ops = { |
| 2391 |
.read = ehci_opreg_read, |
| 2392 |
.write = ehci_opreg_write, |
| 2393 |
.valid.min_access_size = 4,
|
| 2394 |
.valid.max_access_size = 4,
|
| 2395 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2396 |
}; |
| 2397 |
|
| 2398 |
static const MemoryRegionOps ehci_mmio_port_ops = { |
| 2399 |
.read = ehci_port_read, |
| 2400 |
.write = ehci_port_write, |
| 2401 |
.valid.min_access_size = 4,
|
| 2402 |
.valid.max_access_size = 4,
|
| 2403 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2404 |
}; |
| 2405 |
|
| 2406 |
static USBPortOps ehci_port_ops = {
|
| 2407 |
.attach = ehci_attach, |
| 2408 |
.detach = ehci_detach, |
| 2409 |
.child_detach = ehci_child_detach, |
| 2410 |
.wakeup = ehci_wakeup, |
| 2411 |
.complete = ehci_async_complete_packet, |
| 2412 |
}; |
| 2413 |
|
| 2414 |
static USBBusOps ehci_bus_ops = {
|
| 2415 |
.register_companion = ehci_register_companion, |
| 2416 |
.wakeup_endpoint = ehci_wakeup_endpoint, |
| 2417 |
}; |
| 2418 |
|
| 2419 |
static void usb_ehci_pre_save(void *opaque) |
| 2420 |
{
|
| 2421 |
EHCIState *ehci = opaque; |
| 2422 |
uint32_t new_frindex; |
| 2423 |
|
| 2424 |
/* Round down frindex to a multiple of 8 for migration compatibility */
|
| 2425 |
new_frindex = ehci->frindex & ~7;
|
| 2426 |
ehci->last_run_ns -= (ehci->frindex - new_frindex) * UFRAME_TIMER_NS; |
| 2427 |
ehci->frindex = new_frindex; |
| 2428 |
} |
| 2429 |
|
| 2430 |
static int usb_ehci_post_load(void *opaque, int version_id) |
| 2431 |
{
|
| 2432 |
EHCIState *s = opaque; |
| 2433 |
int i;
|
| 2434 |
|
| 2435 |
for (i = 0; i < NB_PORTS; i++) { |
| 2436 |
USBPort *companion = s->companion_ports[i]; |
| 2437 |
if (companion == NULL) { |
| 2438 |
continue;
|
| 2439 |
} |
| 2440 |
if (s->portsc[i] & PORTSC_POWNER) {
|
| 2441 |
companion->dev = s->ports[i].dev; |
| 2442 |
} else {
|
| 2443 |
companion->dev = NULL;
|
| 2444 |
} |
| 2445 |
} |
| 2446 |
|
| 2447 |
return 0; |
| 2448 |
} |
| 2449 |
|
| 2450 |
static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) |
| 2451 |
{
|
| 2452 |
EHCIState *ehci = opaque; |
| 2453 |
|
| 2454 |
/*
|
| 2455 |
* We don't migrate the EHCIQueue-s, instead we rebuild them for the
|
| 2456 |
* schedule in guest memory. We must do the rebuilt ASAP, so that
|
| 2457 |
* USB-devices which have async handled packages have a packet in the
|
| 2458 |
* ep queue to match the completion with.
|
| 2459 |
*/
|
| 2460 |
if (state == RUN_STATE_RUNNING) {
|
| 2461 |
ehci_advance_async_state(ehci); |
| 2462 |
} |
| 2463 |
|
| 2464 |
/*
|
| 2465 |
* The schedule rebuilt from guest memory could cause the migration dest
|
| 2466 |
* to miss a QH unlink, and fail to cancel packets, since the unlinked QH
|
| 2467 |
* will never have existed on the destination. Therefor we must flush the
|
| 2468 |
* async schedule on savevm to catch any not yet noticed unlinks.
|
| 2469 |
*/
|
| 2470 |
if (state == RUN_STATE_SAVE_VM) {
|
| 2471 |
ehci_advance_async_state(ehci); |
| 2472 |
ehci_queues_rip_unseen(ehci, 1);
|
| 2473 |
} |
| 2474 |
} |
| 2475 |
|
| 2476 |
const VMStateDescription vmstate_ehci = {
|
| 2477 |
.name = "ehci-core",
|
| 2478 |
.version_id = 2,
|
| 2479 |
.minimum_version_id = 1,
|
| 2480 |
.pre_save = usb_ehci_pre_save, |
| 2481 |
.post_load = usb_ehci_post_load, |
| 2482 |
.fields = (VMStateField[]) {
|
| 2483 |
/* mmio registers */
|
| 2484 |
VMSTATE_UINT32(usbcmd, EHCIState), |
| 2485 |
VMSTATE_UINT32(usbsts, EHCIState), |
| 2486 |
VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
|
| 2487 |
VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
|
| 2488 |
VMSTATE_UINT32(usbintr, EHCIState), |
| 2489 |
VMSTATE_UINT32(frindex, EHCIState), |
| 2490 |
VMSTATE_UINT32(ctrldssegment, EHCIState), |
| 2491 |
VMSTATE_UINT32(periodiclistbase, EHCIState), |
| 2492 |
VMSTATE_UINT32(asynclistaddr, EHCIState), |
| 2493 |
VMSTATE_UINT32(configflag, EHCIState), |
| 2494 |
VMSTATE_UINT32(portsc[0], EHCIState),
|
| 2495 |
VMSTATE_UINT32(portsc[1], EHCIState),
|
| 2496 |
VMSTATE_UINT32(portsc[2], EHCIState),
|
| 2497 |
VMSTATE_UINT32(portsc[3], EHCIState),
|
| 2498 |
VMSTATE_UINT32(portsc[4], EHCIState),
|
| 2499 |
VMSTATE_UINT32(portsc[5], EHCIState),
|
| 2500 |
/* frame timer */
|
| 2501 |
VMSTATE_TIMER(frame_timer, EHCIState), |
| 2502 |
VMSTATE_UINT64(last_run_ns, EHCIState), |
| 2503 |
VMSTATE_UINT32(async_stepdown, EHCIState), |
| 2504 |
/* schedule state */
|
| 2505 |
VMSTATE_UINT32(astate, EHCIState), |
| 2506 |
VMSTATE_UINT32(pstate, EHCIState), |
| 2507 |
VMSTATE_UINT32(a_fetch_addr, EHCIState), |
| 2508 |
VMSTATE_UINT32(p_fetch_addr, EHCIState), |
| 2509 |
VMSTATE_END_OF_LIST() |
| 2510 |
} |
| 2511 |
}; |
| 2512 |
|
| 2513 |
void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)
|
| 2514 |
{
|
| 2515 |
int i;
|
| 2516 |
|
| 2517 |
if (s->portnr > NB_PORTS) {
|
| 2518 |
error_setg(errp, "Too many ports! Max. port number is %d.",
|
| 2519 |
NB_PORTS); |
| 2520 |
return;
|
| 2521 |
} |
| 2522 |
|
| 2523 |
usb_bus_new(&s->bus, &ehci_bus_ops, dev); |
| 2524 |
for (i = 0; i < s->portnr; i++) { |
| 2525 |
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, |
| 2526 |
USB_SPEED_MASK_HIGH); |
| 2527 |
s->ports[i].dev = 0;
|
| 2528 |
} |
| 2529 |
|
| 2530 |
s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); |
| 2531 |
s->async_bh = qemu_bh_new(ehci_frame_timer, s); |
| 2532 |
|
| 2533 |
qemu_register_reset(ehci_reset, s); |
| 2534 |
qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s); |
| 2535 |
} |
| 2536 |
|
| 2537 |
void usb_ehci_init(EHCIState *s, DeviceState *dev)
|
| 2538 |
{
|
| 2539 |
/* 2.2 host controller interface version */
|
| 2540 |
s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
|
| 2541 |
s->caps[0x01] = 0x00; |
| 2542 |
s->caps[0x02] = 0x00; |
| 2543 |
s->caps[0x03] = 0x01; /* HC version */ |
| 2544 |
s->caps[0x04] = s->portnr; /* Number of downstream ports */ |
| 2545 |
s->caps[0x05] = 0x00; /* No companion ports at present */ |
| 2546 |
s->caps[0x06] = 0x00; |
| 2547 |
s->caps[0x07] = 0x00; |
| 2548 |
s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ |
| 2549 |
s->caps[0x0a] = 0x00; |
| 2550 |
s->caps[0x0b] = 0x00; |
| 2551 |
|
| 2552 |
QTAILQ_INIT(&s->aqueues); |
| 2553 |
QTAILQ_INIT(&s->pqueues); |
| 2554 |
usb_packet_init(&s->ipacket); |
| 2555 |
|
| 2556 |
memory_region_init(&s->mem, NULL, "ehci", MMIO_SIZE); |
| 2557 |
memory_region_init_io(&s->mem_caps, NULL, &ehci_mmio_caps_ops, s,
|
| 2558 |
"capabilities", CAPA_SIZE);
|
| 2559 |
memory_region_init_io(&s->mem_opreg, NULL, &ehci_mmio_opreg_ops, s,
|
| 2560 |
"operational", s->portscbase);
|
| 2561 |
memory_region_init_io(&s->mem_ports, NULL, &ehci_mmio_port_ops, s,
|
| 2562 |
"ports", 4 * s->portnr); |
| 2563 |
|
| 2564 |
memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); |
| 2565 |
memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); |
| 2566 |
memory_region_add_subregion(&s->mem, s->opregbase + s->portscbase, |
| 2567 |
&s->mem_ports); |
| 2568 |
} |
| 2569 |
|
| 2570 |
/*
|
| 2571 |
* vim: expandtab ts=4
|
| 2572 |
*/
|