Revision 2ca1d92b
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 972 | 972 |
} |
| 973 | 973 |
#endif |
| 974 | 974 |
|
| 975 |
static uint32_t compute_all_subx(void) |
|
| 976 |
{
|
|
| 977 |
uint32_t ret; |
|
| 978 |
|
|
| 979 |
ret = get_NZ_icc(CC_DST); |
|
| 980 |
ret |= get_C_sub_icc(CC_DST - CC_SRC2, CC_SRC); |
|
| 981 |
ret |= get_C_sub_icc(CC_DST, CC_SRC2); |
|
| 982 |
ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
|
| 983 |
return ret; |
|
| 984 |
} |
|
| 985 |
|
|
| 986 |
static uint32_t compute_C_subx(void) |
|
| 987 |
{
|
|
| 988 |
uint32_t ret; |
|
| 989 |
|
|
| 990 |
ret = get_C_sub_icc(CC_DST - CC_SRC2, CC_SRC); |
|
| 991 |
ret |= get_C_sub_icc(CC_DST, CC_SRC2); |
|
| 992 |
return ret; |
|
| 993 |
} |
|
| 994 |
|
|
| 995 |
#ifdef TARGET_SPARC64 |
|
| 996 |
static uint32_t compute_all_subx_xcc(void) |
|
| 997 |
{
|
|
| 998 |
uint32_t ret; |
|
| 999 |
|
|
| 1000 |
ret = get_NZ_xcc(CC_DST); |
|
| 1001 |
ret |= get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC); |
|
| 1002 |
ret |= get_C_sub_xcc(CC_DST, CC_SRC2); |
|
| 1003 |
ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
|
| 1004 |
return ret; |
|
| 1005 |
} |
|
| 1006 |
|
|
| 1007 |
static uint32_t compute_C_subx_xcc(void) |
|
| 1008 |
{
|
|
| 1009 |
uint32_t ret; |
|
| 1010 |
|
|
| 1011 |
ret = get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC); |
|
| 1012 |
ret |= get_C_sub_xcc(CC_DST, CC_SRC2); |
|
| 1013 |
return ret; |
|
| 1014 |
} |
|
| 1015 |
#endif |
|
| 1016 |
|
|
| 975 | 1017 |
static uint32_t compute_all_logic(void) |
| 976 | 1018 |
{
|
| 977 | 1019 |
return get_NZ_icc(CC_DST); |
| ... | ... | |
| 1000 | 1042 |
[CC_OP_ADD] = { compute_all_add, compute_C_add },
|
| 1001 | 1043 |
[CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
|
| 1002 | 1044 |
[CC_OP_SUB] = { compute_all_sub, compute_C_sub },
|
| 1045 |
[CC_OP_SUBX] = { compute_all_subx, compute_C_subx },
|
|
| 1003 | 1046 |
[CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
|
| 1004 | 1047 |
}; |
| 1005 | 1048 |
|
| ... | ... | |
| 1010 | 1053 |
[CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
|
| 1011 | 1054 |
[CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
|
| 1012 | 1055 |
[CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
|
| 1056 |
[CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
|
|
| 1013 | 1057 |
[CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
|
| 1014 | 1058 |
}; |
| 1015 | 1059 |
#endif |
| b/target-sparc/translate.c | ||
|---|---|---|
| 635 | 635 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
| 636 | 636 |
} |
| 637 | 637 |
|
| 638 |
static inline void gen_op_subx_cc2(TCGv dst) |
|
| 639 |
{
|
|
| 640 |
gen_cc_NZ_icc(cpu_cc_dst); |
|
| 641 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
|
| 642 |
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 643 |
#ifdef TARGET_SPARC64 |
|
| 644 |
gen_cc_NZ_xcc(cpu_cc_dst); |
|
| 645 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
|
| 646 |
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 647 |
#endif |
|
| 648 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 649 |
} |
|
| 650 |
|
|
| 651 | 638 |
static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) |
| 652 | 639 |
{
|
| 653 | 640 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 654 | 641 |
tcg_gen_movi_tl(cpu_cc_src2, src2); |
| 655 | 642 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 656 | 643 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
| 657 |
gen_cc_clear_icc(); |
|
| 658 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
|
| 659 |
#ifdef TARGET_SPARC64 |
|
| 660 |
gen_cc_clear_xcc(); |
|
| 661 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
|
| 662 |
#endif |
|
| 663 | 644 |
tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
| 664 |
gen_op_subx_cc2(dst);
|
|
| 645 |
tcg_gen_mov_tl(dst, cpu_cc_dst);
|
|
| 665 | 646 |
} |
| 666 | 647 |
|
| 667 | 648 |
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 670 | 651 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 671 | 652 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 672 | 653 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
| 673 |
gen_cc_clear_icc(); |
|
| 674 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
|
| 675 |
#ifdef TARGET_SPARC64 |
|
| 676 |
gen_cc_clear_xcc(); |
|
| 677 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
|
| 678 |
#endif |
|
| 679 | 654 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
| 680 |
gen_op_subx_cc2(dst);
|
|
| 655 |
tcg_gen_mov_tl(dst, cpu_cc_dst);
|
|
| 681 | 656 |
} |
| 682 | 657 |
|
| 683 | 658 |
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 3263 | 3238 |
if (xop & 0x10) {
|
| 3264 | 3239 |
gen_helper_compute_psr(); |
| 3265 | 3240 |
gen_op_subxi_cc(cpu_dst, cpu_src1, simm); |
| 3266 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
|
|
| 3267 |
dc->cc_op = CC_OP_FLAGS;
|
|
| 3241 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
|
|
| 3242 |
dc->cc_op = CC_OP_SUBX;
|
|
| 3268 | 3243 |
} else {
|
| 3269 | 3244 |
gen_helper_compute_psr(); |
| 3270 | 3245 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| ... | ... | |
| 3275 | 3250 |
if (xop & 0x10) {
|
| 3276 | 3251 |
gen_helper_compute_psr(); |
| 3277 | 3252 |
gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
| 3278 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
|
|
| 3279 |
dc->cc_op = CC_OP_FLAGS;
|
|
| 3253 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
|
|
| 3254 |
dc->cc_op = CC_OP_SUBX;
|
|
| 3280 | 3255 |
} else {
|
| 3281 | 3256 |
gen_helper_compute_psr(); |
| 3282 | 3257 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
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