Revision 2ca1d92b target-sparc/translate.c
b/target-sparc/translate.c | ||
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635 | 635 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
636 | 636 |
} |
637 | 637 |
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638 |
static inline void gen_op_subx_cc2(TCGv dst) |
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639 |
{ |
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640 |
gen_cc_NZ_icc(cpu_cc_dst); |
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641 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
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642 |
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
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643 |
#ifdef TARGET_SPARC64 |
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644 |
gen_cc_NZ_xcc(cpu_cc_dst); |
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645 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
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646 |
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
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647 |
#endif |
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648 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
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649 |
} |
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650 |
|
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651 | 638 |
static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) |
652 | 639 |
{ |
653 | 640 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
654 | 641 |
tcg_gen_movi_tl(cpu_cc_src2, src2); |
655 | 642 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
656 | 643 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
657 |
gen_cc_clear_icc(); |
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658 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
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659 |
#ifdef TARGET_SPARC64 |
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660 |
gen_cc_clear_xcc(); |
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661 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
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662 |
#endif |
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663 | 644 |
tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
664 |
gen_op_subx_cc2(dst);
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645 |
tcg_gen_mov_tl(dst, cpu_cc_dst);
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665 | 646 |
} |
666 | 647 |
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667 | 648 |
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
... | ... | |
670 | 651 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
671 | 652 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
672 | 653 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
673 |
gen_cc_clear_icc(); |
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674 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
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675 |
#ifdef TARGET_SPARC64 |
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676 |
gen_cc_clear_xcc(); |
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677 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
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678 |
#endif |
|
679 | 654 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
680 |
gen_op_subx_cc2(dst);
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655 |
tcg_gen_mov_tl(dst, cpu_cc_dst);
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681 | 656 |
} |
682 | 657 |
|
683 | 658 |
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
... | ... | |
3263 | 3238 |
if (xop & 0x10) { |
3264 | 3239 |
gen_helper_compute_psr(); |
3265 | 3240 |
gen_op_subxi_cc(cpu_dst, cpu_src1, simm); |
3266 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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3267 |
dc->cc_op = CC_OP_FLAGS;
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3241 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
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3242 |
dc->cc_op = CC_OP_SUBX;
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3268 | 3243 |
} else { |
3269 | 3244 |
gen_helper_compute_psr(); |
3270 | 3245 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
... | ... | |
3275 | 3250 |
if (xop & 0x10) { |
3276 | 3251 |
gen_helper_compute_psr(); |
3277 | 3252 |
gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
3278 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
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3279 |
dc->cc_op = CC_OP_FLAGS;
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3253 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
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3254 |
dc->cc_op = CC_OP_SUBX;
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3280 | 3255 |
} else { |
3281 | 3256 |
gen_helper_compute_psr(); |
3282 | 3257 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
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