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1 | 0d78f544 | ths | /*
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2 | 0d78f544 | ths | * Renesas SH7751R R2D-PLUS emulation
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3 | 0d78f544 | ths | *
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4 | 0d78f544 | ths | * Copyright (c) 2007 Magnus Damm
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5 | b319feb7 | aurel32 | * Copyright (c) 2008 Paul Mundt
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6 | 0d78f544 | ths | *
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7 | 0d78f544 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 0d78f544 | ths | * of this software and associated documentation files (the "Software"), to deal
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9 | 0d78f544 | ths | * in the Software without restriction, including without limitation the rights
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10 | 0d78f544 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 0d78f544 | ths | * copies of the Software, and to permit persons to whom the Software is
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12 | 0d78f544 | ths | * furnished to do so, subject to the following conditions:
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13 | 0d78f544 | ths | *
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14 | 0d78f544 | ths | * The above copyright notice and this permission notice shall be included in
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15 | 0d78f544 | ths | * all copies or substantial portions of the Software.
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16 | 0d78f544 | ths | *
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17 | 0d78f544 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 0d78f544 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 0d78f544 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 0d78f544 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 0d78f544 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 0d78f544 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 0d78f544 | ths | * THE SOFTWARE.
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24 | 0d78f544 | ths | */
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25 | 0d78f544 | ths | |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sh.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | 87ecb68b | pbrook | #include "boards.h" |
30 | 0d78f544 | ths | |
31 | 0d78f544 | ths | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
32 | 0d78f544 | ths | #define SDRAM_SIZE 0x04000000 |
33 | 0d78f544 | ths | |
34 | b319feb7 | aurel32 | #define PA_POWOFF 0x30 |
35 | b319feb7 | aurel32 | #define PA_VERREG 0x32 |
36 | b319feb7 | aurel32 | #define PA_OUTPORT 0x36 |
37 | b319feb7 | aurel32 | |
38 | b319feb7 | aurel32 | typedef struct { |
39 | b319feb7 | aurel32 | target_phys_addr_t base; |
40 | b319feb7 | aurel32 | |
41 | b319feb7 | aurel32 | uint16_t bcr; |
42 | b319feb7 | aurel32 | uint16_t irlmon; |
43 | b319feb7 | aurel32 | uint16_t cfctl; |
44 | b319feb7 | aurel32 | uint16_t cfpow; |
45 | b319feb7 | aurel32 | uint16_t dispctl; |
46 | b319feb7 | aurel32 | uint16_t sdmpow; |
47 | b319feb7 | aurel32 | uint16_t rtcce; |
48 | b319feb7 | aurel32 | uint16_t pcicd; |
49 | b319feb7 | aurel32 | uint16_t voyagerrts; |
50 | b319feb7 | aurel32 | uint16_t cfrst; |
51 | b319feb7 | aurel32 | uint16_t admrts; |
52 | b319feb7 | aurel32 | uint16_t extrst; |
53 | b319feb7 | aurel32 | uint16_t cfcdintclr; |
54 | b319feb7 | aurel32 | uint16_t keyctlclr; |
55 | b319feb7 | aurel32 | uint16_t pad0; |
56 | b319feb7 | aurel32 | uint16_t pad1; |
57 | b319feb7 | aurel32 | uint16_t powoff; |
58 | b319feb7 | aurel32 | uint16_t verreg; |
59 | b319feb7 | aurel32 | uint16_t inport; |
60 | b319feb7 | aurel32 | uint16_t outport; |
61 | b319feb7 | aurel32 | uint16_t bverreg; |
62 | b319feb7 | aurel32 | } r2d_fpga_t; |
63 | b319feb7 | aurel32 | |
64 | b319feb7 | aurel32 | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
65 | b319feb7 | aurel32 | { |
66 | b319feb7 | aurel32 | r2d_fpga_t *s = opaque; |
67 | b319feb7 | aurel32 | |
68 | b319feb7 | aurel32 | addr -= s->base; |
69 | b319feb7 | aurel32 | |
70 | b319feb7 | aurel32 | switch (addr) {
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71 | b319feb7 | aurel32 | case PA_OUTPORT:
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72 | b319feb7 | aurel32 | return s->outport;
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73 | b319feb7 | aurel32 | case PA_POWOFF:
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74 | b319feb7 | aurel32 | return s->powoff;
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75 | b319feb7 | aurel32 | case PA_VERREG:
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76 | b319feb7 | aurel32 | return 0x10; |
77 | b319feb7 | aurel32 | } |
78 | b319feb7 | aurel32 | |
79 | b319feb7 | aurel32 | return 0; |
80 | b319feb7 | aurel32 | } |
81 | b319feb7 | aurel32 | |
82 | b319feb7 | aurel32 | static void |
83 | b319feb7 | aurel32 | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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84 | b319feb7 | aurel32 | { |
85 | b319feb7 | aurel32 | r2d_fpga_t *s = opaque; |
86 | b319feb7 | aurel32 | |
87 | b319feb7 | aurel32 | addr -= s->base; |
88 | b319feb7 | aurel32 | |
89 | b319feb7 | aurel32 | switch (addr) {
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90 | b319feb7 | aurel32 | case PA_OUTPORT:
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91 | b319feb7 | aurel32 | s->outport = value; |
92 | b319feb7 | aurel32 | break;
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93 | b319feb7 | aurel32 | case PA_POWOFF:
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94 | b319feb7 | aurel32 | s->powoff = value; |
95 | b319feb7 | aurel32 | break;
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96 | b319feb7 | aurel32 | case PA_VERREG:
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97 | b319feb7 | aurel32 | /* Discard writes */
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98 | b319feb7 | aurel32 | break;
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99 | b319feb7 | aurel32 | } |
100 | b319feb7 | aurel32 | } |
101 | b319feb7 | aurel32 | |
102 | b319feb7 | aurel32 | static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
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103 | b319feb7 | aurel32 | r2d_fpga_read, |
104 | b319feb7 | aurel32 | r2d_fpga_read, |
105 | b2463a64 | aurel32 | NULL,
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106 | b319feb7 | aurel32 | }; |
107 | b319feb7 | aurel32 | |
108 | b319feb7 | aurel32 | static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
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109 | b319feb7 | aurel32 | r2d_fpga_write, |
110 | b319feb7 | aurel32 | r2d_fpga_write, |
111 | b2463a64 | aurel32 | NULL,
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112 | b319feb7 | aurel32 | }; |
113 | b319feb7 | aurel32 | |
114 | b319feb7 | aurel32 | static void r2d_fpga_init(target_phys_addr_t base) |
115 | b319feb7 | aurel32 | { |
116 | b319feb7 | aurel32 | int iomemtype;
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117 | b319feb7 | aurel32 | r2d_fpga_t *s; |
118 | b319feb7 | aurel32 | |
119 | b319feb7 | aurel32 | s = qemu_mallocz(sizeof(r2d_fpga_t));
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120 | b319feb7 | aurel32 | if (!s)
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121 | b319feb7 | aurel32 | return;
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122 | b319feb7 | aurel32 | |
123 | b319feb7 | aurel32 | s->base = base; |
124 | b319feb7 | aurel32 | iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
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125 | b319feb7 | aurel32 | r2d_fpga_writefn, s); |
126 | b319feb7 | aurel32 | cpu_register_physical_memory(base, 0x40, iomemtype);
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127 | b319feb7 | aurel32 | } |
128 | b319feb7 | aurel32 | |
129 | 00f82b8a | aurel32 | static void r2d_init(ram_addr_t ram_size, int vga_ram_size, |
130 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState * ds, |
131 | 0d78f544 | ths | const char *kernel_filename, const char *kernel_cmdline, |
132 | 0d78f544 | ths | const char *initrd_filename, const char *cpu_model) |
133 | 0d78f544 | ths | { |
134 | 0d78f544 | ths | CPUState *env; |
135 | 0d78f544 | ths | struct SH7750State *s;
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136 | 0d78f544 | ths | |
137 | aaed909a | bellard | if (!cpu_model)
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138 | 0fd3ca30 | aurel32 | cpu_model = "SH7751R";
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139 | aaed909a | bellard | |
140 | aaed909a | bellard | env = cpu_init(cpu_model); |
141 | aaed909a | bellard | if (!env) {
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142 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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143 | aaed909a | bellard | exit(1);
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144 | aaed909a | bellard | } |
145 | 0d78f544 | ths | |
146 | 0d78f544 | ths | /* Allocate memory space */
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147 | 0d78f544 | ths | cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
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148 | 0d78f544 | ths | /* Register peripherals */
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149 | b319feb7 | aurel32 | r2d_fpga_init(0x04000000);
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150 | 0d78f544 | ths | s = sh7750_init(env); |
151 | 0d78f544 | ths | /* Todo: register on board registers */
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152 | 0d78f544 | ths | { |
153 | 0d78f544 | ths | int kernel_size;
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154 | 0d78f544 | ths | |
155 | 0d78f544 | ths | kernel_size = load_image(kernel_filename, phys_ram_base); |
156 | 0d78f544 | ths | |
157 | 0d78f544 | ths | if (kernel_size < 0) { |
158 | 0d78f544 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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159 | 0d78f544 | ths | exit(1);
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160 | 0d78f544 | ths | } |
161 | 0d78f544 | ths | |
162 | 0d78f544 | ths | env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */ |
163 | 0d78f544 | ths | } |
164 | 0d78f544 | ths | } |
165 | 0d78f544 | ths | |
166 | 0d78f544 | ths | QEMUMachine r2d_machine = { |
167 | 0d78f544 | ths | "r2d",
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168 | 0d78f544 | ths | "r2d-plus board",
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169 | 7fb4fdcf | balrog | r2d_init, |
170 | 7fb4fdcf | balrog | SDRAM_SIZE | RAMSIZE_FIXED |
171 | 0d78f544 | ths | }; |