root / hw / ppc / spapr.c @ 2cf3eb6d
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/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2010 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "sysemu/sysemu.h" |
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#include "hw/hw.h" |
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#include "elf.h" |
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#include "net/net.h" |
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#include "sysemu/blockdev.h" |
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#include "sysemu/cpus.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "hw/boards.h" |
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#include "hw/ppc/ppc.h" |
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#include "hw/loader.h" |
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#include "hw/ppc/spapr.h" |
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#include "hw/ppc/spapr_vio.h" |
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#include "hw/pci-host/spapr.h" |
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#include "hw/ppc/xics.h" |
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#include "hw/pci/msi.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "hw/pci/pci.h" |
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#include "exec/address-spaces.h" |
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#include "hw/usb.h" |
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#include "qemu/config-file.h" |
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#include <libfdt.h> |
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/* SLOF memory layout:
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*
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* SLOF raw image loaded at 0, copies its romfs right below the flat
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* device-tree, then position SLOF itself 31M below that
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*
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* So we set FW_OVERHEAD to 40MB which should account for all of that
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* and more
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*
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* We load our kernel at 4M, leaving space for SLOF initial image
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*/
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#define FDT_MAX_SIZE 0x10000 |
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#define RTAS_MAX_SIZE 0x10000 |
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#define FW_MAX_SIZE 0x400000 |
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#define FW_FILE_NAME "slof.bin" |
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#define FW_OVERHEAD 0x2800000 |
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#define KERNEL_LOAD_ADDR FW_MAX_SIZE
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#define MIN_RMA_SLOF 128UL |
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#define TIMEBASE_FREQ 512000000ULL |
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#define MAX_CPUS 256 |
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#define XICS_IRQS 1024 |
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#define PHANDLE_XICP 0x00001111 |
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#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
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sPAPREnvironment *spapr; |
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int spapr_allocate_irq(int hint, bool lsi) |
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{ |
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int irq;
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if (hint) {
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irq = hint; |
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/* FIXME: we should probably check for collisions somehow */
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} else {
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irq = spapr->next_irq++; |
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} |
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/* Configure irq type */
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if (!xics_get_qirq(spapr->icp, irq)) {
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return 0; |
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} |
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xics_set_irq_type(spapr->icp, irq, lsi); |
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return irq;
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} |
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/* Allocate block of consequtive IRQs, returns a number of the first */
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int spapr_allocate_irq_block(int num, bool lsi) |
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{ |
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int first = -1; |
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int i;
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for (i = 0; i < num; ++i) { |
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int irq;
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irq = spapr_allocate_irq(0, lsi);
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if (!irq) {
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return -1; |
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} |
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if (0 == i) { |
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first = irq; |
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} |
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/* If the above doesn't create a consecutive block then that's
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* an internal bug */
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assert(irq == (first + i)); |
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} |
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return first;
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} |
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static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) |
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{ |
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int ret = 0, offset; |
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CPUPPCState *env; |
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CPUState *cpu; |
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char cpu_model[32]; |
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int smt = kvmppc_smt_threads();
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uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
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assert(spapr->cpu_model); |
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for (env = first_cpu; env != NULL; env = env->next_cpu) { |
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cpu = CPU(ppc_env_get_cpu(env)); |
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uint32_t associativity[] = {cpu_to_be32(0x5),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(cpu->numa_node), |
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cpu_to_be32(cpu->cpu_index)}; |
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if ((cpu->cpu_index % smt) != 0) { |
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continue;
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} |
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snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, |
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cpu->cpu_index); |
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offset = fdt_path_offset(fdt, cpu_model); |
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if (offset < 0) { |
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return offset;
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} |
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if (nb_numa_nodes > 1) { |
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ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
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sizeof(associativity));
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if (ret < 0) { |
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return ret;
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} |
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} |
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ret = fdt_setprop(fdt, offset, "ibm,pft-size",
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pft_size_prop, sizeof(pft_size_prop));
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if (ret < 0) { |
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return ret;
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} |
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} |
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return ret;
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} |
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static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
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size_t maxsize) |
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{ |
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size_t maxcells = maxsize / sizeof(uint32_t);
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int i, j, count;
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uint32_t *p = prop; |
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for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
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struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
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if (!sps->page_shift) {
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break;
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} |
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for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { |
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if (sps->enc[count].page_shift == 0) { |
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break;
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} |
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} |
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if ((p - prop) >= (maxcells - 3 - count * 2)) { |
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break;
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} |
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*(p++) = cpu_to_be32(sps->page_shift); |
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*(p++) = cpu_to_be32(sps->slb_enc); |
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*(p++) = cpu_to_be32(count); |
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for (j = 0; j < count; j++) { |
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*(p++) = cpu_to_be32(sps->enc[j].page_shift); |
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*(p++) = cpu_to_be32(sps->enc[j].pte_enc); |
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} |
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} |
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return (p - prop) * sizeof(uint32_t); |
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} |
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#define _FDT(exp) \
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do { \
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int ret = (exp); \
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if (ret < 0) { \ |
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fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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#exp, fdt_strerror(ret)); \
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exit(1); \
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} \ |
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} while (0) |
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static void *spapr_create_fdt_skel(const char *cpu_model, |
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hwaddr initrd_base, |
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hwaddr initrd_size, |
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hwaddr kernel_size, |
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const char *boot_device, |
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const char *kernel_cmdline, |
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uint32_t epow_irq) |
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{ |
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void *fdt;
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CPUPPCState *env; |
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uint32_t start_prop = cpu_to_be32(initrd_base); |
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uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); |
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char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
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"\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
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char qemu_hypertas_prop[] = "hcall-memop1"; |
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uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
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uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
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char *modelname;
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int i, smt = kvmppc_smt_threads();
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unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
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fdt = g_malloc0(FDT_MAX_SIZE); |
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_FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
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if (kernel_size) {
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_FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); |
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} |
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if (initrd_size) {
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_FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); |
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} |
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_FDT((fdt_finish_reservemap(fdt))); |
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/* Root node */
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_FDT((fdt_begin_node(fdt, "")));
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_FDT((fdt_property_string(fdt, "device_type", "chrp"))); |
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_FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
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_FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); |
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/* /chosen */
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_FDT((fdt_begin_node(fdt, "chosen")));
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/* Set Form1_affinity */
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_FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); |
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_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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_FDT((fdt_property(fdt, "linux,initrd-start",
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&start_prop, sizeof(start_prop))));
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_FDT((fdt_property(fdt, "linux,initrd-end",
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&end_prop, sizeof(end_prop))));
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if (kernel_size) {
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uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
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cpu_to_be64(kernel_size) }; |
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_FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
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} |
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if (boot_device) {
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_FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
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} |
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_FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
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_FDT((fdt_end_node(fdt))); |
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/* cpus */
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_FDT((fdt_begin_node(fdt, "cpus")));
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
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modelname = g_strdup(cpu_model); |
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for (i = 0; i < strlen(modelname); i++) { |
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modelname[i] = toupper(modelname[i]); |
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} |
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/* This is needed during FDT finalization */
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spapr->cpu_model = g_strdup(modelname); |
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for (env = first_cpu; env != NULL; env = env->next_cpu) { |
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CPUState *cpu = CPU(ppc_env_get_cpu(env)); |
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int index = cpu->cpu_index;
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uint32_t servers_prop[smp_threads]; |
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uint32_t gservers_prop[smp_threads * 2];
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char *nodename;
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
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0xffffffff, 0xffffffff}; |
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uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; |
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uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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uint32_t page_sizes_prop[64];
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size_t page_sizes_prop_size; |
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if ((index % smt) != 0) { |
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continue;
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} |
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nodename = g_strdup_printf("%s@%x", modelname, index);
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_FDT((fdt_begin_node(fdt, nodename))); |
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g_free(nodename); |
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_FDT((fdt_property_cell(fdt, "reg", index)));
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_FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
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_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
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_FDT((fdt_property_cell(fdt, "dcache-block-size",
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env->dcache_line_size))); |
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_FDT((fdt_property_cell(fdt, "icache-block-size",
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env->icache_line_size))); |
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_FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
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_FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
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_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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_FDT((fdt_property_string(fdt, "status", "okay"))); |
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_FDT((fdt_property(fdt, "64-bit", NULL, 0))); |
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/* Build interrupt servers and gservers properties */
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for (i = 0; i < smp_threads; i++) { |
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servers_prop[i] = cpu_to_be32(index + i); |
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/* Hack, direct the group queues back to cpu 0 */
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gservers_prop[i*2] = cpu_to_be32(index + i);
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gservers_prop[i*2 + 1] = 0; |
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} |
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_FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
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servers_prop, sizeof(servers_prop))));
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_FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
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gservers_prop, sizeof(gservers_prop))));
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if (env->mmu_model & POWERPC_MMU_1TSEG) {
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_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
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segs, sizeof(segs))));
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} |
362 |
|
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/* Advertise VMX/VSX (vector extensions) if available
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* 0 / no property == no vector extensions
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* 1 == VMX / Altivec available
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* 2 == VSX available */
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if (env->insns_flags & PPC_ALTIVEC) {
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uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; |
369 |
|
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_FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
|
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} |
372 |
|
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/* Advertise DFP (Decimal Floating Point) if available
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* 0 / no property == no DFP
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* 1 == DFP available */
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if (env->insns_flags2 & PPC2_DFP) {
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_FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); |
378 |
} |
379 |
|
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page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, |
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sizeof(page_sizes_prop));
|
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if (page_sizes_prop_size) {
|
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_FDT((fdt_property(fdt, "ibm,segment-page-sizes",
|
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page_sizes_prop, page_sizes_prop_size))); |
385 |
} |
386 |
|
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_FDT((fdt_end_node(fdt))); |
388 |
} |
389 |
|
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g_free(modelname); |
391 |
|
392 |
_FDT((fdt_end_node(fdt))); |
393 |
|
394 |
/* RTAS */
|
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_FDT((fdt_begin_node(fdt, "rtas")));
|
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|
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_FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
|
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sizeof(hypertas_prop))));
|
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_FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
|
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sizeof(qemu_hypertas_prop))));
|
401 |
|
402 |
_FDT((fdt_property(fdt, "ibm,associativity-reference-points",
|
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refpoints, sizeof(refpoints))));
|
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|
405 |
_FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
|
406 |
|
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_FDT((fdt_end_node(fdt))); |
408 |
|
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/* interrupt controller */
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_FDT((fdt_begin_node(fdt, "interrupt-controller")));
|
411 |
|
412 |
_FDT((fdt_property_string(fdt, "device_type",
|
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"PowerPC-External-Interrupt-Presentation")));
|
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_FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); |
415 |
_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
416 |
_FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
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interrupt_server_ranges_prop, |
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sizeof(interrupt_server_ranges_prop))));
|
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_FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
420 |
_FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
|
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_FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
|
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|
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_FDT((fdt_end_node(fdt))); |
424 |
|
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/* vdevice */
|
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_FDT((fdt_begin_node(fdt, "vdevice")));
|
427 |
|
428 |
_FDT((fdt_property_string(fdt, "device_type", "vdevice"))); |
429 |
_FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); |
430 |
_FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
431 |
_FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
432 |
_FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
433 |
_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
434 |
|
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_FDT((fdt_end_node(fdt))); |
436 |
|
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/* event-sources */
|
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spapr_events_fdt_skel(fdt, epow_irq); |
439 |
|
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_FDT((fdt_end_node(fdt))); /* close root node */
|
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_FDT((fdt_finish(fdt))); |
442 |
|
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return fdt;
|
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} |
445 |
|
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static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) |
447 |
{ |
448 |
uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), |
449 |
cpu_to_be32(0x0), cpu_to_be32(0x0), |
450 |
cpu_to_be32(0x0)};
|
451 |
char mem_name[32]; |
452 |
hwaddr node0_size, mem_start; |
453 |
uint64_t mem_reg_property[2];
|
454 |
int i, off;
|
455 |
|
456 |
/* memory node(s) */
|
457 |
node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; |
458 |
if (spapr->rma_size > node0_size) {
|
459 |
spapr->rma_size = node0_size; |
460 |
} |
461 |
|
462 |
/* RMA */
|
463 |
mem_reg_property[0] = 0; |
464 |
mem_reg_property[1] = cpu_to_be64(spapr->rma_size);
|
465 |
off = fdt_add_subnode(fdt, 0, "memory@0"); |
466 |
_FDT(off); |
467 |
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); |
468 |
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
|
469 |
sizeof(mem_reg_property))));
|
470 |
_FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
|
471 |
sizeof(associativity))));
|
472 |
|
473 |
/* RAM: Node 0 */
|
474 |
if (node0_size > spapr->rma_size) {
|
475 |
mem_reg_property[0] = cpu_to_be64(spapr->rma_size);
|
476 |
mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size);
|
477 |
|
478 |
sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size);
|
479 |
off = fdt_add_subnode(fdt, 0, mem_name);
|
480 |
_FDT(off); |
481 |
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); |
482 |
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
|
483 |
sizeof(mem_reg_property))));
|
484 |
_FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
|
485 |
sizeof(associativity))));
|
486 |
} |
487 |
|
488 |
/* RAM: Node 1 and beyond */
|
489 |
mem_start = node0_size; |
490 |
for (i = 1; i < nb_numa_nodes; i++) { |
491 |
mem_reg_property[0] = cpu_to_be64(mem_start);
|
492 |
mem_reg_property[1] = cpu_to_be64(node_mem[i]);
|
493 |
associativity[3] = associativity[4] = cpu_to_be32(i); |
494 |
sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
|
495 |
off = fdt_add_subnode(fdt, 0, mem_name);
|
496 |
_FDT(off); |
497 |
_FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); |
498 |
_FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
|
499 |
sizeof(mem_reg_property))));
|
500 |
_FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
|
501 |
sizeof(associativity))));
|
502 |
mem_start += node_mem[i]; |
503 |
} |
504 |
|
505 |
return 0; |
506 |
} |
507 |
|
508 |
static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
509 |
hwaddr fdt_addr, |
510 |
hwaddr rtas_addr, |
511 |
hwaddr rtas_size) |
512 |
{ |
513 |
int ret;
|
514 |
void *fdt;
|
515 |
sPAPRPHBState *phb; |
516 |
|
517 |
fdt = g_malloc(FDT_MAX_SIZE); |
518 |
|
519 |
/* open out the base tree into a temp buffer for the final tweaks */
|
520 |
_FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); |
521 |
|
522 |
ret = spapr_populate_memory(spapr, fdt); |
523 |
if (ret < 0) { |
524 |
fprintf(stderr, "couldn't setup memory nodes in fdt\n");
|
525 |
exit(1);
|
526 |
} |
527 |
|
528 |
ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
529 |
if (ret < 0) { |
530 |
fprintf(stderr, "couldn't setup vio devices in fdt\n");
|
531 |
exit(1);
|
532 |
} |
533 |
|
534 |
QLIST_FOREACH(phb, &spapr->phbs, list) { |
535 |
ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
536 |
} |
537 |
|
538 |
if (ret < 0) { |
539 |
fprintf(stderr, "couldn't setup PCI devices in fdt\n");
|
540 |
exit(1);
|
541 |
} |
542 |
|
543 |
/* RTAS */
|
544 |
ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); |
545 |
if (ret < 0) { |
546 |
fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
|
547 |
} |
548 |
|
549 |
/* Advertise NUMA via ibm,associativity */
|
550 |
ret = spapr_fixup_cpu_dt(fdt, spapr); |
551 |
if (ret < 0) { |
552 |
fprintf(stderr, "Couldn't finalize CPU device tree properties\n");
|
553 |
} |
554 |
|
555 |
if (!spapr->has_graphics) {
|
556 |
spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
557 |
} |
558 |
|
559 |
_FDT((fdt_pack(fdt))); |
560 |
|
561 |
if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
|
562 |
hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
|
563 |
fdt_totalsize(fdt), FDT_MAX_SIZE); |
564 |
exit(1);
|
565 |
} |
566 |
|
567 |
cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
568 |
|
569 |
g_free(fdt); |
570 |
} |
571 |
|
572 |
static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
573 |
{ |
574 |
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
575 |
} |
576 |
|
577 |
static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
578 |
{ |
579 |
CPUPPCState *env = &cpu->env; |
580 |
|
581 |
if (msr_pr) {
|
582 |
hcall_dprintf("Hypercall made with MSR[PR]=1\n");
|
583 |
env->gpr[3] = H_PRIVILEGE;
|
584 |
} else {
|
585 |
env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
586 |
} |
587 |
} |
588 |
|
589 |
static void spapr_reset_htab(sPAPREnvironment *spapr) |
590 |
{ |
591 |
long shift;
|
592 |
|
593 |
/* allocate hash page table. For now we always make this 16mb,
|
594 |
* later we should probably make it scale to the size of guest
|
595 |
* RAM */
|
596 |
|
597 |
shift = kvmppc_reset_htab(spapr->htab_shift); |
598 |
|
599 |
if (shift > 0) { |
600 |
/* Kernel handles htab, we don't need to allocate one */
|
601 |
spapr->htab_shift = shift; |
602 |
} else {
|
603 |
if (!spapr->htab) {
|
604 |
/* Allocate an htab if we don't yet have one */
|
605 |
spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); |
606 |
} |
607 |
|
608 |
/* And clear it */
|
609 |
memset(spapr->htab, 0, HTAB_SIZE(spapr));
|
610 |
} |
611 |
|
612 |
/* Update the RMA size if necessary */
|
613 |
if (spapr->vrma_adjust) {
|
614 |
spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); |
615 |
} |
616 |
} |
617 |
|
618 |
static void ppc_spapr_reset(void) |
619 |
{ |
620 |
CPUState *first_cpu_cpu; |
621 |
|
622 |
/* Reset the hash table & recalc the RMA */
|
623 |
spapr_reset_htab(spapr); |
624 |
|
625 |
qemu_devices_reset(); |
626 |
|
627 |
/* Load the fdt */
|
628 |
spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, |
629 |
spapr->rtas_size); |
630 |
|
631 |
/* Set up the entry state */
|
632 |
first_cpu_cpu = ENV_GET_CPU(first_cpu); |
633 |
first_cpu->gpr[3] = spapr->fdt_addr;
|
634 |
first_cpu->gpr[5] = 0; |
635 |
first_cpu_cpu->halted = 0;
|
636 |
first_cpu->nip = spapr->entry_point; |
637 |
|
638 |
} |
639 |
|
640 |
static void spapr_cpu_reset(void *opaque) |
641 |
{ |
642 |
PowerPCCPU *cpu = opaque; |
643 |
CPUState *cs = CPU(cpu); |
644 |
CPUPPCState *env = &cpu->env; |
645 |
|
646 |
cpu_reset(cs); |
647 |
|
648 |
/* All CPUs start halted. CPU0 is unhalted from the machine level
|
649 |
* reset code and the rest are explicitly started up by the guest
|
650 |
* using an RTAS call */
|
651 |
cs->halted = 1;
|
652 |
|
653 |
env->spr[SPR_HIOR] = 0;
|
654 |
|
655 |
env->external_htab = spapr->htab; |
656 |
env->htab_base = -1;
|
657 |
env->htab_mask = HTAB_SIZE(spapr) - 1;
|
658 |
env->spr[SPR_SDR1] = (unsigned long)spapr->htab | |
659 |
(spapr->htab_shift - 18);
|
660 |
} |
661 |
|
662 |
static void spapr_create_nvram(sPAPREnvironment *spapr) |
663 |
{ |
664 |
QemuOpts *machine_opts; |
665 |
DeviceState *dev; |
666 |
|
667 |
dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
|
668 |
|
669 |
machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); |
670 |
if (machine_opts) {
|
671 |
const char *drivename; |
672 |
|
673 |
drivename = qemu_opt_get(machine_opts, "nvram");
|
674 |
if (drivename) {
|
675 |
BlockDriverState *bs; |
676 |
|
677 |
bs = bdrv_find(drivename); |
678 |
if (!bs) {
|
679 |
fprintf(stderr, "No such block device \"%s\" for nvram\n",
|
680 |
drivename); |
681 |
exit(1);
|
682 |
} |
683 |
qdev_prop_set_drive_nofail(dev, "drive", bs);
|
684 |
} |
685 |
} |
686 |
|
687 |
qdev_init_nofail(dev); |
688 |
|
689 |
spapr->nvram = (struct sPAPRNVRAM *)dev;
|
690 |
} |
691 |
|
692 |
/* Returns whether we want to use VGA or not */
|
693 |
static int spapr_vga_init(PCIBus *pci_bus) |
694 |
{ |
695 |
switch (vga_interface_type) {
|
696 |
case VGA_NONE:
|
697 |
case VGA_STD:
|
698 |
return pci_vga_init(pci_bus) != NULL; |
699 |
default:
|
700 |
fprintf(stderr, "This vga model is not supported,"
|
701 |
"currently it only supports -vga std\n");
|
702 |
exit(0);
|
703 |
break;
|
704 |
} |
705 |
} |
706 |
|
707 |
/* pSeries LPAR / sPAPR hardware init */
|
708 |
static void ppc_spapr_init(QEMUMachineInitArgs *args) |
709 |
{ |
710 |
ram_addr_t ram_size = args->ram_size; |
711 |
const char *cpu_model = args->cpu_model; |
712 |
const char *kernel_filename = args->kernel_filename; |
713 |
const char *kernel_cmdline = args->kernel_cmdline; |
714 |
const char *initrd_filename = args->initrd_filename; |
715 |
const char *boot_device = args->boot_device; |
716 |
PowerPCCPU *cpu; |
717 |
CPUPPCState *env; |
718 |
PCIHostState *phb; |
719 |
int i;
|
720 |
MemoryRegion *sysmem = get_system_memory(); |
721 |
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
722 |
hwaddr rma_alloc_size; |
723 |
uint32_t initrd_base = 0;
|
724 |
long kernel_size = 0, initrd_size = 0; |
725 |
long load_limit, rtas_limit, fw_size;
|
726 |
char *filename;
|
727 |
|
728 |
msi_supported = true;
|
729 |
|
730 |
spapr = g_malloc0(sizeof(*spapr));
|
731 |
QLIST_INIT(&spapr->phbs); |
732 |
|
733 |
cpu_ppc_hypercall = emulate_spapr_hypercall; |
734 |
|
735 |
/* Allocate RMA if necessary */
|
736 |
rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
|
737 |
|
738 |
if (rma_alloc_size == -1) { |
739 |
hw_error("qemu: Unable to create RMA\n");
|
740 |
exit(1);
|
741 |
} |
742 |
|
743 |
if (rma_alloc_size && (rma_alloc_size < ram_size)) {
|
744 |
spapr->rma_size = rma_alloc_size; |
745 |
} else {
|
746 |
spapr->rma_size = ram_size; |
747 |
|
748 |
/* With KVM, we don't actually know whether KVM supports an
|
749 |
* unbounded RMA (PR KVM) or is limited by the hash table size
|
750 |
* (HV KVM using VRMA), so we always assume the latter
|
751 |
*
|
752 |
* In that case, we also limit the initial allocations for RTAS
|
753 |
* etc... to 256M since we have no way to know what the VRMA size
|
754 |
* is going to be as it depends on the size of the hash table
|
755 |
* isn't determined yet.
|
756 |
*/
|
757 |
if (kvm_enabled()) {
|
758 |
spapr->vrma_adjust = 1;
|
759 |
spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
|
760 |
} |
761 |
} |
762 |
|
763 |
/* We place the device tree and RTAS just below either the top of the RMA,
|
764 |
* or just below 2GB, whichever is lowere, so that it can be
|
765 |
* processed with 32-bit real mode code if necessary */
|
766 |
rtas_limit = MIN(spapr->rma_size, 0x80000000);
|
767 |
spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
768 |
spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; |
769 |
load_limit = spapr->fdt_addr - FW_OVERHEAD; |
770 |
|
771 |
/* We aim for a hash table of size 1/128 the size of RAM. The
|
772 |
* normal rule of thumb is 1/64 the size of RAM, but that's much
|
773 |
* more than needed for the Linux guests we support. */
|
774 |
spapr->htab_shift = 18; /* Minimum architected size */ |
775 |
while (spapr->htab_shift <= 46) { |
776 |
if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { |
777 |
break;
|
778 |
} |
779 |
spapr->htab_shift++; |
780 |
} |
781 |
|
782 |
/* Set up Interrupt Controller before we create the VCPUs */
|
783 |
spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, |
784 |
XICS_IRQS); |
785 |
spapr->next_irq = XICS_IRQ_BASE; |
786 |
|
787 |
/* init CPUs */
|
788 |
if (cpu_model == NULL) { |
789 |
cpu_model = kvm_enabled() ? "host" : "POWER7"; |
790 |
} |
791 |
for (i = 0; i < smp_cpus; i++) { |
792 |
cpu = cpu_ppc_init(cpu_model); |
793 |
if (cpu == NULL) { |
794 |
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
795 |
exit(1);
|
796 |
} |
797 |
env = &cpu->env; |
798 |
|
799 |
xics_cpu_setup(spapr->icp, cpu); |
800 |
|
801 |
/* Set time-base frequency to 512 MHz */
|
802 |
cpu_ppc_tb_init(env, TIMEBASE_FREQ); |
803 |
|
804 |
/* PAPR always has exception vectors in RAM not ROM. To ensure this,
|
805 |
* MSR[IP] should never be set.
|
806 |
*/
|
807 |
env->msr_mask &= ~(1 << 6); |
808 |
|
809 |
/* Tell KVM that we're in PAPR mode */
|
810 |
if (kvm_enabled()) {
|
811 |
kvmppc_set_papr(cpu); |
812 |
} |
813 |
|
814 |
qemu_register_reset(spapr_cpu_reset, cpu); |
815 |
} |
816 |
|
817 |
/* allocate RAM */
|
818 |
spapr->ram_limit = ram_size; |
819 |
if (spapr->ram_limit > rma_alloc_size) {
|
820 |
ram_addr_t nonrma_base = rma_alloc_size; |
821 |
ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; |
822 |
|
823 |
memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
|
824 |
vmstate_register_ram_global(ram); |
825 |
memory_region_add_subregion(sysmem, nonrma_base, ram); |
826 |
} |
827 |
|
828 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
|
829 |
spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
830 |
rtas_limit - spapr->rtas_addr); |
831 |
if (spapr->rtas_size < 0) { |
832 |
hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
833 |
exit(1);
|
834 |
} |
835 |
if (spapr->rtas_size > RTAS_MAX_SIZE) {
|
836 |
hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
|
837 |
spapr->rtas_size, RTAS_MAX_SIZE); |
838 |
exit(1);
|
839 |
} |
840 |
g_free(filename); |
841 |
|
842 |
/* Set up EPOW events infrastructure */
|
843 |
spapr_events_init(spapr); |
844 |
|
845 |
/* Set up IOMMU */
|
846 |
spapr_iommu_init(); |
847 |
|
848 |
/* Set up VIO bus */
|
849 |
spapr->vio_bus = spapr_vio_bus_init(); |
850 |
|
851 |
for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
852 |
if (serial_hds[i]) {
|
853 |
spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
854 |
} |
855 |
} |
856 |
|
857 |
/* We always have at least the nvram device on VIO */
|
858 |
spapr_create_nvram(spapr); |
859 |
|
860 |
/* Set up PCI */
|
861 |
spapr_pci_rtas_init(); |
862 |
|
863 |
phb = spapr_create_phb(spapr, 0);
|
864 |
|
865 |
for (i = 0; i < nb_nics; i++) { |
866 |
NICInfo *nd = &nd_table[i]; |
867 |
|
868 |
if (!nd->model) {
|
869 |
nd->model = g_strdup("ibmveth");
|
870 |
} |
871 |
|
872 |
if (strcmp(nd->model, "ibmveth") == 0) { |
873 |
spapr_vlan_create(spapr->vio_bus, nd); |
874 |
} else {
|
875 |
pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
|
876 |
} |
877 |
} |
878 |
|
879 |
for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
880 |
spapr_vscsi_create(spapr->vio_bus); |
881 |
} |
882 |
|
883 |
/* Graphics */
|
884 |
if (spapr_vga_init(phb->bus)) {
|
885 |
spapr->has_graphics = true;
|
886 |
} |
887 |
|
888 |
if (usb_enabled(spapr->has_graphics)) {
|
889 |
pci_create_simple(phb->bus, -1, "pci-ohci"); |
890 |
if (spapr->has_graphics) {
|
891 |
usbdevice_create("keyboard");
|
892 |
usbdevice_create("mouse");
|
893 |
} |
894 |
} |
895 |
|
896 |
if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
897 |
fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
|
898 |
"%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
|
899 |
exit(1);
|
900 |
} |
901 |
|
902 |
if (kernel_filename) {
|
903 |
uint64_t lowaddr = 0;
|
904 |
|
905 |
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
906 |
NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); |
907 |
if (kernel_size < 0) { |
908 |
kernel_size = load_image_targphys(kernel_filename, |
909 |
KERNEL_LOAD_ADDR, |
910 |
load_limit - KERNEL_LOAD_ADDR); |
911 |
} |
912 |
if (kernel_size < 0) { |
913 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
914 |
kernel_filename); |
915 |
exit(1);
|
916 |
} |
917 |
|
918 |
/* load initrd */
|
919 |
if (initrd_filename) {
|
920 |
/* Try to locate the initrd in the gap between the kernel
|
921 |
* and the firmware. Add a bit of space just in case
|
922 |
*/
|
923 |
initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; |
924 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
925 |
load_limit - initrd_base); |
926 |
if (initrd_size < 0) { |
927 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
928 |
initrd_filename); |
929 |
exit(1);
|
930 |
} |
931 |
} else {
|
932 |
initrd_base = 0;
|
933 |
initrd_size = 0;
|
934 |
} |
935 |
} |
936 |
|
937 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME); |
938 |
fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
|
939 |
if (fw_size < 0) { |
940 |
hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
941 |
exit(1);
|
942 |
} |
943 |
g_free(filename); |
944 |
|
945 |
spapr->entry_point = 0x100;
|
946 |
|
947 |
/* Prepare the device tree */
|
948 |
spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, |
949 |
initrd_base, initrd_size, |
950 |
kernel_size, |
951 |
boot_device, kernel_cmdline, |
952 |
spapr->epow_irq); |
953 |
assert(spapr->fdt_skel != NULL);
|
954 |
} |
955 |
|
956 |
static QEMUMachine spapr_machine = {
|
957 |
.name = "pseries",
|
958 |
.desc = "pSeries Logical Partition (PAPR compliant)",
|
959 |
.init = ppc_spapr_init, |
960 |
.reset = ppc_spapr_reset, |
961 |
.block_default_type = IF_SCSI, |
962 |
.max_cpus = MAX_CPUS, |
963 |
.no_parallel = 1,
|
964 |
.boot_order = NULL,
|
965 |
}; |
966 |
|
967 |
static void spapr_machine_init(void) |
968 |
{ |
969 |
qemu_register_machine(&spapr_machine); |
970 |
} |
971 |
|
972 |
machine_init(spapr_machine_init); |