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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU PC System Emulator
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "fdc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 87ecb68b | pbrook | #include "block.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "audio/audio.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "smbus.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | 376253ec | aliguori | #include "monitor.h" |
35 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
36 | a2fa19f9 | aliguori | #include "virtio-console.h" |
37 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
38 | 9dd986cc | Richard W.M. Jones | #include "watchdog.h" |
39 | b6f6e3d3 | aliguori | #include "smbios.h" |
40 | 80cabfad | bellard | |
41 | b41a2cd1 | bellard | /* output Bochs bios info messages */
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42 | b41a2cd1 | bellard | //#define DEBUG_BIOS
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43 | b41a2cd1 | bellard | |
44 | 80cabfad | bellard | #define BIOS_FILENAME "bios.bin" |
45 | 80cabfad | bellard | #define VGABIOS_FILENAME "vgabios.bin" |
46 | de9258a8 | bellard | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
47 | 80cabfad | bellard | |
48 | 7fb4fdcf | balrog | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
49 | 7fb4fdcf | balrog | |
50 | a80274c3 | pbrook | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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51 | a80274c3 | pbrook | #define ACPI_DATA_SIZE 0x10000 |
52 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
53 | 8a92ea2f | aliguori | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
54 | b6f6e3d3 | aliguori | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
55 | 80cabfad | bellard | |
56 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
57 | e4bcb14c | ths | |
58 | baca51fa | bellard | static fdctrl_t *floppy_controller;
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59 | b0a21b53 | bellard | static RTCState *rtc_state;
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60 | ec844b96 | bellard | static PITState *pit;
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61 | d592d303 | bellard | static IOAPICState *ioapic;
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62 | a5954d5c | bellard | static PCIDevice *i440fx_state;
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63 | 80cabfad | bellard | |
64 | e28f9884 | Glauber Costa | typedef struct rom_reset_data { |
65 | e28f9884 | Glauber Costa | uint8_t *data; |
66 | e28f9884 | Glauber Costa | target_phys_addr_t addr; |
67 | e28f9884 | Glauber Costa | unsigned size;
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68 | e28f9884 | Glauber Costa | } RomResetData; |
69 | e28f9884 | Glauber Costa | |
70 | e28f9884 | Glauber Costa | static void option_rom_reset(void *_rrd) |
71 | e28f9884 | Glauber Costa | { |
72 | e28f9884 | Glauber Costa | RomResetData *rrd = _rrd; |
73 | e28f9884 | Glauber Costa | |
74 | e28f9884 | Glauber Costa | cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); |
75 | e28f9884 | Glauber Costa | } |
76 | e28f9884 | Glauber Costa | |
77 | e28f9884 | Glauber Costa | static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size) |
78 | e28f9884 | Glauber Costa | { |
79 | e28f9884 | Glauber Costa | RomResetData *rrd = qemu_malloc(sizeof *rrd);
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80 | e28f9884 | Glauber Costa | |
81 | e28f9884 | Glauber Costa | rrd->data = qemu_malloc(size); |
82 | e28f9884 | Glauber Costa | cpu_physical_memory_read(addr, rrd->data, size); |
83 | e28f9884 | Glauber Costa | rrd->addr = addr; |
84 | e28f9884 | Glauber Costa | rrd->size = size; |
85 | e28f9884 | Glauber Costa | qemu_register_reset(option_rom_reset, rrd); |
86 | e28f9884 | Glauber Costa | } |
87 | e28f9884 | Glauber Costa | |
88 | b41a2cd1 | bellard | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
89 | 80cabfad | bellard | { |
90 | 80cabfad | bellard | } |
91 | 80cabfad | bellard | |
92 | f929aad6 | bellard | /* MSDOS compatibility mode FPU exception support */
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93 | d537cf6c | pbrook | static qemu_irq ferr_irq;
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94 | f929aad6 | bellard | /* XXX: add IGNNE support */
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95 | f929aad6 | bellard | void cpu_set_ferr(CPUX86State *s)
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96 | f929aad6 | bellard | { |
97 | d537cf6c | pbrook | qemu_irq_raise(ferr_irq); |
98 | f929aad6 | bellard | } |
99 | f929aad6 | bellard | |
100 | f929aad6 | bellard | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
101 | f929aad6 | bellard | { |
102 | d537cf6c | pbrook | qemu_irq_lower(ferr_irq); |
103 | f929aad6 | bellard | } |
104 | f929aad6 | bellard | |
105 | 28ab0e2e | bellard | /* TSC handling */
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106 | 28ab0e2e | bellard | uint64_t cpu_get_tsc(CPUX86State *env) |
107 | 28ab0e2e | bellard | { |
108 | 1dce7c3c | bellard | /* Note: when using kqemu, it is more logical to return the host TSC
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109 | 1dce7c3c | bellard | because kqemu does not trap the RDTSC instruction for
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110 | 1dce7c3c | bellard | performance reasons */
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111 | 640f42e4 | blueswir1 | #ifdef CONFIG_KQEMU
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112 | 1dce7c3c | bellard | if (env->kqemu_enabled) {
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113 | 1dce7c3c | bellard | return cpu_get_real_ticks();
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114 | 5fafdf24 | ths | } else
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115 | 1dce7c3c | bellard | #endif
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116 | 1dce7c3c | bellard | { |
117 | 1dce7c3c | bellard | return cpu_get_ticks();
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118 | 1dce7c3c | bellard | } |
119 | 28ab0e2e | bellard | } |
120 | 28ab0e2e | bellard | |
121 | a5954d5c | bellard | /* SMM support */
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122 | a5954d5c | bellard | void cpu_smm_update(CPUState *env)
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123 | a5954d5c | bellard | { |
124 | a5954d5c | bellard | if (i440fx_state && env == first_cpu)
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125 | a5954d5c | bellard | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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126 | a5954d5c | bellard | } |
127 | a5954d5c | bellard | |
128 | a5954d5c | bellard | |
129 | 3de388f6 | bellard | /* IRQ handling */
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130 | 3de388f6 | bellard | int cpu_get_pic_interrupt(CPUState *env)
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131 | 3de388f6 | bellard | { |
132 | 3de388f6 | bellard | int intno;
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133 | 3de388f6 | bellard | |
134 | 3de388f6 | bellard | intno = apic_get_interrupt(env); |
135 | 3de388f6 | bellard | if (intno >= 0) { |
136 | 3de388f6 | bellard | /* set irq request if a PIC irq is still pending */
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137 | 3de388f6 | bellard | /* XXX: improve that */
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138 | 5fafdf24 | ths | pic_update_irq(isa_pic); |
139 | 3de388f6 | bellard | return intno;
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140 | 3de388f6 | bellard | } |
141 | 3de388f6 | bellard | /* read the irq from the PIC */
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142 | 0e21e12b | ths | if (!apic_accept_pic_intr(env))
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143 | 0e21e12b | ths | return -1; |
144 | 0e21e12b | ths | |
145 | 3de388f6 | bellard | intno = pic_read_irq(isa_pic); |
146 | 3de388f6 | bellard | return intno;
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147 | 3de388f6 | bellard | } |
148 | 3de388f6 | bellard | |
149 | d537cf6c | pbrook | static void pic_irq_request(void *opaque, int irq, int level) |
150 | 3de388f6 | bellard | { |
151 | a5b38b51 | aurel32 | CPUState *env = first_cpu; |
152 | a5b38b51 | aurel32 | |
153 | d5529471 | aurel32 | if (env->apic_state) {
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154 | d5529471 | aurel32 | while (env) {
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155 | d5529471 | aurel32 | if (apic_accept_pic_intr(env))
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156 | 1a7de94a | aurel32 | apic_deliver_pic_intr(env, level); |
157 | d5529471 | aurel32 | env = env->next_cpu; |
158 | d5529471 | aurel32 | } |
159 | d5529471 | aurel32 | } else {
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160 | b614106a | aurel32 | if (level)
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161 | b614106a | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
162 | b614106a | aurel32 | else
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163 | b614106a | aurel32 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
164 | a5b38b51 | aurel32 | } |
165 | 3de388f6 | bellard | } |
166 | 3de388f6 | bellard | |
167 | b0a21b53 | bellard | /* PC cmos mappings */
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168 | b0a21b53 | bellard | |
169 | 80cabfad | bellard | #define REG_EQUIPMENT_BYTE 0x14 |
170 | 80cabfad | bellard | |
171 | 777428f2 | bellard | static int cmos_get_fd_drive_type(int fd0) |
172 | 777428f2 | bellard | { |
173 | 777428f2 | bellard | int val;
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174 | 777428f2 | bellard | |
175 | 777428f2 | bellard | switch (fd0) {
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176 | 777428f2 | bellard | case 0: |
177 | 777428f2 | bellard | /* 1.44 Mb 3"5 drive */
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178 | 777428f2 | bellard | val = 4;
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179 | 777428f2 | bellard | break;
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180 | 777428f2 | bellard | case 1: |
181 | 777428f2 | bellard | /* 2.88 Mb 3"5 drive */
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182 | 777428f2 | bellard | val = 5;
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183 | 777428f2 | bellard | break;
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184 | 777428f2 | bellard | case 2: |
185 | 777428f2 | bellard | /* 1.2 Mb 5"5 drive */
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186 | 777428f2 | bellard | val = 2;
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187 | 777428f2 | bellard | break;
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188 | 777428f2 | bellard | default:
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189 | 777428f2 | bellard | val = 0;
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190 | 777428f2 | bellard | break;
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191 | 777428f2 | bellard | } |
192 | 777428f2 | bellard | return val;
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193 | 777428f2 | bellard | } |
194 | 777428f2 | bellard | |
195 | 5fafdf24 | ths | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
196 | ba6c2377 | bellard | { |
197 | ba6c2377 | bellard | RTCState *s = rtc_state; |
198 | ba6c2377 | bellard | int cylinders, heads, sectors;
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199 | ba6c2377 | bellard | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
200 | ba6c2377 | bellard | rtc_set_memory(s, type_ofs, 47);
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201 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs, cylinders); |
202 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
203 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 2, heads);
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204 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 3, 0xff); |
205 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 4, 0xff); |
206 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
207 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 6, cylinders);
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208 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
209 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 8, sectors);
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210 | ba6c2377 | bellard | } |
211 | ba6c2377 | bellard | |
212 | 6ac0e82d | balrog | /* convert boot_device letter to something recognizable by the bios */
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213 | 6ac0e82d | balrog | static int boot_device2nibble(char boot_device) |
214 | 6ac0e82d | balrog | { |
215 | 6ac0e82d | balrog | switch(boot_device) {
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216 | 6ac0e82d | balrog | case 'a': |
217 | 6ac0e82d | balrog | case 'b': |
218 | 6ac0e82d | balrog | return 0x01; /* floppy boot */ |
219 | 6ac0e82d | balrog | case 'c': |
220 | 6ac0e82d | balrog | return 0x02; /* hard drive boot */ |
221 | 6ac0e82d | balrog | case 'd': |
222 | 6ac0e82d | balrog | return 0x03; /* CD-ROM boot */ |
223 | 6ac0e82d | balrog | case 'n': |
224 | 6ac0e82d | balrog | return 0x04; /* Network boot */ |
225 | 6ac0e82d | balrog | } |
226 | 6ac0e82d | balrog | return 0; |
227 | 6ac0e82d | balrog | } |
228 | 6ac0e82d | balrog | |
229 | 0ecdffbb | aurel32 | /* copy/pasted from cmos_init, should be made a general function
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230 | 0ecdffbb | aurel32 | and used there as well */
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231 | 3b4366de | blueswir1 | static int pc_boot_set(void *opaque, const char *boot_device) |
232 | 0ecdffbb | aurel32 | { |
233 | 376253ec | aliguori | Monitor *mon = cur_mon; |
234 | 0ecdffbb | aurel32 | #define PC_MAX_BOOT_DEVICES 3 |
235 | 3b4366de | blueswir1 | RTCState *s = (RTCState *)opaque; |
236 | 0ecdffbb | aurel32 | int nbds, bds[3] = { 0, }; |
237 | 0ecdffbb | aurel32 | int i;
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238 | 0ecdffbb | aurel32 | |
239 | 0ecdffbb | aurel32 | nbds = strlen(boot_device); |
240 | 0ecdffbb | aurel32 | if (nbds > PC_MAX_BOOT_DEVICES) {
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241 | 376253ec | aliguori | monitor_printf(mon, "Too many boot devices for PC\n");
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242 | 0ecdffbb | aurel32 | return(1); |
243 | 0ecdffbb | aurel32 | } |
244 | 0ecdffbb | aurel32 | for (i = 0; i < nbds; i++) { |
245 | 0ecdffbb | aurel32 | bds[i] = boot_device2nibble(boot_device[i]); |
246 | 0ecdffbb | aurel32 | if (bds[i] == 0) { |
247 | 376253ec | aliguori | monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
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248 | 376253ec | aliguori | boot_device[i]); |
249 | 0ecdffbb | aurel32 | return(1); |
250 | 0ecdffbb | aurel32 | } |
251 | 0ecdffbb | aurel32 | } |
252 | 0ecdffbb | aurel32 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
253 | 0ecdffbb | aurel32 | rtc_set_memory(s, 0x38, (bds[2] << 4)); |
254 | 0ecdffbb | aurel32 | return(0); |
255 | 0ecdffbb | aurel32 | } |
256 | 0ecdffbb | aurel32 | |
257 | ba6c2377 | bellard | /* hd_table must contain 4 block drivers */
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258 | 00f82b8a | aurel32 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
259 | 00f82b8a | aurel32 | const char *boot_device, BlockDriverState **hd_table) |
260 | 80cabfad | bellard | { |
261 | b0a21b53 | bellard | RTCState *s = rtc_state; |
262 | 28c5af54 | j_mayer | int nbds, bds[3] = { 0, }; |
263 | 80cabfad | bellard | int val;
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264 | b41a2cd1 | bellard | int fd0, fd1, nb;
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265 | ba6c2377 | bellard | int i;
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266 | b0a21b53 | bellard | |
267 | b0a21b53 | bellard | /* various important CMOS locations needed by PC/Bochs bios */
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268 | 80cabfad | bellard | |
269 | 80cabfad | bellard | /* memory size */
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270 | 333190eb | bellard | val = 640; /* base memory in K */ |
271 | 333190eb | bellard | rtc_set_memory(s, 0x15, val);
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272 | 333190eb | bellard | rtc_set_memory(s, 0x16, val >> 8); |
273 | 333190eb | bellard | |
274 | 80cabfad | bellard | val = (ram_size / 1024) - 1024; |
275 | 80cabfad | bellard | if (val > 65535) |
276 | 80cabfad | bellard | val = 65535;
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277 | b0a21b53 | bellard | rtc_set_memory(s, 0x17, val);
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278 | b0a21b53 | bellard | rtc_set_memory(s, 0x18, val >> 8); |
279 | b0a21b53 | bellard | rtc_set_memory(s, 0x30, val);
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280 | b0a21b53 | bellard | rtc_set_memory(s, 0x31, val >> 8); |
281 | 80cabfad | bellard | |
282 | 00f82b8a | aurel32 | if (above_4g_mem_size) {
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283 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
284 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
285 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
286 | 00f82b8a | aurel32 | } |
287 | 00f82b8a | aurel32 | |
288 | 9da98861 | bellard | if (ram_size > (16 * 1024 * 1024)) |
289 | 9da98861 | bellard | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
290 | 9da98861 | bellard | else
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291 | 9da98861 | bellard | val = 0;
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292 | 80cabfad | bellard | if (val > 65535) |
293 | 80cabfad | bellard | val = 65535;
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294 | b0a21b53 | bellard | rtc_set_memory(s, 0x34, val);
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295 | b0a21b53 | bellard | rtc_set_memory(s, 0x35, val >> 8); |
296 | 3b46e624 | ths | |
297 | 298e01b6 | aurel32 | /* set the number of CPU */
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298 | 298e01b6 | aurel32 | rtc_set_memory(s, 0x5f, smp_cpus - 1); |
299 | 298e01b6 | aurel32 | |
300 | 6ac0e82d | balrog | /* set boot devices, and disable floppy signature check if requested */
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301 | 28c5af54 | j_mayer | #define PC_MAX_BOOT_DEVICES 3 |
302 | 28c5af54 | j_mayer | nbds = strlen(boot_device); |
303 | 28c5af54 | j_mayer | if (nbds > PC_MAX_BOOT_DEVICES) {
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304 | 28c5af54 | j_mayer | fprintf(stderr, "Too many boot devices for PC\n");
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305 | 28c5af54 | j_mayer | exit(1);
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306 | 28c5af54 | j_mayer | } |
307 | 28c5af54 | j_mayer | for (i = 0; i < nbds; i++) { |
308 | 28c5af54 | j_mayer | bds[i] = boot_device2nibble(boot_device[i]); |
309 | 28c5af54 | j_mayer | if (bds[i] == 0) { |
310 | 28c5af54 | j_mayer | fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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311 | 28c5af54 | j_mayer | boot_device[i]); |
312 | 28c5af54 | j_mayer | exit(1);
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313 | 28c5af54 | j_mayer | } |
314 | 28c5af54 | j_mayer | } |
315 | 28c5af54 | j_mayer | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
316 | 28c5af54 | j_mayer | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
317 | 80cabfad | bellard | |
318 | b41a2cd1 | bellard | /* floppy type */
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319 | b41a2cd1 | bellard | |
320 | baca51fa | bellard | fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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321 | baca51fa | bellard | fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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322 | 80cabfad | bellard | |
323 | 777428f2 | bellard | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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324 | b0a21b53 | bellard | rtc_set_memory(s, 0x10, val);
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325 | 3b46e624 | ths | |
326 | b0a21b53 | bellard | val = 0;
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327 | b41a2cd1 | bellard | nb = 0;
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328 | 80cabfad | bellard | if (fd0 < 3) |
329 | 80cabfad | bellard | nb++; |
330 | 80cabfad | bellard | if (fd1 < 3) |
331 | 80cabfad | bellard | nb++; |
332 | 80cabfad | bellard | switch (nb) {
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333 | 80cabfad | bellard | case 0: |
334 | 80cabfad | bellard | break;
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335 | 80cabfad | bellard | case 1: |
336 | b0a21b53 | bellard | val |= 0x01; /* 1 drive, ready for boot */ |
337 | 80cabfad | bellard | break;
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338 | 80cabfad | bellard | case 2: |
339 | b0a21b53 | bellard | val |= 0x41; /* 2 drives, ready for boot */ |
340 | 80cabfad | bellard | break;
|
341 | 80cabfad | bellard | } |
342 | b0a21b53 | bellard | val |= 0x02; /* FPU is there */ |
343 | b0a21b53 | bellard | val |= 0x04; /* PS/2 mouse installed */ |
344 | b0a21b53 | bellard | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
345 | b0a21b53 | bellard | |
346 | ba6c2377 | bellard | /* hard drives */
|
347 | ba6c2377 | bellard | |
348 | ba6c2377 | bellard | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
349 | ba6c2377 | bellard | if (hd_table[0]) |
350 | ba6c2377 | bellard | cmos_init_hd(0x19, 0x1b, hd_table[0]); |
351 | 5fafdf24 | ths | if (hd_table[1]) |
352 | ba6c2377 | bellard | cmos_init_hd(0x1a, 0x24, hd_table[1]); |
353 | ba6c2377 | bellard | |
354 | ba6c2377 | bellard | val = 0;
|
355 | 40b6ecc6 | bellard | for (i = 0; i < 4; i++) { |
356 | ba6c2377 | bellard | if (hd_table[i]) {
|
357 | 46d4767d | bellard | int cylinders, heads, sectors, translation;
|
358 | 46d4767d | bellard | /* NOTE: bdrv_get_geometry_hint() returns the physical
|
359 | 46d4767d | bellard | geometry. It is always such that: 1 <= sects <= 63, 1
|
360 | 46d4767d | bellard | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
361 | 46d4767d | bellard | geometry can be different if a translation is done. */
|
362 | 46d4767d | bellard | translation = bdrv_get_translation_hint(hd_table[i]); |
363 | 46d4767d | bellard | if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
364 | 46d4767d | bellard | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
365 | 46d4767d | bellard | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
366 | 46d4767d | bellard | /* No translation. */
|
367 | 46d4767d | bellard | translation = 0;
|
368 | 46d4767d | bellard | } else {
|
369 | 46d4767d | bellard | /* LBA translation. */
|
370 | 46d4767d | bellard | translation = 1;
|
371 | 46d4767d | bellard | } |
372 | 40b6ecc6 | bellard | } else {
|
373 | 46d4767d | bellard | translation--; |
374 | ba6c2377 | bellard | } |
375 | ba6c2377 | bellard | val |= translation << (i * 2);
|
376 | ba6c2377 | bellard | } |
377 | 40b6ecc6 | bellard | } |
378 | ba6c2377 | bellard | rtc_set_memory(s, 0x39, val);
|
379 | 80cabfad | bellard | } |
380 | 80cabfad | bellard | |
381 | 59b8ad81 | bellard | void ioport_set_a20(int enable) |
382 | 59b8ad81 | bellard | { |
383 | 59b8ad81 | bellard | /* XXX: send to all CPUs ? */
|
384 | 59b8ad81 | bellard | cpu_x86_set_a20(first_cpu, enable); |
385 | 59b8ad81 | bellard | } |
386 | 59b8ad81 | bellard | |
387 | 59b8ad81 | bellard | int ioport_get_a20(void) |
388 | 59b8ad81 | bellard | { |
389 | 59b8ad81 | bellard | return ((first_cpu->a20_mask >> 20) & 1); |
390 | 59b8ad81 | bellard | } |
391 | 59b8ad81 | bellard | |
392 | e1a23744 | bellard | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
393 | e1a23744 | bellard | { |
394 | 59b8ad81 | bellard | ioport_set_a20((val >> 1) & 1); |
395 | e1a23744 | bellard | /* XXX: bit 0 is fast reset */
|
396 | e1a23744 | bellard | } |
397 | e1a23744 | bellard | |
398 | e1a23744 | bellard | static uint32_t ioport92_read(void *opaque, uint32_t addr) |
399 | e1a23744 | bellard | { |
400 | 59b8ad81 | bellard | return ioport_get_a20() << 1; |
401 | e1a23744 | bellard | } |
402 | e1a23744 | bellard | |
403 | 80cabfad | bellard | /***********************************************************/
|
404 | 80cabfad | bellard | /* Bochs BIOS debug ports */
|
405 | 80cabfad | bellard | |
406 | 9596ebb7 | pbrook | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
407 | 80cabfad | bellard | { |
408 | a2f659ee | bellard | static const char shutdown_str[8] = "Shutdown"; |
409 | a2f659ee | bellard | static int shutdown_index = 0; |
410 | 3b46e624 | ths | |
411 | 80cabfad | bellard | switch(addr) {
|
412 | 80cabfad | bellard | /* Bochs BIOS messages */
|
413 | 80cabfad | bellard | case 0x400: |
414 | 80cabfad | bellard | case 0x401: |
415 | 80cabfad | bellard | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
416 | 80cabfad | bellard | exit(1);
|
417 | 80cabfad | bellard | case 0x402: |
418 | 80cabfad | bellard | case 0x403: |
419 | 80cabfad | bellard | #ifdef DEBUG_BIOS
|
420 | 80cabfad | bellard | fprintf(stderr, "%c", val);
|
421 | 80cabfad | bellard | #endif
|
422 | 80cabfad | bellard | break;
|
423 | a2f659ee | bellard | case 0x8900: |
424 | a2f659ee | bellard | /* same as Bochs power off */
|
425 | a2f659ee | bellard | if (val == shutdown_str[shutdown_index]) {
|
426 | a2f659ee | bellard | shutdown_index++; |
427 | a2f659ee | bellard | if (shutdown_index == 8) { |
428 | a2f659ee | bellard | shutdown_index = 0;
|
429 | a2f659ee | bellard | qemu_system_shutdown_request(); |
430 | a2f659ee | bellard | } |
431 | a2f659ee | bellard | } else {
|
432 | a2f659ee | bellard | shutdown_index = 0;
|
433 | a2f659ee | bellard | } |
434 | a2f659ee | bellard | break;
|
435 | 80cabfad | bellard | |
436 | 80cabfad | bellard | /* LGPL'ed VGA BIOS messages */
|
437 | 80cabfad | bellard | case 0x501: |
438 | 80cabfad | bellard | case 0x502: |
439 | 80cabfad | bellard | fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
440 | 80cabfad | bellard | exit(1);
|
441 | 80cabfad | bellard | case 0x500: |
442 | 80cabfad | bellard | case 0x503: |
443 | 80cabfad | bellard | #ifdef DEBUG_BIOS
|
444 | 80cabfad | bellard | fprintf(stderr, "%c", val);
|
445 | 80cabfad | bellard | #endif
|
446 | 80cabfad | bellard | break;
|
447 | 80cabfad | bellard | } |
448 | 80cabfad | bellard | } |
449 | 80cabfad | bellard | |
450 | 11c2fd3e | aliguori | extern uint64_t node_cpumask[MAX_NODES];
|
451 | 11c2fd3e | aliguori | |
452 | 9596ebb7 | pbrook | static void bochs_bios_init(void) |
453 | 80cabfad | bellard | { |
454 | 3cce6243 | blueswir1 | void *fw_cfg;
|
455 | b6f6e3d3 | aliguori | uint8_t *smbios_table; |
456 | b6f6e3d3 | aliguori | size_t smbios_len; |
457 | 11c2fd3e | aliguori | uint64_t *numa_fw_cfg; |
458 | 11c2fd3e | aliguori | int i, j;
|
459 | 3cce6243 | blueswir1 | |
460 | b41a2cd1 | bellard | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
461 | b41a2cd1 | bellard | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
462 | b41a2cd1 | bellard | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
463 | b41a2cd1 | bellard | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
464 | a2f659ee | bellard | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
465 | b41a2cd1 | bellard | |
466 | b41a2cd1 | bellard | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
467 | b41a2cd1 | bellard | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
468 | b41a2cd1 | bellard | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
469 | b41a2cd1 | bellard | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
470 | 3cce6243 | blueswir1 | |
471 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
472 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
473 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
474 | 80deece2 | blueswir1 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
475 | 80deece2 | blueswir1 | acpi_tables_len); |
476 | b6f6e3d3 | aliguori | |
477 | b6f6e3d3 | aliguori | smbios_table = smbios_get_table(&smbios_len); |
478 | b6f6e3d3 | aliguori | if (smbios_table)
|
479 | b6f6e3d3 | aliguori | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
480 | b6f6e3d3 | aliguori | smbios_table, smbios_len); |
481 | 11c2fd3e | aliguori | |
482 | 11c2fd3e | aliguori | /* allocate memory for the NUMA channel: one (64bit) word for the number
|
483 | 11c2fd3e | aliguori | * of nodes, one word for each VCPU->node and one word for each node to
|
484 | 11c2fd3e | aliguori | * hold the amount of memory.
|
485 | 11c2fd3e | aliguori | */
|
486 | 11c2fd3e | aliguori | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
487 | 11c2fd3e | aliguori | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
488 | 11c2fd3e | aliguori | for (i = 0; i < smp_cpus; i++) { |
489 | 11c2fd3e | aliguori | for (j = 0; j < nb_numa_nodes; j++) { |
490 | 11c2fd3e | aliguori | if (node_cpumask[j] & (1 << i)) { |
491 | 11c2fd3e | aliguori | numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
492 | 11c2fd3e | aliguori | break;
|
493 | 11c2fd3e | aliguori | } |
494 | 11c2fd3e | aliguori | } |
495 | 11c2fd3e | aliguori | } |
496 | 11c2fd3e | aliguori | for (i = 0; i < nb_numa_nodes; i++) { |
497 | 11c2fd3e | aliguori | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
498 | 11c2fd3e | aliguori | } |
499 | 11c2fd3e | aliguori | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
500 | 11c2fd3e | aliguori | (1 + smp_cpus + nb_numa_nodes) * 8); |
501 | 80cabfad | bellard | } |
502 | 80cabfad | bellard | |
503 | 642a4f96 | ths | /* Generate an initial boot sector which sets state and jump to
|
504 | 642a4f96 | ths | a specified vector */
|
505 | 7ffa4767 | pbrook | static void generate_bootsect(target_phys_addr_t option_rom, |
506 | 4fc9af53 | aliguori | uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
507 | 642a4f96 | ths | { |
508 | 4fc9af53 | aliguori | uint8_t rom[512], *p, *reloc;
|
509 | 4fc9af53 | aliguori | uint8_t sum; |
510 | 642a4f96 | ths | int i;
|
511 | 642a4f96 | ths | |
512 | 4fc9af53 | aliguori | memset(rom, 0, sizeof(rom)); |
513 | 4fc9af53 | aliguori | |
514 | 4fc9af53 | aliguori | p = rom; |
515 | 4fc9af53 | aliguori | /* Make sure we have an option rom signature */
|
516 | 4fc9af53 | aliguori | *p++ = 0x55;
|
517 | 4fc9af53 | aliguori | *p++ = 0xaa;
|
518 | 642a4f96 | ths | |
519 | 4fc9af53 | aliguori | /* ROM size in sectors*/
|
520 | 4fc9af53 | aliguori | *p++ = 1;
|
521 | 642a4f96 | ths | |
522 | 4fc9af53 | aliguori | /* Hook int19 */
|
523 | 642a4f96 | ths | |
524 | 4fc9af53 | aliguori | *p++ = 0x50; /* push ax */ |
525 | 4fc9af53 | aliguori | *p++ = 0x1e; /* push ds */ |
526 | 4fc9af53 | aliguori | *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ |
527 | 4fc9af53 | aliguori | *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ |
528 | 642a4f96 | ths | |
529 | 4fc9af53 | aliguori | *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
530 | 4fc9af53 | aliguori | *p++ = 0x64; *p++ = 0x00; |
531 | 4fc9af53 | aliguori | reloc = p; |
532 | 4fc9af53 | aliguori | *p++ = 0x00; *p++ = 0x00; |
533 | 4fc9af53 | aliguori | |
534 | 4fc9af53 | aliguori | *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ |
535 | 4fc9af53 | aliguori | *p++ = 0x66; *p++ = 0x00; |
536 | 4fc9af53 | aliguori | |
537 | 4fc9af53 | aliguori | *p++ = 0x1f; /* pop ds */ |
538 | 4fc9af53 | aliguori | *p++ = 0x58; /* pop ax */ |
539 | 4fc9af53 | aliguori | *p++ = 0xcb; /* lret */ |
540 | 4fc9af53 | aliguori | |
541 | 642a4f96 | ths | /* Actual code */
|
542 | 4fc9af53 | aliguori | *reloc = (p - rom); |
543 | 4fc9af53 | aliguori | |
544 | 642a4f96 | ths | *p++ = 0xfa; /* CLI */ |
545 | 642a4f96 | ths | *p++ = 0xfc; /* CLD */ |
546 | 642a4f96 | ths | |
547 | 642a4f96 | ths | for (i = 0; i < 6; i++) { |
548 | 642a4f96 | ths | if (i == 1) /* Skip CS */ |
549 | 642a4f96 | ths | continue;
|
550 | 642a4f96 | ths | |
551 | 642a4f96 | ths | *p++ = 0xb8; /* MOV AX,imm16 */ |
552 | 642a4f96 | ths | *p++ = segs[i]; |
553 | 642a4f96 | ths | *p++ = segs[i] >> 8;
|
554 | 642a4f96 | ths | *p++ = 0x8e; /* MOV <seg>,AX */ |
555 | 642a4f96 | ths | *p++ = 0xc0 + (i << 3); |
556 | 642a4f96 | ths | } |
557 | 642a4f96 | ths | |
558 | 642a4f96 | ths | for (i = 0; i < 8; i++) { |
559 | 642a4f96 | ths | *p++ = 0x66; /* 32-bit operand size */ |
560 | 642a4f96 | ths | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ |
561 | 642a4f96 | ths | *p++ = gpr[i]; |
562 | 642a4f96 | ths | *p++ = gpr[i] >> 8;
|
563 | 642a4f96 | ths | *p++ = gpr[i] >> 16;
|
564 | 642a4f96 | ths | *p++ = gpr[i] >> 24;
|
565 | 642a4f96 | ths | } |
566 | 642a4f96 | ths | |
567 | 642a4f96 | ths | *p++ = 0xea; /* JMP FAR */ |
568 | 642a4f96 | ths | *p++ = ip; /* IP */
|
569 | 642a4f96 | ths | *p++ = ip >> 8;
|
570 | 642a4f96 | ths | *p++ = segs[1]; /* CS */ |
571 | 642a4f96 | ths | *p++ = segs[1] >> 8; |
572 | 642a4f96 | ths | |
573 | 4fc9af53 | aliguori | /* sign rom */
|
574 | 4fc9af53 | aliguori | sum = 0;
|
575 | 4fc9af53 | aliguori | for (i = 0; i < (sizeof(rom) - 1); i++) |
576 | 4fc9af53 | aliguori | sum += rom[i]; |
577 | 4fc9af53 | aliguori | rom[sizeof(rom) - 1] = -sum; |
578 | 4fc9af53 | aliguori | |
579 | 7ffa4767 | pbrook | cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
|
580 | d6ecb036 | Glauber Costa | option_rom_setup_reset(option_rom, sizeof (rom));
|
581 | 642a4f96 | ths | } |
582 | 80cabfad | bellard | |
583 | 642a4f96 | ths | static long get_file_size(FILE *f) |
584 | 642a4f96 | ths | { |
585 | 642a4f96 | ths | long where, size;
|
586 | 642a4f96 | ths | |
587 | 642a4f96 | ths | /* XXX: on Unix systems, using fstat() probably makes more sense */
|
588 | 642a4f96 | ths | |
589 | 642a4f96 | ths | where = ftell(f); |
590 | 642a4f96 | ths | fseek(f, 0, SEEK_END);
|
591 | 642a4f96 | ths | size = ftell(f); |
592 | 642a4f96 | ths | fseek(f, where, SEEK_SET); |
593 | 642a4f96 | ths | |
594 | 642a4f96 | ths | return size;
|
595 | 642a4f96 | ths | } |
596 | 642a4f96 | ths | |
597 | 7ffa4767 | pbrook | static void load_linux(target_phys_addr_t option_rom, |
598 | 4fc9af53 | aliguori | const char *kernel_filename, |
599 | 642a4f96 | ths | const char *initrd_filename, |
600 | 642a4f96 | ths | const char *kernel_cmdline) |
601 | 642a4f96 | ths | { |
602 | 642a4f96 | ths | uint16_t protocol; |
603 | 642a4f96 | ths | uint32_t gpr[8];
|
604 | 642a4f96 | ths | uint16_t seg[6];
|
605 | 642a4f96 | ths | uint16_t real_seg; |
606 | 642a4f96 | ths | int setup_size, kernel_size, initrd_size, cmdline_size;
|
607 | 642a4f96 | ths | uint32_t initrd_max; |
608 | 642a4f96 | ths | uint8_t header[1024];
|
609 | a37af289 | blueswir1 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr; |
610 | 642a4f96 | ths | FILE *f, *fi; |
611 | 642a4f96 | ths | |
612 | 642a4f96 | ths | /* Align to 16 bytes as a paranoia measure */
|
613 | 642a4f96 | ths | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
614 | 642a4f96 | ths | |
615 | 642a4f96 | ths | /* load the kernel header */
|
616 | 642a4f96 | ths | f = fopen(kernel_filename, "rb");
|
617 | 642a4f96 | ths | if (!f || !(kernel_size = get_file_size(f)) ||
|
618 | 642a4f96 | ths | fread(header, 1, 1024, f) != 1024) { |
619 | 642a4f96 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
620 | 642a4f96 | ths | kernel_filename); |
621 | 642a4f96 | ths | exit(1);
|
622 | 642a4f96 | ths | } |
623 | 642a4f96 | ths | |
624 | 642a4f96 | ths | /* kernel protocol version */
|
625 | bc4edd79 | bellard | #if 0
|
626 | 642a4f96 | ths | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
627 | bc4edd79 | bellard | #endif
|
628 | 642a4f96 | ths | if (ldl_p(header+0x202) == 0x53726448) |
629 | 642a4f96 | ths | protocol = lduw_p(header+0x206);
|
630 | 642a4f96 | ths | else
|
631 | 642a4f96 | ths | protocol = 0;
|
632 | 642a4f96 | ths | |
633 | 642a4f96 | ths | if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
634 | 642a4f96 | ths | /* Low kernel */
|
635 | a37af289 | blueswir1 | real_addr = 0x90000;
|
636 | a37af289 | blueswir1 | cmdline_addr = 0x9a000 - cmdline_size;
|
637 | a37af289 | blueswir1 | prot_addr = 0x10000;
|
638 | 642a4f96 | ths | } else if (protocol < 0x202) { |
639 | 642a4f96 | ths | /* High but ancient kernel */
|
640 | a37af289 | blueswir1 | real_addr = 0x90000;
|
641 | a37af289 | blueswir1 | cmdline_addr = 0x9a000 - cmdline_size;
|
642 | a37af289 | blueswir1 | prot_addr = 0x100000;
|
643 | 642a4f96 | ths | } else {
|
644 | 642a4f96 | ths | /* High and recent kernel */
|
645 | a37af289 | blueswir1 | real_addr = 0x10000;
|
646 | a37af289 | blueswir1 | cmdline_addr = 0x20000;
|
647 | a37af289 | blueswir1 | prot_addr = 0x100000;
|
648 | 642a4f96 | ths | } |
649 | 642a4f96 | ths | |
650 | bc4edd79 | bellard | #if 0
|
651 | 642a4f96 | ths | fprintf(stderr,
|
652 | 526ccb7a | balrog | "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
653 | 526ccb7a | balrog | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
654 | 526ccb7a | balrog | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
655 | a37af289 | blueswir1 | real_addr,
|
656 | a37af289 | blueswir1 | cmdline_addr,
|
657 | a37af289 | blueswir1 | prot_addr);
|
658 | bc4edd79 | bellard | #endif
|
659 | 642a4f96 | ths | |
660 | 642a4f96 | ths | /* highest address for loading the initrd */
|
661 | 642a4f96 | ths | if (protocol >= 0x203) |
662 | 642a4f96 | ths | initrd_max = ldl_p(header+0x22c);
|
663 | 642a4f96 | ths | else
|
664 | 642a4f96 | ths | initrd_max = 0x37ffffff;
|
665 | 642a4f96 | ths | |
666 | 642a4f96 | ths | if (initrd_max >= ram_size-ACPI_DATA_SIZE)
|
667 | 642a4f96 | ths | initrd_max = ram_size-ACPI_DATA_SIZE-1;
|
668 | 642a4f96 | ths | |
669 | 642a4f96 | ths | /* kernel command line */
|
670 | a37af289 | blueswir1 | pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
|
671 | 642a4f96 | ths | |
672 | 642a4f96 | ths | if (protocol >= 0x202) { |
673 | a37af289 | blueswir1 | stl_p(header+0x228, cmdline_addr);
|
674 | 642a4f96 | ths | } else {
|
675 | 642a4f96 | ths | stw_p(header+0x20, 0xA33F); |
676 | 642a4f96 | ths | stw_p(header+0x22, cmdline_addr-real_addr);
|
677 | 642a4f96 | ths | } |
678 | 642a4f96 | ths | |
679 | 642a4f96 | ths | /* loader type */
|
680 | 642a4f96 | ths | /* High nybble = B reserved for Qemu; low nybble is revision number.
|
681 | 642a4f96 | ths | If this code is substantially changed, you may want to consider
|
682 | 642a4f96 | ths | incrementing the revision. */
|
683 | 642a4f96 | ths | if (protocol >= 0x200) |
684 | 642a4f96 | ths | header[0x210] = 0xB0; |
685 | 642a4f96 | ths | |
686 | 642a4f96 | ths | /* heap */
|
687 | 642a4f96 | ths | if (protocol >= 0x201) { |
688 | 642a4f96 | ths | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
689 | 642a4f96 | ths | stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
690 | 642a4f96 | ths | } |
691 | 642a4f96 | ths | |
692 | 642a4f96 | ths | /* load initrd */
|
693 | 642a4f96 | ths | if (initrd_filename) {
|
694 | 642a4f96 | ths | if (protocol < 0x200) { |
695 | 642a4f96 | ths | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
696 | 642a4f96 | ths | exit(1);
|
697 | 642a4f96 | ths | } |
698 | 642a4f96 | ths | |
699 | 642a4f96 | ths | fi = fopen(initrd_filename, "rb");
|
700 | 642a4f96 | ths | if (!fi) {
|
701 | 642a4f96 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
702 | 642a4f96 | ths | initrd_filename); |
703 | 642a4f96 | ths | exit(1);
|
704 | 642a4f96 | ths | } |
705 | 642a4f96 | ths | |
706 | 642a4f96 | ths | initrd_size = get_file_size(fi); |
707 | a37af289 | blueswir1 | initrd_addr = (initrd_max-initrd_size) & ~4095;
|
708 | 642a4f96 | ths | |
709 | 526ccb7a | balrog | fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
|
710 | 526ccb7a | balrog | "\n", initrd_size, initrd_addr);
|
711 | 642a4f96 | ths | |
712 | a37af289 | blueswir1 | if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
|
713 | 642a4f96 | ths | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
|
714 | 642a4f96 | ths | initrd_filename); |
715 | 642a4f96 | ths | exit(1);
|
716 | 642a4f96 | ths | } |
717 | 642a4f96 | ths | fclose(fi); |
718 | 642a4f96 | ths | |
719 | a37af289 | blueswir1 | stl_p(header+0x218, initrd_addr);
|
720 | 642a4f96 | ths | stl_p(header+0x21c, initrd_size);
|
721 | 642a4f96 | ths | } |
722 | 642a4f96 | ths | |
723 | 642a4f96 | ths | /* store the finalized header and load the rest of the kernel */
|
724 | a37af289 | blueswir1 | cpu_physical_memory_write(real_addr, header, 1024);
|
725 | 642a4f96 | ths | |
726 | 642a4f96 | ths | setup_size = header[0x1f1];
|
727 | 642a4f96 | ths | if (setup_size == 0) |
728 | 642a4f96 | ths | setup_size = 4;
|
729 | 642a4f96 | ths | |
730 | 642a4f96 | ths | setup_size = (setup_size+1)*512; |
731 | 642a4f96 | ths | kernel_size -= setup_size; /* Size of protected-mode code */
|
732 | 642a4f96 | ths | |
733 | a37af289 | blueswir1 | if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) || |
734 | a37af289 | blueswir1 | !fread_targphys_ok(prot_addr, kernel_size, f)) { |
735 | 642a4f96 | ths | fprintf(stderr, "qemu: read error on kernel '%s'\n",
|
736 | 642a4f96 | ths | kernel_filename); |
737 | 642a4f96 | ths | exit(1);
|
738 | 642a4f96 | ths | } |
739 | 642a4f96 | ths | fclose(f); |
740 | 642a4f96 | ths | |
741 | 642a4f96 | ths | /* generate bootsector to set up the initial register state */
|
742 | a37af289 | blueswir1 | real_seg = real_addr >> 4;
|
743 | 642a4f96 | ths | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
744 | 642a4f96 | ths | seg[1] = real_seg+0x20; /* CS */ |
745 | 642a4f96 | ths | memset(gpr, 0, sizeof gpr); |
746 | 642a4f96 | ths | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ |
747 | 642a4f96 | ths | |
748 | d6ecb036 | Glauber Costa | option_rom_setup_reset(real_addr, setup_size); |
749 | d6ecb036 | Glauber Costa | option_rom_setup_reset(prot_addr, kernel_size); |
750 | d6ecb036 | Glauber Costa | option_rom_setup_reset(cmdline_addr, cmdline_size); |
751 | d6ecb036 | Glauber Costa | if (initrd_filename)
|
752 | d6ecb036 | Glauber Costa | option_rom_setup_reset(initrd_addr, initrd_size); |
753 | d6ecb036 | Glauber Costa | |
754 | 4fc9af53 | aliguori | generate_bootsect(option_rom, gpr, seg, 0);
|
755 | 642a4f96 | ths | } |
756 | 642a4f96 | ths | |
757 | 59b8ad81 | bellard | static void main_cpu_reset(void *opaque) |
758 | 59b8ad81 | bellard | { |
759 | 59b8ad81 | bellard | CPUState *env = opaque; |
760 | 59b8ad81 | bellard | cpu_reset(env); |
761 | 59b8ad81 | bellard | } |
762 | 59b8ad81 | bellard | |
763 | b41a2cd1 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
764 | b41a2cd1 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
765 | b41a2cd1 | bellard | static const int ide_irq[2] = { 14, 15 }; |
766 | b41a2cd1 | bellard | |
767 | b41a2cd1 | bellard | #define NE2000_NB_MAX 6 |
768 | b41a2cd1 | bellard | |
769 | 8d11df9e | bellard | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
770 | b41a2cd1 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
771 | b41a2cd1 | bellard | |
772 | 8d11df9e | bellard | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
773 | 8d11df9e | bellard | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
774 | 8d11df9e | bellard | |
775 | 6508fe59 | bellard | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
776 | 6508fe59 | bellard | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
777 | 6508fe59 | bellard | |
778 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
779 | d537cf6c | pbrook | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
780 | 6a36d84e | bellard | { |
781 | 6a36d84e | bellard | struct soundhw *c;
|
782 | 6a36d84e | bellard | int audio_enabled = 0; |
783 | 6a36d84e | bellard | |
784 | 6a36d84e | bellard | for (c = soundhw; !audio_enabled && c->name; ++c) {
|
785 | 6a36d84e | bellard | audio_enabled = c->enabled; |
786 | 6a36d84e | bellard | } |
787 | 6a36d84e | bellard | |
788 | 6a36d84e | bellard | if (audio_enabled) {
|
789 | 0d9acba8 | Paul Brook | for (c = soundhw; c->name; ++c) {
|
790 | 0d9acba8 | Paul Brook | if (c->enabled) {
|
791 | 0d9acba8 | Paul Brook | if (c->isa) {
|
792 | 22d83b14 | Paul Brook | c->init.init_isa(pic); |
793 | 22d83b14 | Paul Brook | } else {
|
794 | 0d9acba8 | Paul Brook | if (pci_bus) {
|
795 | 22d83b14 | Paul Brook | c->init.init_pci(pci_bus); |
796 | 6a36d84e | bellard | } |
797 | 6a36d84e | bellard | } |
798 | 6a36d84e | bellard | } |
799 | 6a36d84e | bellard | } |
800 | 6a36d84e | bellard | } |
801 | 6a36d84e | bellard | } |
802 | 6a36d84e | bellard | #endif
|
803 | 6a36d84e | bellard | |
804 | d537cf6c | pbrook | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
805 | a41b2ff2 | pbrook | { |
806 | a41b2ff2 | pbrook | static int nb_ne2k = 0; |
807 | a41b2ff2 | pbrook | |
808 | a41b2ff2 | pbrook | if (nb_ne2k == NE2000_NB_MAX)
|
809 | a41b2ff2 | pbrook | return;
|
810 | d537cf6c | pbrook | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
811 | a41b2ff2 | pbrook | nb_ne2k++; |
812 | a41b2ff2 | pbrook | } |
813 | a41b2ff2 | pbrook | |
814 | f753ff16 | pbrook | static int load_option_rom(const char *oprom, target_phys_addr_t start, |
815 | f753ff16 | pbrook | target_phys_addr_t end) |
816 | f753ff16 | pbrook | { |
817 | f753ff16 | pbrook | int size;
|
818 | f753ff16 | pbrook | |
819 | f753ff16 | pbrook | size = get_image_size(oprom); |
820 | f753ff16 | pbrook | if (size > 0 && start + size > end) { |
821 | f753ff16 | pbrook | fprintf(stderr, "Not enough space to load option rom '%s'\n",
|
822 | f753ff16 | pbrook | oprom); |
823 | f753ff16 | pbrook | exit(1);
|
824 | f753ff16 | pbrook | } |
825 | f753ff16 | pbrook | size = load_image_targphys(oprom, start, end - start); |
826 | f753ff16 | pbrook | if (size < 0) { |
827 | f753ff16 | pbrook | fprintf(stderr, "Could not load option rom '%s'\n", oprom);
|
828 | f753ff16 | pbrook | exit(1);
|
829 | f753ff16 | pbrook | } |
830 | f753ff16 | pbrook | /* Round up optiom rom size to the next 2k boundary */
|
831 | f753ff16 | pbrook | size = (size + 2047) & ~2047; |
832 | e28f9884 | Glauber Costa | option_rom_setup_reset(start, size); |
833 | f753ff16 | pbrook | return size;
|
834 | f753ff16 | pbrook | } |
835 | f753ff16 | pbrook | |
836 | 80cabfad | bellard | /* PC hardware initialisation */
|
837 | fbe1b595 | Paul Brook | static void pc_init1(ram_addr_t ram_size, |
838 | 3023f332 | aliguori | const char *boot_device, |
839 | b5ff2d6e | bellard | const char *kernel_filename, const char *kernel_cmdline, |
840 | 3dbbdc25 | bellard | const char *initrd_filename, |
841 | a049de61 | bellard | int pci_enabled, const char *cpu_model) |
842 | 80cabfad | bellard | { |
843 | 80cabfad | bellard | char buf[1024]; |
844 | 642a4f96 | ths | int ret, linux_boot, i;
|
845 | b584726d | pbrook | ram_addr_t ram_addr, bios_offset, option_rom_offset; |
846 | 00f82b8a | aurel32 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
847 | f753ff16 | pbrook | int bios_size, isa_bios_size, oprom_area_size;
|
848 | 46e50e9d | bellard | PCIBus *pci_bus; |
849 | 5c3ff3a7 | pbrook | int piix3_devfn = -1; |
850 | 59b8ad81 | bellard | CPUState *env; |
851 | d537cf6c | pbrook | qemu_irq *cpu_irq; |
852 | d537cf6c | pbrook | qemu_irq *i8259; |
853 | e4bcb14c | ths | int index;
|
854 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
855 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
856 | 34b39c2b | aliguori | int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
|
857 | d592d303 | bellard | |
858 | 00f82b8a | aurel32 | if (ram_size >= 0xe0000000 ) { |
859 | 00f82b8a | aurel32 | above_4g_mem_size = ram_size - 0xe0000000;
|
860 | 00f82b8a | aurel32 | below_4g_mem_size = 0xe0000000;
|
861 | 00f82b8a | aurel32 | } else {
|
862 | 00f82b8a | aurel32 | below_4g_mem_size = ram_size; |
863 | 00f82b8a | aurel32 | } |
864 | 00f82b8a | aurel32 | |
865 | 80cabfad | bellard | linux_boot = (kernel_filename != NULL);
|
866 | 80cabfad | bellard | |
867 | 59b8ad81 | bellard | /* init CPUs */
|
868 | a049de61 | bellard | if (cpu_model == NULL) { |
869 | a049de61 | bellard | #ifdef TARGET_X86_64
|
870 | a049de61 | bellard | cpu_model = "qemu64";
|
871 | a049de61 | bellard | #else
|
872 | a049de61 | bellard | cpu_model = "qemu32";
|
873 | a049de61 | bellard | #endif
|
874 | a049de61 | bellard | } |
875 | a049de61 | bellard | |
876 | 59b8ad81 | bellard | for(i = 0; i < smp_cpus; i++) { |
877 | aaed909a | bellard | env = cpu_init(cpu_model); |
878 | aaed909a | bellard | if (!env) {
|
879 | aaed909a | bellard | fprintf(stderr, "Unable to find x86 CPU definition\n");
|
880 | aaed909a | bellard | exit(1);
|
881 | aaed909a | bellard | } |
882 | 59b8ad81 | bellard | if (i != 0) |
883 | ce5232c5 | bellard | env->halted = 1;
|
884 | 59b8ad81 | bellard | if (smp_cpus > 1) { |
885 | 59b8ad81 | bellard | /* XXX: enable it in all cases */
|
886 | 59b8ad81 | bellard | env->cpuid_features |= CPUID_APIC; |
887 | 59b8ad81 | bellard | } |
888 | 59b8ad81 | bellard | qemu_register_reset(main_cpu_reset, env); |
889 | 59b8ad81 | bellard | if (pci_enabled) {
|
890 | 59b8ad81 | bellard | apic_init(env); |
891 | 59b8ad81 | bellard | } |
892 | 59b8ad81 | bellard | } |
893 | 59b8ad81 | bellard | |
894 | 26fb5e48 | aurel32 | vmport_init(); |
895 | 26fb5e48 | aurel32 | |
896 | 80cabfad | bellard | /* allocate RAM */
|
897 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(0xa0000);
|
898 | 82b36dc3 | aliguori | cpu_register_physical_memory(0, 0xa0000, ram_addr); |
899 | 82b36dc3 | aliguori | |
900 | 82b36dc3 | aliguori | /* Allocate, even though we won't register, so we don't break the
|
901 | 82b36dc3 | aliguori | * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
|
902 | 82b36dc3 | aliguori | * and some bios areas, which will be registered later
|
903 | 82b36dc3 | aliguori | */
|
904 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); |
905 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
|
906 | 82b36dc3 | aliguori | cpu_register_physical_memory(0x100000,
|
907 | 82b36dc3 | aliguori | below_4g_mem_size - 0x100000,
|
908 | 82b36dc3 | aliguori | ram_addr); |
909 | 00f82b8a | aurel32 | |
910 | 00f82b8a | aurel32 | /* above 4giga memory allocation */
|
911 | 00f82b8a | aurel32 | if (above_4g_mem_size > 0) { |
912 | 82b36dc3 | aliguori | ram_addr = qemu_ram_alloc(above_4g_mem_size); |
913 | 82b36dc3 | aliguori | cpu_register_physical_memory(0x100000000ULL,
|
914 | 526ccb7a | balrog | above_4g_mem_size, |
915 | 82b36dc3 | aliguori | ram_addr); |
916 | 00f82b8a | aurel32 | } |
917 | 80cabfad | bellard | |
918 | 82b36dc3 | aliguori | |
919 | 970ac5a3 | bellard | /* BIOS load */
|
920 | 1192dad8 | j_mayer | if (bios_name == NULL) |
921 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
922 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
923 | 7587cf44 | bellard | bios_size = get_image_size(buf); |
924 | 5fafdf24 | ths | if (bios_size <= 0 || |
925 | 970ac5a3 | bellard | (bios_size % 65536) != 0) { |
926 | 7587cf44 | bellard | goto bios_error;
|
927 | 7587cf44 | bellard | } |
928 | 970ac5a3 | bellard | bios_offset = qemu_ram_alloc(bios_size); |
929 | 44654490 | pbrook | ret = load_image(buf, qemu_get_ram_ptr(bios_offset)); |
930 | 7587cf44 | bellard | if (ret != bios_size) {
|
931 | 7587cf44 | bellard | bios_error:
|
932 | 970ac5a3 | bellard | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
|
933 | 80cabfad | bellard | exit(1);
|
934 | 80cabfad | bellard | } |
935 | 7587cf44 | bellard | /* map the last 128KB of the BIOS in ISA space */
|
936 | 7587cf44 | bellard | isa_bios_size = bios_size; |
937 | 7587cf44 | bellard | if (isa_bios_size > (128 * 1024)) |
938 | 7587cf44 | bellard | isa_bios_size = 128 * 1024; |
939 | 5fafdf24 | ths | cpu_register_physical_memory(0x100000 - isa_bios_size,
|
940 | 5fafdf24 | ths | isa_bios_size, |
941 | 7587cf44 | bellard | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
942 | 9ae02555 | ths | |
943 | 4fc9af53 | aliguori | |
944 | f753ff16 | pbrook | |
945 | f753ff16 | pbrook | option_rom_offset = qemu_ram_alloc(0x20000);
|
946 | f753ff16 | pbrook | oprom_area_size = 0;
|
947 | 49669fc5 | Glauber Costa | cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); |
948 | f753ff16 | pbrook | |
949 | f753ff16 | pbrook | if (using_vga) {
|
950 | f753ff16 | pbrook | /* VGA BIOS load */
|
951 | f753ff16 | pbrook | if (cirrus_vga_enabled) {
|
952 | f753ff16 | pbrook | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, |
953 | f753ff16 | pbrook | VGABIOS_CIRRUS_FILENAME); |
954 | f753ff16 | pbrook | } else {
|
955 | f753ff16 | pbrook | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
956 | 970ac5a3 | bellard | } |
957 | f753ff16 | pbrook | oprom_area_size = load_option_rom(buf, 0xc0000, 0xe0000); |
958 | f753ff16 | pbrook | } |
959 | f753ff16 | pbrook | /* Although video roms can grow larger than 0x8000, the area between
|
960 | f753ff16 | pbrook | * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
|
961 | f753ff16 | pbrook | * for any other kind of option rom inside this area */
|
962 | f753ff16 | pbrook | if (oprom_area_size < 0x8000) |
963 | f753ff16 | pbrook | oprom_area_size = 0x8000;
|
964 | f753ff16 | pbrook | |
965 | f753ff16 | pbrook | if (linux_boot) {
|
966 | 7ffa4767 | pbrook | load_linux(0xc0000 + oprom_area_size,
|
967 | f753ff16 | pbrook | kernel_filename, initrd_filename, kernel_cmdline); |
968 | f753ff16 | pbrook | oprom_area_size += 2048;
|
969 | f753ff16 | pbrook | } |
970 | f753ff16 | pbrook | |
971 | f753ff16 | pbrook | for (i = 0; i < nb_option_roms; i++) { |
972 | f753ff16 | pbrook | oprom_area_size += load_option_rom(option_rom[i], |
973 | f753ff16 | pbrook | 0xc0000 + oprom_area_size, 0xe0000); |
974 | 9ae02555 | ths | } |
975 | 9ae02555 | ths | |
976 | 7587cf44 | bellard | /* map all the bios at the top of memory */
|
977 | 5fafdf24 | ths | cpu_register_physical_memory((uint32_t)(-bios_size), |
978 | 7587cf44 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
979 | 3b46e624 | ths | |
980 | 80cabfad | bellard | bochs_bios_init(); |
981 | 80cabfad | bellard | |
982 | a5b38b51 | aurel32 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
983 | d537cf6c | pbrook | i8259 = i8259_init(cpu_irq[0]);
|
984 | d537cf6c | pbrook | ferr_irq = i8259[13];
|
985 | d537cf6c | pbrook | |
986 | 69b91039 | bellard | if (pci_enabled) {
|
987 | d537cf6c | pbrook | pci_bus = i440fx_init(&i440fx_state, i8259); |
988 | 8f1c91d8 | ths | piix3_devfn = piix3_init(pci_bus, -1);
|
989 | 46e50e9d | bellard | } else {
|
990 | 46e50e9d | bellard | pci_bus = NULL;
|
991 | 69b91039 | bellard | } |
992 | 69b91039 | bellard | |
993 | 80cabfad | bellard | /* init basic PC hardware */
|
994 | b41a2cd1 | bellard | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
995 | 80cabfad | bellard | |
996 | f929aad6 | bellard | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
997 | f929aad6 | bellard | |
998 | 1f04275e | bellard | if (cirrus_vga_enabled) {
|
999 | 1f04275e | bellard | if (pci_enabled) {
|
1000 | fbe1b595 | Paul Brook | pci_cirrus_vga_init(pci_bus); |
1001 | 1f04275e | bellard | } else {
|
1002 | fbe1b595 | Paul Brook | isa_cirrus_vga_init(); |
1003 | 1f04275e | bellard | } |
1004 | d34cab9f | ths | } else if (vmsvga_enabled) { |
1005 | d34cab9f | ths | if (pci_enabled)
|
1006 | fbe1b595 | Paul Brook | pci_vmsvga_init(pci_bus); |
1007 | d34cab9f | ths | else
|
1008 | d34cab9f | ths | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
1009 | c2b3b41a | aliguori | } else if (std_vga_enabled) { |
1010 | 89b6b508 | bellard | if (pci_enabled) {
|
1011 | fbe1b595 | Paul Brook | pci_vga_init(pci_bus, 0, 0); |
1012 | 89b6b508 | bellard | } else {
|
1013 | fbe1b595 | Paul Brook | isa_vga_init(); |
1014 | 89b6b508 | bellard | } |
1015 | 1f04275e | bellard | } |
1016 | 80cabfad | bellard | |
1017 | 42fc73a1 | aurel32 | rtc_state = rtc_init(0x70, i8259[8], 2000); |
1018 | 80cabfad | bellard | |
1019 | 3b4366de | blueswir1 | qemu_register_boot_set(pc_boot_set, rtc_state); |
1020 | 3b4366de | blueswir1 | |
1021 | e1a23744 | bellard | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
1022 | e1a23744 | bellard | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
1023 | e1a23744 | bellard | |
1024 | d592d303 | bellard | if (pci_enabled) {
|
1025 | d592d303 | bellard | ioapic = ioapic_init(); |
1026 | d592d303 | bellard | } |
1027 | d537cf6c | pbrook | pit = pit_init(0x40, i8259[0]); |
1028 | fd06c375 | bellard | pcspk_init(pit); |
1029 | 16b29ae1 | aliguori | if (!no_hpet) {
|
1030 | 16b29ae1 | aliguori | hpet_init(i8259); |
1031 | 16b29ae1 | aliguori | } |
1032 | d592d303 | bellard | if (pci_enabled) {
|
1033 | d592d303 | bellard | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); |
1034 | d592d303 | bellard | } |
1035 | b41a2cd1 | bellard | |
1036 | 8d11df9e | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1037 | 8d11df9e | bellard | if (serial_hds[i]) {
|
1038 | b6cd0ea1 | aurel32 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
|
1039 | b6cd0ea1 | aurel32 | serial_hds[i]); |
1040 | 8d11df9e | bellard | } |
1041 | 8d11df9e | bellard | } |
1042 | b41a2cd1 | bellard | |
1043 | 6508fe59 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1044 | 6508fe59 | bellard | if (parallel_hds[i]) {
|
1045 | d537cf6c | pbrook | parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
1046 | d537cf6c | pbrook | parallel_hds[i]); |
1047 | 6508fe59 | bellard | } |
1048 | 6508fe59 | bellard | } |
1049 | 6508fe59 | bellard | |
1050 | 9dd986cc | Richard W.M. Jones | watchdog_pc_init(pci_bus); |
1051 | 9dd986cc | Richard W.M. Jones | |
1052 | a41b2ff2 | pbrook | for(i = 0; i < nb_nics; i++) { |
1053 | cb457d76 | aliguori | NICInfo *nd = &nd_table[i]; |
1054 | cb457d76 | aliguori | |
1055 | cb457d76 | aliguori | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
1056 | d537cf6c | pbrook | pc_init_ne2k_isa(nd, i8259); |
1057 | cb457d76 | aliguori | else
|
1058 | cb457d76 | aliguori | pci_nic_init(pci_bus, nd, -1, "ne2k_pci"); |
1059 | a41b2ff2 | pbrook | } |
1060 | b41a2cd1 | bellard | |
1061 | 5e3cb534 | aliguori | qemu_system_hot_add_init(); |
1062 | 5e3cb534 | aliguori | |
1063 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
1064 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
1065 | e4bcb14c | ths | exit(1);
|
1066 | e4bcb14c | ths | } |
1067 | e4bcb14c | ths | |
1068 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
1069 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
1070 | e4bcb14c | ths | if (index != -1) |
1071 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
1072 | e4bcb14c | ths | else
|
1073 | e4bcb14c | ths | hd[i] = NULL;
|
1074 | e4bcb14c | ths | } |
1075 | e4bcb14c | ths | |
1076 | a41b2ff2 | pbrook | if (pci_enabled) {
|
1077 | e4bcb14c | ths | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
|
1078 | a41b2ff2 | pbrook | } else {
|
1079 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) { |
1080 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
1081 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
1082 | 69b91039 | bellard | } |
1083 | b41a2cd1 | bellard | } |
1084 | 69b91039 | bellard | |
1085 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
1086 | 7c29d0c0 | bellard | DMA_init(0);
|
1087 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
1088 | d537cf6c | pbrook | audio_init(pci_enabled ? pci_bus : NULL, i8259);
|
1089 | fb065187 | bellard | #endif
|
1090 | 80cabfad | bellard | |
1091 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
1092 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, i);
|
1093 | e4bcb14c | ths | if (index != -1) |
1094 | e4bcb14c | ths | fd[i] = drives_table[index].bdrv; |
1095 | e4bcb14c | ths | else
|
1096 | e4bcb14c | ths | fd[i] = NULL;
|
1097 | e4bcb14c | ths | } |
1098 | e4bcb14c | ths | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
1099 | b41a2cd1 | bellard | |
1100 | 00f82b8a | aurel32 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
1101 | 69b91039 | bellard | |
1102 | bb36d470 | bellard | if (pci_enabled && usb_enabled) {
|
1103 | afcc3cdf | ths | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
1104 | bb36d470 | bellard | } |
1105 | bb36d470 | bellard | |
1106 | 6515b203 | bellard | if (pci_enabled && acpi_enabled) {
|
1107 | 3fffc223 | ths | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
1108 | 0ff596d0 | pbrook | i2c_bus *smbus; |
1109 | 0ff596d0 | pbrook | |
1110 | 0ff596d0 | pbrook | /* TODO: Populate SPD eeprom data. */
|
1111 | cf7a2fe2 | aurel32 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
1112 | 3fffc223 | ths | for (i = 0; i < 8; i++) { |
1113 | 0ff596d0 | pbrook | smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256)); |
1114 | 3fffc223 | ths | } |
1115 | 6515b203 | bellard | } |
1116 | 3b46e624 | ths | |
1117 | a5954d5c | bellard | if (i440fx_state) {
|
1118 | a5954d5c | bellard | i440fx_init_memory_mappings(i440fx_state); |
1119 | a5954d5c | bellard | } |
1120 | e4bcb14c | ths | |
1121 | 7d8406be | pbrook | if (pci_enabled) {
|
1122 | e4bcb14c | ths | int max_bus;
|
1123 | 9be5dafe | Paul Brook | int bus;
|
1124 | 96d30e48 | ths | |
1125 | e4bcb14c | ths | max_bus = drive_get_max_bus(IF_SCSI); |
1126 | e4bcb14c | ths | for (bus = 0; bus <= max_bus; bus++) { |
1127 | 9be5dafe | Paul Brook | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1128 | e4bcb14c | ths | } |
1129 | 7d8406be | pbrook | } |
1130 | 6e02c38d | aliguori | |
1131 | 6e02c38d | aliguori | /* Add virtio block devices */
|
1132 | 6e02c38d | aliguori | if (pci_enabled) {
|
1133 | 6e02c38d | aliguori | int index;
|
1134 | 6e02c38d | aliguori | int unit_id = 0; |
1135 | 6e02c38d | aliguori | |
1136 | 6e02c38d | aliguori | while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { |
1137 | 07e3af9a | Paul Brook | pci_create_simple(pci_bus, -1, "virtio-blk"); |
1138 | 6e02c38d | aliguori | unit_id++; |
1139 | 6e02c38d | aliguori | } |
1140 | 6e02c38d | aliguori | } |
1141 | bd322087 | aliguori | |
1142 | bd322087 | aliguori | /* Add virtio balloon device */
|
1143 | 2d72c572 | Paul Brook | if (pci_enabled) {
|
1144 | 2d72c572 | Paul Brook | pci_create_simple(pci_bus, -1, "virtio-balloon"); |
1145 | 2d72c572 | Paul Brook | } |
1146 | a2fa19f9 | aliguori | |
1147 | a2fa19f9 | aliguori | /* Add virtio console devices */
|
1148 | a2fa19f9 | aliguori | if (pci_enabled) {
|
1149 | a2fa19f9 | aliguori | for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { |
1150 | a2fa19f9 | aliguori | if (virtcon_hds[i])
|
1151 | a2fa19f9 | aliguori | virtio_console_init(pci_bus, virtcon_hds[i]); |
1152 | a2fa19f9 | aliguori | } |
1153 | a2fa19f9 | aliguori | } |
1154 | 80cabfad | bellard | } |
1155 | b5ff2d6e | bellard | |
1156 | fbe1b595 | Paul Brook | static void pc_init_pci(ram_addr_t ram_size, |
1157 | 3023f332 | aliguori | const char *boot_device, |
1158 | 5fafdf24 | ths | const char *kernel_filename, |
1159 | 3dbbdc25 | bellard | const char *kernel_cmdline, |
1160 | 94fc95cd | j_mayer | const char *initrd_filename, |
1161 | 94fc95cd | j_mayer | const char *cpu_model) |
1162 | 3dbbdc25 | bellard | { |
1163 | fbe1b595 | Paul Brook | pc_init1(ram_size, boot_device, |
1164 | 3dbbdc25 | bellard | kernel_filename, kernel_cmdline, |
1165 | a049de61 | bellard | initrd_filename, 1, cpu_model);
|
1166 | 3dbbdc25 | bellard | } |
1167 | 3dbbdc25 | bellard | |
1168 | fbe1b595 | Paul Brook | static void pc_init_isa(ram_addr_t ram_size, |
1169 | 3023f332 | aliguori | const char *boot_device, |
1170 | 5fafdf24 | ths | const char *kernel_filename, |
1171 | 3dbbdc25 | bellard | const char *kernel_cmdline, |
1172 | 94fc95cd | j_mayer | const char *initrd_filename, |
1173 | 94fc95cd | j_mayer | const char *cpu_model) |
1174 | 3dbbdc25 | bellard | { |
1175 | fbe1b595 | Paul Brook | pc_init1(ram_size, boot_device, |
1176 | 3dbbdc25 | bellard | kernel_filename, kernel_cmdline, |
1177 | a049de61 | bellard | initrd_filename, 0, cpu_model);
|
1178 | 3dbbdc25 | bellard | } |
1179 | 3dbbdc25 | bellard | |
1180 | 0bacd130 | aliguori | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
1181 | 0bacd130 | aliguori | BIOS will read it and start S3 resume at POST Entry */
|
1182 | 0bacd130 | aliguori | void cmos_set_s3_resume(void) |
1183 | 0bacd130 | aliguori | { |
1184 | 0bacd130 | aliguori | if (rtc_state)
|
1185 | 0bacd130 | aliguori | rtc_set_memory(rtc_state, 0xF, 0xFE); |
1186 | 0bacd130 | aliguori | } |
1187 | 0bacd130 | aliguori | |
1188 | b5ff2d6e | bellard | QEMUMachine pc_machine = { |
1189 | a245f2e7 | aurel32 | .name = "pc",
|
1190 | a245f2e7 | aurel32 | .desc = "Standard PC",
|
1191 | a245f2e7 | aurel32 | .init = pc_init_pci, |
1192 | b2097003 | aliguori | .max_cpus = 255,
|
1193 | 3dbbdc25 | bellard | }; |
1194 | 3dbbdc25 | bellard | |
1195 | 3dbbdc25 | bellard | QEMUMachine isapc_machine = { |
1196 | a245f2e7 | aurel32 | .name = "isapc",
|
1197 | a245f2e7 | aurel32 | .desc = "ISA-only PC",
|
1198 | a245f2e7 | aurel32 | .init = pc_init_isa, |
1199 | b2097003 | aliguori | .max_cpus = 1,
|
1200 | b5ff2d6e | bellard | }; |