root / ppc-dis.c @ 2d72c572
History | View | Annotate | Download (237.2 kB)
1 | b9adb4a6 | bellard | /* ppc-dis.c -- Disassemble PowerPC instructions
|
---|---|---|---|
2 | ee8ae9e4 | blueswir1 | Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
|
3 | eca8f888 | blueswir1 | Free Software Foundation, Inc.
|
4 | b9adb4a6 | bellard | Written by Ian Lance Taylor, Cygnus Support
|
5 | b9adb4a6 | bellard | |
6 | b9adb4a6 | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
7 | b9adb4a6 | bellard | |
8 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
9 | b9adb4a6 | bellard | them and/or modify them under the terms of the GNU General Public
|
10 | b9adb4a6 | bellard | License as published by the Free Software Foundation; either version
|
11 | b9adb4a6 | bellard | 2, or (at your option) any later version.
|
12 | b9adb4a6 | bellard | |
13 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
14 | b9adb4a6 | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
15 | b9adb4a6 | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
16 | b9adb4a6 | bellard | the GNU General Public License for more details.
|
17 | b9adb4a6 | bellard | |
18 | b9adb4a6 | bellard | You should have received a copy of the GNU General Public License
|
19 | b9adb4a6 | bellard | along with this file; see the file COPYING. If not, write to the Free
|
20 | fad6cb1a | aurel32 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
21 | b9adb4a6 | bellard | #include "dis-asm.h" |
22 | eca8f888 | blueswir1 | #define BFD_DEFAULT_TARGET_SIZE 64 |
23 | b9adb4a6 | bellard | |
24 | b9adb4a6 | bellard | /* ppc.h -- Header file for PowerPC opcode table
|
25 | ee8ae9e4 | blueswir1 | Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
|
26 | ee8ae9e4 | blueswir1 | 2007 Free Software Foundation, Inc.
|
27 | b9adb4a6 | bellard | Written by Ian Lance Taylor, Cygnus Support
|
28 | b9adb4a6 | bellard | |
29 | b9adb4a6 | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
30 | b9adb4a6 | bellard | |
31 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
32 | b9adb4a6 | bellard | them and/or modify them under the terms of the GNU General Public
|
33 | b9adb4a6 | bellard | License as published by the Free Software Foundation; either version
|
34 | b9adb4a6 | bellard | 1, or (at your option) any later version.
|
35 | b9adb4a6 | bellard | |
36 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
37 | b9adb4a6 | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
38 | b9adb4a6 | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
39 | b9adb4a6 | bellard | the GNU General Public License for more details.
|
40 | b9adb4a6 | bellard | |
41 | b9adb4a6 | bellard | You should have received a copy of the GNU General Public License
|
42 | b9adb4a6 | bellard | along with this file; see the file COPYING. If not, write to the Free
|
43 | eca8f888 | blueswir1 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
44 | b9adb4a6 | bellard | |
45 | b9adb4a6 | bellard | /* The opcode table is an array of struct powerpc_opcode. */
|
46 | b9adb4a6 | bellard | |
47 | b9adb4a6 | bellard | struct powerpc_opcode
|
48 | b9adb4a6 | bellard | { |
49 | b9adb4a6 | bellard | /* The opcode name. */
|
50 | b9adb4a6 | bellard | const char *name; |
51 | b9adb4a6 | bellard | |
52 | b9adb4a6 | bellard | /* The opcode itself. Those bits which will be filled in with
|
53 | b9adb4a6 | bellard | operands are zeroes. */
|
54 | eca8f888 | blueswir1 | unsigned long opcode; |
55 | b9adb4a6 | bellard | |
56 | b9adb4a6 | bellard | /* The opcode mask. This is used by the disassembler. This is a
|
57 | b9adb4a6 | bellard | mask containing ones indicating those bits which must match the
|
58 | b9adb4a6 | bellard | opcode field, and zeroes indicating those bits which need not
|
59 | b9adb4a6 | bellard | match (and are presumably filled in by operands). */
|
60 | eca8f888 | blueswir1 | unsigned long mask; |
61 | b9adb4a6 | bellard | |
62 | b9adb4a6 | bellard | /* One bit flags for the opcode. These are used to indicate which
|
63 | b9adb4a6 | bellard | specific processors support the instructions. The defined values
|
64 | b9adb4a6 | bellard | are listed below. */
|
65 | eca8f888 | blueswir1 | unsigned long flags; |
66 | b9adb4a6 | bellard | |
67 | b9adb4a6 | bellard | /* An array of operand codes. Each code is an index into the
|
68 | b9adb4a6 | bellard | operand table. They appear in the order which the operands must
|
69 | b9adb4a6 | bellard | appear in assembly code, and are terminated by a zero. */
|
70 | b9adb4a6 | bellard | unsigned char operands[8]; |
71 | b9adb4a6 | bellard | }; |
72 | b9adb4a6 | bellard | |
73 | b9adb4a6 | bellard | /* The table itself is sorted by major opcode number, and is otherwise
|
74 | b9adb4a6 | bellard | in the order in which the disassembler should consider
|
75 | b9adb4a6 | bellard | instructions. */
|
76 | b9adb4a6 | bellard | extern const struct powerpc_opcode powerpc_opcodes[]; |
77 | b9adb4a6 | bellard | extern const int powerpc_num_opcodes; |
78 | b9adb4a6 | bellard | |
79 | b9adb4a6 | bellard | /* Values defined for the flags field of a struct powerpc_opcode. */
|
80 | b9adb4a6 | bellard | |
81 | b9adb4a6 | bellard | /* Opcode is defined for the PowerPC architecture. */
|
82 | eca8f888 | blueswir1 | #define PPC_OPCODE_PPC 1 |
83 | b9adb4a6 | bellard | |
84 | b9adb4a6 | bellard | /* Opcode is defined for the POWER (RS/6000) architecture. */
|
85 | eca8f888 | blueswir1 | #define PPC_OPCODE_POWER 2 |
86 | b9adb4a6 | bellard | |
87 | b9adb4a6 | bellard | /* Opcode is defined for the POWER2 (Rios 2) architecture. */
|
88 | eca8f888 | blueswir1 | #define PPC_OPCODE_POWER2 4 |
89 | b9adb4a6 | bellard | |
90 | b9adb4a6 | bellard | /* Opcode is only defined on 32 bit architectures. */
|
91 | eca8f888 | blueswir1 | #define PPC_OPCODE_32 8 |
92 | b9adb4a6 | bellard | |
93 | b9adb4a6 | bellard | /* Opcode is only defined on 64 bit architectures. */
|
94 | eca8f888 | blueswir1 | #define PPC_OPCODE_64 0x10 |
95 | b9adb4a6 | bellard | |
96 | b9adb4a6 | bellard | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
|
97 | b9adb4a6 | bellard | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
|
98 | b9adb4a6 | bellard | but it also supports many additional POWER instructions. */
|
99 | eca8f888 | blueswir1 | #define PPC_OPCODE_601 0x20 |
100 | eca8f888 | blueswir1 | |
101 | eca8f888 | blueswir1 | /* Opcode is supported in both the Power and PowerPC architectures
|
102 | eca8f888 | blueswir1 | (ie, compiler's -mcpu=common or assembler's -mcom). */
|
103 | eca8f888 | blueswir1 | #define PPC_OPCODE_COMMON 0x40 |
104 | eca8f888 | blueswir1 | |
105 | eca8f888 | blueswir1 | /* Opcode is supported for any Power or PowerPC platform (this is
|
106 | eca8f888 | blueswir1 | for the assembler's -many option, and it eliminates duplicates). */
|
107 | eca8f888 | blueswir1 | #define PPC_OPCODE_ANY 0x80 |
108 | eca8f888 | blueswir1 | |
109 | eca8f888 | blueswir1 | /* Opcode is supported as part of the 64-bit bridge. */
|
110 | eca8f888 | blueswir1 | #define PPC_OPCODE_64_BRIDGE 0x100 |
111 | eca8f888 | blueswir1 | |
112 | eca8f888 | blueswir1 | /* Opcode is supported by Altivec Vector Unit */
|
113 | eca8f888 | blueswir1 | #define PPC_OPCODE_ALTIVEC 0x200 |
114 | eca8f888 | blueswir1 | |
115 | eca8f888 | blueswir1 | /* Opcode is supported by PowerPC 403 processor. */
|
116 | eca8f888 | blueswir1 | #define PPC_OPCODE_403 0x400 |
117 | eca8f888 | blueswir1 | |
118 | eca8f888 | blueswir1 | /* Opcode is supported by PowerPC BookE processor. */
|
119 | eca8f888 | blueswir1 | #define PPC_OPCODE_BOOKE 0x800 |
120 | eca8f888 | blueswir1 | |
121 | eca8f888 | blueswir1 | /* Opcode is only supported by 64-bit PowerPC BookE processor. */
|
122 | eca8f888 | blueswir1 | #define PPC_OPCODE_BOOKE64 0x1000 |
123 | eca8f888 | blueswir1 | |
124 | eca8f888 | blueswir1 | /* Opcode is supported by PowerPC 440 processor. */
|
125 | eca8f888 | blueswir1 | #define PPC_OPCODE_440 0x2000 |
126 | eca8f888 | blueswir1 | |
127 | eca8f888 | blueswir1 | /* Opcode is only supported by Power4 architecture. */
|
128 | eca8f888 | blueswir1 | #define PPC_OPCODE_POWER4 0x4000 |
129 | eca8f888 | blueswir1 | |
130 | eca8f888 | blueswir1 | /* Opcode isn't supported by Power4 architecture. */
|
131 | eca8f888 | blueswir1 | #define PPC_OPCODE_NOPOWER4 0x8000 |
132 | eca8f888 | blueswir1 | |
133 | eca8f888 | blueswir1 | /* Opcode is only supported by POWERPC Classic architecture. */
|
134 | eca8f888 | blueswir1 | #define PPC_OPCODE_CLASSIC 0x10000 |
135 | eca8f888 | blueswir1 | |
136 | eca8f888 | blueswir1 | /* Opcode is only supported by e500x2 Core. */
|
137 | eca8f888 | blueswir1 | #define PPC_OPCODE_SPE 0x20000 |
138 | eca8f888 | blueswir1 | |
139 | eca8f888 | blueswir1 | /* Opcode is supported by e500x2 Integer select APU. */
|
140 | eca8f888 | blueswir1 | #define PPC_OPCODE_ISEL 0x40000 |
141 | eca8f888 | blueswir1 | |
142 | eca8f888 | blueswir1 | /* Opcode is an e500 SPE floating point instruction. */
|
143 | eca8f888 | blueswir1 | #define PPC_OPCODE_EFS 0x80000 |
144 | eca8f888 | blueswir1 | |
145 | eca8f888 | blueswir1 | /* Opcode is supported by branch locking APU. */
|
146 | eca8f888 | blueswir1 | #define PPC_OPCODE_BRLOCK 0x100000 |
147 | eca8f888 | blueswir1 | |
148 | eca8f888 | blueswir1 | /* Opcode is supported by performance monitor APU. */
|
149 | eca8f888 | blueswir1 | #define PPC_OPCODE_PMR 0x200000 |
150 | eca8f888 | blueswir1 | |
151 | eca8f888 | blueswir1 | /* Opcode is supported by cache locking APU. */
|
152 | eca8f888 | blueswir1 | #define PPC_OPCODE_CACHELCK 0x400000 |
153 | eca8f888 | blueswir1 | |
154 | eca8f888 | blueswir1 | /* Opcode is supported by machine check APU. */
|
155 | eca8f888 | blueswir1 | #define PPC_OPCODE_RFMCI 0x800000 |
156 | eca8f888 | blueswir1 | |
157 | eca8f888 | blueswir1 | /* Opcode is only supported by Power5 architecture. */
|
158 | ee8ae9e4 | blueswir1 | #define PPC_OPCODE_POWER5 0x1000000 |
159 | eca8f888 | blueswir1 | |
160 | eca8f888 | blueswir1 | /* Opcode is supported by PowerPC e300 family. */
|
161 | ee8ae9e4 | blueswir1 | #define PPC_OPCODE_E300 0x2000000 |
162 | ee8ae9e4 | blueswir1 | |
163 | ee8ae9e4 | blueswir1 | /* Opcode is only supported by Power6 architecture. */
|
164 | ee8ae9e4 | blueswir1 | #define PPC_OPCODE_POWER6 0x4000000 |
165 | ee8ae9e4 | blueswir1 | |
166 | ee8ae9e4 | blueswir1 | /* Opcode is only supported by PowerPC Cell family. */
|
167 | ee8ae9e4 | blueswir1 | #define PPC_OPCODE_CELL 0x8000000 |
168 | b9adb4a6 | bellard | |
169 | b9adb4a6 | bellard | /* A macro to extract the major opcode from an instruction. */
|
170 | b9adb4a6 | bellard | #define PPC_OP(i) (((i) >> 26) & 0x3f) |
171 | b9adb4a6 | bellard | |
172 | b9adb4a6 | bellard | /* The operands table is an array of struct powerpc_operand. */
|
173 | b9adb4a6 | bellard | |
174 | b9adb4a6 | bellard | struct powerpc_operand
|
175 | b9adb4a6 | bellard | { |
176 | ee8ae9e4 | blueswir1 | /* A bitmask of bits in the operand. */
|
177 | ee8ae9e4 | blueswir1 | unsigned int bitm; |
178 | b9adb4a6 | bellard | |
179 | ee8ae9e4 | blueswir1 | /* How far the operand is left shifted in the instruction.
|
180 | ee8ae9e4 | blueswir1 | -1 to indicate that BITM and SHIFT cannot be used to determine
|
181 | ee8ae9e4 | blueswir1 | where the operand goes in the insn. */
|
182 | b9adb4a6 | bellard | int shift;
|
183 | b9adb4a6 | bellard | |
184 | b9adb4a6 | bellard | /* Insertion function. This is used by the assembler. To insert an
|
185 | b9adb4a6 | bellard | operand value into an instruction, check this field.
|
186 | b9adb4a6 | bellard | |
187 | b9adb4a6 | bellard | If it is NULL, execute
|
188 | ee8ae9e4 | blueswir1 | i |= (op & o->bitm) << o->shift;
|
189 | b9adb4a6 | bellard | (i is the instruction which we are filling in, o is a pointer to
|
190 | ee8ae9e4 | blueswir1 | this structure, and op is the operand value).
|
191 | b9adb4a6 | bellard | |
192 | b9adb4a6 | bellard | If this field is not NULL, then simply call it with the
|
193 | b9adb4a6 | bellard | instruction and the operand value. It will return the new value
|
194 | b9adb4a6 | bellard | of the instruction. If the ERRMSG argument is not NULL, then if
|
195 | b9adb4a6 | bellard | the operand value is illegal, *ERRMSG will be set to a warning
|
196 | b9adb4a6 | bellard | string (the operand will be inserted in any case). If the
|
197 | b9adb4a6 | bellard | operand value is legal, *ERRMSG will be unchanged (most operands
|
198 | b9adb4a6 | bellard | can accept any value). */
|
199 | eca8f888 | blueswir1 | unsigned long (*insert) |
200 | eca8f888 | blueswir1 | (unsigned long instruction, long op, int dialect, const char **errmsg); |
201 | b9adb4a6 | bellard | |
202 | b9adb4a6 | bellard | /* Extraction function. This is used by the disassembler. To
|
203 | b9adb4a6 | bellard | extract this operand type from an instruction, check this field.
|
204 | b9adb4a6 | bellard | |
205 | b9adb4a6 | bellard | If it is NULL, compute
|
206 | ee8ae9e4 | blueswir1 | op = (i >> o->shift) & o->bitm;
|
207 | ee8ae9e4 | blueswir1 | if ((o->flags & PPC_OPERAND_SIGNED) != 0)
|
208 | ee8ae9e4 | blueswir1 | sign_extend (op);
|
209 | b9adb4a6 | bellard | (i is the instruction, o is a pointer to this structure, and op
|
210 | ee8ae9e4 | blueswir1 | is the result).
|
211 | b9adb4a6 | bellard | |
212 | b9adb4a6 | bellard | If this field is not NULL, then simply call it with the
|
213 | b9adb4a6 | bellard | instruction value. It will return the value of the operand. If
|
214 | b9adb4a6 | bellard | the INVALID argument is not NULL, *INVALID will be set to
|
215 | b9adb4a6 | bellard | non-zero if this operand type can not actually be extracted from
|
216 | b9adb4a6 | bellard | this operand (i.e., the instruction does not match). If the
|
217 | b9adb4a6 | bellard | operand is valid, *INVALID will not be changed. */
|
218 | eca8f888 | blueswir1 | long (*extract) (unsigned long instruction, int dialect, int *invalid); |
219 | b9adb4a6 | bellard | |
220 | b9adb4a6 | bellard | /* One bit syntax flags. */
|
221 | eca8f888 | blueswir1 | unsigned long flags; |
222 | b9adb4a6 | bellard | }; |
223 | b9adb4a6 | bellard | |
224 | b9adb4a6 | bellard | /* Elements in the table are retrieved by indexing with values from
|
225 | b9adb4a6 | bellard | the operands field of the powerpc_opcodes table. */
|
226 | b9adb4a6 | bellard | |
227 | b9adb4a6 | bellard | extern const struct powerpc_operand powerpc_operands[]; |
228 | ee8ae9e4 | blueswir1 | extern const unsigned int num_powerpc_operands; |
229 | b9adb4a6 | bellard | |
230 | b9adb4a6 | bellard | /* Values defined for the flags field of a struct powerpc_operand. */
|
231 | b9adb4a6 | bellard | |
232 | b9adb4a6 | bellard | /* This operand takes signed values. */
|
233 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_SIGNED (0x1) |
234 | b9adb4a6 | bellard | |
235 | b9adb4a6 | bellard | /* This operand takes signed values, but also accepts a full positive
|
236 | b9adb4a6 | bellard | range of values when running in 32 bit mode. That is, if bits is
|
237 | b9adb4a6 | bellard | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
|
238 | b9adb4a6 | bellard | this flag is ignored. */
|
239 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_SIGNOPT (0x2) |
240 | b9adb4a6 | bellard | |
241 | b9adb4a6 | bellard | /* This operand does not actually exist in the assembler input. This
|
242 | b9adb4a6 | bellard | is used to support extended mnemonics such as mr, for which two
|
243 | b9adb4a6 | bellard | operands fields are identical. The assembler should call the
|
244 | b9adb4a6 | bellard | insert function with any op value. The disassembler should call
|
245 | b9adb4a6 | bellard | the extract function, ignore the return value, and check the value
|
246 | b9adb4a6 | bellard | placed in the valid argument. */
|
247 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_FAKE (0x4) |
248 | b9adb4a6 | bellard | |
249 | b9adb4a6 | bellard | /* The next operand should be wrapped in parentheses rather than
|
250 | b9adb4a6 | bellard | separated from this one by a comma. This is used for the load and
|
251 | b9adb4a6 | bellard | store instructions which want their operands to look like
|
252 | b9adb4a6 | bellard | reg,displacement(reg)
|
253 | b9adb4a6 | bellard | */
|
254 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_PARENS (0x8) |
255 | b9adb4a6 | bellard | |
256 | b9adb4a6 | bellard | /* This operand may use the symbolic names for the CR fields, which
|
257 | b9adb4a6 | bellard | are
|
258 | b9adb4a6 | bellard | lt 0 gt 1 eq 2 so 3 un 3
|
259 | b9adb4a6 | bellard | cr0 0 cr1 1 cr2 2 cr3 3
|
260 | b9adb4a6 | bellard | cr4 4 cr5 5 cr6 6 cr7 7
|
261 | b9adb4a6 | bellard | These may be combined arithmetically, as in cr2*4+gt. These are
|
262 | b9adb4a6 | bellard | only supported on the PowerPC, not the POWER. */
|
263 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_CR (0x10) |
264 | b9adb4a6 | bellard | |
265 | b9adb4a6 | bellard | /* This operand names a register. The disassembler uses this to print
|
266 | b9adb4a6 | bellard | register names with a leading 'r'. */
|
267 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_GPR (0x20) |
268 | b9adb4a6 | bellard | |
269 | eca8f888 | blueswir1 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
|
270 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_GPR_0 (0x40) |
271 | eca8f888 | blueswir1 | |
272 | b9adb4a6 | bellard | /* This operand names a floating point register. The disassembler
|
273 | b9adb4a6 | bellard | prints these with a leading 'f'. */
|
274 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_FPR (0x80) |
275 | b9adb4a6 | bellard | |
276 | b9adb4a6 | bellard | /* This operand is a relative branch displacement. The disassembler
|
277 | b9adb4a6 | bellard | prints these symbolically if possible. */
|
278 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_RELATIVE (0x100) |
279 | b9adb4a6 | bellard | |
280 | b9adb4a6 | bellard | /* This operand is an absolute branch address. The disassembler
|
281 | b9adb4a6 | bellard | prints these symbolically if possible. */
|
282 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_ABSOLUTE (0x200) |
283 | b9adb4a6 | bellard | |
284 | b9adb4a6 | bellard | /* This operand is optional, and is zero if omitted. This is used for
|
285 | eca8f888 | blueswir1 | example, in the optional BF field in the comparison instructions. The
|
286 | b9adb4a6 | bellard | assembler must count the number of operands remaining on the line,
|
287 | b9adb4a6 | bellard | and the number of operands remaining for the opcode, and decide
|
288 | b9adb4a6 | bellard | whether this operand is present or not. The disassembler should
|
289 | b9adb4a6 | bellard | print this operand out only if it is not zero. */
|
290 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_OPTIONAL (0x400) |
291 | b9adb4a6 | bellard | |
292 | b9adb4a6 | bellard | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
|
293 | b9adb4a6 | bellard | is omitted, then for the next operand use this operand value plus
|
294 | b9adb4a6 | bellard | 1, ignoring the next operand field for the opcode. This wretched
|
295 | b9adb4a6 | bellard | hack is needed because the Power rotate instructions can take
|
296 | b9adb4a6 | bellard | either 4 or 5 operands. The disassembler should print this operand
|
297 | b9adb4a6 | bellard | out regardless of the PPC_OPERAND_OPTIONAL field. */
|
298 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_NEXT (0x800) |
299 | b9adb4a6 | bellard | |
300 | b9adb4a6 | bellard | /* This operand should be regarded as a negative number for the
|
301 | b9adb4a6 | bellard | purposes of overflow checking (i.e., the normal most negative
|
302 | b9adb4a6 | bellard | number is disallowed and one more than the normal most positive
|
303 | b9adb4a6 | bellard | number is allowed). This flag will only be set for a signed
|
304 | b9adb4a6 | bellard | operand. */
|
305 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_NEGATIVE (0x1000) |
306 | eca8f888 | blueswir1 | |
307 | eca8f888 | blueswir1 | /* This operand names a vector unit register. The disassembler
|
308 | eca8f888 | blueswir1 | prints these with a leading 'v'. */
|
309 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_VR (0x2000) |
310 | eca8f888 | blueswir1 | |
311 | eca8f888 | blueswir1 | /* This operand is for the DS field in a DS form instruction. */
|
312 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_DS (0x4000) |
313 | eca8f888 | blueswir1 | |
314 | eca8f888 | blueswir1 | /* This operand is for the DQ field in a DQ form instruction. */
|
315 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_DQ (0x8000) |
316 | ee8ae9e4 | blueswir1 | |
317 | ee8ae9e4 | blueswir1 | /* Valid range of operand is 0..n rather than 0..n-1. */
|
318 | ee8ae9e4 | blueswir1 | #define PPC_OPERAND_PLUS1 (0x10000) |
319 | b9adb4a6 | bellard | |
320 | b9adb4a6 | bellard | /* The POWER and PowerPC assemblers use a few macros. We keep them
|
321 | b9adb4a6 | bellard | with the operands table for simplicity. The macro table is an
|
322 | b9adb4a6 | bellard | array of struct powerpc_macro. */
|
323 | b9adb4a6 | bellard | |
324 | b9adb4a6 | bellard | struct powerpc_macro
|
325 | b9adb4a6 | bellard | { |
326 | b9adb4a6 | bellard | /* The macro name. */
|
327 | b9adb4a6 | bellard | const char *name; |
328 | b9adb4a6 | bellard | |
329 | b9adb4a6 | bellard | /* The number of operands the macro takes. */
|
330 | b9adb4a6 | bellard | unsigned int operands; |
331 | b9adb4a6 | bellard | |
332 | b9adb4a6 | bellard | /* One bit flags for the opcode. These are used to indicate which
|
333 | b9adb4a6 | bellard | specific processors support the instructions. The values are the
|
334 | b9adb4a6 | bellard | same as those for the struct powerpc_opcode flags field. */
|
335 | eca8f888 | blueswir1 | unsigned long flags; |
336 | b9adb4a6 | bellard | |
337 | b9adb4a6 | bellard | /* A format string to turn the macro into a normal instruction.
|
338 | b9adb4a6 | bellard | Each %N in the string is replaced with operand number N (zero
|
339 | b9adb4a6 | bellard | based). */
|
340 | b9adb4a6 | bellard | const char *format; |
341 | b9adb4a6 | bellard | }; |
342 | b9adb4a6 | bellard | |
343 | b9adb4a6 | bellard | extern const struct powerpc_macro powerpc_macros[]; |
344 | b9adb4a6 | bellard | extern const int powerpc_num_macros; |
345 | b9adb4a6 | bellard | |
346 | b9adb4a6 | bellard | /* ppc-opc.c -- PowerPC opcode list
|
347 | eca8f888 | blueswir1 | Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
|
348 | ee8ae9e4 | blueswir1 | 2005, 2006, 2007 Free Software Foundation, Inc.
|
349 | b9adb4a6 | bellard | Written by Ian Lance Taylor, Cygnus Support
|
350 | b9adb4a6 | bellard | |
351 | eca8f888 | blueswir1 | This file is part of GDB, GAS, and the GNU binutils.
|
352 | b9adb4a6 | bellard | |
353 | eca8f888 | blueswir1 | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
354 | eca8f888 | blueswir1 | them and/or modify them under the terms of the GNU General Public
|
355 | eca8f888 | blueswir1 | License as published by the Free Software Foundation; either version
|
356 | eca8f888 | blueswir1 | 2, or (at your option) any later version.
|
357 | b9adb4a6 | bellard | |
358 | eca8f888 | blueswir1 | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
359 | eca8f888 | blueswir1 | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
360 | eca8f888 | blueswir1 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
361 | eca8f888 | blueswir1 | the GNU General Public License for more details.
|
362 | b9adb4a6 | bellard | |
363 | eca8f888 | blueswir1 | You should have received a copy of the GNU General Public License
|
364 | eca8f888 | blueswir1 | along with this file; see the file COPYING. If not, write to the Free
|
365 | eca8f888 | blueswir1 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
366 | eca8f888 | blueswir1 | 02110-1301, USA. */
|
367 | b9adb4a6 | bellard | |
368 | b9adb4a6 | bellard | /* This file holds the PowerPC opcode table. The opcode table
|
369 | b9adb4a6 | bellard | includes almost all of the extended instruction mnemonics. This
|
370 | b9adb4a6 | bellard | permits the disassembler to use them, and simplifies the assembler
|
371 | b9adb4a6 | bellard | logic, at the cost of increasing the table size. The table is
|
372 | b9adb4a6 | bellard | strictly constant data, so the compiler should be able to put it in
|
373 | b9adb4a6 | bellard | the .text section.
|
374 | b9adb4a6 | bellard | |
375 | b9adb4a6 | bellard | This file also holds the operand table. All knowledge about
|
376 | b9adb4a6 | bellard | inserting operands into instructions and vice-versa is kept in this
|
377 | b9adb4a6 | bellard | file. */
|
378 | b9adb4a6 | bellard | |
379 | b9adb4a6 | bellard | /* Local insertion and extraction functions. */
|
380 | b9adb4a6 | bellard | |
381 | eca8f888 | blueswir1 | static unsigned long insert_bat (unsigned long, long, int, const char **); |
382 | eca8f888 | blueswir1 | static long extract_bat (unsigned long, int, int *); |
383 | eca8f888 | blueswir1 | static unsigned long insert_bba (unsigned long, long, int, const char **); |
384 | eca8f888 | blueswir1 | static long extract_bba (unsigned long, int, int *); |
385 | eca8f888 | blueswir1 | static unsigned long insert_bdm (unsigned long, long, int, const char **); |
386 | eca8f888 | blueswir1 | static long extract_bdm (unsigned long, int, int *); |
387 | eca8f888 | blueswir1 | static unsigned long insert_bdp (unsigned long, long, int, const char **); |
388 | eca8f888 | blueswir1 | static long extract_bdp (unsigned long, int, int *); |
389 | eca8f888 | blueswir1 | static unsigned long insert_bo (unsigned long, long, int, const char **); |
390 | eca8f888 | blueswir1 | static long extract_bo (unsigned long, int, int *); |
391 | eca8f888 | blueswir1 | static unsigned long insert_boe (unsigned long, long, int, const char **); |
392 | eca8f888 | blueswir1 | static long extract_boe (unsigned long, int, int *); |
393 | eca8f888 | blueswir1 | static unsigned long insert_fxm (unsigned long, long, int, const char **); |
394 | eca8f888 | blueswir1 | static long extract_fxm (unsigned long, int, int *); |
395 | eca8f888 | blueswir1 | static unsigned long insert_mbe (unsigned long, long, int, const char **); |
396 | eca8f888 | blueswir1 | static long extract_mbe (unsigned long, int, int *); |
397 | eca8f888 | blueswir1 | static unsigned long insert_mb6 (unsigned long, long, int, const char **); |
398 | eca8f888 | blueswir1 | static long extract_mb6 (unsigned long, int, int *); |
399 | eca8f888 | blueswir1 | static long extract_nb (unsigned long, int, int *); |
400 | eca8f888 | blueswir1 | static unsigned long insert_nsi (unsigned long, long, int, const char **); |
401 | eca8f888 | blueswir1 | static long extract_nsi (unsigned long, int, int *); |
402 | eca8f888 | blueswir1 | static unsigned long insert_ral (unsigned long, long, int, const char **); |
403 | eca8f888 | blueswir1 | static unsigned long insert_ram (unsigned long, long, int, const char **); |
404 | eca8f888 | blueswir1 | static unsigned long insert_raq (unsigned long, long, int, const char **); |
405 | eca8f888 | blueswir1 | static unsigned long insert_ras (unsigned long, long, int, const char **); |
406 | eca8f888 | blueswir1 | static unsigned long insert_rbs (unsigned long, long, int, const char **); |
407 | eca8f888 | blueswir1 | static long extract_rbs (unsigned long, int, int *); |
408 | eca8f888 | blueswir1 | static unsigned long insert_sh6 (unsigned long, long, int, const char **); |
409 | eca8f888 | blueswir1 | static long extract_sh6 (unsigned long, int, int *); |
410 | eca8f888 | blueswir1 | static unsigned long insert_spr (unsigned long, long, int, const char **); |
411 | eca8f888 | blueswir1 | static long extract_spr (unsigned long, int, int *); |
412 | eca8f888 | blueswir1 | static unsigned long insert_sprg (unsigned long, long, int, const char **); |
413 | eca8f888 | blueswir1 | static long extract_sprg (unsigned long, int, int *); |
414 | eca8f888 | blueswir1 | static unsigned long insert_tbr (unsigned long, long, int, const char **); |
415 | eca8f888 | blueswir1 | static long extract_tbr (unsigned long, int, int *); |
416 | b9adb4a6 | bellard | |
417 | b9adb4a6 | bellard | /* The operands table.
|
418 | b9adb4a6 | bellard | |
419 | ee8ae9e4 | blueswir1 | The fields are bitm, shift, insert, extract, flags.
|
420 | eca8f888 | blueswir1 | |
421 | eca8f888 | blueswir1 | We used to put parens around the various additions, like the one
|
422 | eca8f888 | blueswir1 | for BA just below. However, that caused trouble with feeble
|
423 | eca8f888 | blueswir1 | compilers with a limit on depth of a parenthesized expression, like
|
424 | eca8f888 | blueswir1 | (reportedly) the compiler in Microsoft Developer Studio 5. So we
|
425 | eca8f888 | blueswir1 | omit the parens, since the macros are never used in a context where
|
426 | eca8f888 | blueswir1 | the addition will be ambiguous. */
|
427 | b9adb4a6 | bellard | |
428 | b9adb4a6 | bellard | const struct powerpc_operand powerpc_operands[] = |
429 | b9adb4a6 | bellard | { |
430 | b9adb4a6 | bellard | /* The zero index is used to indicate the end of the list of
|
431 | b9adb4a6 | bellard | operands. */
|
432 | eca8f888 | blueswir1 | #define UNUSED 0 |
433 | eca8f888 | blueswir1 | { 0, 0, NULL, NULL, 0 }, |
434 | b9adb4a6 | bellard | |
435 | b9adb4a6 | bellard | /* The BA field in an XL form instruction. */
|
436 | eca8f888 | blueswir1 | #define BA UNUSED + 1 |
437 | ee8ae9e4 | blueswir1 | /* The BI field in a B form or XL form instruction. */
|
438 | ee8ae9e4 | blueswir1 | #define BI BA
|
439 | ee8ae9e4 | blueswir1 | #define BI_MASK (0x1f << 16) |
440 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, |
441 | b9adb4a6 | bellard | |
442 | b9adb4a6 | bellard | /* The BA field in an XL form instruction when it must be the same
|
443 | b9adb4a6 | bellard | as the BT field in the same instruction. */
|
444 | eca8f888 | blueswir1 | #define BAT BA + 1 |
445 | ee8ae9e4 | blueswir1 | { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
446 | b9adb4a6 | bellard | |
447 | b9adb4a6 | bellard | /* The BB field in an XL form instruction. */
|
448 | eca8f888 | blueswir1 | #define BB BAT + 1 |
449 | b9adb4a6 | bellard | #define BB_MASK (0x1f << 11) |
450 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, |
451 | b9adb4a6 | bellard | |
452 | b9adb4a6 | bellard | /* The BB field in an XL form instruction when it must be the same
|
453 | b9adb4a6 | bellard | as the BA field in the same instruction. */
|
454 | eca8f888 | blueswir1 | #define BBA BB + 1 |
455 | ee8ae9e4 | blueswir1 | { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
456 | b9adb4a6 | bellard | |
457 | b9adb4a6 | bellard | /* The BD field in a B form instruction. The lower two bits are
|
458 | b9adb4a6 | bellard | forced to zero. */
|
459 | eca8f888 | blueswir1 | #define BD BBA + 1 |
460 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
461 | b9adb4a6 | bellard | |
462 | b9adb4a6 | bellard | /* The BD field in a B form instruction when absolute addressing is
|
463 | b9adb4a6 | bellard | used. */
|
464 | eca8f888 | blueswir1 | #define BDA BD + 1 |
465 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
466 | b9adb4a6 | bellard | |
467 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the - modifier is used.
|
468 | b9adb4a6 | bellard | This sets the y bit of the BO field appropriately. */
|
469 | eca8f888 | blueswir1 | #define BDM BDA + 1 |
470 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, insert_bdm, extract_bdm, |
471 | b9adb4a6 | bellard | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
472 | b9adb4a6 | bellard | |
473 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the - modifier is used
|
474 | b9adb4a6 | bellard | and absolute address is used. */
|
475 | eca8f888 | blueswir1 | #define BDMA BDM + 1 |
476 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, insert_bdm, extract_bdm, |
477 | b9adb4a6 | bellard | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
478 | b9adb4a6 | bellard | |
479 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the + modifier is used.
|
480 | b9adb4a6 | bellard | This sets the y bit of the BO field appropriately. */
|
481 | eca8f888 | blueswir1 | #define BDP BDMA + 1 |
482 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, insert_bdp, extract_bdp, |
483 | b9adb4a6 | bellard | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
484 | b9adb4a6 | bellard | |
485 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the + modifier is used
|
486 | b9adb4a6 | bellard | and absolute addressing is used. */
|
487 | eca8f888 | blueswir1 | #define BDPA BDP + 1 |
488 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, insert_bdp, extract_bdp, |
489 | b9adb4a6 | bellard | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
490 | b9adb4a6 | bellard | |
491 | b9adb4a6 | bellard | /* The BF field in an X or XL form instruction. */
|
492 | eca8f888 | blueswir1 | #define BF BDPA + 1 |
493 | ee8ae9e4 | blueswir1 | /* The CRFD field in an X form instruction. */
|
494 | ee8ae9e4 | blueswir1 | #define CRFD BF
|
495 | ee8ae9e4 | blueswir1 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, |
496 | ee8ae9e4 | blueswir1 | |
497 | ee8ae9e4 | blueswir1 | /* The BF field in an X or XL form instruction. */
|
498 | ee8ae9e4 | blueswir1 | #define BFF BF + 1 |
499 | ee8ae9e4 | blueswir1 | { 0x7, 23, NULL, NULL, 0 }, |
500 | b9adb4a6 | bellard | |
501 | b9adb4a6 | bellard | /* An optional BF field. This is used for comparison instructions,
|
502 | b9adb4a6 | bellard | in which an omitted BF field is taken as zero. */
|
503 | ee8ae9e4 | blueswir1 | #define OBF BFF + 1 |
504 | ee8ae9e4 | blueswir1 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
505 | b9adb4a6 | bellard | |
506 | b9adb4a6 | bellard | /* The BFA field in an X or XL form instruction. */
|
507 | eca8f888 | blueswir1 | #define BFA OBF + 1 |
508 | ee8ae9e4 | blueswir1 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, |
509 | b9adb4a6 | bellard | |
510 | b9adb4a6 | bellard | /* The BO field in a B form instruction. Certain values are
|
511 | b9adb4a6 | bellard | illegal. */
|
512 | ee8ae9e4 | blueswir1 | #define BO BFA + 1 |
513 | b9adb4a6 | bellard | #define BO_MASK (0x1f << 21) |
514 | ee8ae9e4 | blueswir1 | { 0x1f, 21, insert_bo, extract_bo, 0 }, |
515 | b9adb4a6 | bellard | |
516 | b9adb4a6 | bellard | /* The BO field in a B form instruction when the + or - modifier is
|
517 | b9adb4a6 | bellard | used. This is like the BO field, but it must be even. */
|
518 | eca8f888 | blueswir1 | #define BOE BO + 1 |
519 | ee8ae9e4 | blueswir1 | { 0x1e, 21, insert_boe, extract_boe, 0 }, |
520 | b9adb4a6 | bellard | |
521 | eca8f888 | blueswir1 | #define BH BOE + 1 |
522 | ee8ae9e4 | blueswir1 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
523 | eca8f888 | blueswir1 | |
524 | b9adb4a6 | bellard | /* The BT field in an X or XL form instruction. */
|
525 | eca8f888 | blueswir1 | #define BT BH + 1 |
526 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, |
527 | b9adb4a6 | bellard | |
528 | b9adb4a6 | bellard | /* The condition register number portion of the BI field in a B form
|
529 | b9adb4a6 | bellard | or XL form instruction. This is used for the extended
|
530 | b9adb4a6 | bellard | conditional branch mnemonics, which set the lower two bits of the
|
531 | b9adb4a6 | bellard | BI field. This field is optional. */
|
532 | eca8f888 | blueswir1 | #define CR BT + 1 |
533 | ee8ae9e4 | blueswir1 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
534 | eca8f888 | blueswir1 | |
535 | eca8f888 | blueswir1 | /* The CRB field in an X form instruction. */
|
536 | eca8f888 | blueswir1 | #define CRB CR + 1 |
537 | ee8ae9e4 | blueswir1 | /* The MB field in an M form instruction. */
|
538 | ee8ae9e4 | blueswir1 | #define MB CRB
|
539 | ee8ae9e4 | blueswir1 | #define MB_MASK (0x1f << 6) |
540 | ee8ae9e4 | blueswir1 | { 0x1f, 6, NULL, NULL, 0 }, |
541 | eca8f888 | blueswir1 | |
542 | eca8f888 | blueswir1 | /* The CRFS field in an X form instruction. */
|
543 | ee8ae9e4 | blueswir1 | #define CRFS CRB + 1 |
544 | ee8ae9e4 | blueswir1 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, |
545 | eca8f888 | blueswir1 | |
546 | eca8f888 | blueswir1 | /* The CT field in an X form instruction. */
|
547 | eca8f888 | blueswir1 | #define CT CRFS + 1 |
548 | ee8ae9e4 | blueswir1 | /* The MO field in an mbar instruction. */
|
549 | ee8ae9e4 | blueswir1 | #define MO CT
|
550 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
551 | b9adb4a6 | bellard | |
552 | b9adb4a6 | bellard | /* The D field in a D form instruction. This is a displacement off
|
553 | b9adb4a6 | bellard | a register, and implies that the next operand is a register in
|
554 | b9adb4a6 | bellard | parentheses. */
|
555 | eca8f888 | blueswir1 | #define D CT + 1 |
556 | ee8ae9e4 | blueswir1 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
557 | eca8f888 | blueswir1 | |
558 | eca8f888 | blueswir1 | /* The DE field in a DE form instruction. This is like D, but is 12
|
559 | eca8f888 | blueswir1 | bits only. */
|
560 | eca8f888 | blueswir1 | #define DE D + 1 |
561 | ee8ae9e4 | blueswir1 | { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
562 | eca8f888 | blueswir1 | |
563 | eca8f888 | blueswir1 | /* The DES field in a DES form instruction. This is like DS, but is 14
|
564 | eca8f888 | blueswir1 | bits only (12 stored.) */
|
565 | eca8f888 | blueswir1 | #define DES DE + 1 |
566 | ee8ae9e4 | blueswir1 | { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
567 | eca8f888 | blueswir1 | |
568 | eca8f888 | blueswir1 | /* The DQ field in a DQ form instruction. This is like D, but the
|
569 | eca8f888 | blueswir1 | lower four bits are forced to zero. */
|
570 | eca8f888 | blueswir1 | #define DQ DES + 1 |
571 | ee8ae9e4 | blueswir1 | { 0xfff0, 0, NULL, NULL, |
572 | ee8ae9e4 | blueswir1 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, |
573 | b9adb4a6 | bellard | |
574 | b9adb4a6 | bellard | /* The DS field in a DS form instruction. This is like D, but the
|
575 | b9adb4a6 | bellard | lower two bits are forced to zero. */
|
576 | eca8f888 | blueswir1 | #define DS DQ + 1 |
577 | ee8ae9e4 | blueswir1 | { 0xfffc, 0, NULL, NULL, |
578 | ee8ae9e4 | blueswir1 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, |
579 | eca8f888 | blueswir1 | |
580 | eca8f888 | blueswir1 | /* The E field in a wrteei instruction. */
|
581 | eca8f888 | blueswir1 | #define E DS + 1 |
582 | ee8ae9e4 | blueswir1 | { 0x1, 15, NULL, NULL, 0 }, |
583 | b9adb4a6 | bellard | |
584 | b9adb4a6 | bellard | /* The FL1 field in a POWER SC form instruction. */
|
585 | eca8f888 | blueswir1 | #define FL1 E + 1 |
586 | ee8ae9e4 | blueswir1 | /* The U field in an X form instruction. */
|
587 | ee8ae9e4 | blueswir1 | #define U FL1
|
588 | ee8ae9e4 | blueswir1 | { 0xf, 12, NULL, NULL, 0 }, |
589 | b9adb4a6 | bellard | |
590 | b9adb4a6 | bellard | /* The FL2 field in a POWER SC form instruction. */
|
591 | eca8f888 | blueswir1 | #define FL2 FL1 + 1 |
592 | ee8ae9e4 | blueswir1 | { 0x7, 2, NULL, NULL, 0 }, |
593 | b9adb4a6 | bellard | |
594 | b9adb4a6 | bellard | /* The FLM field in an XFL form instruction. */
|
595 | eca8f888 | blueswir1 | #define FLM FL2 + 1 |
596 | ee8ae9e4 | blueswir1 | { 0xff, 17, NULL, NULL, 0 }, |
597 | b9adb4a6 | bellard | |
598 | b9adb4a6 | bellard | /* The FRA field in an X or A form instruction. */
|
599 | eca8f888 | blueswir1 | #define FRA FLM + 1 |
600 | b9adb4a6 | bellard | #define FRA_MASK (0x1f << 16) |
601 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, |
602 | b9adb4a6 | bellard | |
603 | b9adb4a6 | bellard | /* The FRB field in an X or A form instruction. */
|
604 | eca8f888 | blueswir1 | #define FRB FRA + 1 |
605 | b9adb4a6 | bellard | #define FRB_MASK (0x1f << 11) |
606 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, |
607 | b9adb4a6 | bellard | |
608 | b9adb4a6 | bellard | /* The FRC field in an A form instruction. */
|
609 | eca8f888 | blueswir1 | #define FRC FRB + 1 |
610 | b9adb4a6 | bellard | #define FRC_MASK (0x1f << 6) |
611 | ee8ae9e4 | blueswir1 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, |
612 | b9adb4a6 | bellard | |
613 | b9adb4a6 | bellard | /* The FRS field in an X form instruction or the FRT field in a D, X
|
614 | b9adb4a6 | bellard | or A form instruction. */
|
615 | eca8f888 | blueswir1 | #define FRS FRC + 1 |
616 | eca8f888 | blueswir1 | #define FRT FRS
|
617 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, |
618 | b9adb4a6 | bellard | |
619 | b9adb4a6 | bellard | /* The FXM field in an XFX instruction. */
|
620 | eca8f888 | blueswir1 | #define FXM FRS + 1 |
621 | ee8ae9e4 | blueswir1 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, |
622 | eca8f888 | blueswir1 | |
623 | eca8f888 | blueswir1 | /* Power4 version for mfcr. */
|
624 | eca8f888 | blueswir1 | #define FXM4 FXM + 1 |
625 | ee8ae9e4 | blueswir1 | { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
626 | b9adb4a6 | bellard | |
627 | b9adb4a6 | bellard | /* The L field in a D or X form instruction. */
|
628 | eca8f888 | blueswir1 | #define L FXM4 + 1 |
629 | ee8ae9e4 | blueswir1 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
630 | b9adb4a6 | bellard | |
631 | eca8f888 | blueswir1 | /* The LEV field in a POWER SVC form instruction. */
|
632 | eca8f888 | blueswir1 | #define SVC_LEV L + 1 |
633 | ee8ae9e4 | blueswir1 | { 0x7f, 5, NULL, NULL, 0 }, |
634 | eca8f888 | blueswir1 | |
635 | eca8f888 | blueswir1 | /* The LEV field in an SC form instruction. */
|
636 | eca8f888 | blueswir1 | #define LEV SVC_LEV + 1 |
637 | ee8ae9e4 | blueswir1 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
638 | b9adb4a6 | bellard | |
639 | b9adb4a6 | bellard | /* The LI field in an I form instruction. The lower two bits are
|
640 | b9adb4a6 | bellard | forced to zero. */
|
641 | eca8f888 | blueswir1 | #define LI LEV + 1 |
642 | ee8ae9e4 | blueswir1 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
643 | b9adb4a6 | bellard | |
644 | b9adb4a6 | bellard | /* The LI field in an I form instruction when used as an absolute
|
645 | b9adb4a6 | bellard | address. */
|
646 | eca8f888 | blueswir1 | #define LIA LI + 1 |
647 | ee8ae9e4 | blueswir1 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
648 | b9adb4a6 | bellard | |
649 | eca8f888 | blueswir1 | /* The LS field in an X (sync) form instruction. */
|
650 | eca8f888 | blueswir1 | #define LS LIA + 1 |
651 | ee8ae9e4 | blueswir1 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
652 | b9adb4a6 | bellard | |
653 | b9adb4a6 | bellard | /* The ME field in an M form instruction. */
|
654 | ee8ae9e4 | blueswir1 | #define ME LS + 1 |
655 | b9adb4a6 | bellard | #define ME_MASK (0x1f << 1) |
656 | ee8ae9e4 | blueswir1 | { 0x1f, 1, NULL, NULL, 0 }, |
657 | b9adb4a6 | bellard | |
658 | b9adb4a6 | bellard | /* The MB and ME fields in an M form instruction expressed a single
|
659 | b9adb4a6 | bellard | operand which is a bitmask indicating which bits to select. This
|
660 | b9adb4a6 | bellard | is a two operand form using PPC_OPERAND_NEXT. See the
|
661 | b9adb4a6 | bellard | description in opcode/ppc.h for what this means. */
|
662 | eca8f888 | blueswir1 | #define MBE ME + 1 |
663 | ee8ae9e4 | blueswir1 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
664 | ee8ae9e4 | blueswir1 | { -1, 0, insert_mbe, extract_mbe, 0 }, |
665 | b9adb4a6 | bellard | |
666 | b9adb4a6 | bellard | /* The MB or ME field in an MD or MDS form instruction. The high
|
667 | b9adb4a6 | bellard | bit is wrapped to the low end. */
|
668 | eca8f888 | blueswir1 | #define MB6 MBE + 2 |
669 | eca8f888 | blueswir1 | #define ME6 MB6
|
670 | b9adb4a6 | bellard | #define MB6_MASK (0x3f << 5) |
671 | ee8ae9e4 | blueswir1 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, |
672 | eca8f888 | blueswir1 | |
673 | b9adb4a6 | bellard | /* The NB field in an X form instruction. The value 32 is stored as
|
674 | b9adb4a6 | bellard | 0. */
|
675 | ee8ae9e4 | blueswir1 | #define NB MB6 + 1 |
676 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, |
677 | b9adb4a6 | bellard | |
678 | b9adb4a6 | bellard | /* The NSI field in a D form instruction. This is the same as the
|
679 | b9adb4a6 | bellard | SI field, only negated. */
|
680 | eca8f888 | blueswir1 | #define NSI NB + 1 |
681 | ee8ae9e4 | blueswir1 | { 0xffff, 0, insert_nsi, extract_nsi, |
682 | b9adb4a6 | bellard | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
683 | b9adb4a6 | bellard | |
684 | eca8f888 | blueswir1 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
|
685 | eca8f888 | blueswir1 | #define RA NSI + 1 |
686 | b9adb4a6 | bellard | #define RA_MASK (0x1f << 16) |
687 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, |
688 | eca8f888 | blueswir1 | |
689 | eca8f888 | blueswir1 | /* As above, but 0 in the RA field means zero, not r0. */
|
690 | eca8f888 | blueswir1 | #define RA0 RA + 1 |
691 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, |
692 | eca8f888 | blueswir1 | |
693 | eca8f888 | blueswir1 | /* The RA field in the DQ form lq instruction, which has special
|
694 | eca8f888 | blueswir1 | value restrictions. */
|
695 | eca8f888 | blueswir1 | #define RAQ RA0 + 1 |
696 | ee8ae9e4 | blueswir1 | { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, |
697 | b9adb4a6 | bellard | |
698 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
699 | b9adb4a6 | bellard | load, which means that the RA field may not be zero and may not
|
700 | b9adb4a6 | bellard | equal the RT field. */
|
701 | eca8f888 | blueswir1 | #define RAL RAQ + 1 |
702 | ee8ae9e4 | blueswir1 | { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, |
703 | b9adb4a6 | bellard | |
704 | b9adb4a6 | bellard | /* The RA field in an lmw instruction, which has special value
|
705 | b9adb4a6 | bellard | restrictions. */
|
706 | eca8f888 | blueswir1 | #define RAM RAL + 1 |
707 | ee8ae9e4 | blueswir1 | { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, |
708 | b9adb4a6 | bellard | |
709 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
710 | b9adb4a6 | bellard | store or an updating floating point load, which means that the RA
|
711 | b9adb4a6 | bellard | field may not be zero. */
|
712 | eca8f888 | blueswir1 | #define RAS RAM + 1 |
713 | ee8ae9e4 | blueswir1 | { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, |
714 | eca8f888 | blueswir1 | |
715 | eca8f888 | blueswir1 | /* The RA field of the tlbwe instruction, which is optional. */
|
716 | eca8f888 | blueswir1 | #define RAOPT RAS + 1 |
717 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
718 | b9adb4a6 | bellard | |
719 | b9adb4a6 | bellard | /* The RB field in an X, XO, M, or MDS form instruction. */
|
720 | eca8f888 | blueswir1 | #define RB RAOPT + 1 |
721 | b9adb4a6 | bellard | #define RB_MASK (0x1f << 11) |
722 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, |
723 | b9adb4a6 | bellard | |
724 | b9adb4a6 | bellard | /* The RB field in an X form instruction when it must be the same as
|
725 | b9adb4a6 | bellard | the RS field in the instruction. This is used for extended
|
726 | b9adb4a6 | bellard | mnemonics like mr. */
|
727 | eca8f888 | blueswir1 | #define RBS RB + 1 |
728 | ee8ae9e4 | blueswir1 | { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
729 | b9adb4a6 | bellard | |
730 | b9adb4a6 | bellard | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
|
731 | b9adb4a6 | bellard | instruction or the RT field in a D, DS, X, XFX or XO form
|
732 | b9adb4a6 | bellard | instruction. */
|
733 | eca8f888 | blueswir1 | #define RS RBS + 1 |
734 | eca8f888 | blueswir1 | #define RT RS
|
735 | b9adb4a6 | bellard | #define RT_MASK (0x1f << 21) |
736 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, |
737 | eca8f888 | blueswir1 | |
738 | ee8ae9e4 | blueswir1 | /* The RS and RT fields of the DS form stq instruction, which have
|
739 | ee8ae9e4 | blueswir1 | special value restrictions. */
|
740 | eca8f888 | blueswir1 | #define RSQ RS + 1 |
741 | ee8ae9e4 | blueswir1 | #define RTQ RSQ
|
742 | ee8ae9e4 | blueswir1 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, |
743 | eca8f888 | blueswir1 | |
744 | eca8f888 | blueswir1 | /* The RS field of the tlbwe instruction, which is optional. */
|
745 | ee8ae9e4 | blueswir1 | #define RSO RSQ + 1 |
746 | eca8f888 | blueswir1 | #define RTO RSO
|
747 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
748 | b9adb4a6 | bellard | |
749 | b9adb4a6 | bellard | /* The SH field in an X or M form instruction. */
|
750 | eca8f888 | blueswir1 | #define SH RSO + 1 |
751 | b9adb4a6 | bellard | #define SH_MASK (0x1f << 11) |
752 | ee8ae9e4 | blueswir1 | /* The other UIMM field in a EVX form instruction. */
|
753 | ee8ae9e4 | blueswir1 | #define EVUIMM SH
|
754 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, NULL, 0 }, |
755 | b9adb4a6 | bellard | |
756 | b9adb4a6 | bellard | /* The SH field in an MD form instruction. This is split. */
|
757 | eca8f888 | blueswir1 | #define SH6 SH + 1 |
758 | b9adb4a6 | bellard | #define SH6_MASK ((0x1f << 11) | (1 << 1)) |
759 | ee8ae9e4 | blueswir1 | { 0x3f, -1, insert_sh6, extract_sh6, 0 }, |
760 | b9adb4a6 | bellard | |
761 | eca8f888 | blueswir1 | /* The SH field of the tlbwe instruction, which is optional. */
|
762 | eca8f888 | blueswir1 | #define SHO SH6 + 1 |
763 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
764 | eca8f888 | blueswir1 | |
765 | b9adb4a6 | bellard | /* The SI field in a D form instruction. */
|
766 | eca8f888 | blueswir1 | #define SI SHO + 1 |
767 | ee8ae9e4 | blueswir1 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
768 | b9adb4a6 | bellard | |
769 | b9adb4a6 | bellard | /* The SI field in a D form instruction when we accept a wide range
|
770 | b9adb4a6 | bellard | of positive values. */
|
771 | eca8f888 | blueswir1 | #define SISIGNOPT SI + 1 |
772 | ee8ae9e4 | blueswir1 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
773 | b9adb4a6 | bellard | |
774 | b9adb4a6 | bellard | /* The SPR field in an XFX form instruction. This is flipped--the
|
775 | b9adb4a6 | bellard | lower 5 bits are stored in the upper 5 and vice- versa. */
|
776 | eca8f888 | blueswir1 | #define SPR SISIGNOPT + 1 |
777 | eca8f888 | blueswir1 | #define PMR SPR
|
778 | b9adb4a6 | bellard | #define SPR_MASK (0x3ff << 11) |
779 | ee8ae9e4 | blueswir1 | { 0x3ff, 11, insert_spr, extract_spr, 0 }, |
780 | b9adb4a6 | bellard | |
781 | b9adb4a6 | bellard | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
|
782 | eca8f888 | blueswir1 | #define SPRBAT SPR + 1 |
783 | b9adb4a6 | bellard | #define SPRBAT_MASK (0x3 << 17) |
784 | ee8ae9e4 | blueswir1 | { 0x3, 17, NULL, NULL, 0 }, |
785 | b9adb4a6 | bellard | |
786 | b9adb4a6 | bellard | /* The SPRG register number in an XFX form m[ft]sprg instruction. */
|
787 | eca8f888 | blueswir1 | #define SPRG SPRBAT + 1 |
788 | ee8ae9e4 | blueswir1 | { 0x1f, 16, insert_sprg, extract_sprg, 0 }, |
789 | b9adb4a6 | bellard | |
790 | b9adb4a6 | bellard | /* The SR field in an X form instruction. */
|
791 | eca8f888 | blueswir1 | #define SR SPRG + 1 |
792 | ee8ae9e4 | blueswir1 | { 0xf, 16, NULL, NULL, 0 }, |
793 | eca8f888 | blueswir1 | |
794 | eca8f888 | blueswir1 | /* The STRM field in an X AltiVec form instruction. */
|
795 | eca8f888 | blueswir1 | #define STRM SR + 1 |
796 | ee8ae9e4 | blueswir1 | { 0x3, 21, NULL, NULL, 0 }, |
797 | b9adb4a6 | bellard | |
798 | b9adb4a6 | bellard | /* The SV field in a POWER SC form instruction. */
|
799 | eca8f888 | blueswir1 | #define SV STRM + 1 |
800 | ee8ae9e4 | blueswir1 | { 0x3fff, 2, NULL, NULL, 0 }, |
801 | b9adb4a6 | bellard | |
802 | b9adb4a6 | bellard | /* The TBR field in an XFX form instruction. This is like the SPR
|
803 | b9adb4a6 | bellard | field, but it is optional. */
|
804 | eca8f888 | blueswir1 | #define TBR SV + 1 |
805 | ee8ae9e4 | blueswir1 | { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, |
806 | b9adb4a6 | bellard | |
807 | b9adb4a6 | bellard | /* The TO field in a D or X form instruction. */
|
808 | eca8f888 | blueswir1 | #define TO TBR + 1 |
809 | b9adb4a6 | bellard | #define TO_MASK (0x1f << 21) |
810 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, 0 }, |
811 | b9adb4a6 | bellard | |
812 | b9adb4a6 | bellard | /* The UI field in a D form instruction. */
|
813 | ee8ae9e4 | blueswir1 | #define UI TO + 1 |
814 | ee8ae9e4 | blueswir1 | { 0xffff, 0, NULL, NULL, 0 }, |
815 | eca8f888 | blueswir1 | |
816 | eca8f888 | blueswir1 | /* The VA field in a VA, VX or VXR form instruction. */
|
817 | eca8f888 | blueswir1 | #define VA UI + 1 |
818 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, |
819 | eca8f888 | blueswir1 | |
820 | eca8f888 | blueswir1 | /* The VB field in a VA, VX or VXR form instruction. */
|
821 | eca8f888 | blueswir1 | #define VB VA + 1 |
822 | ee8ae9e4 | blueswir1 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, |
823 | eca8f888 | blueswir1 | |
824 | eca8f888 | blueswir1 | /* The VC field in a VA form instruction. */
|
825 | eca8f888 | blueswir1 | #define VC VB + 1 |
826 | ee8ae9e4 | blueswir1 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, |
827 | eca8f888 | blueswir1 | |
828 | eca8f888 | blueswir1 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */
|
829 | eca8f888 | blueswir1 | #define VD VC + 1 |
830 | eca8f888 | blueswir1 | #define VS VD
|
831 | ee8ae9e4 | blueswir1 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, |
832 | eca8f888 | blueswir1 | |
833 | eca8f888 | blueswir1 | /* The SIMM field in a VX form instruction. */
|
834 | eca8f888 | blueswir1 | #define SIMM VD + 1 |
835 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, |
836 | eca8f888 | blueswir1 | |
837 | ee8ae9e4 | blueswir1 | /* The UIMM field in a VX form instruction, and TE in Z form. */
|
838 | eca8f888 | blueswir1 | #define UIMM SIMM + 1 |
839 | ee8ae9e4 | blueswir1 | #define TE UIMM
|
840 | ee8ae9e4 | blueswir1 | { 0x1f, 16, NULL, NULL, 0 }, |
841 | eca8f888 | blueswir1 | |
842 | eca8f888 | blueswir1 | /* The SHB field in a VA form instruction. */
|
843 | eca8f888 | blueswir1 | #define SHB UIMM + 1 |
844 | ee8ae9e4 | blueswir1 | { 0xf, 6, NULL, NULL, 0 }, |
845 | eca8f888 | blueswir1 | |
846 | eca8f888 | blueswir1 | /* The other UIMM field in a half word EVX form instruction. */
|
847 | ee8ae9e4 | blueswir1 | #define EVUIMM_2 SHB + 1 |
848 | ee8ae9e4 | blueswir1 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
849 | eca8f888 | blueswir1 | |
850 | eca8f888 | blueswir1 | /* The other UIMM field in a word EVX form instruction. */
|
851 | eca8f888 | blueswir1 | #define EVUIMM_4 EVUIMM_2 + 1 |
852 | ee8ae9e4 | blueswir1 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, |
853 | eca8f888 | blueswir1 | |
854 | eca8f888 | blueswir1 | /* The other UIMM field in a double EVX form instruction. */
|
855 | eca8f888 | blueswir1 | #define EVUIMM_8 EVUIMM_4 + 1 |
856 | ee8ae9e4 | blueswir1 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
857 | eca8f888 | blueswir1 | |
858 | eca8f888 | blueswir1 | /* The WS field. */
|
859 | eca8f888 | blueswir1 | #define WS EVUIMM_8 + 1 |
860 | ee8ae9e4 | blueswir1 | { 0x7, 11, NULL, NULL, 0 }, |
861 | ee8ae9e4 | blueswir1 | |
862 | ee8ae9e4 | blueswir1 | /* The L field in an mtmsrd or A form instruction or W in an X form. */
|
863 | ee8ae9e4 | blueswir1 | #define A_L WS + 1 |
864 | ee8ae9e4 | blueswir1 | #define W A_L
|
865 | ee8ae9e4 | blueswir1 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
866 | ee8ae9e4 | blueswir1 | |
867 | ee8ae9e4 | blueswir1 | #define RMC A_L + 1 |
868 | ee8ae9e4 | blueswir1 | { 0x3, 9, NULL, NULL, 0 }, |
869 | ee8ae9e4 | blueswir1 | |
870 | ee8ae9e4 | blueswir1 | #define R RMC + 1 |
871 | ee8ae9e4 | blueswir1 | { 0x1, 16, NULL, NULL, 0 }, |
872 | eca8f888 | blueswir1 | |
873 | ee8ae9e4 | blueswir1 | #define SP R + 1 |
874 | ee8ae9e4 | blueswir1 | { 0x3, 19, NULL, NULL, 0 }, |
875 | eca8f888 | blueswir1 | |
876 | ee8ae9e4 | blueswir1 | #define S SP + 1 |
877 | ee8ae9e4 | blueswir1 | { 0x1, 20, NULL, NULL, 0 }, |
878 | ee8ae9e4 | blueswir1 | |
879 | ee8ae9e4 | blueswir1 | /* SH field starting at bit position 16. */
|
880 | ee8ae9e4 | blueswir1 | #define SH16 S + 1 |
881 | ee8ae9e4 | blueswir1 | /* The DCM and DGM fields in a Z form instruction. */
|
882 | ee8ae9e4 | blueswir1 | #define DCM SH16
|
883 | ee8ae9e4 | blueswir1 | #define DGM DCM
|
884 | ee8ae9e4 | blueswir1 | { 0x3f, 10, NULL, NULL, 0 }, |
885 | ee8ae9e4 | blueswir1 | |
886 | ee8ae9e4 | blueswir1 | /* The EH field in larx instruction. */
|
887 | ee8ae9e4 | blueswir1 | #define EH SH16 + 1 |
888 | ee8ae9e4 | blueswir1 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
889 | ee8ae9e4 | blueswir1 | |
890 | ee8ae9e4 | blueswir1 | /* The L field in an mtfsf or XFL form instruction. */
|
891 | ee8ae9e4 | blueswir1 | #define XFL_L EH + 1 |
892 | ee8ae9e4 | blueswir1 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, |
893 | b9adb4a6 | bellard | }; |
894 | b9adb4a6 | bellard | |
895 | ee8ae9e4 | blueswir1 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) |
896 | ee8ae9e4 | blueswir1 | / sizeof (powerpc_operands[0])); |
897 | ee8ae9e4 | blueswir1 | |
898 | b9adb4a6 | bellard | /* The functions used to insert and extract complicated operands. */
|
899 | b9adb4a6 | bellard | |
900 | b9adb4a6 | bellard | /* The BA field in an XL form instruction when it must be the same as
|
901 | b9adb4a6 | bellard | the BT field in the same instruction. This operand is marked FAKE.
|
902 | b9adb4a6 | bellard | The insertion function just copies the BT field into the BA field,
|
903 | b9adb4a6 | bellard | and the extraction function just checks that the fields are the
|
904 | b9adb4a6 | bellard | same. */
|
905 | b9adb4a6 | bellard | |
906 | 5fafdf24 | ths | static unsigned long |
907 | eca8f888 | blueswir1 | insert_bat (unsigned long insn, |
908 | eca8f888 | blueswir1 | long value ATTRIBUTE_UNUSED,
|
909 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
910 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
911 | b9adb4a6 | bellard | { |
912 | b9adb4a6 | bellard | return insn | (((insn >> 21) & 0x1f) << 16); |
913 | b9adb4a6 | bellard | } |
914 | b9adb4a6 | bellard | |
915 | b9adb4a6 | bellard | static long |
916 | eca8f888 | blueswir1 | extract_bat (unsigned long insn, |
917 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
918 | eca8f888 | blueswir1 | int *invalid)
|
919 | b9adb4a6 | bellard | { |
920 | eca8f888 | blueswir1 | if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
921 | b9adb4a6 | bellard | *invalid = 1;
|
922 | b9adb4a6 | bellard | return 0; |
923 | b9adb4a6 | bellard | } |
924 | b9adb4a6 | bellard | |
925 | b9adb4a6 | bellard | /* The BB field in an XL form instruction when it must be the same as
|
926 | b9adb4a6 | bellard | the BA field in the same instruction. This operand is marked FAKE.
|
927 | b9adb4a6 | bellard | The insertion function just copies the BA field into the BB field,
|
928 | b9adb4a6 | bellard | and the extraction function just checks that the fields are the
|
929 | b9adb4a6 | bellard | same. */
|
930 | b9adb4a6 | bellard | |
931 | b9adb4a6 | bellard | static unsigned long |
932 | eca8f888 | blueswir1 | insert_bba (unsigned long insn, |
933 | eca8f888 | blueswir1 | long value ATTRIBUTE_UNUSED,
|
934 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
935 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
936 | b9adb4a6 | bellard | { |
937 | b9adb4a6 | bellard | return insn | (((insn >> 16) & 0x1f) << 11); |
938 | b9adb4a6 | bellard | } |
939 | b9adb4a6 | bellard | |
940 | b9adb4a6 | bellard | static long |
941 | eca8f888 | blueswir1 | extract_bba (unsigned long insn, |
942 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
943 | eca8f888 | blueswir1 | int *invalid)
|
944 | b9adb4a6 | bellard | { |
945 | eca8f888 | blueswir1 | if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
946 | b9adb4a6 | bellard | *invalid = 1;
|
947 | b9adb4a6 | bellard | return 0; |
948 | b9adb4a6 | bellard | } |
949 | b9adb4a6 | bellard | |
950 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the - modifier is used.
|
951 | b9adb4a6 | bellard | This modifier means that the branch is not expected to be taken.
|
952 | eca8f888 | blueswir1 | For chips built to versions of the architecture prior to version 2
|
953 | eca8f888 | blueswir1 | (ie. not Power4 compatible), we set the y bit of the BO field to 1
|
954 | eca8f888 | blueswir1 | if the offset is negative. When extracting, we require that the y
|
955 | eca8f888 | blueswir1 | bit be 1 and that the offset be positive, since if the y bit is 0
|
956 | eca8f888 | blueswir1 | we just want to print the normal form of the instruction.
|
957 | eca8f888 | blueswir1 | Power4 compatible targets use two bits, "a", and "t", instead of
|
958 | eca8f888 | blueswir1 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
|
959 | eca8f888 | blueswir1 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
|
960 | eca8f888 | blueswir1 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
|
961 | ee8ae9e4 | blueswir1 | for branch on CTR. We only handle the taken/not-taken hint here.
|
962 | ee8ae9e4 | blueswir1 | Note that we don't relax the conditions tested here when
|
963 | ee8ae9e4 | blueswir1 | disassembling with -Many because insns using extract_bdm and
|
964 | ee8ae9e4 | blueswir1 | extract_bdp always occur in pairs. One or the other will always
|
965 | ee8ae9e4 | blueswir1 | be valid. */
|
966 | b9adb4a6 | bellard | |
967 | b9adb4a6 | bellard | static unsigned long |
968 | eca8f888 | blueswir1 | insert_bdm (unsigned long insn, |
969 | eca8f888 | blueswir1 | long value,
|
970 | eca8f888 | blueswir1 | int dialect,
|
971 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
972 | b9adb4a6 | bellard | { |
973 | eca8f888 | blueswir1 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
974 | eca8f888 | blueswir1 | { |
975 | eca8f888 | blueswir1 | if ((value & 0x8000) != 0) |
976 | eca8f888 | blueswir1 | insn |= 1 << 21; |
977 | eca8f888 | blueswir1 | } |
978 | eca8f888 | blueswir1 | else
|
979 | eca8f888 | blueswir1 | { |
980 | eca8f888 | blueswir1 | if ((insn & (0x14 << 21)) == (0x04 << 21)) |
981 | eca8f888 | blueswir1 | insn |= 0x02 << 21; |
982 | eca8f888 | blueswir1 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
983 | eca8f888 | blueswir1 | insn |= 0x08 << 21; |
984 | eca8f888 | blueswir1 | } |
985 | b9adb4a6 | bellard | return insn | (value & 0xfffc); |
986 | b9adb4a6 | bellard | } |
987 | b9adb4a6 | bellard | |
988 | b9adb4a6 | bellard | static long |
989 | eca8f888 | blueswir1 | extract_bdm (unsigned long insn, |
990 | eca8f888 | blueswir1 | int dialect,
|
991 | eca8f888 | blueswir1 | int *invalid)
|
992 | b9adb4a6 | bellard | { |
993 | eca8f888 | blueswir1 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
994 | eca8f888 | blueswir1 | { |
995 | eca8f888 | blueswir1 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) |
996 | eca8f888 | blueswir1 | *invalid = 1;
|
997 | eca8f888 | blueswir1 | } |
998 | b9adb4a6 | bellard | else
|
999 | eca8f888 | blueswir1 | { |
1000 | eca8f888 | blueswir1 | if ((insn & (0x17 << 21)) != (0x06 << 21) |
1001 | eca8f888 | blueswir1 | && (insn & (0x1d << 21)) != (0x18 << 21)) |
1002 | eca8f888 | blueswir1 | *invalid = 1;
|
1003 | eca8f888 | blueswir1 | } |
1004 | eca8f888 | blueswir1 | |
1005 | eca8f888 | blueswir1 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1006 | b9adb4a6 | bellard | } |
1007 | b9adb4a6 | bellard | |
1008 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the + modifier is used.
|
1009 | b9adb4a6 | bellard | This is like BDM, above, except that the branch is expected to be
|
1010 | b9adb4a6 | bellard | taken. */
|
1011 | b9adb4a6 | bellard | |
1012 | b9adb4a6 | bellard | static unsigned long |
1013 | eca8f888 | blueswir1 | insert_bdp (unsigned long insn, |
1014 | eca8f888 | blueswir1 | long value,
|
1015 | eca8f888 | blueswir1 | int dialect,
|
1016 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1017 | b9adb4a6 | bellard | { |
1018 | eca8f888 | blueswir1 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
1019 | eca8f888 | blueswir1 | { |
1020 | eca8f888 | blueswir1 | if ((value & 0x8000) == 0) |
1021 | eca8f888 | blueswir1 | insn |= 1 << 21; |
1022 | eca8f888 | blueswir1 | } |
1023 | eca8f888 | blueswir1 | else
|
1024 | eca8f888 | blueswir1 | { |
1025 | eca8f888 | blueswir1 | if ((insn & (0x14 << 21)) == (0x04 << 21)) |
1026 | eca8f888 | blueswir1 | insn |= 0x03 << 21; |
1027 | eca8f888 | blueswir1 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
1028 | eca8f888 | blueswir1 | insn |= 0x09 << 21; |
1029 | eca8f888 | blueswir1 | } |
1030 | b9adb4a6 | bellard | return insn | (value & 0xfffc); |
1031 | b9adb4a6 | bellard | } |
1032 | b9adb4a6 | bellard | |
1033 | b9adb4a6 | bellard | static long |
1034 | eca8f888 | blueswir1 | extract_bdp (unsigned long insn, |
1035 | eca8f888 | blueswir1 | int dialect,
|
1036 | eca8f888 | blueswir1 | int *invalid)
|
1037 | b9adb4a6 | bellard | { |
1038 | eca8f888 | blueswir1 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
1039 | eca8f888 | blueswir1 | { |
1040 | eca8f888 | blueswir1 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) |
1041 | eca8f888 | blueswir1 | *invalid = 1;
|
1042 | eca8f888 | blueswir1 | } |
1043 | b9adb4a6 | bellard | else
|
1044 | eca8f888 | blueswir1 | { |
1045 | eca8f888 | blueswir1 | if ((insn & (0x17 << 21)) != (0x07 << 21) |
1046 | eca8f888 | blueswir1 | && (insn & (0x1d << 21)) != (0x19 << 21)) |
1047 | eca8f888 | blueswir1 | *invalid = 1;
|
1048 | eca8f888 | blueswir1 | } |
1049 | eca8f888 | blueswir1 | |
1050 | eca8f888 | blueswir1 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1051 | b9adb4a6 | bellard | } |
1052 | b9adb4a6 | bellard | |
1053 | b9adb4a6 | bellard | /* Check for legal values of a BO field. */
|
1054 | b9adb4a6 | bellard | |
1055 | b9adb4a6 | bellard | static int |
1056 | ee8ae9e4 | blueswir1 | valid_bo (long value, int dialect, int extract) |
1057 | eca8f888 | blueswir1 | { |
1058 | eca8f888 | blueswir1 | if ((dialect & PPC_OPCODE_POWER4) == 0) |
1059 | eca8f888 | blueswir1 | { |
1060 | ee8ae9e4 | blueswir1 | int valid;
|
1061 | eca8f888 | blueswir1 | /* Certain encodings have bits that are required to be zero.
|
1062 | eca8f888 | blueswir1 | These are (z must be zero, y may be anything):
|
1063 | eca8f888 | blueswir1 | 001zy
|
1064 | eca8f888 | blueswir1 | 011zy
|
1065 | eca8f888 | blueswir1 | 1z00y
|
1066 | eca8f888 | blueswir1 | 1z01y
|
1067 | eca8f888 | blueswir1 | 1z1zz
|
1068 | eca8f888 | blueswir1 | */
|
1069 | eca8f888 | blueswir1 | switch (value & 0x14) |
1070 | eca8f888 | blueswir1 | { |
1071 | eca8f888 | blueswir1 | default:
|
1072 | eca8f888 | blueswir1 | case 0: |
1073 | ee8ae9e4 | blueswir1 | valid = 1;
|
1074 | ee8ae9e4 | blueswir1 | break;
|
1075 | eca8f888 | blueswir1 | case 0x4: |
1076 | ee8ae9e4 | blueswir1 | valid = (value & 0x2) == 0; |
1077 | ee8ae9e4 | blueswir1 | break;
|
1078 | eca8f888 | blueswir1 | case 0x10: |
1079 | ee8ae9e4 | blueswir1 | valid = (value & 0x8) == 0; |
1080 | ee8ae9e4 | blueswir1 | break;
|
1081 | eca8f888 | blueswir1 | case 0x14: |
1082 | ee8ae9e4 | blueswir1 | valid = value == 0x14;
|
1083 | ee8ae9e4 | blueswir1 | break;
|
1084 | eca8f888 | blueswir1 | } |
1085 | ee8ae9e4 | blueswir1 | /* When disassembling with -Many, accept power4 encodings too. */
|
1086 | ee8ae9e4 | blueswir1 | if (valid
|
1087 | ee8ae9e4 | blueswir1 | || (dialect & PPC_OPCODE_ANY) == 0
|
1088 | ee8ae9e4 | blueswir1 | || !extract) |
1089 | ee8ae9e4 | blueswir1 | return valid;
|
1090 | eca8f888 | blueswir1 | } |
1091 | ee8ae9e4 | blueswir1 | |
1092 | ee8ae9e4 | blueswir1 | /* Certain encodings have bits that are required to be zero.
|
1093 | ee8ae9e4 | blueswir1 | These are (z must be zero, a & t may be anything):
|
1094 | ee8ae9e4 | blueswir1 | 0000z
|
1095 | ee8ae9e4 | blueswir1 | 0001z
|
1096 | ee8ae9e4 | blueswir1 | 0100z
|
1097 | ee8ae9e4 | blueswir1 | 0101z
|
1098 | ee8ae9e4 | blueswir1 | 001at
|
1099 | ee8ae9e4 | blueswir1 | 011at
|
1100 | ee8ae9e4 | blueswir1 | 1a00t
|
1101 | ee8ae9e4 | blueswir1 | 1a01t
|
1102 | ee8ae9e4 | blueswir1 | 1z1zz
|
1103 | ee8ae9e4 | blueswir1 | */
|
1104 | ee8ae9e4 | blueswir1 | if ((value & 0x14) == 0) |
1105 | ee8ae9e4 | blueswir1 | return (value & 0x1) == 0; |
1106 | ee8ae9e4 | blueswir1 | else if ((value & 0x14) == 0x14) |
1107 | ee8ae9e4 | blueswir1 | return value == 0x14; |
1108 | eca8f888 | blueswir1 | else
|
1109 | ee8ae9e4 | blueswir1 | return 1; |
1110 | b9adb4a6 | bellard | } |
1111 | b9adb4a6 | bellard | |
1112 | b9adb4a6 | bellard | /* The BO field in a B form instruction. Warn about attempts to set
|
1113 | b9adb4a6 | bellard | the field to an illegal value. */
|
1114 | b9adb4a6 | bellard | |
1115 | b9adb4a6 | bellard | static unsigned long |
1116 | eca8f888 | blueswir1 | insert_bo (unsigned long insn, |
1117 | eca8f888 | blueswir1 | long value,
|
1118 | eca8f888 | blueswir1 | int dialect,
|
1119 | eca8f888 | blueswir1 | const char **errmsg) |
1120 | eca8f888 | blueswir1 | { |
1121 | ee8ae9e4 | blueswir1 | if (!valid_bo (value, dialect, 0)) |
1122 | eca8f888 | blueswir1 | *errmsg = _("invalid conditional option");
|
1123 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 21); |
1124 | b9adb4a6 | bellard | } |
1125 | b9adb4a6 | bellard | |
1126 | b9adb4a6 | bellard | static long |
1127 | eca8f888 | blueswir1 | extract_bo (unsigned long insn, |
1128 | eca8f888 | blueswir1 | int dialect,
|
1129 | eca8f888 | blueswir1 | int *invalid)
|
1130 | b9adb4a6 | bellard | { |
1131 | eca8f888 | blueswir1 | long value;
|
1132 | b9adb4a6 | bellard | |
1133 | b9adb4a6 | bellard | value = (insn >> 21) & 0x1f; |
1134 | ee8ae9e4 | blueswir1 | if (!valid_bo (value, dialect, 1)) |
1135 | b9adb4a6 | bellard | *invalid = 1;
|
1136 | b9adb4a6 | bellard | return value;
|
1137 | b9adb4a6 | bellard | } |
1138 | b9adb4a6 | bellard | |
1139 | b9adb4a6 | bellard | /* The BO field in a B form instruction when the + or - modifier is
|
1140 | b9adb4a6 | bellard | used. This is like the BO field, but it must be even. When
|
1141 | b9adb4a6 | bellard | extracting it, we force it to be even. */
|
1142 | b9adb4a6 | bellard | |
1143 | b9adb4a6 | bellard | static unsigned long |
1144 | eca8f888 | blueswir1 | insert_boe (unsigned long insn, |
1145 | eca8f888 | blueswir1 | long value,
|
1146 | eca8f888 | blueswir1 | int dialect,
|
1147 | eca8f888 | blueswir1 | const char **errmsg) |
1148 | b9adb4a6 | bellard | { |
1149 | ee8ae9e4 | blueswir1 | if (!valid_bo (value, dialect, 0)) |
1150 | eca8f888 | blueswir1 | *errmsg = _("invalid conditional option");
|
1151 | eca8f888 | blueswir1 | else if ((value & 1) != 0) |
1152 | eca8f888 | blueswir1 | *errmsg = _("attempt to set y bit when using + or - modifier");
|
1153 | eca8f888 | blueswir1 | |
1154 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 21); |
1155 | b9adb4a6 | bellard | } |
1156 | b9adb4a6 | bellard | |
1157 | b9adb4a6 | bellard | static long |
1158 | eca8f888 | blueswir1 | extract_boe (unsigned long insn, |
1159 | eca8f888 | blueswir1 | int dialect,
|
1160 | eca8f888 | blueswir1 | int *invalid)
|
1161 | b9adb4a6 | bellard | { |
1162 | eca8f888 | blueswir1 | long value;
|
1163 | b9adb4a6 | bellard | |
1164 | b9adb4a6 | bellard | value = (insn >> 21) & 0x1f; |
1165 | ee8ae9e4 | blueswir1 | if (!valid_bo (value, dialect, 1)) |
1166 | b9adb4a6 | bellard | *invalid = 1;
|
1167 | b9adb4a6 | bellard | return value & 0x1e; |
1168 | b9adb4a6 | bellard | } |
1169 | b9adb4a6 | bellard | |
1170 | eca8f888 | blueswir1 | /* FXM mask in mfcr and mtcrf instructions. */
|
1171 | eca8f888 | blueswir1 | |
1172 | eca8f888 | blueswir1 | static unsigned long |
1173 | eca8f888 | blueswir1 | insert_fxm (unsigned long insn, |
1174 | eca8f888 | blueswir1 | long value,
|
1175 | eca8f888 | blueswir1 | int dialect,
|
1176 | eca8f888 | blueswir1 | const char **errmsg) |
1177 | eca8f888 | blueswir1 | { |
1178 | eca8f888 | blueswir1 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly
|
1179 | eca8f888 | blueswir1 | one bit of the mask field is set. */
|
1180 | eca8f888 | blueswir1 | if ((insn & (1 << 20)) != 0) |
1181 | eca8f888 | blueswir1 | { |
1182 | eca8f888 | blueswir1 | if (value == 0 || (value & -value) != value) |
1183 | eca8f888 | blueswir1 | { |
1184 | eca8f888 | blueswir1 | *errmsg = _("invalid mask field");
|
1185 | eca8f888 | blueswir1 | value = 0;
|
1186 | eca8f888 | blueswir1 | } |
1187 | eca8f888 | blueswir1 | } |
1188 | eca8f888 | blueswir1 | |
1189 | eca8f888 | blueswir1 | /* If the optional field on mfcr is missing that means we want to use
|
1190 | eca8f888 | blueswir1 | the old form of the instruction that moves the whole cr. In that
|
1191 | eca8f888 | blueswir1 | case we'll have VALUE zero. There doesn't seem to be a way to
|
1192 | eca8f888 | blueswir1 | distinguish this from the case where someone writes mfcr %r3,0. */
|
1193 | eca8f888 | blueswir1 | else if (value == 0) |
1194 | eca8f888 | blueswir1 | ; |
1195 | eca8f888 | blueswir1 | |
1196 | eca8f888 | blueswir1 | /* If only one bit of the FXM field is set, we can use the new form
|
1197 | eca8f888 | blueswir1 | of the instruction, which is faster. Unlike the Power4 branch hint
|
1198 | eca8f888 | blueswir1 | encoding, this is not backward compatible. Do not generate the
|
1199 | eca8f888 | blueswir1 | new form unless -mpower4 has been given, or -many and the two
|
1200 | eca8f888 | blueswir1 | operand form of mfcr was used. */
|
1201 | eca8f888 | blueswir1 | else if ((value & -value) == value |
1202 | eca8f888 | blueswir1 | && ((dialect & PPC_OPCODE_POWER4) != 0
|
1203 | eca8f888 | blueswir1 | || ((dialect & PPC_OPCODE_ANY) != 0
|
1204 | eca8f888 | blueswir1 | && (insn & (0x3ff << 1)) == 19 << 1))) |
1205 | eca8f888 | blueswir1 | insn |= 1 << 20; |
1206 | eca8f888 | blueswir1 | |
1207 | eca8f888 | blueswir1 | /* Any other value on mfcr is an error. */
|
1208 | eca8f888 | blueswir1 | else if ((insn & (0x3ff << 1)) == 19 << 1) |
1209 | eca8f888 | blueswir1 | { |
1210 | eca8f888 | blueswir1 | *errmsg = _("ignoring invalid mfcr mask");
|
1211 | eca8f888 | blueswir1 | value = 0;
|
1212 | eca8f888 | blueswir1 | } |
1213 | eca8f888 | blueswir1 | |
1214 | eca8f888 | blueswir1 | return insn | ((value & 0xff) << 12); |
1215 | eca8f888 | blueswir1 | } |
1216 | eca8f888 | blueswir1 | |
1217 | eca8f888 | blueswir1 | static long |
1218 | eca8f888 | blueswir1 | extract_fxm (unsigned long insn, |
1219 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1220 | eca8f888 | blueswir1 | int *invalid)
|
1221 | eca8f888 | blueswir1 | { |
1222 | eca8f888 | blueswir1 | long mask = (insn >> 12) & 0xff; |
1223 | eca8f888 | blueswir1 | |
1224 | eca8f888 | blueswir1 | /* Is this a Power4 insn? */
|
1225 | eca8f888 | blueswir1 | if ((insn & (1 << 20)) != 0) |
1226 | eca8f888 | blueswir1 | { |
1227 | eca8f888 | blueswir1 | /* Exactly one bit of MASK should be set. */
|
1228 | eca8f888 | blueswir1 | if (mask == 0 || (mask & -mask) != mask) |
1229 | eca8f888 | blueswir1 | *invalid = 1;
|
1230 | eca8f888 | blueswir1 | } |
1231 | eca8f888 | blueswir1 | |
1232 | eca8f888 | blueswir1 | /* Check that non-power4 form of mfcr has a zero MASK. */
|
1233 | eca8f888 | blueswir1 | else if ((insn & (0x3ff << 1)) == 19 << 1) |
1234 | eca8f888 | blueswir1 | { |
1235 | eca8f888 | blueswir1 | if (mask != 0) |
1236 | eca8f888 | blueswir1 | *invalid = 1;
|
1237 | eca8f888 | blueswir1 | } |
1238 | eca8f888 | blueswir1 | |
1239 | eca8f888 | blueswir1 | return mask;
|
1240 | b9adb4a6 | bellard | } |
1241 | b9adb4a6 | bellard | |
1242 | b9adb4a6 | bellard | /* The MB and ME fields in an M form instruction expressed as a single
|
1243 | b9adb4a6 | bellard | operand which is itself a bitmask. The extraction function always
|
1244 | b9adb4a6 | bellard | marks it as invalid, since we never want to recognize an
|
1245 | b9adb4a6 | bellard | instruction which uses a field of this type. */
|
1246 | b9adb4a6 | bellard | |
1247 | b9adb4a6 | bellard | static unsigned long |
1248 | eca8f888 | blueswir1 | insert_mbe (unsigned long insn, |
1249 | eca8f888 | blueswir1 | long value,
|
1250 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1251 | eca8f888 | blueswir1 | const char **errmsg) |
1252 | b9adb4a6 | bellard | { |
1253 | eca8f888 | blueswir1 | unsigned long uval, mask; |
1254 | eca8f888 | blueswir1 | int mb, me, mx, count, last;
|
1255 | b9adb4a6 | bellard | |
1256 | b9adb4a6 | bellard | uval = value; |
1257 | b9adb4a6 | bellard | |
1258 | b9adb4a6 | bellard | if (uval == 0) |
1259 | b9adb4a6 | bellard | { |
1260 | eca8f888 | blueswir1 | *errmsg = _("illegal bitmask");
|
1261 | b9adb4a6 | bellard | return insn;
|
1262 | b9adb4a6 | bellard | } |
1263 | b9adb4a6 | bellard | |
1264 | eca8f888 | blueswir1 | mb = 0;
|
1265 | eca8f888 | blueswir1 | me = 32;
|
1266 | eca8f888 | blueswir1 | if ((uval & 1) != 0) |
1267 | eca8f888 | blueswir1 | last = 1;
|
1268 | eca8f888 | blueswir1 | else
|
1269 | eca8f888 | blueswir1 | last = 0;
|
1270 | eca8f888 | blueswir1 | count = 0;
|
1271 | b9adb4a6 | bellard | |
1272 | eca8f888 | blueswir1 | /* mb: location of last 0->1 transition */
|
1273 | eca8f888 | blueswir1 | /* me: location of last 1->0 transition */
|
1274 | eca8f888 | blueswir1 | /* count: # transitions */
|
1275 | b9adb4a6 | bellard | |
1276 | eca8f888 | blueswir1 | for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) |
1277 | b9adb4a6 | bellard | { |
1278 | eca8f888 | blueswir1 | if ((uval & mask) && !last)
|
1279 | eca8f888 | blueswir1 | { |
1280 | eca8f888 | blueswir1 | ++count; |
1281 | eca8f888 | blueswir1 | mb = mx; |
1282 | eca8f888 | blueswir1 | last = 1;
|
1283 | eca8f888 | blueswir1 | } |
1284 | eca8f888 | blueswir1 | else if (!(uval & mask) && last) |
1285 | eca8f888 | blueswir1 | { |
1286 | eca8f888 | blueswir1 | ++count; |
1287 | eca8f888 | blueswir1 | me = mx; |
1288 | eca8f888 | blueswir1 | last = 0;
|
1289 | eca8f888 | blueswir1 | } |
1290 | b9adb4a6 | bellard | } |
1291 | eca8f888 | blueswir1 | if (me == 0) |
1292 | eca8f888 | blueswir1 | me = 32;
|
1293 | b9adb4a6 | bellard | |
1294 | eca8f888 | blueswir1 | if (count != 2 && (count != 0 || ! last)) |
1295 | eca8f888 | blueswir1 | *errmsg = _("illegal bitmask");
|
1296 | eca8f888 | blueswir1 | |
1297 | eca8f888 | blueswir1 | return insn | (mb << 6) | ((me - 1) << 1); |
1298 | b9adb4a6 | bellard | } |
1299 | b9adb4a6 | bellard | |
1300 | b9adb4a6 | bellard | static long |
1301 | eca8f888 | blueswir1 | extract_mbe (unsigned long insn, |
1302 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1303 | eca8f888 | blueswir1 | int *invalid)
|
1304 | b9adb4a6 | bellard | { |
1305 | b9adb4a6 | bellard | long ret;
|
1306 | b9adb4a6 | bellard | int mb, me;
|
1307 | b9adb4a6 | bellard | int i;
|
1308 | b9adb4a6 | bellard | |
1309 | eca8f888 | blueswir1 | *invalid = 1;
|
1310 | b9adb4a6 | bellard | |
1311 | b9adb4a6 | bellard | mb = (insn >> 6) & 0x1f; |
1312 | b9adb4a6 | bellard | me = (insn >> 1) & 0x1f; |
1313 | eca8f888 | blueswir1 | if (mb < me + 1) |
1314 | eca8f888 | blueswir1 | { |
1315 | eca8f888 | blueswir1 | ret = 0;
|
1316 | eca8f888 | blueswir1 | for (i = mb; i <= me; i++)
|
1317 | eca8f888 | blueswir1 | ret |= 1L << (31 - i); |
1318 | eca8f888 | blueswir1 | } |
1319 | eca8f888 | blueswir1 | else if (mb == me + 1) |
1320 | eca8f888 | blueswir1 | ret = ~0;
|
1321 | eca8f888 | blueswir1 | else /* (mb > me + 1) */ |
1322 | eca8f888 | blueswir1 | { |
1323 | eca8f888 | blueswir1 | ret = ~0;
|
1324 | eca8f888 | blueswir1 | for (i = me + 1; i < mb; i++) |
1325 | eca8f888 | blueswir1 | ret &= ~(1L << (31 - i)); |
1326 | eca8f888 | blueswir1 | } |
1327 | b9adb4a6 | bellard | return ret;
|
1328 | b9adb4a6 | bellard | } |
1329 | b9adb4a6 | bellard | |
1330 | b9adb4a6 | bellard | /* The MB or ME field in an MD or MDS form instruction. The high bit
|
1331 | b9adb4a6 | bellard | is wrapped to the low end. */
|
1332 | b9adb4a6 | bellard | |
1333 | b9adb4a6 | bellard | static unsigned long |
1334 | eca8f888 | blueswir1 | insert_mb6 (unsigned long insn, |
1335 | eca8f888 | blueswir1 | long value,
|
1336 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1337 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1338 | b9adb4a6 | bellard | { |
1339 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 6) | (value & 0x20); |
1340 | b9adb4a6 | bellard | } |
1341 | b9adb4a6 | bellard | |
1342 | b9adb4a6 | bellard | static long |
1343 | eca8f888 | blueswir1 | extract_mb6 (unsigned long insn, |
1344 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1345 | eca8f888 | blueswir1 | int *invalid ATTRIBUTE_UNUSED)
|
1346 | b9adb4a6 | bellard | { |
1347 | b9adb4a6 | bellard | return ((insn >> 6) & 0x1f) | (insn & 0x20); |
1348 | b9adb4a6 | bellard | } |
1349 | b9adb4a6 | bellard | |
1350 | b9adb4a6 | bellard | /* The NB field in an X form instruction. The value 32 is stored as
|
1351 | b9adb4a6 | bellard | 0. */
|
1352 | b9adb4a6 | bellard | |
1353 | b9adb4a6 | bellard | static long |
1354 | eca8f888 | blueswir1 | extract_nb (unsigned long insn, |
1355 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1356 | eca8f888 | blueswir1 | int *invalid ATTRIBUTE_UNUSED)
|
1357 | b9adb4a6 | bellard | { |
1358 | b9adb4a6 | bellard | long ret;
|
1359 | b9adb4a6 | bellard | |
1360 | b9adb4a6 | bellard | ret = (insn >> 11) & 0x1f; |
1361 | b9adb4a6 | bellard | if (ret == 0) |
1362 | b9adb4a6 | bellard | ret = 32;
|
1363 | b9adb4a6 | bellard | return ret;
|
1364 | b9adb4a6 | bellard | } |
1365 | b9adb4a6 | bellard | |
1366 | b9adb4a6 | bellard | /* The NSI field in a D form instruction. This is the same as the SI
|
1367 | b9adb4a6 | bellard | field, only negated. The extraction function always marks it as
|
1368 | b9adb4a6 | bellard | invalid, since we never want to recognize an instruction which uses
|
1369 | b9adb4a6 | bellard | a field of this type. */
|
1370 | b9adb4a6 | bellard | |
1371 | b9adb4a6 | bellard | static unsigned long |
1372 | eca8f888 | blueswir1 | insert_nsi (unsigned long insn, |
1373 | eca8f888 | blueswir1 | long value,
|
1374 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1375 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1376 | b9adb4a6 | bellard | { |
1377 | eca8f888 | blueswir1 | return insn | (-value & 0xffff); |
1378 | b9adb4a6 | bellard | } |
1379 | b9adb4a6 | bellard | |
1380 | b9adb4a6 | bellard | static long |
1381 | eca8f888 | blueswir1 | extract_nsi (unsigned long insn, |
1382 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1383 | eca8f888 | blueswir1 | int *invalid)
|
1384 | b9adb4a6 | bellard | { |
1385 | eca8f888 | blueswir1 | *invalid = 1;
|
1386 | eca8f888 | blueswir1 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); |
1387 | b9adb4a6 | bellard | } |
1388 | b9adb4a6 | bellard | |
1389 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
1390 | b9adb4a6 | bellard | load, which means that the RA field may not be zero and may not
|
1391 | b9adb4a6 | bellard | equal the RT field. */
|
1392 | b9adb4a6 | bellard | |
1393 | b9adb4a6 | bellard | static unsigned long |
1394 | eca8f888 | blueswir1 | insert_ral (unsigned long insn, |
1395 | eca8f888 | blueswir1 | long value,
|
1396 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1397 | eca8f888 | blueswir1 | const char **errmsg) |
1398 | b9adb4a6 | bellard | { |
1399 | b9adb4a6 | bellard | if (value == 0 |
1400 | eca8f888 | blueswir1 | || (unsigned long) value == ((insn >> 21) & 0x1f)) |
1401 | b9adb4a6 | bellard | *errmsg = "invalid register operand when updating";
|
1402 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16); |
1403 | b9adb4a6 | bellard | } |
1404 | b9adb4a6 | bellard | |
1405 | b9adb4a6 | bellard | /* The RA field in an lmw instruction, which has special value
|
1406 | b9adb4a6 | bellard | restrictions. */
|
1407 | b9adb4a6 | bellard | |
1408 | b9adb4a6 | bellard | static unsigned long |
1409 | eca8f888 | blueswir1 | insert_ram (unsigned long insn, |
1410 | eca8f888 | blueswir1 | long value,
|
1411 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1412 | eca8f888 | blueswir1 | const char **errmsg) |
1413 | b9adb4a6 | bellard | { |
1414 | eca8f888 | blueswir1 | if ((unsigned long) value >= ((insn >> 21) & 0x1f)) |
1415 | eca8f888 | blueswir1 | *errmsg = _("index register in load range");
|
1416 | eca8f888 | blueswir1 | return insn | ((value & 0x1f) << 16); |
1417 | eca8f888 | blueswir1 | } |
1418 | eca8f888 | blueswir1 | |
1419 | eca8f888 | blueswir1 | /* The RA field in the DQ form lq instruction, which has special
|
1420 | eca8f888 | blueswir1 | value restrictions. */
|
1421 | eca8f888 | blueswir1 | |
1422 | eca8f888 | blueswir1 | static unsigned long |
1423 | eca8f888 | blueswir1 | insert_raq (unsigned long insn, |
1424 | eca8f888 | blueswir1 | long value,
|
1425 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1426 | eca8f888 | blueswir1 | const char **errmsg) |
1427 | eca8f888 | blueswir1 | { |
1428 | eca8f888 | blueswir1 | long rtvalue = (insn & RT_MASK) >> 21; |
1429 | eca8f888 | blueswir1 | |
1430 | eca8f888 | blueswir1 | if (value == rtvalue)
|
1431 | eca8f888 | blueswir1 | *errmsg = _("source and target register operands must be different");
|
1432 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16); |
1433 | b9adb4a6 | bellard | } |
1434 | b9adb4a6 | bellard | |
1435 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
1436 | b9adb4a6 | bellard | store or an updating floating point load, which means that the RA
|
1437 | b9adb4a6 | bellard | field may not be zero. */
|
1438 | b9adb4a6 | bellard | |
1439 | b9adb4a6 | bellard | static unsigned long |
1440 | eca8f888 | blueswir1 | insert_ras (unsigned long insn, |
1441 | eca8f888 | blueswir1 | long value,
|
1442 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1443 | eca8f888 | blueswir1 | const char **errmsg) |
1444 | b9adb4a6 | bellard | { |
1445 | b9adb4a6 | bellard | if (value == 0) |
1446 | eca8f888 | blueswir1 | *errmsg = _("invalid register operand when updating");
|
1447 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16); |
1448 | b9adb4a6 | bellard | } |
1449 | b9adb4a6 | bellard | |
1450 | b9adb4a6 | bellard | /* The RB field in an X form instruction when it must be the same as
|
1451 | b9adb4a6 | bellard | the RS field in the instruction. This is used for extended
|
1452 | b9adb4a6 | bellard | mnemonics like mr. This operand is marked FAKE. The insertion
|
1453 | b9adb4a6 | bellard | function just copies the BT field into the BA field, and the
|
1454 | b9adb4a6 | bellard | extraction function just checks that the fields are the same. */
|
1455 | b9adb4a6 | bellard | |
1456 | 5fafdf24 | ths | static unsigned long |
1457 | eca8f888 | blueswir1 | insert_rbs (unsigned long insn, |
1458 | eca8f888 | blueswir1 | long value ATTRIBUTE_UNUSED,
|
1459 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1460 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1461 | b9adb4a6 | bellard | { |
1462 | b9adb4a6 | bellard | return insn | (((insn >> 21) & 0x1f) << 11); |
1463 | b9adb4a6 | bellard | } |
1464 | b9adb4a6 | bellard | |
1465 | b9adb4a6 | bellard | static long |
1466 | eca8f888 | blueswir1 | extract_rbs (unsigned long insn, |
1467 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1468 | eca8f888 | blueswir1 | int *invalid)
|
1469 | b9adb4a6 | bellard | { |
1470 | eca8f888 | blueswir1 | if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
1471 | b9adb4a6 | bellard | *invalid = 1;
|
1472 | b9adb4a6 | bellard | return 0; |
1473 | b9adb4a6 | bellard | } |
1474 | b9adb4a6 | bellard | |
1475 | b9adb4a6 | bellard | /* The SH field in an MD form instruction. This is split. */
|
1476 | b9adb4a6 | bellard | |
1477 | b9adb4a6 | bellard | static unsigned long |
1478 | eca8f888 | blueswir1 | insert_sh6 (unsigned long insn, |
1479 | eca8f888 | blueswir1 | long value,
|
1480 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1481 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1482 | b9adb4a6 | bellard | { |
1483 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
1484 | b9adb4a6 | bellard | } |
1485 | b9adb4a6 | bellard | |
1486 | b9adb4a6 | bellard | static long |
1487 | eca8f888 | blueswir1 | extract_sh6 (unsigned long insn, |
1488 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1489 | eca8f888 | blueswir1 | int *invalid ATTRIBUTE_UNUSED)
|
1490 | b9adb4a6 | bellard | { |
1491 | b9adb4a6 | bellard | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
1492 | b9adb4a6 | bellard | } |
1493 | b9adb4a6 | bellard | |
1494 | b9adb4a6 | bellard | /* The SPR field in an XFX form instruction. This is flipped--the
|
1495 | b9adb4a6 | bellard | lower 5 bits are stored in the upper 5 and vice- versa. */
|
1496 | b9adb4a6 | bellard | |
1497 | b9adb4a6 | bellard | static unsigned long |
1498 | eca8f888 | blueswir1 | insert_spr (unsigned long insn, |
1499 | eca8f888 | blueswir1 | long value,
|
1500 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1501 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1502 | b9adb4a6 | bellard | { |
1503 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1504 | b9adb4a6 | bellard | } |
1505 | b9adb4a6 | bellard | |
1506 | b9adb4a6 | bellard | static long |
1507 | eca8f888 | blueswir1 | extract_spr (unsigned long insn, |
1508 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1509 | eca8f888 | blueswir1 | int *invalid ATTRIBUTE_UNUSED)
|
1510 | b9adb4a6 | bellard | { |
1511 | b9adb4a6 | bellard | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
1512 | b9adb4a6 | bellard | } |
1513 | b9adb4a6 | bellard | |
1514 | eca8f888 | blueswir1 | /* Some dialects have 8 SPRG registers instead of the standard 4. */
|
1515 | eca8f888 | blueswir1 | |
1516 | eca8f888 | blueswir1 | static unsigned long |
1517 | eca8f888 | blueswir1 | insert_sprg (unsigned long insn, |
1518 | eca8f888 | blueswir1 | long value,
|
1519 | eca8f888 | blueswir1 | int dialect,
|
1520 | eca8f888 | blueswir1 | const char **errmsg) |
1521 | eca8f888 | blueswir1 | { |
1522 | eca8f888 | blueswir1 | /* This check uses PPC_OPCODE_403 because PPC405 is later defined
|
1523 | eca8f888 | blueswir1 | as a synonym. If ever a 405 specific dialect is added this
|
1524 | eca8f888 | blueswir1 | check should use that instead. */
|
1525 | eca8f888 | blueswir1 | if (value > 7 |
1526 | eca8f888 | blueswir1 | || (value > 3
|
1527 | eca8f888 | blueswir1 | && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
|
1528 | eca8f888 | blueswir1 | *errmsg = _("invalid sprg number");
|
1529 | eca8f888 | blueswir1 | |
1530 | eca8f888 | blueswir1 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in
|
1531 | eca8f888 | blueswir1 | user mode. Anything else must use spr 272..279. */
|
1532 | eca8f888 | blueswir1 | if (value <= 3 || (insn & 0x100) != 0) |
1533 | eca8f888 | blueswir1 | value |= 0x10;
|
1534 | eca8f888 | blueswir1 | |
1535 | eca8f888 | blueswir1 | return insn | ((value & 0x17) << 16); |
1536 | eca8f888 | blueswir1 | } |
1537 | eca8f888 | blueswir1 | |
1538 | eca8f888 | blueswir1 | static long |
1539 | eca8f888 | blueswir1 | extract_sprg (unsigned long insn, |
1540 | eca8f888 | blueswir1 | int dialect,
|
1541 | eca8f888 | blueswir1 | int *invalid)
|
1542 | eca8f888 | blueswir1 | { |
1543 | eca8f888 | blueswir1 | unsigned long val = (insn >> 16) & 0x1f; |
1544 | eca8f888 | blueswir1 | |
1545 | eca8f888 | blueswir1 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
|
1546 | eca8f888 | blueswir1 | If not BOOKE or 405, then both use only 272..275. */
|
1547 | eca8f888 | blueswir1 | if (val <= 3 |
1548 | eca8f888 | blueswir1 | || (val < 0x10 && (insn & 0x100) != 0) |
1549 | eca8f888 | blueswir1 | || (val - 0x10 > 3 |
1550 | eca8f888 | blueswir1 | && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
|
1551 | eca8f888 | blueswir1 | *invalid = 1;
|
1552 | eca8f888 | blueswir1 | return val & 7; |
1553 | eca8f888 | blueswir1 | } |
1554 | eca8f888 | blueswir1 | |
1555 | b9adb4a6 | bellard | /* The TBR field in an XFX instruction. This is just like SPR, but it
|
1556 | b9adb4a6 | bellard | is optional. When TBR is omitted, it must be inserted as 268 (the
|
1557 | b9adb4a6 | bellard | magic number of the TB register). These functions treat 0
|
1558 | b9adb4a6 | bellard | (indicating an omitted optional operand) as 268. This means that
|
1559 | b9adb4a6 | bellard | ``mftb 4,0'' is not handled correctly. This does not matter very
|
1560 | b9adb4a6 | bellard | much, since the architecture manual does not define mftb as
|
1561 | b9adb4a6 | bellard | accepting any values other than 268 or 269. */
|
1562 | b9adb4a6 | bellard | |
1563 | b9adb4a6 | bellard | #define TB (268) |
1564 | b9adb4a6 | bellard | |
1565 | b9adb4a6 | bellard | static unsigned long |
1566 | eca8f888 | blueswir1 | insert_tbr (unsigned long insn, |
1567 | eca8f888 | blueswir1 | long value,
|
1568 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1569 | eca8f888 | blueswir1 | const char **errmsg ATTRIBUTE_UNUSED) |
1570 | b9adb4a6 | bellard | { |
1571 | b9adb4a6 | bellard | if (value == 0) |
1572 | b9adb4a6 | bellard | value = TB; |
1573 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1574 | b9adb4a6 | bellard | } |
1575 | b9adb4a6 | bellard | |
1576 | b9adb4a6 | bellard | static long |
1577 | eca8f888 | blueswir1 | extract_tbr (unsigned long insn, |
1578 | eca8f888 | blueswir1 | int dialect ATTRIBUTE_UNUSED,
|
1579 | eca8f888 | blueswir1 | int *invalid ATTRIBUTE_UNUSED)
|
1580 | b9adb4a6 | bellard | { |
1581 | b9adb4a6 | bellard | long ret;
|
1582 | b9adb4a6 | bellard | |
1583 | b9adb4a6 | bellard | ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
1584 | b9adb4a6 | bellard | if (ret == TB)
|
1585 | b9adb4a6 | bellard | ret = 0;
|
1586 | b9adb4a6 | bellard | return ret;
|
1587 | b9adb4a6 | bellard | } |
1588 | b9adb4a6 | bellard | |
1589 | b9adb4a6 | bellard | /* Macros used to form opcodes. */
|
1590 | b9adb4a6 | bellard | |
1591 | b9adb4a6 | bellard | /* The main opcode. */
|
1592 | eca8f888 | blueswir1 | #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) |
1593 | b9adb4a6 | bellard | #define OP_MASK OP (0x3f) |
1594 | b9adb4a6 | bellard | |
1595 | b9adb4a6 | bellard | /* The main opcode combined with a trap code in the TO field of a D
|
1596 | b9adb4a6 | bellard | form instruction. Used for extended mnemonics for the trap
|
1597 | b9adb4a6 | bellard | instructions. */
|
1598 | eca8f888 | blueswir1 | #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) |
1599 | b9adb4a6 | bellard | #define OPTO_MASK (OP_MASK | TO_MASK)
|
1600 | b9adb4a6 | bellard | |
1601 | b9adb4a6 | bellard | /* The main opcode combined with a comparison size bit in the L field
|
1602 | b9adb4a6 | bellard | of a D form or X form instruction. Used for extended mnemonics for
|
1603 | b9adb4a6 | bellard | the comparison instructions. */
|
1604 | eca8f888 | blueswir1 | #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) |
1605 | b9adb4a6 | bellard | #define OPL_MASK OPL (0x3f,1) |
1606 | b9adb4a6 | bellard | |
1607 | b9adb4a6 | bellard | /* An A form instruction. */
|
1608 | eca8f888 | blueswir1 | #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) |
1609 | b9adb4a6 | bellard | #define A_MASK A (0x3f, 0x1f, 1) |
1610 | b9adb4a6 | bellard | |
1611 | b9adb4a6 | bellard | /* An A_MASK with the FRB field fixed. */
|
1612 | b9adb4a6 | bellard | #define AFRB_MASK (A_MASK | FRB_MASK)
|
1613 | b9adb4a6 | bellard | |
1614 | b9adb4a6 | bellard | /* An A_MASK with the FRC field fixed. */
|
1615 | b9adb4a6 | bellard | #define AFRC_MASK (A_MASK | FRC_MASK)
|
1616 | b9adb4a6 | bellard | |
1617 | b9adb4a6 | bellard | /* An A_MASK with the FRA and FRC fields fixed. */
|
1618 | b9adb4a6 | bellard | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
|
1619 | b9adb4a6 | bellard | |
1620 | ee8ae9e4 | blueswir1 | /* An AFRAFRC_MASK, but with L bit clear. */
|
1621 | ee8ae9e4 | blueswir1 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) |
1622 | ee8ae9e4 | blueswir1 | |
1623 | b9adb4a6 | bellard | /* A B form instruction. */
|
1624 | eca8f888 | blueswir1 | #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) |
1625 | b9adb4a6 | bellard | #define B_MASK B (0x3f, 1, 1) |
1626 | b9adb4a6 | bellard | |
1627 | b9adb4a6 | bellard | /* A B form instruction setting the BO field. */
|
1628 | eca8f888 | blueswir1 | #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
1629 | b9adb4a6 | bellard | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
1630 | b9adb4a6 | bellard | |
1631 | b9adb4a6 | bellard | /* A BBO_MASK with the y bit of the BO field removed. This permits
|
1632 | b9adb4a6 | bellard | matching a conditional branch regardless of the setting of the y
|
1633 | eca8f888 | blueswir1 | bit. Similarly for the 'at' bits used for power4 branch hints. */
|
1634 | eca8f888 | blueswir1 | #define Y_MASK (((unsigned long) 1) << 21) |
1635 | eca8f888 | blueswir1 | #define AT1_MASK (((unsigned long) 3) << 21) |
1636 | eca8f888 | blueswir1 | #define AT2_MASK (((unsigned long) 9) << 21) |
1637 | eca8f888 | blueswir1 | #define BBOY_MASK (BBO_MASK &~ Y_MASK)
|
1638 | eca8f888 | blueswir1 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
|
1639 | b9adb4a6 | bellard | |
1640 | b9adb4a6 | bellard | /* A B form instruction setting the BO field and the condition bits of
|
1641 | b9adb4a6 | bellard | the BI field. */
|
1642 | b9adb4a6 | bellard | #define BBOCB(op, bo, cb, aa, lk) \
|
1643 | eca8f888 | blueswir1 | (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) |
1644 | b9adb4a6 | bellard | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
1645 | b9adb4a6 | bellard | |
1646 | b9adb4a6 | bellard | /* A BBOCB_MASK with the y bit of the BO field removed. */
|
1647 | b9adb4a6 | bellard | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
|
1648 | eca8f888 | blueswir1 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
|
1649 | eca8f888 | blueswir1 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
|
1650 | b9adb4a6 | bellard | |
1651 | b9adb4a6 | bellard | /* A BBOYCB_MASK in which the BI field is fixed. */
|
1652 | b9adb4a6 | bellard | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
|
1653 | eca8f888 | blueswir1 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
|
1654 | eca8f888 | blueswir1 | |
1655 | eca8f888 | blueswir1 | /* An Context form instruction. */
|
1656 | eca8f888 | blueswir1 | #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) |
1657 | eca8f888 | blueswir1 | #define CTX_MASK CTX(0x3f, 0x7) |
1658 | eca8f888 | blueswir1 | |
1659 | eca8f888 | blueswir1 | /* An User Context form instruction. */
|
1660 | eca8f888 | blueswir1 | #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
1661 | eca8f888 | blueswir1 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
1662 | b9adb4a6 | bellard | |
1663 | b9adb4a6 | bellard | /* The main opcode mask with the RA field clear. */
|
1664 | b9adb4a6 | bellard | #define DRA_MASK (OP_MASK | RA_MASK)
|
1665 | b9adb4a6 | bellard | |
1666 | b9adb4a6 | bellard | /* A DS form instruction. */
|
1667 | b9adb4a6 | bellard | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
1668 | b9adb4a6 | bellard | #define DS_MASK DSO (0x3f, 3) |
1669 | b9adb4a6 | bellard | |
1670 | eca8f888 | blueswir1 | /* A DE form instruction. */
|
1671 | eca8f888 | blueswir1 | #define DEO(op, xop) (OP (op) | ((xop) & 0xf)) |
1672 | eca8f888 | blueswir1 | #define DE_MASK DEO (0x3e, 0xf) |
1673 | eca8f888 | blueswir1 | |
1674 | eca8f888 | blueswir1 | /* An EVSEL form instruction. */
|
1675 | eca8f888 | blueswir1 | #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) |
1676 | eca8f888 | blueswir1 | #define EVSEL_MASK EVSEL(0x3f, 0xff) |
1677 | eca8f888 | blueswir1 | |
1678 | b9adb4a6 | bellard | /* An M form instruction. */
|
1679 | b9adb4a6 | bellard | #define M(op, rc) (OP (op) | ((rc) & 1)) |
1680 | b9adb4a6 | bellard | #define M_MASK M (0x3f, 1) |
1681 | b9adb4a6 | bellard | |
1682 | b9adb4a6 | bellard | /* An M form instruction with the ME field specified. */
|
1683 | eca8f888 | blueswir1 | #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) |
1684 | b9adb4a6 | bellard | |
1685 | b9adb4a6 | bellard | /* An M_MASK with the MB and ME fields fixed. */
|
1686 | b9adb4a6 | bellard | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
|
1687 | b9adb4a6 | bellard | |
1688 | b9adb4a6 | bellard | /* An M_MASK with the SH and ME fields fixed. */
|
1689 | b9adb4a6 | bellard | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
|
1690 | b9adb4a6 | bellard | |
1691 | b9adb4a6 | bellard | /* An MD form instruction. */
|
1692 | eca8f888 | blueswir1 | #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) |
1693 | b9adb4a6 | bellard | #define MD_MASK MD (0x3f, 0x7, 1) |
1694 | b9adb4a6 | bellard | |
1695 | b9adb4a6 | bellard | /* An MD_MASK with the MB field fixed. */
|
1696 | b9adb4a6 | bellard | #define MDMB_MASK (MD_MASK | MB6_MASK)
|
1697 | b9adb4a6 | bellard | |
1698 | b9adb4a6 | bellard | /* An MD_MASK with the SH field fixed. */
|
1699 | b9adb4a6 | bellard | #define MDSH_MASK (MD_MASK | SH6_MASK)
|
1700 | b9adb4a6 | bellard | |
1701 | b9adb4a6 | bellard | /* An MDS form instruction. */
|
1702 | eca8f888 | blueswir1 | #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) |
1703 | b9adb4a6 | bellard | #define MDS_MASK MDS (0x3f, 0xf, 1) |
1704 | b9adb4a6 | bellard | |
1705 | b9adb4a6 | bellard | /* An MDS_MASK with the MB field fixed. */
|
1706 | b9adb4a6 | bellard | #define MDSMB_MASK (MDS_MASK | MB6_MASK)
|
1707 | b9adb4a6 | bellard | |
1708 | b9adb4a6 | bellard | /* An SC form instruction. */
|
1709 | eca8f888 | blueswir1 | #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) |
1710 | eca8f888 | blueswir1 | #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) |
1711 | eca8f888 | blueswir1 | |
1712 | eca8f888 | blueswir1 | /* An VX form instruction. */
|
1713 | eca8f888 | blueswir1 | #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
1714 | eca8f888 | blueswir1 | |
1715 | eca8f888 | blueswir1 | /* The mask for an VX form instruction. */
|
1716 | eca8f888 | blueswir1 | #define VX_MASK VX(0x3f, 0x7ff) |
1717 | eca8f888 | blueswir1 | |
1718 | eca8f888 | blueswir1 | /* An VA form instruction. */
|
1719 | eca8f888 | blueswir1 | #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) |
1720 | eca8f888 | blueswir1 | |
1721 | eca8f888 | blueswir1 | /* The mask for an VA form instruction. */
|
1722 | eca8f888 | blueswir1 | #define VXA_MASK VXA(0x3f, 0x3f) |
1723 | eca8f888 | blueswir1 | |
1724 | eca8f888 | blueswir1 | /* An VXR form instruction. */
|
1725 | eca8f888 | blueswir1 | #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
1726 | eca8f888 | blueswir1 | |
1727 | eca8f888 | blueswir1 | /* The mask for a VXR form instruction. */
|
1728 | eca8f888 | blueswir1 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
1729 | b9adb4a6 | bellard | |
1730 | b9adb4a6 | bellard | /* An X form instruction. */
|
1731 | eca8f888 | blueswir1 | #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
1732 | b9adb4a6 | bellard | |
1733 | ee8ae9e4 | blueswir1 | /* A Z form instruction. */
|
1734 | ee8ae9e4 | blueswir1 | #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) |
1735 | ee8ae9e4 | blueswir1 | |
1736 | b9adb4a6 | bellard | /* An X form instruction with the RC bit specified. */
|
1737 | b9adb4a6 | bellard | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) |
1738 | b9adb4a6 | bellard | |
1739 | ee8ae9e4 | blueswir1 | /* A Z form instruction with the RC bit specified. */
|
1740 | ee8ae9e4 | blueswir1 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) |
1741 | ee8ae9e4 | blueswir1 | |
1742 | b9adb4a6 | bellard | /* The mask for an X form instruction. */
|
1743 | b9adb4a6 | bellard | #define X_MASK XRC (0x3f, 0x3ff, 1) |
1744 | b9adb4a6 | bellard | |
1745 | ee8ae9e4 | blueswir1 | /* The mask for a Z form instruction. */
|
1746 | ee8ae9e4 | blueswir1 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) |
1747 | ee8ae9e4 | blueswir1 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
1748 | ee8ae9e4 | blueswir1 | |
1749 | b9adb4a6 | bellard | /* An X_MASK with the RA field fixed. */
|
1750 | b9adb4a6 | bellard | #define XRA_MASK (X_MASK | RA_MASK)
|
1751 | b9adb4a6 | bellard | |
1752 | ee8ae9e4 | blueswir1 | /* An XRA_MASK with the W field clear. */
|
1753 | ee8ae9e4 | blueswir1 | #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) |
1754 | ee8ae9e4 | blueswir1 | |
1755 | b9adb4a6 | bellard | /* An X_MASK with the RB field fixed. */
|
1756 | b9adb4a6 | bellard | #define XRB_MASK (X_MASK | RB_MASK)
|
1757 | b9adb4a6 | bellard | |
1758 | b9adb4a6 | bellard | /* An X_MASK with the RT field fixed. */
|
1759 | b9adb4a6 | bellard | #define XRT_MASK (X_MASK | RT_MASK)
|
1760 | b9adb4a6 | bellard | |
1761 | ee8ae9e4 | blueswir1 | /* An XRT_MASK mask with the L bits clear. */
|
1762 | ee8ae9e4 | blueswir1 | #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) |
1763 | ee8ae9e4 | blueswir1 | |
1764 | b9adb4a6 | bellard | /* An X_MASK with the RA and RB fields fixed. */
|
1765 | b9adb4a6 | bellard | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
|
1766 | b9adb4a6 | bellard | |
1767 | eca8f888 | blueswir1 | /* An XRARB_MASK, but with the L bit clear. */
|
1768 | eca8f888 | blueswir1 | #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) |
1769 | eca8f888 | blueswir1 | |
1770 | b9adb4a6 | bellard | /* An X_MASK with the RT and RA fields fixed. */
|
1771 | b9adb4a6 | bellard | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
|
1772 | b9adb4a6 | bellard | |
1773 | eca8f888 | blueswir1 | /* An XRTRA_MASK, but with L bit clear. */
|
1774 | eca8f888 | blueswir1 | #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) |
1775 | eca8f888 | blueswir1 | |
1776 | eca8f888 | blueswir1 | /* An X form instruction with the L bit specified. */
|
1777 | eca8f888 | blueswir1 | #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) |
1778 | b9adb4a6 | bellard | |
1779 | b9adb4a6 | bellard | /* The mask for an X form comparison instruction. */
|
1780 | eca8f888 | blueswir1 | #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) |
1781 | b9adb4a6 | bellard | |
1782 | b9adb4a6 | bellard | /* The mask for an X form comparison instruction with the L field
|
1783 | b9adb4a6 | bellard | fixed. */
|
1784 | eca8f888 | blueswir1 | #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) |
1785 | b9adb4a6 | bellard | |
1786 | b9adb4a6 | bellard | /* An X form trap instruction with the TO field specified. */
|
1787 | eca8f888 | blueswir1 | #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) |
1788 | b9adb4a6 | bellard | #define XTO_MASK (X_MASK | TO_MASK)
|
1789 | b9adb4a6 | bellard | |
1790 | eca8f888 | blueswir1 | /* An X form tlb instruction with the SH field specified. */
|
1791 | eca8f888 | blueswir1 | #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) |
1792 | eca8f888 | blueswir1 | #define XTLB_MASK (X_MASK | SH_MASK)
|
1793 | eca8f888 | blueswir1 | |
1794 | eca8f888 | blueswir1 | /* An X form sync instruction. */
|
1795 | eca8f888 | blueswir1 | #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
1796 | eca8f888 | blueswir1 | |
1797 | eca8f888 | blueswir1 | /* An X form sync instruction with everything filled in except the LS field. */
|
1798 | eca8f888 | blueswir1 | #define XSYNC_MASK (0xff9fffff) |
1799 | eca8f888 | blueswir1 | |
1800 | ee8ae9e4 | blueswir1 | /* An X_MASK, but with the EH bit clear. */
|
1801 | ee8ae9e4 | blueswir1 | #define XEH_MASK (X_MASK & ~((unsigned long )1)) |
1802 | ee8ae9e4 | blueswir1 | |
1803 | eca8f888 | blueswir1 | /* An X form AltiVec dss instruction. */
|
1804 | eca8f888 | blueswir1 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) |
1805 | eca8f888 | blueswir1 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
1806 | eca8f888 | blueswir1 | |
1807 | b9adb4a6 | bellard | /* An XFL form instruction. */
|
1808 | eca8f888 | blueswir1 | #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) |
1809 | ee8ae9e4 | blueswir1 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
1810 | eca8f888 | blueswir1 | |
1811 | eca8f888 | blueswir1 | /* An X form isel instruction. */
|
1812 | eca8f888 | blueswir1 | #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
1813 | eca8f888 | blueswir1 | #define XISEL_MASK XISEL(0x3f, 0x1f) |
1814 | b9adb4a6 | bellard | |
1815 | b9adb4a6 | bellard | /* An XL form instruction with the LK field set to 0. */
|
1816 | eca8f888 | blueswir1 | #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
1817 | b9adb4a6 | bellard | |
1818 | b9adb4a6 | bellard | /* An XL form instruction which uses the LK field. */
|
1819 | b9adb4a6 | bellard | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) |
1820 | b9adb4a6 | bellard | |
1821 | b9adb4a6 | bellard | /* The mask for an XL form instruction. */
|
1822 | b9adb4a6 | bellard | #define XL_MASK XLLK (0x3f, 0x3ff, 1) |
1823 | b9adb4a6 | bellard | |
1824 | b9adb4a6 | bellard | /* An XL form instruction which explicitly sets the BO field. */
|
1825 | b9adb4a6 | bellard | #define XLO(op, bo, xop, lk) \
|
1826 | eca8f888 | blueswir1 | (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
1827 | b9adb4a6 | bellard | #define XLO_MASK (XL_MASK | BO_MASK)
|
1828 | b9adb4a6 | bellard | |
1829 | b9adb4a6 | bellard | /* An XL form instruction which explicitly sets the y bit of the BO
|
1830 | b9adb4a6 | bellard | field. */
|
1831 | eca8f888 | blueswir1 | #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) |
1832 | b9adb4a6 | bellard | #define XLYLK_MASK (XL_MASK | Y_MASK)
|
1833 | b9adb4a6 | bellard | |
1834 | b9adb4a6 | bellard | /* An XL form instruction which sets the BO field and the condition
|
1835 | b9adb4a6 | bellard | bits of the BI field. */
|
1836 | b9adb4a6 | bellard | #define XLOCB(op, bo, cb, xop, lk) \
|
1837 | eca8f888 | blueswir1 | (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) |
1838 | b9adb4a6 | bellard | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
1839 | b9adb4a6 | bellard | |
1840 | b9adb4a6 | bellard | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
|
1841 | b9adb4a6 | bellard | #define XLBB_MASK (XL_MASK | BB_MASK)
|
1842 | b9adb4a6 | bellard | #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
|
1843 | b9adb4a6 | bellard | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
|
1844 | b9adb4a6 | bellard | |
1845 | eca8f888 | blueswir1 | /* A mask for branch instructions using the BH field. */
|
1846 | eca8f888 | blueswir1 | #define XLBH_MASK (XL_MASK | (0x1c << 11)) |
1847 | eca8f888 | blueswir1 | |
1848 | b9adb4a6 | bellard | /* An XL_MASK with the BO and BB fields fixed. */
|
1849 | b9adb4a6 | bellard | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
|
1850 | b9adb4a6 | bellard | |
1851 | b9adb4a6 | bellard | /* An XL_MASK with the BO, BI and BB fields fixed. */
|
1852 | b9adb4a6 | bellard | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
|
1853 | b9adb4a6 | bellard | |
1854 | b9adb4a6 | bellard | /* An XO form instruction. */
|
1855 | b9adb4a6 | bellard | #define XO(op, xop, oe, rc) \
|
1856 | eca8f888 | blueswir1 | (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) |
1857 | b9adb4a6 | bellard | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
1858 | b9adb4a6 | bellard | |
1859 | b9adb4a6 | bellard | /* An XO_MASK with the RB field fixed. */
|
1860 | b9adb4a6 | bellard | #define XORB_MASK (XO_MASK | RB_MASK)
|
1861 | b9adb4a6 | bellard | |
1862 | b9adb4a6 | bellard | /* An XS form instruction. */
|
1863 | eca8f888 | blueswir1 | #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) |
1864 | b9adb4a6 | bellard | #define XS_MASK XS (0x3f, 0x1ff, 1) |
1865 | b9adb4a6 | bellard | |
1866 | b9adb4a6 | bellard | /* A mask for the FXM version of an XFX form instruction. */
|
1867 | eca8f888 | blueswir1 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
1868 | b9adb4a6 | bellard | |
1869 | b9adb4a6 | bellard | /* An XFX form instruction with the FXM field filled in. */
|
1870 | eca8f888 | blueswir1 | #define XFXM(op, xop, fxm, p4) \
|
1871 | eca8f888 | blueswir1 | (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ |
1872 | eca8f888 | blueswir1 | | ((unsigned long)(p4) << 20)) |
1873 | b9adb4a6 | bellard | |
1874 | b9adb4a6 | bellard | /* An XFX form instruction with the SPR field filled in. */
|
1875 | b9adb4a6 | bellard | #define XSPR(op, xop, spr) \
|
1876 | eca8f888 | blueswir1 | (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) |
1877 | b9adb4a6 | bellard | #define XSPR_MASK (X_MASK | SPR_MASK)
|
1878 | b9adb4a6 | bellard | |
1879 | b9adb4a6 | bellard | /* An XFX form instruction with the SPR field filled in except for the
|
1880 | b9adb4a6 | bellard | SPRBAT field. */
|
1881 | b9adb4a6 | bellard | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
|
1882 | b9adb4a6 | bellard | |
1883 | b9adb4a6 | bellard | /* An XFX form instruction with the SPR field filled in except for the
|
1884 | b9adb4a6 | bellard | SPRG field. */
|
1885 | ee8ae9e4 | blueswir1 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
1886 | eca8f888 | blueswir1 | |
1887 | eca8f888 | blueswir1 | /* An X form instruction with everything filled in except the E field. */
|
1888 | eca8f888 | blueswir1 | #define XE_MASK (0xffff7fff) |
1889 | eca8f888 | blueswir1 | |
1890 | eca8f888 | blueswir1 | /* An X form user context instruction. */
|
1891 | eca8f888 | blueswir1 | #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
1892 | eca8f888 | blueswir1 | #define XUC_MASK XUC(0x3f, 0x1f) |
1893 | b9adb4a6 | bellard | |
1894 | b9adb4a6 | bellard | /* The BO encodings used in extended conditional branch mnemonics. */
|
1895 | b9adb4a6 | bellard | #define BODNZF (0x0) |
1896 | b9adb4a6 | bellard | #define BODNZFP (0x1) |
1897 | b9adb4a6 | bellard | #define BODZF (0x2) |
1898 | b9adb4a6 | bellard | #define BODZFP (0x3) |
1899 | b9adb4a6 | bellard | #define BODNZT (0x8) |
1900 | b9adb4a6 | bellard | #define BODNZTP (0x9) |
1901 | b9adb4a6 | bellard | #define BODZT (0xa) |
1902 | b9adb4a6 | bellard | #define BODZTP (0xb) |
1903 | eca8f888 | blueswir1 | |
1904 | eca8f888 | blueswir1 | #define BOF (0x4) |
1905 | eca8f888 | blueswir1 | #define BOFP (0x5) |
1906 | eca8f888 | blueswir1 | #define BOFM4 (0x6) |
1907 | eca8f888 | blueswir1 | #define BOFP4 (0x7) |
1908 | b9adb4a6 | bellard | #define BOT (0xc) |
1909 | b9adb4a6 | bellard | #define BOTP (0xd) |
1910 | eca8f888 | blueswir1 | #define BOTM4 (0xe) |
1911 | eca8f888 | blueswir1 | #define BOTP4 (0xf) |
1912 | eca8f888 | blueswir1 | |
1913 | b9adb4a6 | bellard | #define BODNZ (0x10) |
1914 | b9adb4a6 | bellard | #define BODNZP (0x11) |
1915 | b9adb4a6 | bellard | #define BODZ (0x12) |
1916 | b9adb4a6 | bellard | #define BODZP (0x13) |
1917 | eca8f888 | blueswir1 | #define BODNZM4 (0x18) |
1918 | eca8f888 | blueswir1 | #define BODNZP4 (0x19) |
1919 | eca8f888 | blueswir1 | #define BODZM4 (0x1a) |
1920 | eca8f888 | blueswir1 | #define BODZP4 (0x1b) |
1921 | eca8f888 | blueswir1 | |
1922 | b9adb4a6 | bellard | #define BOU (0x14) |
1923 | b9adb4a6 | bellard | |
1924 | b9adb4a6 | bellard | /* The BI condition bit encodings used in extended conditional branch
|
1925 | b9adb4a6 | bellard | mnemonics. */
|
1926 | b9adb4a6 | bellard | #define CBLT (0) |
1927 | b9adb4a6 | bellard | #define CBGT (1) |
1928 | b9adb4a6 | bellard | #define CBEQ (2) |
1929 | b9adb4a6 | bellard | #define CBSO (3) |
1930 | b9adb4a6 | bellard | |
1931 | b9adb4a6 | bellard | /* The TO encodings used in extended trap mnemonics. */
|
1932 | b9adb4a6 | bellard | #define TOLGT (0x1) |
1933 | b9adb4a6 | bellard | #define TOLLT (0x2) |
1934 | b9adb4a6 | bellard | #define TOEQ (0x4) |
1935 | b9adb4a6 | bellard | #define TOLGE (0x5) |
1936 | b9adb4a6 | bellard | #define TOLNL (0x5) |
1937 | b9adb4a6 | bellard | #define TOLLE (0x6) |
1938 | b9adb4a6 | bellard | #define TOLNG (0x6) |
1939 | b9adb4a6 | bellard | #define TOGT (0x8) |
1940 | b9adb4a6 | bellard | #define TOGE (0xc) |
1941 | b9adb4a6 | bellard | #define TONL (0xc) |
1942 | b9adb4a6 | bellard | #define TOLT (0x10) |
1943 | b9adb4a6 | bellard | #define TOLE (0x14) |
1944 | b9adb4a6 | bellard | #define TONG (0x14) |
1945 | b9adb4a6 | bellard | #define TONE (0x18) |
1946 | b9adb4a6 | bellard | #define TOU (0x1f) |
1947 | b9adb4a6 | bellard | |
1948 | b9adb4a6 | bellard | /* Smaller names for the flags so each entry in the opcodes table will
|
1949 | b9adb4a6 | bellard | fit on a single line. */
|
1950 | eca8f888 | blueswir1 | #undef PPC
|
1951 | eca8f888 | blueswir1 | #define PPC PPC_OPCODE_PPC
|
1952 | eca8f888 | blueswir1 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
|
1953 | eca8f888 | blueswir1 | #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
|
1954 | eca8f888 | blueswir1 | #define POWER4 PPC_OPCODE_POWER4
|
1955 | eca8f888 | blueswir1 | #define POWER5 PPC_OPCODE_POWER5
|
1956 | ee8ae9e4 | blueswir1 | #define POWER6 PPC_OPCODE_POWER6
|
1957 | ee8ae9e4 | blueswir1 | #define CELL PPC_OPCODE_CELL
|
1958 | eca8f888 | blueswir1 | #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
|
1959 | eca8f888 | blueswir1 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
|
1960 | eca8f888 | blueswir1 | #define PPC403 PPC_OPCODE_403
|
1961 | eca8f888 | blueswir1 | #define PPC405 PPC403
|
1962 | eca8f888 | blueswir1 | #define PPC440 PPC_OPCODE_440
|
1963 | eca8f888 | blueswir1 | #define PPC750 PPC
|
1964 | eca8f888 | blueswir1 | #define PPC860 PPC
|
1965 | eca8f888 | blueswir1 | #define PPCVEC PPC_OPCODE_ALTIVEC
|
1966 | eca8f888 | blueswir1 | #define POWER PPC_OPCODE_POWER
|
1967 | eca8f888 | blueswir1 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
|
1968 | eca8f888 | blueswir1 | #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
|
1969 | eca8f888 | blueswir1 | #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
|
1970 | eca8f888 | blueswir1 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
|
1971 | eca8f888 | blueswir1 | #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
|
1972 | eca8f888 | blueswir1 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
|
1973 | eca8f888 | blueswir1 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
|
1974 | eca8f888 | blueswir1 | #define MFDEC1 PPC_OPCODE_POWER
|
1975 | eca8f888 | blueswir1 | #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
|
1976 | eca8f888 | blueswir1 | #define BOOKE PPC_OPCODE_BOOKE
|
1977 | eca8f888 | blueswir1 | #define BOOKE64 PPC_OPCODE_BOOKE64
|
1978 | eca8f888 | blueswir1 | #define CLASSIC PPC_OPCODE_CLASSIC
|
1979 | eca8f888 | blueswir1 | #define PPCE300 PPC_OPCODE_E300
|
1980 | eca8f888 | blueswir1 | #define PPCSPE PPC_OPCODE_SPE
|
1981 | eca8f888 | blueswir1 | #define PPCISEL PPC_OPCODE_ISEL
|
1982 | eca8f888 | blueswir1 | #define PPCEFS PPC_OPCODE_EFS
|
1983 | eca8f888 | blueswir1 | #define PPCBRLK PPC_OPCODE_BRLOCK
|
1984 | eca8f888 | blueswir1 | #define PPCPMR PPC_OPCODE_PMR
|
1985 | eca8f888 | blueswir1 | #define PPCCHLK PPC_OPCODE_CACHELCK
|
1986 | eca8f888 | blueswir1 | #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
|
1987 | eca8f888 | blueswir1 | #define PPCRFMCI PPC_OPCODE_RFMCI
|
1988 | b9adb4a6 | bellard | |
1989 | b9adb4a6 | bellard | /* The opcode table.
|
1990 | b9adb4a6 | bellard | |
1991 | b9adb4a6 | bellard | The format of the opcode table is:
|
1992 | b9adb4a6 | bellard | |
1993 | b9adb4a6 | bellard | NAME OPCODE MASK FLAGS { OPERANDS }
|
1994 | b9adb4a6 | bellard | |
1995 | b9adb4a6 | bellard | NAME is the name of the instruction.
|
1996 | b9adb4a6 | bellard | OPCODE is the instruction opcode.
|
1997 | b9adb4a6 | bellard | MASK is the opcode mask; this is used to tell the disassembler
|
1998 | b9adb4a6 | bellard | which bits in the actual opcode must match OPCODE.
|
1999 | b9adb4a6 | bellard | FLAGS are flags indicated what processors support the instruction.
|
2000 | b9adb4a6 | bellard | OPERANDS is the list of operands.
|
2001 | b9adb4a6 | bellard | |
2002 | b9adb4a6 | bellard | The disassembler reads the table in order and prints the first
|
2003 | b9adb4a6 | bellard | instruction which matches, so this table is sorted to put more
|
2004 | b9adb4a6 | bellard | specific instructions before more general instructions. It is also
|
2005 | b9adb4a6 | bellard | sorted by major opcode. */
|
2006 | b9adb4a6 | bellard | |
2007 | b9adb4a6 | bellard | const struct powerpc_opcode powerpc_opcodes[] = { |
2008 | eca8f888 | blueswir1 | { "attn", X(0,256), X_MASK, POWER4, { 0 } }, |
2009 | eca8f888 | blueswir1 | { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, |
2010 | eca8f888 | blueswir1 | { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, |
2011 | eca8f888 | blueswir1 | { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, |
2012 | eca8f888 | blueswir1 | { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, |
2013 | eca8f888 | blueswir1 | { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, |
2014 | eca8f888 | blueswir1 | { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, |
2015 | eca8f888 | blueswir1 | { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, |
2016 | eca8f888 | blueswir1 | { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, |
2017 | eca8f888 | blueswir1 | { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, |
2018 | eca8f888 | blueswir1 | { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, |
2019 | eca8f888 | blueswir1 | { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, |
2020 | eca8f888 | blueswir1 | { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, |
2021 | eca8f888 | blueswir1 | { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, |
2022 | eca8f888 | blueswir1 | { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, |
2023 | eca8f888 | blueswir1 | { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, |
2024 | eca8f888 | blueswir1 | |
2025 | eca8f888 | blueswir1 | { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2026 | eca8f888 | blueswir1 | { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2027 | eca8f888 | blueswir1 | { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2028 | eca8f888 | blueswir1 | { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2029 | eca8f888 | blueswir1 | { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, |
2030 | eca8f888 | blueswir1 | { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, |
2031 | eca8f888 | blueswir1 | { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2032 | eca8f888 | blueswir1 | { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2033 | eca8f888 | blueswir1 | { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, |
2034 | eca8f888 | blueswir1 | { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, |
2035 | eca8f888 | blueswir1 | { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2036 | eca8f888 | blueswir1 | { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2037 | eca8f888 | blueswir1 | { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, |
2038 | eca8f888 | blueswir1 | { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, |
2039 | eca8f888 | blueswir1 | { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2040 | eca8f888 | blueswir1 | { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2041 | eca8f888 | blueswir1 | { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2042 | eca8f888 | blueswir1 | { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2043 | eca8f888 | blueswir1 | { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, |
2044 | eca8f888 | blueswir1 | { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, |
2045 | eca8f888 | blueswir1 | { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, |
2046 | eca8f888 | blueswir1 | { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, |
2047 | eca8f888 | blueswir1 | { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2048 | eca8f888 | blueswir1 | { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2049 | eca8f888 | blueswir1 | { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, |
2050 | eca8f888 | blueswir1 | { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, |
2051 | eca8f888 | blueswir1 | { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, |
2052 | eca8f888 | blueswir1 | { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, |
2053 | eca8f888 | blueswir1 | { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, |
2054 | eca8f888 | blueswir1 | { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, |
2055 | eca8f888 | blueswir1 | |
2056 | eca8f888 | blueswir1 | { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2057 | eca8f888 | blueswir1 | { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2058 | eca8f888 | blueswir1 | { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2059 | eca8f888 | blueswir1 | { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2060 | eca8f888 | blueswir1 | { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2061 | eca8f888 | blueswir1 | { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2062 | eca8f888 | blueswir1 | { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2063 | eca8f888 | blueswir1 | { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2064 | eca8f888 | blueswir1 | { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2065 | eca8f888 | blueswir1 | { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2066 | eca8f888 | blueswir1 | { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2067 | eca8f888 | blueswir1 | { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2068 | eca8f888 | blueswir1 | { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2069 | eca8f888 | blueswir1 | { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2070 | eca8f888 | blueswir1 | { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2071 | eca8f888 | blueswir1 | { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2072 | eca8f888 | blueswir1 | { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2073 | eca8f888 | blueswir1 | { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2074 | eca8f888 | blueswir1 | { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2075 | eca8f888 | blueswir1 | { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2076 | eca8f888 | blueswir1 | { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2077 | eca8f888 | blueswir1 | { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2078 | eca8f888 | blueswir1 | { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2079 | eca8f888 | blueswir1 | { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2080 | eca8f888 | blueswir1 | { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2081 | eca8f888 | blueswir1 | { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2082 | eca8f888 | blueswir1 | { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2083 | eca8f888 | blueswir1 | { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2084 | eca8f888 | blueswir1 | { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2085 | eca8f888 | blueswir1 | { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2086 | eca8f888 | blueswir1 | { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2087 | eca8f888 | blueswir1 | { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2088 | eca8f888 | blueswir1 | { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2089 | eca8f888 | blueswir1 | { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2090 | eca8f888 | blueswir1 | { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2091 | eca8f888 | blueswir1 | { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2092 | eca8f888 | blueswir1 | { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2093 | eca8f888 | blueswir1 | { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2094 | eca8f888 | blueswir1 | { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2095 | eca8f888 | blueswir1 | { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2096 | eca8f888 | blueswir1 | { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2097 | eca8f888 | blueswir1 | { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2098 | eca8f888 | blueswir1 | { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2099 | eca8f888 | blueswir1 | { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2100 | eca8f888 | blueswir1 | { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2101 | eca8f888 | blueswir1 | { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2102 | eca8f888 | blueswir1 | { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2103 | eca8f888 | blueswir1 | { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2104 | eca8f888 | blueswir1 | { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2105 | eca8f888 | blueswir1 | { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2106 | eca8f888 | blueswir1 | { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2107 | eca8f888 | blueswir1 | { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2108 | eca8f888 | blueswir1 | { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2109 | eca8f888 | blueswir1 | { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2110 | eca8f888 | blueswir1 | { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2111 | eca8f888 | blueswir1 | { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2112 | eca8f888 | blueswir1 | { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2113 | eca8f888 | blueswir1 | { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2114 | eca8f888 | blueswir1 | { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2115 | eca8f888 | blueswir1 | { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2116 | eca8f888 | blueswir1 | { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2117 | eca8f888 | blueswir1 | { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2118 | eca8f888 | blueswir1 | { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2119 | eca8f888 | blueswir1 | { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2120 | eca8f888 | blueswir1 | { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2121 | eca8f888 | blueswir1 | { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2122 | eca8f888 | blueswir1 | { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2123 | eca8f888 | blueswir1 | { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2124 | eca8f888 | blueswir1 | { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2125 | eca8f888 | blueswir1 | { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2126 | eca8f888 | blueswir1 | { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2127 | eca8f888 | blueswir1 | { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2128 | eca8f888 | blueswir1 | { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2129 | eca8f888 | blueswir1 | { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2130 | eca8f888 | blueswir1 | { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2131 | eca8f888 | blueswir1 | { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2132 | eca8f888 | blueswir1 | { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2133 | eca8f888 | blueswir1 | { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2134 | eca8f888 | blueswir1 | { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2135 | eca8f888 | blueswir1 | { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2136 | eca8f888 | blueswir1 | { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2137 | eca8f888 | blueswir1 | { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2138 | eca8f888 | blueswir1 | { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2139 | eca8f888 | blueswir1 | { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, |
2140 | eca8f888 | blueswir1 | { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, |
2141 | eca8f888 | blueswir1 | { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, |
2142 | eca8f888 | blueswir1 | |
2143 | eca8f888 | blueswir1 | /* Double-precision opcodes. */
|
2144 | eca8f888 | blueswir1 | /* Some of these conflict with AltiVec, so move them before, since
|
2145 | eca8f888 | blueswir1 | PPCVEC includes the PPC_OPCODE_PPC set. */
|
2146 | eca8f888 | blueswir1 | { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, |
2147 | eca8f888 | blueswir1 | { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, |
2148 | eca8f888 | blueswir1 | { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, |
2149 | eca8f888 | blueswir1 | { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, |
2150 | eca8f888 | blueswir1 | { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2151 | eca8f888 | blueswir1 | { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2152 | eca8f888 | blueswir1 | { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2153 | eca8f888 | blueswir1 | { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2154 | eca8f888 | blueswir1 | { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2155 | eca8f888 | blueswir1 | { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2156 | eca8f888 | blueswir1 | { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2157 | eca8f888 | blueswir1 | { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2158 | eca8f888 | blueswir1 | { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2159 | eca8f888 | blueswir1 | { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2160 | eca8f888 | blueswir1 | { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, |
2161 | eca8f888 | blueswir1 | { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, |
2162 | eca8f888 | blueswir1 | { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, |
2163 | eca8f888 | blueswir1 | { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, |
2164 | eca8f888 | blueswir1 | { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, |
2165 | eca8f888 | blueswir1 | { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, |
2166 | eca8f888 | blueswir1 | { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, |
2167 | eca8f888 | blueswir1 | { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, |
2168 | eca8f888 | blueswir1 | { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, |
2169 | eca8f888 | blueswir1 | { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, |
2170 | eca8f888 | blueswir1 | { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, |
2171 | eca8f888 | blueswir1 | { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, |
2172 | eca8f888 | blueswir1 | { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, |
2173 | eca8f888 | blueswir1 | { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, |
2174 | eca8f888 | blueswir1 | { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, |
2175 | eca8f888 | blueswir1 | /* End of double-precision opcodes. */
|
2176 | eca8f888 | blueswir1 | |
2177 | eca8f888 | blueswir1 | { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2178 | eca8f888 | blueswir1 | { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2179 | eca8f888 | blueswir1 | { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2180 | eca8f888 | blueswir1 | { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2181 | eca8f888 | blueswir1 | { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2182 | eca8f888 | blueswir1 | { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2183 | eca8f888 | blueswir1 | { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2184 | eca8f888 | blueswir1 | { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2185 | eca8f888 | blueswir1 | { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2186 | eca8f888 | blueswir1 | { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2187 | eca8f888 | blueswir1 | { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2188 | eca8f888 | blueswir1 | { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2189 | eca8f888 | blueswir1 | { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2190 | eca8f888 | blueswir1 | { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2191 | eca8f888 | blueswir1 | { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2192 | eca8f888 | blueswir1 | { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2193 | eca8f888 | blueswir1 | { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2194 | eca8f888 | blueswir1 | { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2195 | eca8f888 | blueswir1 | { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2196 | eca8f888 | blueswir1 | { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2197 | eca8f888 | blueswir1 | { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2198 | eca8f888 | blueswir1 | { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2199 | eca8f888 | blueswir1 | { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2200 | eca8f888 | blueswir1 | { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2201 | eca8f888 | blueswir1 | { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2202 | eca8f888 | blueswir1 | { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2203 | eca8f888 | blueswir1 | { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2204 | eca8f888 | blueswir1 | { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2205 | eca8f888 | blueswir1 | { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2206 | eca8f888 | blueswir1 | { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2207 | eca8f888 | blueswir1 | { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2208 | eca8f888 | blueswir1 | { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2209 | eca8f888 | blueswir1 | { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2210 | eca8f888 | blueswir1 | { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2211 | eca8f888 | blueswir1 | { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2212 | eca8f888 | blueswir1 | { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2213 | eca8f888 | blueswir1 | { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2214 | eca8f888 | blueswir1 | { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2215 | eca8f888 | blueswir1 | { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2216 | eca8f888 | blueswir1 | { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2217 | eca8f888 | blueswir1 | { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2218 | eca8f888 | blueswir1 | { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2219 | eca8f888 | blueswir1 | { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2220 | eca8f888 | blueswir1 | { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2221 | eca8f888 | blueswir1 | { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2222 | eca8f888 | blueswir1 | { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2223 | eca8f888 | blueswir1 | { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
2224 | eca8f888 | blueswir1 | { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2225 | eca8f888 | blueswir1 | { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2226 | eca8f888 | blueswir1 | { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, |
2227 | eca8f888 | blueswir1 | { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, |
2228 | eca8f888 | blueswir1 | { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, |
2229 | eca8f888 | blueswir1 | { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2230 | eca8f888 | blueswir1 | { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2231 | eca8f888 | blueswir1 | { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2232 | eca8f888 | blueswir1 | { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2233 | eca8f888 | blueswir1 | { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2234 | eca8f888 | blueswir1 | { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2235 | eca8f888 | blueswir1 | { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2236 | eca8f888 | blueswir1 | { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2237 | eca8f888 | blueswir1 | { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2238 | eca8f888 | blueswir1 | { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2239 | eca8f888 | blueswir1 | { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2240 | eca8f888 | blueswir1 | { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2241 | eca8f888 | blueswir1 | { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2242 | eca8f888 | blueswir1 | { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2243 | eca8f888 | blueswir1 | { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2244 | eca8f888 | blueswir1 | { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2245 | eca8f888 | blueswir1 | { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2246 | eca8f888 | blueswir1 | { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2247 | eca8f888 | blueswir1 | { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2248 | eca8f888 | blueswir1 | { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2249 | eca8f888 | blueswir1 | { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2250 | eca8f888 | blueswir1 | { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2251 | eca8f888 | blueswir1 | { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2252 | eca8f888 | blueswir1 | { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2253 | eca8f888 | blueswir1 | { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2254 | eca8f888 | blueswir1 | { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2255 | eca8f888 | blueswir1 | { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2256 | eca8f888 | blueswir1 | { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2257 | eca8f888 | blueswir1 | { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2258 | eca8f888 | blueswir1 | { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2259 | eca8f888 | blueswir1 | { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2260 | eca8f888 | blueswir1 | { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2261 | eca8f888 | blueswir1 | { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2262 | eca8f888 | blueswir1 | { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2263 | eca8f888 | blueswir1 | { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2264 | eca8f888 | blueswir1 | { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2265 | eca8f888 | blueswir1 | { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2266 | eca8f888 | blueswir1 | { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, |
2267 | eca8f888 | blueswir1 | { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2268 | eca8f888 | blueswir1 | { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2269 | eca8f888 | blueswir1 | { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2270 | eca8f888 | blueswir1 | { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2271 | eca8f888 | blueswir1 | { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2272 | eca8f888 | blueswir1 | { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2273 | eca8f888 | blueswir1 | { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2274 | eca8f888 | blueswir1 | { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2275 | eca8f888 | blueswir1 | { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2276 | eca8f888 | blueswir1 | { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2277 | eca8f888 | blueswir1 | { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2278 | eca8f888 | blueswir1 | { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2279 | eca8f888 | blueswir1 | { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, |
2280 | eca8f888 | blueswir1 | { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, |
2281 | eca8f888 | blueswir1 | { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, |
2282 | eca8f888 | blueswir1 | { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, |
2283 | eca8f888 | blueswir1 | { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, |
2284 | eca8f888 | blueswir1 | { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2285 | eca8f888 | blueswir1 | { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2286 | eca8f888 | blueswir1 | { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2287 | eca8f888 | blueswir1 | { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, |
2288 | eca8f888 | blueswir1 | { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
2289 | eca8f888 | blueswir1 | { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2290 | eca8f888 | blueswir1 | { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2291 | eca8f888 | blueswir1 | { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, |
2292 | eca8f888 | blueswir1 | { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2293 | eca8f888 | blueswir1 | { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2294 | eca8f888 | blueswir1 | { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2295 | eca8f888 | blueswir1 | { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2296 | eca8f888 | blueswir1 | { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2297 | eca8f888 | blueswir1 | { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, |
2298 | eca8f888 | blueswir1 | { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, |
2299 | eca8f888 | blueswir1 | { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, |
2300 | eca8f888 | blueswir1 | { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
2301 | eca8f888 | blueswir1 | { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2302 | eca8f888 | blueswir1 | { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2303 | eca8f888 | blueswir1 | { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2304 | eca8f888 | blueswir1 | { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2305 | eca8f888 | blueswir1 | { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2306 | eca8f888 | blueswir1 | { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2307 | eca8f888 | blueswir1 | { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2308 | eca8f888 | blueswir1 | { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2309 | eca8f888 | blueswir1 | { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2310 | eca8f888 | blueswir1 | { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2311 | eca8f888 | blueswir1 | { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2312 | eca8f888 | blueswir1 | { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2313 | eca8f888 | blueswir1 | { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2314 | eca8f888 | blueswir1 | { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2315 | eca8f888 | blueswir1 | { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2316 | eca8f888 | blueswir1 | { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2317 | eca8f888 | blueswir1 | { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2318 | eca8f888 | blueswir1 | { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2319 | eca8f888 | blueswir1 | { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2320 | eca8f888 | blueswir1 | { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2321 | eca8f888 | blueswir1 | { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2322 | eca8f888 | blueswir1 | { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2323 | eca8f888 | blueswir1 | { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2324 | eca8f888 | blueswir1 | { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2325 | eca8f888 | blueswir1 | { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, |
2326 | eca8f888 | blueswir1 | { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, |
2327 | eca8f888 | blueswir1 | { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, |
2328 | eca8f888 | blueswir1 | { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, |
2329 | eca8f888 | blueswir1 | { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, |
2330 | eca8f888 | blueswir1 | { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, |
2331 | eca8f888 | blueswir1 | { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, |
2332 | eca8f888 | blueswir1 | |
2333 | eca8f888 | blueswir1 | { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2334 | eca8f888 | blueswir1 | { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, |
2335 | eca8f888 | blueswir1 | { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2336 | eca8f888 | blueswir1 | { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, |
2337 | eca8f888 | blueswir1 | { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, |
2338 | eca8f888 | blueswir1 | { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, |
2339 | eca8f888 | blueswir1 | { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, |
2340 | eca8f888 | blueswir1 | { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, |
2341 | eca8f888 | blueswir1 | { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, |
2342 | eca8f888 | blueswir1 | { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, |
2343 | eca8f888 | blueswir1 | { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, |
2344 | eca8f888 | blueswir1 | { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, |
2345 | eca8f888 | blueswir1 | { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, |
2346 | eca8f888 | blueswir1 | |
2347 | eca8f888 | blueswir1 | { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2348 | eca8f888 | blueswir1 | |
2349 | eca8f888 | blueswir1 | { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2350 | eca8f888 | blueswir1 | { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2351 | eca8f888 | blueswir1 | { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, |
2352 | eca8f888 | blueswir1 | { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2353 | eca8f888 | blueswir1 | { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2354 | eca8f888 | blueswir1 | { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2355 | eca8f888 | blueswir1 | { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2356 | eca8f888 | blueswir1 | { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2357 | eca8f888 | blueswir1 | { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, |
2358 | eca8f888 | blueswir1 | { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2359 | eca8f888 | blueswir1 | |
2360 | eca8f888 | blueswir1 | { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2361 | eca8f888 | blueswir1 | { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2362 | eca8f888 | blueswir1 | { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2363 | eca8f888 | blueswir1 | { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2364 | eca8f888 | blueswir1 | { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2365 | eca8f888 | blueswir1 | { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2366 | eca8f888 | blueswir1 | { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2367 | eca8f888 | blueswir1 | { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, |
2368 | eca8f888 | blueswir1 | { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, |
2369 | eca8f888 | blueswir1 | { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, |
2370 | eca8f888 | blueswir1 | { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2371 | eca8f888 | blueswir1 | { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2372 | eca8f888 | blueswir1 | { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2373 | eca8f888 | blueswir1 | { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2374 | eca8f888 | blueswir1 | |
2375 | eca8f888 | blueswir1 | { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2376 | eca8f888 | blueswir1 | { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2377 | eca8f888 | blueswir1 | { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2378 | eca8f888 | blueswir1 | { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2379 | eca8f888 | blueswir1 | { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2380 | eca8f888 | blueswir1 | { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, |
2381 | eca8f888 | blueswir1 | |
2382 | eca8f888 | blueswir1 | { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2383 | eca8f888 | blueswir1 | { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2384 | eca8f888 | blueswir1 | { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2385 | eca8f888 | blueswir1 | { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2386 | eca8f888 | blueswir1 | { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2387 | eca8f888 | blueswir1 | { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2388 | eca8f888 | blueswir1 | { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2389 | eca8f888 | blueswir1 | { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2390 | eca8f888 | blueswir1 | { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2391 | eca8f888 | blueswir1 | { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2392 | eca8f888 | blueswir1 | { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2393 | eca8f888 | blueswir1 | { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2394 | eca8f888 | blueswir1 | { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2395 | eca8f888 | blueswir1 | { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2396 | eca8f888 | blueswir1 | { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2397 | eca8f888 | blueswir1 | { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2398 | eca8f888 | blueswir1 | { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, |
2399 | eca8f888 | blueswir1 | { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2400 | eca8f888 | blueswir1 | { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, |
2401 | eca8f888 | blueswir1 | { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2402 | eca8f888 | blueswir1 | { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, |
2403 | eca8f888 | blueswir1 | { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2404 | eca8f888 | blueswir1 | |
2405 | eca8f888 | blueswir1 | { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2406 | eca8f888 | blueswir1 | { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2407 | eca8f888 | blueswir1 | { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2408 | eca8f888 | blueswir1 | { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2409 | eca8f888 | blueswir1 | { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, |
2410 | eca8f888 | blueswir1 | { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2411 | eca8f888 | blueswir1 | { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2412 | eca8f888 | blueswir1 | { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2413 | eca8f888 | blueswir1 | { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2414 | eca8f888 | blueswir1 | { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2415 | eca8f888 | blueswir1 | { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2416 | eca8f888 | blueswir1 | { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2417 | eca8f888 | blueswir1 | { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, |
2418 | eca8f888 | blueswir1 | { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2419 | eca8f888 | blueswir1 | |
2420 | eca8f888 | blueswir1 | { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, |
2421 | eca8f888 | blueswir1 | { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, |
2422 | eca8f888 | blueswir1 | { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, |
2423 | eca8f888 | blueswir1 | { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2424 | eca8f888 | blueswir1 | { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2425 | eca8f888 | blueswir1 | { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2426 | eca8f888 | blueswir1 | { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2427 | eca8f888 | blueswir1 | { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2428 | eca8f888 | blueswir1 | { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2429 | eca8f888 | blueswir1 | { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2430 | eca8f888 | blueswir1 | { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2431 | eca8f888 | blueswir1 | { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2432 | eca8f888 | blueswir1 | { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, |
2433 | eca8f888 | blueswir1 | { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, |
2434 | eca8f888 | blueswir1 | { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, |
2435 | eca8f888 | blueswir1 | { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, |
2436 | eca8f888 | blueswir1 | { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, |
2437 | eca8f888 | blueswir1 | { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, |
2438 | eca8f888 | blueswir1 | { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, |
2439 | eca8f888 | blueswir1 | { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, |
2440 | eca8f888 | blueswir1 | { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, |
2441 | eca8f888 | blueswir1 | { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, |
2442 | eca8f888 | blueswir1 | { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, |
2443 | eca8f888 | blueswir1 | |
2444 | eca8f888 | blueswir1 | { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, |
2445 | eca8f888 | blueswir1 | { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, |
2446 | eca8f888 | blueswir1 | { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, |
2447 | eca8f888 | blueswir1 | { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2448 | eca8f888 | blueswir1 | { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2449 | eca8f888 | blueswir1 | { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2450 | eca8f888 | blueswir1 | { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, |
2451 | eca8f888 | blueswir1 | { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2452 | eca8f888 | blueswir1 | { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2453 | eca8f888 | blueswir1 | { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2454 | eca8f888 | blueswir1 | { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2455 | eca8f888 | blueswir1 | { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2456 | eca8f888 | blueswir1 | { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, |
2457 | eca8f888 | blueswir1 | { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, |
2458 | eca8f888 | blueswir1 | { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, |
2459 | eca8f888 | blueswir1 | { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, |
2460 | eca8f888 | blueswir1 | { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, |
2461 | eca8f888 | blueswir1 | { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, |
2462 | eca8f888 | blueswir1 | { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, |
2463 | eca8f888 | blueswir1 | { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, |
2464 | eca8f888 | blueswir1 | { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, |
2465 | eca8f888 | blueswir1 | { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, |
2466 | eca8f888 | blueswir1 | { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, |
2467 | eca8f888 | blueswir1 | |
2468 | eca8f888 | blueswir1 | { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2469 | eca8f888 | blueswir1 | { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2470 | eca8f888 | blueswir1 | { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2471 | eca8f888 | blueswir1 | { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2472 | eca8f888 | blueswir1 | { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2473 | eca8f888 | blueswir1 | { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2474 | eca8f888 | blueswir1 | { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2475 | eca8f888 | blueswir1 | { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2476 | eca8f888 | blueswir1 | { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2477 | eca8f888 | blueswir1 | { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2478 | eca8f888 | blueswir1 | { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2479 | eca8f888 | blueswir1 | { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2480 | eca8f888 | blueswir1 | { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2481 | eca8f888 | blueswir1 | { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2482 | eca8f888 | blueswir1 | { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2483 | eca8f888 | blueswir1 | { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2484 | eca8f888 | blueswir1 | |
2485 | eca8f888 | blueswir1 | { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2486 | eca8f888 | blueswir1 | { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2487 | eca8f888 | blueswir1 | { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2488 | eca8f888 | blueswir1 | { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2489 | eca8f888 | blueswir1 | { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2490 | eca8f888 | blueswir1 | { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2491 | eca8f888 | blueswir1 | { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2492 | eca8f888 | blueswir1 | { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2493 | eca8f888 | blueswir1 | { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2494 | eca8f888 | blueswir1 | { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2495 | eca8f888 | blueswir1 | { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2496 | eca8f888 | blueswir1 | { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2497 | eca8f888 | blueswir1 | |
2498 | eca8f888 | blueswir1 | { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2499 | eca8f888 | blueswir1 | { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2500 | eca8f888 | blueswir1 | { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2501 | eca8f888 | blueswir1 | { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2502 | eca8f888 | blueswir1 | { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2503 | eca8f888 | blueswir1 | { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2504 | eca8f888 | blueswir1 | { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2505 | eca8f888 | blueswir1 | { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2506 | eca8f888 | blueswir1 | { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2507 | eca8f888 | blueswir1 | { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2508 | eca8f888 | blueswir1 | { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2509 | eca8f888 | blueswir1 | { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2510 | eca8f888 | blueswir1 | |
2511 | eca8f888 | blueswir1 | { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2512 | eca8f888 | blueswir1 | { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2513 | eca8f888 | blueswir1 | { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2514 | eca8f888 | blueswir1 | { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2515 | eca8f888 | blueswir1 | { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2516 | eca8f888 | blueswir1 | { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2517 | eca8f888 | blueswir1 | |
2518 | eca8f888 | blueswir1 | { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2519 | eca8f888 | blueswir1 | { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2520 | eca8f888 | blueswir1 | { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2521 | eca8f888 | blueswir1 | { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2522 | eca8f888 | blueswir1 | { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2523 | eca8f888 | blueswir1 | { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2524 | eca8f888 | blueswir1 | |
2525 | eca8f888 | blueswir1 | { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2526 | eca8f888 | blueswir1 | { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2527 | eca8f888 | blueswir1 | { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2528 | eca8f888 | blueswir1 | { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2529 | eca8f888 | blueswir1 | { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2530 | eca8f888 | blueswir1 | { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2531 | eca8f888 | blueswir1 | { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2532 | eca8f888 | blueswir1 | { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2533 | eca8f888 | blueswir1 | |
2534 | eca8f888 | blueswir1 | { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2535 | eca8f888 | blueswir1 | { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2536 | eca8f888 | blueswir1 | |
2537 | eca8f888 | blueswir1 | { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2538 | eca8f888 | blueswir1 | { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2539 | eca8f888 | blueswir1 | { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2540 | eca8f888 | blueswir1 | { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2541 | eca8f888 | blueswir1 | |
2542 | eca8f888 | blueswir1 | { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2543 | eca8f888 | blueswir1 | { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2544 | eca8f888 | blueswir1 | { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2545 | eca8f888 | blueswir1 | { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2546 | eca8f888 | blueswir1 | |
2547 | eca8f888 | blueswir1 | { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2548 | eca8f888 | blueswir1 | { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2549 | eca8f888 | blueswir1 | { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2550 | eca8f888 | blueswir1 | { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2551 | eca8f888 | blueswir1 | { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2552 | eca8f888 | blueswir1 | { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2553 | eca8f888 | blueswir1 | { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2554 | eca8f888 | blueswir1 | { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2555 | eca8f888 | blueswir1 | |
2556 | eca8f888 | blueswir1 | { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2557 | eca8f888 | blueswir1 | { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2558 | eca8f888 | blueswir1 | { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2559 | eca8f888 | blueswir1 | { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2560 | eca8f888 | blueswir1 | |
2561 | eca8f888 | blueswir1 | { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2562 | eca8f888 | blueswir1 | { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2563 | eca8f888 | blueswir1 | { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2564 | eca8f888 | blueswir1 | { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2565 | eca8f888 | blueswir1 | |
2566 | eca8f888 | blueswir1 | { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, |
2567 | eca8f888 | blueswir1 | { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, |
2568 | eca8f888 | blueswir1 | { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, |
2569 | eca8f888 | blueswir1 | { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, |
2570 | eca8f888 | blueswir1 | |
2571 | eca8f888 | blueswir1 | { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, |
2572 | eca8f888 | blueswir1 | { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, |
2573 | eca8f888 | blueswir1 | { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, |
2574 | eca8f888 | blueswir1 | { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, |
2575 | eca8f888 | blueswir1 | |
2576 | eca8f888 | blueswir1 | { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, |
2577 | eca8f888 | blueswir1 | |
2578 | eca8f888 | blueswir1 | { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2579 | eca8f888 | blueswir1 | { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, |
2580 | eca8f888 | blueswir1 | |
2581 | eca8f888 | blueswir1 | { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2582 | eca8f888 | blueswir1 | { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2583 | eca8f888 | blueswir1 | |
2584 | eca8f888 | blueswir1 | { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2585 | eca8f888 | blueswir1 | { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2586 | eca8f888 | blueswir1 | |
2587 | eca8f888 | blueswir1 | { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, |
2588 | eca8f888 | blueswir1 | |
2589 | eca8f888 | blueswir1 | { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, |
2590 | eca8f888 | blueswir1 | { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, |
2591 | eca8f888 | blueswir1 | { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, |
2592 | eca8f888 | blueswir1 | { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, |
2593 | eca8f888 | blueswir1 | |
2594 | eca8f888 | blueswir1 | { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, |
2595 | eca8f888 | blueswir1 | { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, |
2596 | b9adb4a6 | bellard | { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, |
2597 | eca8f888 | blueswir1 | { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, |
2598 | b9adb4a6 | bellard | |
2599 | eca8f888 | blueswir1 | { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, |
2600 | eca8f888 | blueswir1 | { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, |
2601 | b9adb4a6 | bellard | { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, |
2602 | eca8f888 | blueswir1 | { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, |
2603 | eca8f888 | blueswir1 | |
2604 | eca8f888 | blueswir1 | { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2605 | eca8f888 | blueswir1 | { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2606 | eca8f888 | blueswir1 | { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
2607 | eca8f888 | blueswir1 | |
2608 | eca8f888 | blueswir1 | { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, |
2609 | eca8f888 | blueswir1 | { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, |
2610 | eca8f888 | blueswir1 | { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
2611 | eca8f888 | blueswir1 | |
2612 | eca8f888 | blueswir1 | { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, |
2613 | eca8f888 | blueswir1 | { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, |
2614 | eca8f888 | blueswir1 | { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, |
2615 | eca8f888 | blueswir1 | { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
2616 | eca8f888 | blueswir1 | { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, |
2617 | eca8f888 | blueswir1 | { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, |
2618 | eca8f888 | blueswir1 | |
2619 | eca8f888 | blueswir1 | { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, |
2620 | eca8f888 | blueswir1 | { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, |
2621 | eca8f888 | blueswir1 | { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, |
2622 | eca8f888 | blueswir1 | { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, |
2623 | eca8f888 | blueswir1 | { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, |
2624 | eca8f888 | blueswir1 | |
2625 | eca8f888 | blueswir1 | { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, |
2626 | eca8f888 | blueswir1 | { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, |
2627 | eca8f888 | blueswir1 | { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, |
2628 | eca8f888 | blueswir1 | { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, |
2629 | eca8f888 | blueswir1 | { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, |
2630 | eca8f888 | blueswir1 | { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, |
2631 | eca8f888 | blueswir1 | { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, |
2632 | eca8f888 | blueswir1 | { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, |
2633 | eca8f888 | blueswir1 | { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2634 | eca8f888 | blueswir1 | { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2635 | eca8f888 | blueswir1 | { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, |
2636 | eca8f888 | blueswir1 | { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, |
2637 | eca8f888 | blueswir1 | { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2638 | eca8f888 | blueswir1 | { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2639 | eca8f888 | blueswir1 | { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, |
2640 | eca8f888 | blueswir1 | { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, |
2641 | eca8f888 | blueswir1 | { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, |
2642 | eca8f888 | blueswir1 | { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, |
2643 | eca8f888 | blueswir1 | { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, |
2644 | eca8f888 | blueswir1 | { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, |
2645 | eca8f888 | blueswir1 | { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, |
2646 | eca8f888 | blueswir1 | { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, |
2647 | eca8f888 | blueswir1 | { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2648 | eca8f888 | blueswir1 | { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2649 | eca8f888 | blueswir1 | { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, |
2650 | eca8f888 | blueswir1 | { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, |
2651 | eca8f888 | blueswir1 | { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, |
2652 | eca8f888 | blueswir1 | { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, |
2653 | eca8f888 | blueswir1 | { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2654 | eca8f888 | blueswir1 | { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2655 | eca8f888 | blueswir1 | { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2656 | eca8f888 | blueswir1 | { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2657 | eca8f888 | blueswir1 | { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2658 | eca8f888 | blueswir1 | { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2659 | eca8f888 | blueswir1 | { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2660 | eca8f888 | blueswir1 | { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2661 | eca8f888 | blueswir1 | { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2662 | eca8f888 | blueswir1 | { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2663 | eca8f888 | blueswir1 | { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2664 | eca8f888 | blueswir1 | { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2665 | eca8f888 | blueswir1 | { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2666 | eca8f888 | blueswir1 | { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2667 | eca8f888 | blueswir1 | { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2668 | eca8f888 | blueswir1 | { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2669 | eca8f888 | blueswir1 | { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2670 | eca8f888 | blueswir1 | { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2671 | eca8f888 | blueswir1 | { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2672 | eca8f888 | blueswir1 | { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2673 | eca8f888 | blueswir1 | { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2674 | eca8f888 | blueswir1 | { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2675 | eca8f888 | blueswir1 | { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2676 | eca8f888 | blueswir1 | { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2677 | eca8f888 | blueswir1 | { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2678 | eca8f888 | blueswir1 | { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2679 | eca8f888 | blueswir1 | { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2680 | eca8f888 | blueswir1 | { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2681 | eca8f888 | blueswir1 | { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2682 | eca8f888 | blueswir1 | { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2683 | eca8f888 | blueswir1 | { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2684 | eca8f888 | blueswir1 | { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2685 | eca8f888 | blueswir1 | { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2686 | eca8f888 | blueswir1 | { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2687 | eca8f888 | blueswir1 | { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2688 | eca8f888 | blueswir1 | { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2689 | eca8f888 | blueswir1 | { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2690 | eca8f888 | blueswir1 | { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2691 | eca8f888 | blueswir1 | { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2692 | eca8f888 | blueswir1 | { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2693 | eca8f888 | blueswir1 | { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2694 | eca8f888 | blueswir1 | { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2695 | eca8f888 | blueswir1 | { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2696 | eca8f888 | blueswir1 | { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2697 | eca8f888 | blueswir1 | { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2698 | eca8f888 | blueswir1 | { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2699 | eca8f888 | blueswir1 | { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2700 | eca8f888 | blueswir1 | { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2701 | eca8f888 | blueswir1 | { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2702 | eca8f888 | blueswir1 | { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2703 | eca8f888 | blueswir1 | { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2704 | eca8f888 | blueswir1 | { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2705 | eca8f888 | blueswir1 | { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2706 | eca8f888 | blueswir1 | { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2707 | eca8f888 | blueswir1 | { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2708 | eca8f888 | blueswir1 | { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2709 | eca8f888 | blueswir1 | { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2710 | eca8f888 | blueswir1 | { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2711 | eca8f888 | blueswir1 | { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2712 | eca8f888 | blueswir1 | { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2713 | eca8f888 | blueswir1 | { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2714 | eca8f888 | blueswir1 | { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2715 | eca8f888 | blueswir1 | { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2716 | eca8f888 | blueswir1 | { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2717 | eca8f888 | blueswir1 | { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2718 | eca8f888 | blueswir1 | { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2719 | eca8f888 | blueswir1 | { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2720 | eca8f888 | blueswir1 | { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2721 | eca8f888 | blueswir1 | { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2722 | eca8f888 | blueswir1 | { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2723 | eca8f888 | blueswir1 | { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2724 | eca8f888 | blueswir1 | { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2725 | eca8f888 | blueswir1 | { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2726 | eca8f888 | blueswir1 | { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2727 | eca8f888 | blueswir1 | { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2728 | eca8f888 | blueswir1 | { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2729 | eca8f888 | blueswir1 | { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2730 | eca8f888 | blueswir1 | { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2731 | eca8f888 | blueswir1 | { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2732 | eca8f888 | blueswir1 | { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2733 | eca8f888 | blueswir1 | { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2734 | eca8f888 | blueswir1 | { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2735 | eca8f888 | blueswir1 | { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2736 | eca8f888 | blueswir1 | { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2737 | eca8f888 | blueswir1 | { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2738 | eca8f888 | blueswir1 | { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2739 | eca8f888 | blueswir1 | { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2740 | eca8f888 | blueswir1 | { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2741 | eca8f888 | blueswir1 | { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2742 | eca8f888 | blueswir1 | { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2743 | eca8f888 | blueswir1 | { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2744 | eca8f888 | blueswir1 | { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2745 | eca8f888 | blueswir1 | { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2746 | eca8f888 | blueswir1 | { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2747 | eca8f888 | blueswir1 | { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2748 | eca8f888 | blueswir1 | { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2749 | eca8f888 | blueswir1 | { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2750 | eca8f888 | blueswir1 | { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2751 | eca8f888 | blueswir1 | { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2752 | eca8f888 | blueswir1 | { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2753 | eca8f888 | blueswir1 | { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2754 | eca8f888 | blueswir1 | { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2755 | eca8f888 | blueswir1 | { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2756 | eca8f888 | blueswir1 | { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2757 | eca8f888 | blueswir1 | { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2758 | eca8f888 | blueswir1 | { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2759 | eca8f888 | blueswir1 | { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2760 | eca8f888 | blueswir1 | { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2761 | eca8f888 | blueswir1 | { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2762 | eca8f888 | blueswir1 | { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2763 | eca8f888 | blueswir1 | { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2764 | eca8f888 | blueswir1 | { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2765 | eca8f888 | blueswir1 | { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2766 | eca8f888 | blueswir1 | { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2767 | eca8f888 | blueswir1 | { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2768 | eca8f888 | blueswir1 | { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2769 | eca8f888 | blueswir1 | { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2770 | eca8f888 | blueswir1 | { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2771 | eca8f888 | blueswir1 | { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2772 | eca8f888 | blueswir1 | { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2773 | eca8f888 | blueswir1 | { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2774 | eca8f888 | blueswir1 | { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2775 | eca8f888 | blueswir1 | { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
2776 | eca8f888 | blueswir1 | { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2777 | eca8f888 | blueswir1 | { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2778 | eca8f888 | blueswir1 | { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
2779 | eca8f888 | blueswir1 | { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2780 | eca8f888 | blueswir1 | { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2781 | eca8f888 | blueswir1 | { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
2782 | eca8f888 | blueswir1 | { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2783 | eca8f888 | blueswir1 | { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2784 | eca8f888 | blueswir1 | { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
2785 | eca8f888 | blueswir1 | { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2786 | eca8f888 | blueswir1 | { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2787 | eca8f888 | blueswir1 | { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2788 | eca8f888 | blueswir1 | { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
2789 | eca8f888 | blueswir1 | { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
2790 | eca8f888 | blueswir1 | { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
2791 | eca8f888 | blueswir1 | { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2792 | eca8f888 | blueswir1 | { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2793 | eca8f888 | blueswir1 | { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2794 | eca8f888 | blueswir1 | { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
2795 | eca8f888 | blueswir1 | { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
2796 | eca8f888 | blueswir1 | { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
2797 | eca8f888 | blueswir1 | { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2798 | eca8f888 | blueswir1 | { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2799 | eca8f888 | blueswir1 | { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2800 | eca8f888 | blueswir1 | { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2801 | eca8f888 | blueswir1 | { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2802 | eca8f888 | blueswir1 | { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2803 | eca8f888 | blueswir1 | { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2804 | eca8f888 | blueswir1 | { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2805 | eca8f888 | blueswir1 | { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2806 | eca8f888 | blueswir1 | { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2807 | eca8f888 | blueswir1 | { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2808 | eca8f888 | blueswir1 | { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2809 | eca8f888 | blueswir1 | { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2810 | eca8f888 | blueswir1 | { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2811 | eca8f888 | blueswir1 | { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2812 | eca8f888 | blueswir1 | { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2813 | eca8f888 | blueswir1 | { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2814 | eca8f888 | blueswir1 | { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2815 | eca8f888 | blueswir1 | { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2816 | eca8f888 | blueswir1 | { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2817 | eca8f888 | blueswir1 | { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2818 | eca8f888 | blueswir1 | { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2819 | eca8f888 | blueswir1 | { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2820 | eca8f888 | blueswir1 | { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2821 | eca8f888 | blueswir1 | { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2822 | eca8f888 | blueswir1 | { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2823 | eca8f888 | blueswir1 | { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2824 | eca8f888 | blueswir1 | { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2825 | eca8f888 | blueswir1 | { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2826 | eca8f888 | blueswir1 | { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2827 | eca8f888 | blueswir1 | { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2828 | eca8f888 | blueswir1 | { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2829 | eca8f888 | blueswir1 | { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2830 | eca8f888 | blueswir1 | { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2831 | eca8f888 | blueswir1 | { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2832 | eca8f888 | blueswir1 | { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2833 | eca8f888 | blueswir1 | { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2834 | eca8f888 | blueswir1 | { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2835 | eca8f888 | blueswir1 | { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2836 | eca8f888 | blueswir1 | { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2837 | eca8f888 | blueswir1 | { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2838 | eca8f888 | blueswir1 | { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2839 | eca8f888 | blueswir1 | { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2840 | eca8f888 | blueswir1 | { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2841 | eca8f888 | blueswir1 | { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
2842 | eca8f888 | blueswir1 | { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
2843 | eca8f888 | blueswir1 | { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, |
2844 | eca8f888 | blueswir1 | { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, |
2845 | eca8f888 | blueswir1 | { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2846 | eca8f888 | blueswir1 | { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2847 | eca8f888 | blueswir1 | { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2848 | eca8f888 | blueswir1 | { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2849 | eca8f888 | blueswir1 | { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
2850 | eca8f888 | blueswir1 | { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
2851 | eca8f888 | blueswir1 | { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
2852 | eca8f888 | blueswir1 | { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, |
2853 | eca8f888 | blueswir1 | { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2854 | eca8f888 | blueswir1 | { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2855 | eca8f888 | blueswir1 | { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2856 | eca8f888 | blueswir1 | { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2857 | eca8f888 | blueswir1 | { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2858 | eca8f888 | blueswir1 | { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2859 | eca8f888 | blueswir1 | { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2860 | eca8f888 | blueswir1 | { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2861 | eca8f888 | blueswir1 | { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2862 | eca8f888 | blueswir1 | { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2863 | eca8f888 | blueswir1 | { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2864 | eca8f888 | blueswir1 | { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2865 | eca8f888 | blueswir1 | { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2866 | eca8f888 | blueswir1 | { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2867 | eca8f888 | blueswir1 | { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
2868 | eca8f888 | blueswir1 | { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
2869 | eca8f888 | blueswir1 | { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
2870 | eca8f888 | blueswir1 | { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
2871 | eca8f888 | blueswir1 | { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2872 | eca8f888 | blueswir1 | { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2873 | eca8f888 | blueswir1 | { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2874 | eca8f888 | blueswir1 | { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
2875 | eca8f888 | blueswir1 | { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
2876 | eca8f888 | blueswir1 | { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
2877 | eca8f888 | blueswir1 | { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
2878 | eca8f888 | blueswir1 | { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, |
2879 | eca8f888 | blueswir1 | { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, |
2880 | eca8f888 | blueswir1 | { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
2881 | eca8f888 | blueswir1 | { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, |
2882 | eca8f888 | blueswir1 | { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, |
2883 | eca8f888 | blueswir1 | { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
2884 | eca8f888 | blueswir1 | { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, |
2885 | eca8f888 | blueswir1 | { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, |
2886 | eca8f888 | blueswir1 | { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
2887 | eca8f888 | blueswir1 | { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, |
2888 | eca8f888 | blueswir1 | { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, |
2889 | eca8f888 | blueswir1 | |
2890 | eca8f888 | blueswir1 | { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } }, |
2891 | eca8f888 | blueswir1 | { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, |
2892 | eca8f888 | blueswir1 | { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, |
2893 | eca8f888 | blueswir1 | { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, |
2894 | b9adb4a6 | bellard | { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, |
2895 | b9adb4a6 | bellard | |
2896 | eca8f888 | blueswir1 | { "b", B(18,0,0), B_MASK, COM, { LI } }, |
2897 | eca8f888 | blueswir1 | { "bl", B(18,0,1), B_MASK, COM, { LI } }, |
2898 | eca8f888 | blueswir1 | { "ba", B(18,1,0), B_MASK, COM, { LIA } }, |
2899 | eca8f888 | blueswir1 | { "bla", B(18,1,1), B_MASK, COM, { LIA } }, |
2900 | eca8f888 | blueswir1 | |
2901 | eca8f888 | blueswir1 | { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, |
2902 | eca8f888 | blueswir1 | |
2903 | eca8f888 | blueswir1 | { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2904 | eca8f888 | blueswir1 | { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, |
2905 | eca8f888 | blueswir1 | { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2906 | eca8f888 | blueswir1 | { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, |
2907 | eca8f888 | blueswir1 | { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2908 | eca8f888 | blueswir1 | { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2909 | eca8f888 | blueswir1 | { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2910 | eca8f888 | blueswir1 | { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2911 | eca8f888 | blueswir1 | { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2912 | eca8f888 | blueswir1 | { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2913 | eca8f888 | blueswir1 | { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2914 | eca8f888 | blueswir1 | { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2915 | eca8f888 | blueswir1 | { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2916 | eca8f888 | blueswir1 | { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2917 | eca8f888 | blueswir1 | { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2918 | eca8f888 | blueswir1 | { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2919 | eca8f888 | blueswir1 | { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2920 | eca8f888 | blueswir1 | { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2921 | eca8f888 | blueswir1 | { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
2922 | eca8f888 | blueswir1 | { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
2923 | eca8f888 | blueswir1 | { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2924 | eca8f888 | blueswir1 | { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2925 | eca8f888 | blueswir1 | { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
2926 | eca8f888 | blueswir1 | { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
2927 | eca8f888 | blueswir1 | { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2928 | eca8f888 | blueswir1 | { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2929 | eca8f888 | blueswir1 | { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2930 | eca8f888 | blueswir1 | { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2931 | eca8f888 | blueswir1 | { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2932 | eca8f888 | blueswir1 | { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2933 | eca8f888 | blueswir1 | { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2934 | eca8f888 | blueswir1 | { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2935 | eca8f888 | blueswir1 | { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2936 | eca8f888 | blueswir1 | { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2937 | eca8f888 | blueswir1 | { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2938 | eca8f888 | blueswir1 | { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2939 | eca8f888 | blueswir1 | { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2940 | eca8f888 | blueswir1 | { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2941 | eca8f888 | blueswir1 | { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2942 | eca8f888 | blueswir1 | { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2943 | eca8f888 | blueswir1 | { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2944 | eca8f888 | blueswir1 | { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2945 | eca8f888 | blueswir1 | { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2946 | eca8f888 | blueswir1 | { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2947 | eca8f888 | blueswir1 | { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2948 | eca8f888 | blueswir1 | { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2949 | eca8f888 | blueswir1 | { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2950 | eca8f888 | blueswir1 | { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2951 | eca8f888 | blueswir1 | { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2952 | eca8f888 | blueswir1 | { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2953 | eca8f888 | blueswir1 | { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2954 | eca8f888 | blueswir1 | { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2955 | eca8f888 | blueswir1 | { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2956 | eca8f888 | blueswir1 | { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2957 | eca8f888 | blueswir1 | { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2958 | eca8f888 | blueswir1 | { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2959 | eca8f888 | blueswir1 | { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2960 | eca8f888 | blueswir1 | { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2961 | eca8f888 | blueswir1 | { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2962 | eca8f888 | blueswir1 | { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2963 | eca8f888 | blueswir1 | { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2964 | eca8f888 | blueswir1 | { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2965 | eca8f888 | blueswir1 | { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2966 | eca8f888 | blueswir1 | { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2967 | eca8f888 | blueswir1 | { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2968 | eca8f888 | blueswir1 | { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2969 | eca8f888 | blueswir1 | { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2970 | eca8f888 | blueswir1 | { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2971 | eca8f888 | blueswir1 | { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2972 | eca8f888 | blueswir1 | { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2973 | eca8f888 | blueswir1 | { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2974 | eca8f888 | blueswir1 | { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2975 | eca8f888 | blueswir1 | { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2976 | eca8f888 | blueswir1 | { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2977 | eca8f888 | blueswir1 | { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2978 | eca8f888 | blueswir1 | { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2979 | eca8f888 | blueswir1 | { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2980 | eca8f888 | blueswir1 | { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2981 | eca8f888 | blueswir1 | { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2982 | eca8f888 | blueswir1 | { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2983 | eca8f888 | blueswir1 | { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2984 | eca8f888 | blueswir1 | { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2985 | eca8f888 | blueswir1 | { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2986 | eca8f888 | blueswir1 | { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2987 | eca8f888 | blueswir1 | { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2988 | eca8f888 | blueswir1 | { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2989 | eca8f888 | blueswir1 | { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
2990 | eca8f888 | blueswir1 | { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2991 | eca8f888 | blueswir1 | { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2992 | eca8f888 | blueswir1 | { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2993 | eca8f888 | blueswir1 | { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2994 | eca8f888 | blueswir1 | { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2995 | eca8f888 | blueswir1 | { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
2996 | eca8f888 | blueswir1 | { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
2997 | eca8f888 | blueswir1 | { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
2998 | eca8f888 | blueswir1 | { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
2999 | eca8f888 | blueswir1 | { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3000 | eca8f888 | blueswir1 | { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3001 | eca8f888 | blueswir1 | { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3002 | eca8f888 | blueswir1 | { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3003 | eca8f888 | blueswir1 | { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3004 | eca8f888 | blueswir1 | { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3005 | eca8f888 | blueswir1 | { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3006 | eca8f888 | blueswir1 | { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3007 | eca8f888 | blueswir1 | { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3008 | eca8f888 | blueswir1 | { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3009 | eca8f888 | blueswir1 | { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3010 | eca8f888 | blueswir1 | { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3011 | eca8f888 | blueswir1 | { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3012 | eca8f888 | blueswir1 | { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3013 | eca8f888 | blueswir1 | { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3014 | eca8f888 | blueswir1 | { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3015 | eca8f888 | blueswir1 | { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3016 | eca8f888 | blueswir1 | { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3017 | eca8f888 | blueswir1 | { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3018 | eca8f888 | blueswir1 | { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3019 | eca8f888 | blueswir1 | { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3020 | eca8f888 | blueswir1 | { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3021 | eca8f888 | blueswir1 | { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3022 | eca8f888 | blueswir1 | { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3023 | eca8f888 | blueswir1 | { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3024 | eca8f888 | blueswir1 | { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3025 | eca8f888 | blueswir1 | { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3026 | eca8f888 | blueswir1 | { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3027 | eca8f888 | blueswir1 | { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3028 | eca8f888 | blueswir1 | { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3029 | eca8f888 | blueswir1 | { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3030 | eca8f888 | blueswir1 | { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3031 | eca8f888 | blueswir1 | { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3032 | eca8f888 | blueswir1 | { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3033 | eca8f888 | blueswir1 | { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3034 | eca8f888 | blueswir1 | { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3035 | eca8f888 | blueswir1 | { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3036 | eca8f888 | blueswir1 | { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3037 | eca8f888 | blueswir1 | { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3038 | eca8f888 | blueswir1 | { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3039 | eca8f888 | blueswir1 | { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3040 | eca8f888 | blueswir1 | { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3041 | eca8f888 | blueswir1 | { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3042 | eca8f888 | blueswir1 | { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3043 | eca8f888 | blueswir1 | { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3044 | eca8f888 | blueswir1 | { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3045 | eca8f888 | blueswir1 | { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3046 | eca8f888 | blueswir1 | { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3047 | eca8f888 | blueswir1 | { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3048 | eca8f888 | blueswir1 | { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3049 | eca8f888 | blueswir1 | { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3050 | eca8f888 | blueswir1 | { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3051 | eca8f888 | blueswir1 | { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3052 | eca8f888 | blueswir1 | { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3053 | eca8f888 | blueswir1 | { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3054 | eca8f888 | blueswir1 | { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3055 | eca8f888 | blueswir1 | { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3056 | eca8f888 | blueswir1 | { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
3057 | eca8f888 | blueswir1 | { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3058 | eca8f888 | blueswir1 | { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3059 | eca8f888 | blueswir1 | { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3060 | eca8f888 | blueswir1 | { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3061 | eca8f888 | blueswir1 | { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3062 | eca8f888 | blueswir1 | { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3063 | eca8f888 | blueswir1 | { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3064 | eca8f888 | blueswir1 | { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3065 | eca8f888 | blueswir1 | { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3066 | eca8f888 | blueswir1 | { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3067 | eca8f888 | blueswir1 | { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3068 | eca8f888 | blueswir1 | { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3069 | eca8f888 | blueswir1 | { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3070 | eca8f888 | blueswir1 | { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3071 | eca8f888 | blueswir1 | { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3072 | eca8f888 | blueswir1 | { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
3073 | eca8f888 | blueswir1 | { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3074 | eca8f888 | blueswir1 | { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3075 | eca8f888 | blueswir1 | { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3076 | eca8f888 | blueswir1 | { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3077 | eca8f888 | blueswir1 | { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3078 | eca8f888 | blueswir1 | { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
3079 | eca8f888 | blueswir1 | { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3080 | eca8f888 | blueswir1 | { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3081 | eca8f888 | blueswir1 | { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3082 | eca8f888 | blueswir1 | { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3083 | eca8f888 | blueswir1 | { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, |
3084 | eca8f888 | blueswir1 | { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
3085 | eca8f888 | blueswir1 | { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3086 | eca8f888 | blueswir1 | { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3087 | eca8f888 | blueswir1 | { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3088 | eca8f888 | blueswir1 | { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3089 | eca8f888 | blueswir1 | { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
3090 | eca8f888 | blueswir1 | { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
3091 | eca8f888 | blueswir1 | { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3092 | eca8f888 | blueswir1 | { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3093 | eca8f888 | blueswir1 | { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3094 | eca8f888 | blueswir1 | { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3095 | eca8f888 | blueswir1 | { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3096 | eca8f888 | blueswir1 | { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3097 | eca8f888 | blueswir1 | { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3098 | eca8f888 | blueswir1 | { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3099 | eca8f888 | blueswir1 | { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3100 | eca8f888 | blueswir1 | { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3101 | eca8f888 | blueswir1 | { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3102 | eca8f888 | blueswir1 | { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3103 | eca8f888 | blueswir1 | { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3104 | eca8f888 | blueswir1 | { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3105 | eca8f888 | blueswir1 | { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3106 | eca8f888 | blueswir1 | { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3107 | eca8f888 | blueswir1 | { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3108 | eca8f888 | blueswir1 | { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3109 | eca8f888 | blueswir1 | { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3110 | eca8f888 | blueswir1 | { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3111 | eca8f888 | blueswir1 | { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3112 | eca8f888 | blueswir1 | { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3113 | eca8f888 | blueswir1 | { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3114 | eca8f888 | blueswir1 | { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3115 | eca8f888 | blueswir1 | { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3116 | eca8f888 | blueswir1 | { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3117 | eca8f888 | blueswir1 | { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3118 | eca8f888 | blueswir1 | { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3119 | eca8f888 | blueswir1 | { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3120 | eca8f888 | blueswir1 | { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3121 | eca8f888 | blueswir1 | { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
3122 | eca8f888 | blueswir1 | { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, |
3123 | eca8f888 | blueswir1 | { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, |
3124 | eca8f888 | blueswir1 | { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, |
3125 | eca8f888 | blueswir1 | |
3126 | eca8f888 | blueswir1 | { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, |
3127 | eca8f888 | blueswir1 | |
3128 | eca8f888 | blueswir1 | { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
3129 | eca8f888 | blueswir1 | { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, |
3130 | eca8f888 | blueswir1 | { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, |
3131 | eca8f888 | blueswir1 | |
3132 | eca8f888 | blueswir1 | { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, |
3133 | eca8f888 | blueswir1 | { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, |
3134 | b9adb4a6 | bellard | |
3135 | b9adb4a6 | bellard | { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, |
3136 | b9adb4a6 | bellard | |
3137 | eca8f888 | blueswir1 | { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, |
3138 | eca8f888 | blueswir1 | |
3139 | eca8f888 | blueswir1 | { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, |
3140 | eca8f888 | blueswir1 | { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, |
3141 | eca8f888 | blueswir1 | |
3142 | eca8f888 | blueswir1 | { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, |
3143 | eca8f888 | blueswir1 | { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, |
3144 | eca8f888 | blueswir1 | |
3145 | eca8f888 | blueswir1 | { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, |
3146 | eca8f888 | blueswir1 | |
3147 | eca8f888 | blueswir1 | { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, |
3148 | eca8f888 | blueswir1 | |
3149 | ee8ae9e4 | blueswir1 | { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, |
3150 | eca8f888 | blueswir1 | |
3151 | eca8f888 | blueswir1 | { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, |
3152 | eca8f888 | blueswir1 | { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, |
3153 | eca8f888 | blueswir1 | |
3154 | ee8ae9e4 | blueswir1 | { "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, |
3155 | ee8ae9e4 | blueswir1 | |
3156 | eca8f888 | blueswir1 | { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, |
3157 | eca8f888 | blueswir1 | |
3158 | ee8ae9e4 | blueswir1 | { "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, |
3159 | ee8ae9e4 | blueswir1 | |
3160 | eca8f888 | blueswir1 | { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
3161 | eca8f888 | blueswir1 | { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, |
3162 | eca8f888 | blueswir1 | |
3163 | ee8ae9e4 | blueswir1 | { "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, |
3164 | ee8ae9e4 | blueswir1 | { "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, |
3165 | ee8ae9e4 | blueswir1 | |
3166 | eca8f888 | blueswir1 | { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, |
3167 | eca8f888 | blueswir1 | { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, |
3168 | eca8f888 | blueswir1 | { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3169 | eca8f888 | blueswir1 | { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3170 | eca8f888 | blueswir1 | { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3171 | eca8f888 | blueswir1 | { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3172 | eca8f888 | blueswir1 | { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3173 | eca8f888 | blueswir1 | { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3174 | eca8f888 | blueswir1 | { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3175 | eca8f888 | blueswir1 | { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3176 | eca8f888 | blueswir1 | { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3177 | eca8f888 | blueswir1 | { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3178 | eca8f888 | blueswir1 | { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3179 | eca8f888 | blueswir1 | { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3180 | eca8f888 | blueswir1 | { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3181 | eca8f888 | blueswir1 | { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3182 | eca8f888 | blueswir1 | { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3183 | eca8f888 | blueswir1 | { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3184 | eca8f888 | blueswir1 | { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3185 | eca8f888 | blueswir1 | { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3186 | eca8f888 | blueswir1 | { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3187 | eca8f888 | blueswir1 | { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3188 | eca8f888 | blueswir1 | { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3189 | eca8f888 | blueswir1 | { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3190 | eca8f888 | blueswir1 | { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3191 | eca8f888 | blueswir1 | { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3192 | eca8f888 | blueswir1 | { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3193 | eca8f888 | blueswir1 | { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3194 | eca8f888 | blueswir1 | { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3195 | eca8f888 | blueswir1 | { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3196 | eca8f888 | blueswir1 | { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3197 | eca8f888 | blueswir1 | { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3198 | eca8f888 | blueswir1 | { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3199 | eca8f888 | blueswir1 | { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3200 | eca8f888 | blueswir1 | { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3201 | eca8f888 | blueswir1 | { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3202 | eca8f888 | blueswir1 | { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3203 | eca8f888 | blueswir1 | { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3204 | eca8f888 | blueswir1 | { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3205 | eca8f888 | blueswir1 | { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3206 | eca8f888 | blueswir1 | { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3207 | eca8f888 | blueswir1 | { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3208 | eca8f888 | blueswir1 | { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3209 | eca8f888 | blueswir1 | { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3210 | eca8f888 | blueswir1 | { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3211 | eca8f888 | blueswir1 | { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3212 | eca8f888 | blueswir1 | { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3213 | eca8f888 | blueswir1 | { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3214 | eca8f888 | blueswir1 | { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3215 | eca8f888 | blueswir1 | { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3216 | eca8f888 | blueswir1 | { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3217 | eca8f888 | blueswir1 | { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3218 | eca8f888 | blueswir1 | { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3219 | eca8f888 | blueswir1 | { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3220 | eca8f888 | blueswir1 | { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3221 | eca8f888 | blueswir1 | { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3222 | eca8f888 | blueswir1 | { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3223 | eca8f888 | blueswir1 | { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3224 | eca8f888 | blueswir1 | { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3225 | eca8f888 | blueswir1 | { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3226 | eca8f888 | blueswir1 | { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3227 | eca8f888 | blueswir1 | { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3228 | eca8f888 | blueswir1 | { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3229 | eca8f888 | blueswir1 | { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3230 | eca8f888 | blueswir1 | { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3231 | eca8f888 | blueswir1 | { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3232 | eca8f888 | blueswir1 | { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3233 | eca8f888 | blueswir1 | { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3234 | eca8f888 | blueswir1 | { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3235 | eca8f888 | blueswir1 | { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3236 | eca8f888 | blueswir1 | { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3237 | eca8f888 | blueswir1 | { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3238 | eca8f888 | blueswir1 | { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3239 | eca8f888 | blueswir1 | { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3240 | eca8f888 | blueswir1 | { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3241 | eca8f888 | blueswir1 | { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3242 | eca8f888 | blueswir1 | { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3243 | eca8f888 | blueswir1 | { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3244 | eca8f888 | blueswir1 | { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3245 | eca8f888 | blueswir1 | { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3246 | eca8f888 | blueswir1 | { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3247 | eca8f888 | blueswir1 | { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3248 | eca8f888 | blueswir1 | { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3249 | eca8f888 | blueswir1 | { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3250 | eca8f888 | blueswir1 | { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3251 | eca8f888 | blueswir1 | { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3252 | eca8f888 | blueswir1 | { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3253 | eca8f888 | blueswir1 | { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3254 | eca8f888 | blueswir1 | { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3255 | eca8f888 | blueswir1 | { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3256 | eca8f888 | blueswir1 | { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3257 | eca8f888 | blueswir1 | { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3258 | eca8f888 | blueswir1 | { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3259 | eca8f888 | blueswir1 | { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3260 | eca8f888 | blueswir1 | { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3261 | eca8f888 | blueswir1 | { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3262 | eca8f888 | blueswir1 | { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3263 | eca8f888 | blueswir1 | { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3264 | eca8f888 | blueswir1 | { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3265 | eca8f888 | blueswir1 | { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3266 | eca8f888 | blueswir1 | { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3267 | eca8f888 | blueswir1 | { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3268 | eca8f888 | blueswir1 | { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3269 | eca8f888 | blueswir1 | { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3270 | eca8f888 | blueswir1 | { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3271 | eca8f888 | blueswir1 | { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3272 | eca8f888 | blueswir1 | { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3273 | eca8f888 | blueswir1 | { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3274 | eca8f888 | blueswir1 | { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3275 | eca8f888 | blueswir1 | { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3276 | eca8f888 | blueswir1 | { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3277 | eca8f888 | blueswir1 | { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3278 | eca8f888 | blueswir1 | { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3279 | eca8f888 | blueswir1 | { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3280 | eca8f888 | blueswir1 | { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3281 | eca8f888 | blueswir1 | { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3282 | eca8f888 | blueswir1 | { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
3283 | eca8f888 | blueswir1 | { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
3284 | eca8f888 | blueswir1 | { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3285 | eca8f888 | blueswir1 | { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3286 | eca8f888 | blueswir1 | { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
3287 | eca8f888 | blueswir1 | { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
3288 | eca8f888 | blueswir1 | { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3289 | eca8f888 | blueswir1 | { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3290 | eca8f888 | blueswir1 | { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3291 | eca8f888 | blueswir1 | { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3292 | eca8f888 | blueswir1 | { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3293 | eca8f888 | blueswir1 | { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3294 | eca8f888 | blueswir1 | { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3295 | eca8f888 | blueswir1 | { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3296 | eca8f888 | blueswir1 | { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3297 | eca8f888 | blueswir1 | { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3298 | eca8f888 | blueswir1 | { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
3299 | eca8f888 | blueswir1 | { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3300 | eca8f888 | blueswir1 | { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3301 | eca8f888 | blueswir1 | { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
3302 | eca8f888 | blueswir1 | { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
3303 | eca8f888 | blueswir1 | { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
3304 | eca8f888 | blueswir1 | { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3305 | eca8f888 | blueswir1 | { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3306 | eca8f888 | blueswir1 | { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
3307 | eca8f888 | blueswir1 | { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
3308 | eca8f888 | blueswir1 | { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3309 | eca8f888 | blueswir1 | { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3310 | eca8f888 | blueswir1 | { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3311 | eca8f888 | blueswir1 | { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
3312 | eca8f888 | blueswir1 | { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3313 | eca8f888 | blueswir1 | { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, |
3314 | eca8f888 | blueswir1 | { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
3315 | eca8f888 | blueswir1 | { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, |
3316 | ee8ae9e4 | blueswir1 | { "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } }, |
3317 | ee8ae9e4 | blueswir1 | { "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } }, |
3318 | eca8f888 | blueswir1 | |
3319 | eca8f888 | blueswir1 | { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3320 | eca8f888 | blueswir1 | { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3321 | eca8f888 | blueswir1 | |
3322 | eca8f888 | blueswir1 | { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3323 | eca8f888 | blueswir1 | { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3324 | eca8f888 | blueswir1 | |
3325 | eca8f888 | blueswir1 | { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, |
3326 | eca8f888 | blueswir1 | { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, |
3327 | eca8f888 | blueswir1 | { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3328 | eca8f888 | blueswir1 | { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3329 | eca8f888 | blueswir1 | { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, |
3330 | eca8f888 | blueswir1 | { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, |
3331 | eca8f888 | blueswir1 | { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
3332 | eca8f888 | blueswir1 | { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, |
3333 | eca8f888 | blueswir1 | |
3334 | eca8f888 | blueswir1 | { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, |
3335 | eca8f888 | blueswir1 | { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, |
3336 | eca8f888 | blueswir1 | |
3337 | eca8f888 | blueswir1 | { "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, |
3338 | eca8f888 | blueswir1 | { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, |
3339 | eca8f888 | blueswir1 | { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, |
3340 | eca8f888 | blueswir1 | { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, |
3341 | eca8f888 | blueswir1 | |
3342 | eca8f888 | blueswir1 | { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, |
3343 | eca8f888 | blueswir1 | { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, |
3344 | eca8f888 | blueswir1 | { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, |
3345 | eca8f888 | blueswir1 | { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, |
3346 | eca8f888 | blueswir1 | { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, |
3347 | eca8f888 | blueswir1 | { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, |
3348 | eca8f888 | blueswir1 | |
3349 | eca8f888 | blueswir1 | { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, |
3350 | eca8f888 | blueswir1 | { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3351 | eca8f888 | blueswir1 | { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3352 | eca8f888 | blueswir1 | |
3353 | eca8f888 | blueswir1 | { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3354 | eca8f888 | blueswir1 | { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3355 | eca8f888 | blueswir1 | |
3356 | eca8f888 | blueswir1 | { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3357 | eca8f888 | blueswir1 | { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3358 | eca8f888 | blueswir1 | |
3359 | eca8f888 | blueswir1 | { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3360 | eca8f888 | blueswir1 | { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3361 | eca8f888 | blueswir1 | |
3362 | eca8f888 | blueswir1 | { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3363 | eca8f888 | blueswir1 | { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3364 | eca8f888 | blueswir1 | |
3365 | eca8f888 | blueswir1 | { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, |
3366 | eca8f888 | blueswir1 | { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, |
3367 | eca8f888 | blueswir1 | |
3368 | eca8f888 | blueswir1 | { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, |
3369 | eca8f888 | blueswir1 | { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, |
3370 | eca8f888 | blueswir1 | { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3371 | eca8f888 | blueswir1 | { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, |
3372 | eca8f888 | blueswir1 | { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, |
3373 | eca8f888 | blueswir1 | { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3374 | eca8f888 | blueswir1 | |
3375 | eca8f888 | blueswir1 | { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, |
3376 | eca8f888 | blueswir1 | { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, |
3377 | eca8f888 | blueswir1 | |
3378 | eca8f888 | blueswir1 | { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3379 | eca8f888 | blueswir1 | { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3380 | eca8f888 | blueswir1 | |
3381 | eca8f888 | blueswir1 | { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3382 | eca8f888 | blueswir1 | { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, |
3383 | eca8f888 | blueswir1 | |
3384 | eca8f888 | blueswir1 | { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, |
3385 | eca8f888 | blueswir1 | { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, |
3386 | eca8f888 | blueswir1 | { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, |
3387 | eca8f888 | blueswir1 | { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, |
3388 | eca8f888 | blueswir1 | |
3389 | eca8f888 | blueswir1 | { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, |
3390 | eca8f888 | blueswir1 | { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, |
3391 | eca8f888 | blueswir1 | |
3392 | eca8f888 | blueswir1 | { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, |
3393 | eca8f888 | blueswir1 | { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, |
3394 | b9adb4a6 | bellard | { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, |
3395 | eca8f888 | blueswir1 | { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, |
3396 | eca8f888 | blueswir1 | |
3397 | eca8f888 | blueswir1 | { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, |
3398 | eca8f888 | blueswir1 | { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, |
3399 | eca8f888 | blueswir1 | { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, |
3400 | eca8f888 | blueswir1 | { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, |
3401 | eca8f888 | blueswir1 | { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, |
3402 | eca8f888 | blueswir1 | { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, |
3403 | eca8f888 | blueswir1 | { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, |
3404 | eca8f888 | blueswir1 | { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, |
3405 | eca8f888 | blueswir1 | { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, |
3406 | eca8f888 | blueswir1 | { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, |
3407 | eca8f888 | blueswir1 | { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, |
3408 | eca8f888 | blueswir1 | { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, |
3409 | eca8f888 | blueswir1 | { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, |
3410 | eca8f888 | blueswir1 | { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, |
3411 | eca8f888 | blueswir1 | { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, |
3412 | eca8f888 | blueswir1 | { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, |
3413 | eca8f888 | blueswir1 | { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, |
3414 | eca8f888 | blueswir1 | { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, |
3415 | eca8f888 | blueswir1 | { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, |
3416 | eca8f888 | blueswir1 | { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, |
3417 | eca8f888 | blueswir1 | { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, |
3418 | eca8f888 | blueswir1 | { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, |
3419 | eca8f888 | blueswir1 | { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, |
3420 | eca8f888 | blueswir1 | { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, |
3421 | eca8f888 | blueswir1 | { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, |
3422 | eca8f888 | blueswir1 | { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, |
3423 | eca8f888 | blueswir1 | { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, |
3424 | eca8f888 | blueswir1 | { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, |
3425 | eca8f888 | blueswir1 | { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, |
3426 | eca8f888 | blueswir1 | { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, |
3427 | eca8f888 | blueswir1 | { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, |
3428 | eca8f888 | blueswir1 | |
3429 | eca8f888 | blueswir1 | { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3430 | eca8f888 | blueswir1 | { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3431 | b9adb4a6 | bellard | { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
3432 | eca8f888 | blueswir1 | { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3433 | eca8f888 | blueswir1 | { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3434 | eca8f888 | blueswir1 | { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, |
3435 | eca8f888 | blueswir1 | { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3436 | eca8f888 | blueswir1 | { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3437 | b9adb4a6 | bellard | { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
3438 | eca8f888 | blueswir1 | { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3439 | eca8f888 | blueswir1 | { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3440 | b9adb4a6 | bellard | { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
3441 | b9adb4a6 | bellard | |
3442 | eca8f888 | blueswir1 | { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3443 | eca8f888 | blueswir1 | { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3444 | b9adb4a6 | bellard | |
3445 | eca8f888 | blueswir1 | { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3446 | eca8f888 | blueswir1 | { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3447 | eca8f888 | blueswir1 | { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3448 | eca8f888 | blueswir1 | { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3449 | eca8f888 | blueswir1 | { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3450 | eca8f888 | blueswir1 | { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3451 | eca8f888 | blueswir1 | { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3452 | eca8f888 | blueswir1 | { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3453 | b9adb4a6 | bellard | |
3454 | b9adb4a6 | bellard | { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
3455 | b9adb4a6 | bellard | { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
3456 | b9adb4a6 | bellard | |
3457 | eca8f888 | blueswir1 | { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, |
3458 | eca8f888 | blueswir1 | { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, |
3459 | eca8f888 | blueswir1 | { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, |
3460 | eca8f888 | blueswir1 | { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, |
3461 | eca8f888 | blueswir1 | |
3462 | eca8f888 | blueswir1 | { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, |
3463 | ee8ae9e4 | blueswir1 | { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, |
3464 | eca8f888 | blueswir1 | { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, |
3465 | eca8f888 | blueswir1 | |
3466 | ee8ae9e4 | blueswir1 | { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, |
3467 | eca8f888 | blueswir1 | |
3468 | eca8f888 | blueswir1 | { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, |
3469 | eca8f888 | blueswir1 | |
3470 | eca8f888 | blueswir1 | { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, |
3471 | eca8f888 | blueswir1 | { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, |
3472 | b9adb4a6 | bellard | |
3473 | eca8f888 | blueswir1 | { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, |
3474 | eca8f888 | blueswir1 | { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, |
3475 | b9adb4a6 | bellard | |
3476 | eca8f888 | blueswir1 | { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
3477 | eca8f888 | blueswir1 | { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, |
3478 | eca8f888 | blueswir1 | { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
3479 | eca8f888 | blueswir1 | { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, |
3480 | b9adb4a6 | bellard | |
3481 | eca8f888 | blueswir1 | { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, |
3482 | eca8f888 | blueswir1 | { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, |
3483 | eca8f888 | blueswir1 | { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, |
3484 | eca8f888 | blueswir1 | { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, |
3485 | b9adb4a6 | bellard | |
3486 | eca8f888 | blueswir1 | { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, |
3487 | eca8f888 | blueswir1 | { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, |
3488 | b9adb4a6 | bellard | |
3489 | eca8f888 | blueswir1 | { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, |
3490 | eca8f888 | blueswir1 | { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, |
3491 | b9adb4a6 | bellard | |
3492 | eca8f888 | blueswir1 | { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, |
3493 | eca8f888 | blueswir1 | { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, |
3494 | b9adb4a6 | bellard | |
3495 | eca8f888 | blueswir1 | { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, |
3496 | b9adb4a6 | bellard | |
3497 | eca8f888 | blueswir1 | { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3498 | b9adb4a6 | bellard | |
3499 | eca8f888 | blueswir1 | { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, |
3500 | eca8f888 | blueswir1 | { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, |
3501 | eca8f888 | blueswir1 | { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, |
3502 | eca8f888 | blueswir1 | { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, |
3503 | b9adb4a6 | bellard | |
3504 | b9adb4a6 | bellard | { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
3505 | b9adb4a6 | bellard | { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
3506 | b9adb4a6 | bellard | { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
3507 | b9adb4a6 | bellard | { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, |
3508 | b9adb4a6 | bellard | { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
3509 | b9adb4a6 | bellard | { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
3510 | b9adb4a6 | bellard | { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
3511 | b9adb4a6 | bellard | { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
3512 | b9adb4a6 | bellard | |
3513 | eca8f888 | blueswir1 | { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, |
3514 | b9adb4a6 | bellard | |
3515 | b9adb4a6 | bellard | { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, |
3516 | b9adb4a6 | bellard | |
3517 | eca8f888 | blueswir1 | { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, |
3518 | eca8f888 | blueswir1 | { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, |
3519 | eca8f888 | blueswir1 | |
3520 | eca8f888 | blueswir1 | { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, |
3521 | eca8f888 | blueswir1 | |
3522 | eca8f888 | blueswir1 | { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, |
3523 | eca8f888 | blueswir1 | |
3524 | eca8f888 | blueswir1 | { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, |
3525 | eca8f888 | blueswir1 | { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, |
3526 | eca8f888 | blueswir1 | |
3527 | eca8f888 | blueswir1 | { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, |
3528 | eca8f888 | blueswir1 | { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, |
3529 | eca8f888 | blueswir1 | |
3530 | eca8f888 | blueswir1 | { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, |
3531 | eca8f888 | blueswir1 | { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, |
3532 | eca8f888 | blueswir1 | { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, |
3533 | eca8f888 | blueswir1 | { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, |
3534 | eca8f888 | blueswir1 | { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, |
3535 | eca8f888 | blueswir1 | { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, |
3536 | eca8f888 | blueswir1 | { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, |
3537 | eca8f888 | blueswir1 | { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, |
3538 | eca8f888 | blueswir1 | { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, |
3539 | eca8f888 | blueswir1 | { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, |
3540 | eca8f888 | blueswir1 | { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, |
3541 | eca8f888 | blueswir1 | { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, |
3542 | eca8f888 | blueswir1 | { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, |
3543 | eca8f888 | blueswir1 | { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, |
3544 | eca8f888 | blueswir1 | { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, |
3545 | eca8f888 | blueswir1 | |
3546 | eca8f888 | blueswir1 | { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3547 | eca8f888 | blueswir1 | { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3548 | b9adb4a6 | bellard | |
3549 | b9adb4a6 | bellard | { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
3550 | b9adb4a6 | bellard | { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
3551 | b9adb4a6 | bellard | |
3552 | eca8f888 | blueswir1 | { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, |
3553 | eca8f888 | blueswir1 | { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, |
3554 | b9adb4a6 | bellard | |
3555 | eca8f888 | blueswir1 | { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, |
3556 | eca8f888 | blueswir1 | |
3557 | eca8f888 | blueswir1 | { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, |
3558 | eca8f888 | blueswir1 | |
3559 | ee8ae9e4 | blueswir1 | { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, |
3560 | b9adb4a6 | bellard | |
3561 | ee8ae9e4 | blueswir1 | { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, |
3562 | ee8ae9e4 | blueswir1 | { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } }, |
3563 | b9adb4a6 | bellard | |
3564 | eca8f888 | blueswir1 | { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, |
3565 | eca8f888 | blueswir1 | |
3566 | eca8f888 | blueswir1 | { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, |
3567 | eca8f888 | blueswir1 | |
3568 | eca8f888 | blueswir1 | { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3569 | eca8f888 | blueswir1 | |
3570 | eca8f888 | blueswir1 | { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, |
3571 | eca8f888 | blueswir1 | { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, |
3572 | eca8f888 | blueswir1 | { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, |
3573 | eca8f888 | blueswir1 | { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, |
3574 | eca8f888 | blueswir1 | |
3575 | eca8f888 | blueswir1 | { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, |
3576 | eca8f888 | blueswir1 | { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, |
3577 | eca8f888 | blueswir1 | { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, |
3578 | eca8f888 | blueswir1 | { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, |
3579 | eca8f888 | blueswir1 | |
3580 | eca8f888 | blueswir1 | { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, |
3581 | eca8f888 | blueswir1 | |
3582 | eca8f888 | blueswir1 | { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, |
3583 | eca8f888 | blueswir1 | |
3584 | eca8f888 | blueswir1 | { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, |
3585 | eca8f888 | blueswir1 | |
3586 | eca8f888 | blueswir1 | { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } }, |
3587 | eca8f888 | blueswir1 | |
3588 | eca8f888 | blueswir1 | { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, |
3589 | eca8f888 | blueswir1 | { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, |
3590 | eca8f888 | blueswir1 | { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, |
3591 | eca8f888 | blueswir1 | { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, |
3592 | eca8f888 | blueswir1 | |
3593 | eca8f888 | blueswir1 | { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3594 | eca8f888 | blueswir1 | |
3595 | eca8f888 | blueswir1 | { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, |
3596 | eca8f888 | blueswir1 | |
3597 | eca8f888 | blueswir1 | { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, |
3598 | eca8f888 | blueswir1 | |
3599 | eca8f888 | blueswir1 | { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, |
3600 | eca8f888 | blueswir1 | |
3601 | eca8f888 | blueswir1 | { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3602 | eca8f888 | blueswir1 | { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3603 | eca8f888 | blueswir1 | { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3604 | eca8f888 | blueswir1 | { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3605 | eca8f888 | blueswir1 | { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3606 | eca8f888 | blueswir1 | { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3607 | eca8f888 | blueswir1 | { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3608 | eca8f888 | blueswir1 | { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3609 | eca8f888 | blueswir1 | |
3610 | eca8f888 | blueswir1 | { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3611 | eca8f888 | blueswir1 | { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3612 | eca8f888 | blueswir1 | { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3613 | eca8f888 | blueswir1 | { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3614 | eca8f888 | blueswir1 | { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3615 | eca8f888 | blueswir1 | { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3616 | eca8f888 | blueswir1 | { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3617 | eca8f888 | blueswir1 | { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3618 | eca8f888 | blueswir1 | |
3619 | eca8f888 | blueswir1 | { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, |
3620 | eca8f888 | blueswir1 | |
3621 | eca8f888 | blueswir1 | { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, |
3622 | eca8f888 | blueswir1 | { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, |
3623 | eca8f888 | blueswir1 | { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, |
3624 | eca8f888 | blueswir1 | |
3625 | eca8f888 | blueswir1 | { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, |
3626 | eca8f888 | blueswir1 | |
3627 | eca8f888 | blueswir1 | { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, |
3628 | eca8f888 | blueswir1 | |
3629 | eca8f888 | blueswir1 | { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, |
3630 | eca8f888 | blueswir1 | |
3631 | eca8f888 | blueswir1 | { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, |
3632 | eca8f888 | blueswir1 | { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, |
3633 | eca8f888 | blueswir1 | |
3634 | eca8f888 | blueswir1 | { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, |
3635 | eca8f888 | blueswir1 | |
3636 | eca8f888 | blueswir1 | { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, |
3637 | b9adb4a6 | bellard | |
3638 | eca8f888 | blueswir1 | { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, |
3639 | eca8f888 | blueswir1 | { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, |
3640 | b9adb4a6 | bellard | |
3641 | eca8f888 | blueswir1 | { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, |
3642 | eca8f888 | blueswir1 | { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, |
3643 | b9adb4a6 | bellard | |
3644 | ee8ae9e4 | blueswir1 | { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, |
3645 | ee8ae9e4 | blueswir1 | |
3646 | eca8f888 | blueswir1 | { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, |
3647 | b9adb4a6 | bellard | |
3648 | eca8f888 | blueswir1 | { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, |
3649 | eca8f888 | blueswir1 | { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
3650 | b9adb4a6 | bellard | |
3651 | ee8ae9e4 | blueswir1 | { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } }, |
3652 | b9adb4a6 | bellard | |
3653 | eca8f888 | blueswir1 | { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, |
3654 | b9adb4a6 | bellard | |
3655 | eca8f888 | blueswir1 | { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, |
3656 | eca8f888 | blueswir1 | { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, |
3657 | b9adb4a6 | bellard | |
3658 | eca8f888 | blueswir1 | { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, |
3659 | eca8f888 | blueswir1 | { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, |
3660 | b9adb4a6 | bellard | |
3661 | ee8ae9e4 | blueswir1 | { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, |
3662 | ee8ae9e4 | blueswir1 | |
3663 | eca8f888 | blueswir1 | { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, |
3664 | b9adb4a6 | bellard | |
3665 | eca8f888 | blueswir1 | { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3666 | eca8f888 | blueswir1 | { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3667 | eca8f888 | blueswir1 | { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3668 | eca8f888 | blueswir1 | { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3669 | eca8f888 | blueswir1 | { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3670 | eca8f888 | blueswir1 | { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3671 | eca8f888 | blueswir1 | { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3672 | eca8f888 | blueswir1 | { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3673 | b9adb4a6 | bellard | |
3674 | eca8f888 | blueswir1 | { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3675 | eca8f888 | blueswir1 | { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3676 | eca8f888 | blueswir1 | { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3677 | eca8f888 | blueswir1 | { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3678 | eca8f888 | blueswir1 | { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3679 | eca8f888 | blueswir1 | { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3680 | eca8f888 | blueswir1 | { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3681 | eca8f888 | blueswir1 | { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3682 | b9adb4a6 | bellard | |
3683 | eca8f888 | blueswir1 | { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, |
3684 | b9adb4a6 | bellard | |
3685 | eca8f888 | blueswir1 | { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, |
3686 | b9adb4a6 | bellard | |
3687 | eca8f888 | blueswir1 | { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, |
3688 | b9adb4a6 | bellard | |
3689 | eca8f888 | blueswir1 | { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, |
3690 | eca8f888 | blueswir1 | { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, |
3691 | b9adb4a6 | bellard | |
3692 | eca8f888 | blueswir1 | { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, |
3693 | eca8f888 | blueswir1 | { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, |
3694 | b9adb4a6 | bellard | |
3695 | eca8f888 | blueswir1 | { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, |
3696 | b9adb4a6 | bellard | |
3697 | eca8f888 | blueswir1 | { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, |
3698 | b9adb4a6 | bellard | |
3699 | eca8f888 | blueswir1 | { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3700 | eca8f888 | blueswir1 | { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3701 | eca8f888 | blueswir1 | { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3702 | eca8f888 | blueswir1 | { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3703 | eca8f888 | blueswir1 | { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3704 | eca8f888 | blueswir1 | { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3705 | eca8f888 | blueswir1 | { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3706 | eca8f888 | blueswir1 | { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3707 | b9adb4a6 | bellard | |
3708 | eca8f888 | blueswir1 | { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3709 | eca8f888 | blueswir1 | { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3710 | eca8f888 | blueswir1 | { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, |
3711 | eca8f888 | blueswir1 | { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, |
3712 | b9adb4a6 | bellard | |
3713 | eca8f888 | blueswir1 | { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3714 | eca8f888 | blueswir1 | { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3715 | eca8f888 | blueswir1 | { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3716 | eca8f888 | blueswir1 | { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3717 | eca8f888 | blueswir1 | { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
3718 | eca8f888 | blueswir1 | { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, |
3719 | eca8f888 | blueswir1 | { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
3720 | eca8f888 | blueswir1 | { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, |
3721 | b9adb4a6 | bellard | |
3722 | eca8f888 | blueswir1 | { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3723 | eca8f888 | blueswir1 | { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3724 | eca8f888 | blueswir1 | { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3725 | eca8f888 | blueswir1 | { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3726 | eca8f888 | blueswir1 | { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3727 | eca8f888 | blueswir1 | { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3728 | eca8f888 | blueswir1 | { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3729 | eca8f888 | blueswir1 | { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3730 | b9adb4a6 | bellard | |
3731 | eca8f888 | blueswir1 | { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
3732 | eca8f888 | blueswir1 | { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, |
3733 | eca8f888 | blueswir1 | { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, |
3734 | b9adb4a6 | bellard | |
3735 | eca8f888 | blueswir1 | { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, |
3736 | b9adb4a6 | bellard | |
3737 | eca8f888 | blueswir1 | { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, |
3738 | eca8f888 | blueswir1 | |
3739 | eca8f888 | blueswir1 | { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, |
3740 | eca8f888 | blueswir1 | { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, |
3741 | eca8f888 | blueswir1 | |
3742 | eca8f888 | blueswir1 | { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, |
3743 | eca8f888 | blueswir1 | |
3744 | eca8f888 | blueswir1 | { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, |
3745 | eca8f888 | blueswir1 | |
3746 | eca8f888 | blueswir1 | { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, |
3747 | eca8f888 | blueswir1 | |
3748 | eca8f888 | blueswir1 | { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, |
3749 | eca8f888 | blueswir1 | { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, |
3750 | eca8f888 | blueswir1 | { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, |
3751 | eca8f888 | blueswir1 | { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, |
3752 | eca8f888 | blueswir1 | |
3753 | eca8f888 | blueswir1 | { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3754 | eca8f888 | blueswir1 | { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3755 | eca8f888 | blueswir1 | { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3756 | eca8f888 | blueswir1 | { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3757 | eca8f888 | blueswir1 | { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3758 | eca8f888 | blueswir1 | { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3759 | eca8f888 | blueswir1 | { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
3760 | eca8f888 | blueswir1 | { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, |
3761 | eca8f888 | blueswir1 | |
3762 | eca8f888 | blueswir1 | { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } }, |
3763 | eca8f888 | blueswir1 | |
3764 | eca8f888 | blueswir1 | { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, |
3765 | eca8f888 | blueswir1 | |
3766 | eca8f888 | blueswir1 | { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, |
3767 | eca8f888 | blueswir1 | { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, |
3768 | eca8f888 | blueswir1 | |
3769 | ee8ae9e4 | blueswir1 | { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, |
3770 | eca8f888 | blueswir1 | |
3771 | eca8f888 | blueswir1 | { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, |
3772 | eca8f888 | blueswir1 | |
3773 | eca8f888 | blueswir1 | { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, |
3774 | eca8f888 | blueswir1 | { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, |
3775 | eca8f888 | blueswir1 | |
3776 | eca8f888 | blueswir1 | { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, |
3777 | eca8f888 | blueswir1 | |
3778 | eca8f888 | blueswir1 | { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, |
3779 | eca8f888 | blueswir1 | |
3780 | eca8f888 | blueswir1 | { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, |
3781 | eca8f888 | blueswir1 | { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, |
3782 | b9adb4a6 | bellard | |
3783 | b9adb4a6 | bellard | { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, |
3784 | b9adb4a6 | bellard | |
3785 | eca8f888 | blueswir1 | { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, |
3786 | eca8f888 | blueswir1 | |
3787 | eca8f888 | blueswir1 | { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, |
3788 | eca8f888 | blueswir1 | { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, |
3789 | eca8f888 | blueswir1 | |
3790 | eca8f888 | blueswir1 | { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, |
3791 | eca8f888 | blueswir1 | |
3792 | eca8f888 | blueswir1 | { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, |
3793 | eca8f888 | blueswir1 | { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, |
3794 | eca8f888 | blueswir1 | { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, |
3795 | eca8f888 | blueswir1 | { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, |
3796 | eca8f888 | blueswir1 | { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, |
3797 | eca8f888 | blueswir1 | { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, |
3798 | eca8f888 | blueswir1 | { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, |
3799 | eca8f888 | blueswir1 | { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, |
3800 | eca8f888 | blueswir1 | { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, |
3801 | eca8f888 | blueswir1 | { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, |
3802 | eca8f888 | blueswir1 | { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, |
3803 | eca8f888 | blueswir1 | { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, |
3804 | eca8f888 | blueswir1 | { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, |
3805 | eca8f888 | blueswir1 | { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, |
3806 | eca8f888 | blueswir1 | { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, |
3807 | eca8f888 | blueswir1 | { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, |
3808 | eca8f888 | blueswir1 | { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, |
3809 | eca8f888 | blueswir1 | { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, |
3810 | eca8f888 | blueswir1 | { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, |
3811 | eca8f888 | blueswir1 | { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, |
3812 | eca8f888 | blueswir1 | { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, |
3813 | eca8f888 | blueswir1 | { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, |
3814 | eca8f888 | blueswir1 | { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, |
3815 | eca8f888 | blueswir1 | { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, |
3816 | eca8f888 | blueswir1 | { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, |
3817 | eca8f888 | blueswir1 | { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, |
3818 | eca8f888 | blueswir1 | { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, |
3819 | eca8f888 | blueswir1 | { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, |
3820 | eca8f888 | blueswir1 | { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, |
3821 | eca8f888 | blueswir1 | { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, |
3822 | eca8f888 | blueswir1 | { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, |
3823 | eca8f888 | blueswir1 | { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, |
3824 | eca8f888 | blueswir1 | { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, |
3825 | eca8f888 | blueswir1 | { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, |
3826 | eca8f888 | blueswir1 | { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, |
3827 | eca8f888 | blueswir1 | |
3828 | eca8f888 | blueswir1 | { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, |
3829 | eca8f888 | blueswir1 | { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, |
3830 | eca8f888 | blueswir1 | { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, |
3831 | eca8f888 | blueswir1 | { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, |
3832 | eca8f888 | blueswir1 | |
3833 | eca8f888 | blueswir1 | { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, |
3834 | eca8f888 | blueswir1 | |
3835 | eca8f888 | blueswir1 | { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, |
3836 | eca8f888 | blueswir1 | { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, |
3837 | eca8f888 | blueswir1 | { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, |
3838 | eca8f888 | blueswir1 | { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, |
3839 | eca8f888 | blueswir1 | { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, |
3840 | eca8f888 | blueswir1 | { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, |
3841 | eca8f888 | blueswir1 | { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, |
3842 | eca8f888 | blueswir1 | { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, |
3843 | eca8f888 | blueswir1 | { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, |
3844 | eca8f888 | blueswir1 | { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, |
3845 | eca8f888 | blueswir1 | { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, |
3846 | eca8f888 | blueswir1 | { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, |
3847 | eca8f888 | blueswir1 | { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, |
3848 | eca8f888 | blueswir1 | { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, |
3849 | eca8f888 | blueswir1 | { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, |
3850 | ee8ae9e4 | blueswir1 | { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } }, |
3851 | eca8f888 | blueswir1 | { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, |
3852 | eca8f888 | blueswir1 | { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, |
3853 | eca8f888 | blueswir1 | { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, |
3854 | eca8f888 | blueswir1 | { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, |
3855 | eca8f888 | blueswir1 | { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, |
3856 | eca8f888 | blueswir1 | { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, |
3857 | eca8f888 | blueswir1 | { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, |
3858 | eca8f888 | blueswir1 | { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, |
3859 | eca8f888 | blueswir1 | { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, |
3860 | eca8f888 | blueswir1 | { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, |
3861 | eca8f888 | blueswir1 | { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, |
3862 | eca8f888 | blueswir1 | { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, |
3863 | eca8f888 | blueswir1 | { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, |
3864 | eca8f888 | blueswir1 | { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, |
3865 | eca8f888 | blueswir1 | { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, |
3866 | eca8f888 | blueswir1 | { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, |
3867 | eca8f888 | blueswir1 | { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, |
3868 | eca8f888 | blueswir1 | { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, |
3869 | eca8f888 | blueswir1 | { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, |
3870 | eca8f888 | blueswir1 | { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, |
3871 | eca8f888 | blueswir1 | { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, |
3872 | eca8f888 | blueswir1 | { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, |
3873 | eca8f888 | blueswir1 | { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, |
3874 | eca8f888 | blueswir1 | { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, |
3875 | eca8f888 | blueswir1 | { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, |
3876 | eca8f888 | blueswir1 | { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, |
3877 | eca8f888 | blueswir1 | { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, |
3878 | eca8f888 | blueswir1 | { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, |
3879 | eca8f888 | blueswir1 | { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, |
3880 | eca8f888 | blueswir1 | { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, |
3881 | eca8f888 | blueswir1 | { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, |
3882 | eca8f888 | blueswir1 | { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, |
3883 | eca8f888 | blueswir1 | { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, |
3884 | eca8f888 | blueswir1 | { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } }, |
3885 | eca8f888 | blueswir1 | { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, |
3886 | eca8f888 | blueswir1 | { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, |
3887 | eca8f888 | blueswir1 | { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, |
3888 | eca8f888 | blueswir1 | { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, |
3889 | eca8f888 | blueswir1 | { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3890 | eca8f888 | blueswir1 | { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3891 | eca8f888 | blueswir1 | { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3892 | eca8f888 | blueswir1 | { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } }, |
3893 | eca8f888 | blueswir1 | { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, |
3894 | eca8f888 | blueswir1 | { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, |
3895 | eca8f888 | blueswir1 | { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, |
3896 | eca8f888 | blueswir1 | { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, |
3897 | eca8f888 | blueswir1 | { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, |
3898 | eca8f888 | blueswir1 | { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, |
3899 | eca8f888 | blueswir1 | { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, |
3900 | eca8f888 | blueswir1 | { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, |
3901 | eca8f888 | blueswir1 | { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, |
3902 | eca8f888 | blueswir1 | { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, |
3903 | eca8f888 | blueswir1 | { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, |
3904 | eca8f888 | blueswir1 | { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, |
3905 | eca8f888 | blueswir1 | { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, |
3906 | eca8f888 | blueswir1 | { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, |
3907 | eca8f888 | blueswir1 | { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, |
3908 | eca8f888 | blueswir1 | { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, |
3909 | eca8f888 | blueswir1 | { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, |
3910 | eca8f888 | blueswir1 | { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, |
3911 | eca8f888 | blueswir1 | { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, |
3912 | eca8f888 | blueswir1 | { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, |
3913 | eca8f888 | blueswir1 | { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, |
3914 | eca8f888 | blueswir1 | { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, |
3915 | eca8f888 | blueswir1 | { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, |
3916 | eca8f888 | blueswir1 | { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, |
3917 | eca8f888 | blueswir1 | { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, |
3918 | eca8f888 | blueswir1 | { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, |
3919 | eca8f888 | blueswir1 | { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, |
3920 | eca8f888 | blueswir1 | { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, |
3921 | eca8f888 | blueswir1 | { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, |
3922 | eca8f888 | blueswir1 | { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, |
3923 | eca8f888 | blueswir1 | { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, |
3924 | eca8f888 | blueswir1 | { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, |
3925 | eca8f888 | blueswir1 | { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, |
3926 | eca8f888 | blueswir1 | { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, |
3927 | eca8f888 | blueswir1 | { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, |
3928 | eca8f888 | blueswir1 | { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, |
3929 | eca8f888 | blueswir1 | { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, |
3930 | eca8f888 | blueswir1 | { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, |
3931 | eca8f888 | blueswir1 | { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, |
3932 | eca8f888 | blueswir1 | { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, |
3933 | eca8f888 | blueswir1 | { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, |
3934 | eca8f888 | blueswir1 | { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, |
3935 | eca8f888 | blueswir1 | { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, |
3936 | eca8f888 | blueswir1 | { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, |
3937 | eca8f888 | blueswir1 | { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, |
3938 | eca8f888 | blueswir1 | { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, |
3939 | eca8f888 | blueswir1 | { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, |
3940 | eca8f888 | blueswir1 | { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, |
3941 | eca8f888 | blueswir1 | { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, |
3942 | eca8f888 | blueswir1 | { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, |
3943 | eca8f888 | blueswir1 | { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, |
3944 | eca8f888 | blueswir1 | { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, |
3945 | eca8f888 | blueswir1 | { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, |
3946 | eca8f888 | blueswir1 | { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, |
3947 | eca8f888 | blueswir1 | { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3948 | eca8f888 | blueswir1 | { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3949 | eca8f888 | blueswir1 | { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3950 | eca8f888 | blueswir1 | { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
3951 | eca8f888 | blueswir1 | { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, |
3952 | eca8f888 | blueswir1 | { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, |
3953 | eca8f888 | blueswir1 | { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, |
3954 | eca8f888 | blueswir1 | { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, |
3955 | eca8f888 | blueswir1 | { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, |
3956 | eca8f888 | blueswir1 | { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, |
3957 | eca8f888 | blueswir1 | { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, |
3958 | eca8f888 | blueswir1 | { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, |
3959 | eca8f888 | blueswir1 | { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, |
3960 | eca8f888 | blueswir1 | { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, |
3961 | eca8f888 | blueswir1 | { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, |
3962 | eca8f888 | blueswir1 | { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, |
3963 | eca8f888 | blueswir1 | { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, |
3964 | eca8f888 | blueswir1 | { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, |
3965 | eca8f888 | blueswir1 | { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, |
3966 | eca8f888 | blueswir1 | { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, |
3967 | eca8f888 | blueswir1 | { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, |
3968 | eca8f888 | blueswir1 | { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, |
3969 | eca8f888 | blueswir1 | { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, |
3970 | eca8f888 | blueswir1 | { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, |
3971 | eca8f888 | blueswir1 | { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, |
3972 | eca8f888 | blueswir1 | { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, |
3973 | eca8f888 | blueswir1 | { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, |
3974 | eca8f888 | blueswir1 | { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, |
3975 | eca8f888 | blueswir1 | { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, |
3976 | eca8f888 | blueswir1 | { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, |
3977 | eca8f888 | blueswir1 | { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, |
3978 | eca8f888 | blueswir1 | { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, |
3979 | eca8f888 | blueswir1 | { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, |
3980 | eca8f888 | blueswir1 | { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, |
3981 | eca8f888 | blueswir1 | { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, |
3982 | eca8f888 | blueswir1 | { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, |
3983 | eca8f888 | blueswir1 | { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, |
3984 | eca8f888 | blueswir1 | { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, |
3985 | eca8f888 | blueswir1 | { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, |
3986 | eca8f888 | blueswir1 | { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, |
3987 | eca8f888 | blueswir1 | { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, |
3988 | eca8f888 | blueswir1 | { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, |
3989 | eca8f888 | blueswir1 | { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, |
3990 | eca8f888 | blueswir1 | { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, |
3991 | eca8f888 | blueswir1 | { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, |
3992 | eca8f888 | blueswir1 | { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, |
3993 | eca8f888 | blueswir1 | { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, |
3994 | eca8f888 | blueswir1 | { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, |
3995 | eca8f888 | blueswir1 | { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, |
3996 | eca8f888 | blueswir1 | { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, |
3997 | eca8f888 | blueswir1 | { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, |
3998 | eca8f888 | blueswir1 | { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, |
3999 | eca8f888 | blueswir1 | { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, |
4000 | eca8f888 | blueswir1 | { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, |
4001 | eca8f888 | blueswir1 | { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, |
4002 | eca8f888 | blueswir1 | { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, |
4003 | eca8f888 | blueswir1 | { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, |
4004 | eca8f888 | blueswir1 | { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, |
4005 | eca8f888 | blueswir1 | { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, |
4006 | eca8f888 | blueswir1 | { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, |
4007 | eca8f888 | blueswir1 | { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, |
4008 | eca8f888 | blueswir1 | { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, |
4009 | eca8f888 | blueswir1 | { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, |
4010 | eca8f888 | blueswir1 | { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, |
4011 | eca8f888 | blueswir1 | { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, |
4012 | eca8f888 | blueswir1 | { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, |
4013 | eca8f888 | blueswir1 | { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, |
4014 | eca8f888 | blueswir1 | { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, |
4015 | eca8f888 | blueswir1 | { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, |
4016 | eca8f888 | blueswir1 | { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, |
4017 | eca8f888 | blueswir1 | { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, |
4018 | eca8f888 | blueswir1 | { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, |
4019 | eca8f888 | blueswir1 | { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, |
4020 | eca8f888 | blueswir1 | { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, |
4021 | eca8f888 | blueswir1 | { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, |
4022 | eca8f888 | blueswir1 | { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, |
4023 | eca8f888 | blueswir1 | |
4024 | eca8f888 | blueswir1 | { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, |
4025 | eca8f888 | blueswir1 | |
4026 | eca8f888 | blueswir1 | { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4027 | eca8f888 | blueswir1 | { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4028 | eca8f888 | blueswir1 | |
4029 | eca8f888 | blueswir1 | { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, |
4030 | eca8f888 | blueswir1 | |
4031 | eca8f888 | blueswir1 | { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4032 | eca8f888 | blueswir1 | |
4033 | eca8f888 | blueswir1 | { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4034 | eca8f888 | blueswir1 | { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
4035 | eca8f888 | blueswir1 | |
4036 | eca8f888 | blueswir1 | { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, |
4037 | eca8f888 | blueswir1 | |
4038 | eca8f888 | blueswir1 | { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, |
4039 | eca8f888 | blueswir1 | { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, |
4040 | eca8f888 | blueswir1 | { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, |
4041 | eca8f888 | blueswir1 | { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, |
4042 | eca8f888 | blueswir1 | |
4043 | eca8f888 | blueswir1 | { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, |
4044 | eca8f888 | blueswir1 | { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, |
4045 | eca8f888 | blueswir1 | { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, |
4046 | eca8f888 | blueswir1 | { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, |
4047 | b9adb4a6 | bellard | |
4048 | b9adb4a6 | bellard | { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, |
4049 | b9adb4a6 | bellard | |
4050 | eca8f888 | blueswir1 | { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, |
4051 | eca8f888 | blueswir1 | |
4052 | eca8f888 | blueswir1 | { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, |
4053 | eca8f888 | blueswir1 | |
4054 | eca8f888 | blueswir1 | { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, |
4055 | eca8f888 | blueswir1 | |
4056 | eca8f888 | blueswir1 | { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, |
4057 | eca8f888 | blueswir1 | |
4058 | eca8f888 | blueswir1 | { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, |
4059 | b9adb4a6 | bellard | |
4060 | eca8f888 | blueswir1 | { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4061 | eca8f888 | blueswir1 | { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4062 | b9adb4a6 | bellard | |
4063 | eca8f888 | blueswir1 | { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4064 | eca8f888 | blueswir1 | { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, |
4065 | b9adb4a6 | bellard | |
4066 | eca8f888 | blueswir1 | { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
4067 | eca8f888 | blueswir1 | |
4068 | eca8f888 | blueswir1 | { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, |
4069 | eca8f888 | blueswir1 | |
4070 | eca8f888 | blueswir1 | { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, |
4071 | b9adb4a6 | bellard | |
4072 | ee8ae9e4 | blueswir1 | { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } }, |
4073 | ee8ae9e4 | blueswir1 | |
4074 | b9adb4a6 | bellard | { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, |
4075 | b9adb4a6 | bellard | |
4076 | ee8ae9e4 | blueswir1 | { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } }, |
4077 | ee8ae9e4 | blueswir1 | |
4078 | b9adb4a6 | bellard | { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, |
4079 | b9adb4a6 | bellard | |
4080 | b9adb4a6 | bellard | { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, |
4081 | b9adb4a6 | bellard | |
4082 | ee8ae9e4 | blueswir1 | { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } }, |
4083 | ee8ae9e4 | blueswir1 | |
4084 | b9adb4a6 | bellard | { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, |
4085 | b9adb4a6 | bellard | |
4086 | eca8f888 | blueswir1 | { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, |
4087 | eca8f888 | blueswir1 | { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, |
4088 | b9adb4a6 | bellard | |
4089 | eca8f888 | blueswir1 | { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, |
4090 | eca8f888 | blueswir1 | { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, |
4091 | b9adb4a6 | bellard | |
4092 | eca8f888 | blueswir1 | { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4093 | b9adb4a6 | bellard | |
4094 | eca8f888 | blueswir1 | { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, |
4095 | b9adb4a6 | bellard | |
4096 | eca8f888 | blueswir1 | { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, |
4097 | b9adb4a6 | bellard | |
4098 | eca8f888 | blueswir1 | { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, |
4099 | eca8f888 | blueswir1 | |
4100 | eca8f888 | blueswir1 | { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, |
4101 | eca8f888 | blueswir1 | |
4102 | ee8ae9e4 | blueswir1 | { "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }}, |
4103 | ee8ae9e4 | blueswir1 | { "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }}, |
4104 | ee8ae9e4 | blueswir1 | { "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }}, |
4105 | ee8ae9e4 | blueswir1 | { "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }}, |
4106 | ee8ae9e4 | blueswir1 | { "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }}, |
4107 | ee8ae9e4 | blueswir1 | { "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }}, |
4108 | ee8ae9e4 | blueswir1 | { "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }}, |
4109 | eca8f888 | blueswir1 | { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, |
4110 | eca8f888 | blueswir1 | { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, |
4111 | eca8f888 | blueswir1 | { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, |
4112 | eca8f888 | blueswir1 | { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, |
4113 | eca8f888 | blueswir1 | |
4114 | eca8f888 | blueswir1 | { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, |
4115 | eca8f888 | blueswir1 | { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, |
4116 | eca8f888 | blueswir1 | { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, |
4117 | eca8f888 | blueswir1 | { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, |
4118 | eca8f888 | blueswir1 | { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, |
4119 | eca8f888 | blueswir1 | { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, |
4120 | eca8f888 | blueswir1 | { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, |
4121 | eca8f888 | blueswir1 | { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, |
4122 | eca8f888 | blueswir1 | { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, |
4123 | eca8f888 | blueswir1 | { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, |
4124 | eca8f888 | blueswir1 | { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, |
4125 | eca8f888 | blueswir1 | { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, |
4126 | eca8f888 | blueswir1 | { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, |
4127 | eca8f888 | blueswir1 | { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, |
4128 | eca8f888 | blueswir1 | { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, |
4129 | eca8f888 | blueswir1 | { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, |
4130 | eca8f888 | blueswir1 | { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, |
4131 | eca8f888 | blueswir1 | { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, |
4132 | eca8f888 | blueswir1 | { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, |
4133 | eca8f888 | blueswir1 | { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, |
4134 | eca8f888 | blueswir1 | { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, |
4135 | eca8f888 | blueswir1 | { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, |
4136 | eca8f888 | blueswir1 | { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, |
4137 | eca8f888 | blueswir1 | { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, |
4138 | eca8f888 | blueswir1 | { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, |
4139 | eca8f888 | blueswir1 | { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, |
4140 | eca8f888 | blueswir1 | { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, |
4141 | eca8f888 | blueswir1 | { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, |
4142 | eca8f888 | blueswir1 | { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, |
4143 | eca8f888 | blueswir1 | { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, |
4144 | eca8f888 | blueswir1 | { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, |
4145 | eca8f888 | blueswir1 | { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, |
4146 | eca8f888 | blueswir1 | { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, |
4147 | eca8f888 | blueswir1 | { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, |
4148 | eca8f888 | blueswir1 | { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, |
4149 | eca8f888 | blueswir1 | |
4150 | eca8f888 | blueswir1 | { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4151 | eca8f888 | blueswir1 | { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4152 | eca8f888 | blueswir1 | |
4153 | eca8f888 | blueswir1 | { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4154 | eca8f888 | blueswir1 | { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4155 | eca8f888 | blueswir1 | { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4156 | eca8f888 | blueswir1 | { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4157 | eca8f888 | blueswir1 | |
4158 | eca8f888 | blueswir1 | { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4159 | eca8f888 | blueswir1 | { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4160 | b9adb4a6 | bellard | |
4161 | b9adb4a6 | bellard | { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
4162 | b9adb4a6 | bellard | { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
4163 | b9adb4a6 | bellard | { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
4164 | b9adb4a6 | bellard | { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
4165 | b9adb4a6 | bellard | |
4166 | eca8f888 | blueswir1 | { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, |
4167 | eca8f888 | blueswir1 | { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, |
4168 | eca8f888 | blueswir1 | { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, |
4169 | eca8f888 | blueswir1 | { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, |
4170 | eca8f888 | blueswir1 | { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, |
4171 | eca8f888 | blueswir1 | { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, |
4172 | eca8f888 | blueswir1 | { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, |
4173 | eca8f888 | blueswir1 | { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, |
4174 | eca8f888 | blueswir1 | { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, |
4175 | eca8f888 | blueswir1 | { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, |
4176 | eca8f888 | blueswir1 | { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, |
4177 | eca8f888 | blueswir1 | { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, |
4178 | eca8f888 | blueswir1 | { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, |
4179 | eca8f888 | blueswir1 | { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, |
4180 | ee8ae9e4 | blueswir1 | { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } }, |
4181 | eca8f888 | blueswir1 | { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, |
4182 | eca8f888 | blueswir1 | { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, |
4183 | eca8f888 | blueswir1 | { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, |
4184 | eca8f888 | blueswir1 | { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, |
4185 | eca8f888 | blueswir1 | { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, |
4186 | eca8f888 | blueswir1 | { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, |
4187 | eca8f888 | blueswir1 | { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, |
4188 | eca8f888 | blueswir1 | { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, |
4189 | eca8f888 | blueswir1 | { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, |
4190 | eca8f888 | blueswir1 | { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, |
4191 | eca8f888 | blueswir1 | { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, |
4192 | eca8f888 | blueswir1 | { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, |
4193 | eca8f888 | blueswir1 | { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, |
4194 | eca8f888 | blueswir1 | { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, |
4195 | eca8f888 | blueswir1 | { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, |
4196 | eca8f888 | blueswir1 | { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, |
4197 | eca8f888 | blueswir1 | { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, |
4198 | eca8f888 | blueswir1 | { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, |
4199 | eca8f888 | blueswir1 | { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, |
4200 | eca8f888 | blueswir1 | { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, |
4201 | eca8f888 | blueswir1 | { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, |
4202 | eca8f888 | blueswir1 | { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, |
4203 | eca8f888 | blueswir1 | { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, |
4204 | eca8f888 | blueswir1 | { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, |
4205 | eca8f888 | blueswir1 | { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, |
4206 | eca8f888 | blueswir1 | { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, |
4207 | eca8f888 | blueswir1 | { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, |
4208 | eca8f888 | blueswir1 | { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, |
4209 | eca8f888 | blueswir1 | { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } }, |
4210 | eca8f888 | blueswir1 | { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, |
4211 | eca8f888 | blueswir1 | { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, |
4212 | eca8f888 | blueswir1 | { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, |
4213 | eca8f888 | blueswir1 | { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, |
4214 | eca8f888 | blueswir1 | { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4215 | eca8f888 | blueswir1 | { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4216 | eca8f888 | blueswir1 | { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4217 | eca8f888 | blueswir1 | { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, |
4218 | eca8f888 | blueswir1 | { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, |
4219 | eca8f888 | blueswir1 | { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, |
4220 | eca8f888 | blueswir1 | { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, |
4221 | eca8f888 | blueswir1 | { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, |
4222 | eca8f888 | blueswir1 | { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, |
4223 | eca8f888 | blueswir1 | { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, |
4224 | eca8f888 | blueswir1 | { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, |
4225 | eca8f888 | blueswir1 | { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, |
4226 | eca8f888 | blueswir1 | { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, |
4227 | eca8f888 | blueswir1 | { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, |
4228 | eca8f888 | blueswir1 | { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, |
4229 | eca8f888 | blueswir1 | { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, |
4230 | eca8f888 | blueswir1 | { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, |
4231 | eca8f888 | blueswir1 | { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, |
4232 | eca8f888 | blueswir1 | { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, |
4233 | eca8f888 | blueswir1 | { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, |
4234 | eca8f888 | blueswir1 | { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, |
4235 | eca8f888 | blueswir1 | { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, |
4236 | eca8f888 | blueswir1 | { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, |
4237 | eca8f888 | blueswir1 | { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, |
4238 | eca8f888 | blueswir1 | { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, |
4239 | eca8f888 | blueswir1 | { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, |
4240 | eca8f888 | blueswir1 | { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, |
4241 | eca8f888 | blueswir1 | { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, |
4242 | eca8f888 | blueswir1 | { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, |
4243 | eca8f888 | blueswir1 | { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, |
4244 | eca8f888 | blueswir1 | { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, |
4245 | eca8f888 | blueswir1 | { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, |
4246 | eca8f888 | blueswir1 | { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, |
4247 | eca8f888 | blueswir1 | { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, |
4248 | eca8f888 | blueswir1 | { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, |
4249 | eca8f888 | blueswir1 | { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, |
4250 | eca8f888 | blueswir1 | { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, |
4251 | eca8f888 | blueswir1 | { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, |
4252 | eca8f888 | blueswir1 | { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, |
4253 | eca8f888 | blueswir1 | { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, |
4254 | eca8f888 | blueswir1 | { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, |
4255 | eca8f888 | blueswir1 | { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, |
4256 | eca8f888 | blueswir1 | { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, |
4257 | eca8f888 | blueswir1 | { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, |
4258 | eca8f888 | blueswir1 | { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, |
4259 | eca8f888 | blueswir1 | { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, |
4260 | eca8f888 | blueswir1 | { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, |
4261 | eca8f888 | blueswir1 | { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, |
4262 | eca8f888 | blueswir1 | { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, |
4263 | eca8f888 | blueswir1 | { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, |
4264 | eca8f888 | blueswir1 | { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, |
4265 | eca8f888 | blueswir1 | { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, |
4266 | eca8f888 | blueswir1 | { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, |
4267 | eca8f888 | blueswir1 | { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, |
4268 | eca8f888 | blueswir1 | { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, |
4269 | eca8f888 | blueswir1 | { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, |
4270 | eca8f888 | blueswir1 | { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, |
4271 | eca8f888 | blueswir1 | { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, |
4272 | eca8f888 | blueswir1 | { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4273 | eca8f888 | blueswir1 | { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4274 | eca8f888 | blueswir1 | { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4275 | eca8f888 | blueswir1 | { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
4276 | eca8f888 | blueswir1 | { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, |
4277 | eca8f888 | blueswir1 | { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, |
4278 | eca8f888 | blueswir1 | { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, |
4279 | eca8f888 | blueswir1 | { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, |
4280 | eca8f888 | blueswir1 | { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, |
4281 | eca8f888 | blueswir1 | { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, |
4282 | eca8f888 | blueswir1 | { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, |
4283 | eca8f888 | blueswir1 | { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, |
4284 | eca8f888 | blueswir1 | { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, |
4285 | eca8f888 | blueswir1 | { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, |
4286 | eca8f888 | blueswir1 | { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, |
4287 | eca8f888 | blueswir1 | { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, |
4288 | eca8f888 | blueswir1 | { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, |
4289 | eca8f888 | blueswir1 | { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, |
4290 | eca8f888 | blueswir1 | { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, |
4291 | eca8f888 | blueswir1 | { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, |
4292 | eca8f888 | blueswir1 | { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, |
4293 | eca8f888 | blueswir1 | { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, |
4294 | eca8f888 | blueswir1 | { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, |
4295 | eca8f888 | blueswir1 | { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, |
4296 | eca8f888 | blueswir1 | { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, |
4297 | eca8f888 | blueswir1 | { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, |
4298 | eca8f888 | blueswir1 | { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, |
4299 | eca8f888 | blueswir1 | { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, |
4300 | eca8f888 | blueswir1 | { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, |
4301 | eca8f888 | blueswir1 | { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, |
4302 | eca8f888 | blueswir1 | { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, |
4303 | eca8f888 | blueswir1 | { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, |
4304 | eca8f888 | blueswir1 | { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, |
4305 | eca8f888 | blueswir1 | { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, |
4306 | eca8f888 | blueswir1 | { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, |
4307 | eca8f888 | blueswir1 | { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, |
4308 | eca8f888 | blueswir1 | { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, |
4309 | eca8f888 | blueswir1 | { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, |
4310 | eca8f888 | blueswir1 | { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, |
4311 | eca8f888 | blueswir1 | { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, |
4312 | eca8f888 | blueswir1 | { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, |
4313 | eca8f888 | blueswir1 | { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, |
4314 | eca8f888 | blueswir1 | { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, |
4315 | eca8f888 | blueswir1 | { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, |
4316 | eca8f888 | blueswir1 | { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, |
4317 | eca8f888 | blueswir1 | { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, |
4318 | eca8f888 | blueswir1 | { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, |
4319 | b9adb4a6 | bellard | |
4320 | b9adb4a6 | bellard | { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, |
4321 | b9adb4a6 | bellard | |
4322 | eca8f888 | blueswir1 | { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, |
4323 | eca8f888 | blueswir1 | { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, |
4324 | b9adb4a6 | bellard | |
4325 | eca8f888 | blueswir1 | { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, |
4326 | b9adb4a6 | bellard | |
4327 | eca8f888 | blueswir1 | { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, |
4328 | eca8f888 | blueswir1 | |
4329 | eca8f888 | blueswir1 | { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, |
4330 | eca8f888 | blueswir1 | |
4331 | eca8f888 | blueswir1 | { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, |
4332 | eca8f888 | blueswir1 | |
4333 | eca8f888 | blueswir1 | { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, |
4334 | eca8f888 | blueswir1 | { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4335 | eca8f888 | blueswir1 | { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, |
4336 | eca8f888 | blueswir1 | { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, |
4337 | eca8f888 | blueswir1 | { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4338 | eca8f888 | blueswir1 | { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, |
4339 | eca8f888 | blueswir1 | |
4340 | eca8f888 | blueswir1 | { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4341 | eca8f888 | blueswir1 | { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4342 | eca8f888 | blueswir1 | { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, |
4343 | eca8f888 | blueswir1 | { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, |
4344 | eca8f888 | blueswir1 | |
4345 | eca8f888 | blueswir1 | { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4346 | eca8f888 | blueswir1 | { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, |
4347 | b9adb4a6 | bellard | |
4348 | b9adb4a6 | bellard | { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
4349 | b9adb4a6 | bellard | { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
4350 | b9adb4a6 | bellard | { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
4351 | b9adb4a6 | bellard | { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
4352 | b9adb4a6 | bellard | |
4353 | eca8f888 | blueswir1 | { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, |
4354 | eca8f888 | blueswir1 | |
4355 | eca8f888 | blueswir1 | { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, |
4356 | b9adb4a6 | bellard | |
4357 | b9adb4a6 | bellard | { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, |
4358 | b9adb4a6 | bellard | |
4359 | eca8f888 | blueswir1 | { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, |
4360 | eca8f888 | blueswir1 | |
4361 | eca8f888 | blueswir1 | { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, |
4362 | b9adb4a6 | bellard | |
4363 | eca8f888 | blueswir1 | { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, |
4364 | eca8f888 | blueswir1 | { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, |
4365 | b9adb4a6 | bellard | |
4366 | eca8f888 | blueswir1 | { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, |
4367 | b9adb4a6 | bellard | |
4368 | ee8ae9e4 | blueswir1 | { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, |
4369 | ee8ae9e4 | blueswir1 | |
4370 | eca8f888 | blueswir1 | { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, |
4371 | eca8f888 | blueswir1 | { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, |
4372 | b9adb4a6 | bellard | |
4373 | eca8f888 | blueswir1 | { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, |
4374 | eca8f888 | blueswir1 | { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, |
4375 | b9adb4a6 | bellard | |
4376 | eca8f888 | blueswir1 | { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, |
4377 | b9adb4a6 | bellard | |
4378 | eca8f888 | blueswir1 | { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
4379 | eca8f888 | blueswir1 | { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, |
4380 | eca8f888 | blueswir1 | { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
4381 | eca8f888 | blueswir1 | { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, |
4382 | b9adb4a6 | bellard | |
4383 | eca8f888 | blueswir1 | { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, |
4384 | eca8f888 | blueswir1 | { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, |
4385 | b9adb4a6 | bellard | |
4386 | eca8f888 | blueswir1 | { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, |
4387 | eca8f888 | blueswir1 | { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, |
4388 | eca8f888 | blueswir1 | |
4389 | eca8f888 | blueswir1 | { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, |
4390 | eca8f888 | blueswir1 | { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, |
4391 | eca8f888 | blueswir1 | |
4392 | eca8f888 | blueswir1 | { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4393 | eca8f888 | blueswir1 | |
4394 | eca8f888 | blueswir1 | { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, |
4395 | eca8f888 | blueswir1 | |
4396 | eca8f888 | blueswir1 | { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, |
4397 | b9adb4a6 | bellard | |
4398 | b9adb4a6 | bellard | { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, |
4399 | b9adb4a6 | bellard | |
4400 | eca8f888 | blueswir1 | { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, |
4401 | eca8f888 | blueswir1 | |
4402 | eca8f888 | blueswir1 | { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, |
4403 | eca8f888 | blueswir1 | |
4404 | eca8f888 | blueswir1 | { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, |
4405 | eca8f888 | blueswir1 | |
4406 | eca8f888 | blueswir1 | { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, |
4407 | eca8f888 | blueswir1 | { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, |
4408 | eca8f888 | blueswir1 | |
4409 | eca8f888 | blueswir1 | { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, |
4410 | eca8f888 | blueswir1 | { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, |
4411 | eca8f888 | blueswir1 | { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, |
4412 | eca8f888 | blueswir1 | { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, |
4413 | eca8f888 | blueswir1 | { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, |
4414 | eca8f888 | blueswir1 | |
4415 | eca8f888 | blueswir1 | { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, |
4416 | eca8f888 | blueswir1 | |
4417 | eca8f888 | blueswir1 | { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, |
4418 | eca8f888 | blueswir1 | |
4419 | ee8ae9e4 | blueswir1 | { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, |
4420 | ee8ae9e4 | blueswir1 | |
4421 | eca8f888 | blueswir1 | { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, |
4422 | eca8f888 | blueswir1 | |
4423 | eca8f888 | blueswir1 | { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, |
4424 | eca8f888 | blueswir1 | |
4425 | eca8f888 | blueswir1 | { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, |
4426 | eca8f888 | blueswir1 | |
4427 | eca8f888 | blueswir1 | { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, |
4428 | eca8f888 | blueswir1 | |
4429 | eca8f888 | blueswir1 | { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, |
4430 | eca8f888 | blueswir1 | |
4431 | ee8ae9e4 | blueswir1 | { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, |
4432 | ee8ae9e4 | blueswir1 | |
4433 | eca8f888 | blueswir1 | { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, |
4434 | eca8f888 | blueswir1 | { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, |
4435 | eca8f888 | blueswir1 | |
4436 | eca8f888 | blueswir1 | { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, |
4437 | eca8f888 | blueswir1 | { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, |
4438 | eca8f888 | blueswir1 | |
4439 | eca8f888 | blueswir1 | { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, |
4440 | b9adb4a6 | bellard | |
4441 | eca8f888 | blueswir1 | { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, |
4442 | eca8f888 | blueswir1 | { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, |
4443 | b9adb4a6 | bellard | |
4444 | eca8f888 | blueswir1 | { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, |
4445 | eca8f888 | blueswir1 | { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, |
4446 | b9adb4a6 | bellard | |
4447 | eca8f888 | blueswir1 | { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4448 | b9adb4a6 | bellard | |
4449 | eca8f888 | blueswir1 | { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, |
4450 | b9adb4a6 | bellard | |
4451 | eca8f888 | blueswir1 | { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, |
4452 | b9adb4a6 | bellard | |
4453 | eca8f888 | blueswir1 | { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, |
4454 | eca8f888 | blueswir1 | { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, |
4455 | b9adb4a6 | bellard | |
4456 | eca8f888 | blueswir1 | { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, |
4457 | b9adb4a6 | bellard | |
4458 | eca8f888 | blueswir1 | { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, |
4459 | eca8f888 | blueswir1 | { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, |
4460 | b9adb4a6 | bellard | |
4461 | eca8f888 | blueswir1 | { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, |
4462 | b9adb4a6 | bellard | |
4463 | eca8f888 | blueswir1 | { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, |
4464 | eca8f888 | blueswir1 | { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, |
4465 | b9adb4a6 | bellard | |
4466 | eca8f888 | blueswir1 | { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, |
4467 | eca8f888 | blueswir1 | { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, |
4468 | b9adb4a6 | bellard | |
4469 | eca8f888 | blueswir1 | { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, |
4470 | b9adb4a6 | bellard | |
4471 | ee8ae9e4 | blueswir1 | { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, |
4472 | ee8ae9e4 | blueswir1 | |
4473 | eca8f888 | blueswir1 | { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, |
4474 | b9adb4a6 | bellard | |
4475 | eca8f888 | blueswir1 | { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, |
4476 | b9adb4a6 | bellard | |
4477 | eca8f888 | blueswir1 | { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, |
4478 | eca8f888 | blueswir1 | { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, |
4479 | b9adb4a6 | bellard | |
4480 | eca8f888 | blueswir1 | { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, |
4481 | b9adb4a6 | bellard | |
4482 | eca8f888 | blueswir1 | { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, |
4483 | b9adb4a6 | bellard | |
4484 | eca8f888 | blueswir1 | { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, |
4485 | eca8f888 | blueswir1 | { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, |
4486 | b9adb4a6 | bellard | |
4487 | ee8ae9e4 | blueswir1 | { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, |
4488 | ee8ae9e4 | blueswir1 | |
4489 | eca8f888 | blueswir1 | { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, |
4490 | b9adb4a6 | bellard | |
4491 | eca8f888 | blueswir1 | { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
4492 | eca8f888 | blueswir1 | { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, |
4493 | eca8f888 | blueswir1 | { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
4494 | eca8f888 | blueswir1 | { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, |
4495 | b9adb4a6 | bellard | |
4496 | eca8f888 | blueswir1 | { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, |
4497 | eca8f888 | blueswir1 | { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, |
4498 | b9adb4a6 | bellard | |
4499 | eca8f888 | blueswir1 | { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4500 | b9adb4a6 | bellard | |
4501 | eca8f888 | blueswir1 | { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4502 | eca8f888 | blueswir1 | { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, |
4503 | b9adb4a6 | bellard | |
4504 | eca8f888 | blueswir1 | { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, |
4505 | b9adb4a6 | bellard | |
4506 | ee8ae9e4 | blueswir1 | { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, |
4507 | ee8ae9e4 | blueswir1 | |
4508 | eca8f888 | blueswir1 | { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, |
4509 | eca8f888 | blueswir1 | { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, |
4510 | b9adb4a6 | bellard | |
4511 | eca8f888 | blueswir1 | { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, |
4512 | eca8f888 | blueswir1 | { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, |
4513 | eca8f888 | blueswir1 | { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, |
4514 | eca8f888 | blueswir1 | { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, |
4515 | b9adb4a6 | bellard | |
4516 | eca8f888 | blueswir1 | { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, |
4517 | eca8f888 | blueswir1 | |
4518 | ee8ae9e4 | blueswir1 | { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, |
4519 | ee8ae9e4 | blueswir1 | |
4520 | eca8f888 | blueswir1 | { "mbar", X(31,854), X_MASK, BOOKE, { MO } }, |
4521 | b9adb4a6 | bellard | { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, |
4522 | b9adb4a6 | bellard | |
4523 | ee8ae9e4 | blueswir1 | { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, |
4524 | ee8ae9e4 | blueswir1 | |
4525 | ee8ae9e4 | blueswir1 | { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, |
4526 | ee8ae9e4 | blueswir1 | |
4527 | eca8f888 | blueswir1 | { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, |
4528 | eca8f888 | blueswir1 | { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, |
4529 | ee8ae9e4 | blueswir1 | { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } }, |
4530 | ee8ae9e4 | blueswir1 | { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } }, |
4531 | eca8f888 | blueswir1 | |
4532 | eca8f888 | blueswir1 | { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, |
4533 | eca8f888 | blueswir1 | |
4534 | ee8ae9e4 | blueswir1 | { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, |
4535 | ee8ae9e4 | blueswir1 | |
4536 | eca8f888 | blueswir1 | { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, |
4537 | eca8f888 | blueswir1 | |
4538 | eca8f888 | blueswir1 | { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, |
4539 | eca8f888 | blueswir1 | { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, |
4540 | b9adb4a6 | bellard | |
4541 | eca8f888 | blueswir1 | { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, |
4542 | eca8f888 | blueswir1 | { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, |
4543 | b9adb4a6 | bellard | |
4544 | eca8f888 | blueswir1 | { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, |
4545 | eca8f888 | blueswir1 | { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, |
4546 | eca8f888 | blueswir1 | { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, |
4547 | eca8f888 | blueswir1 | { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, |
4548 | b9adb4a6 | bellard | |
4549 | eca8f888 | blueswir1 | { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4550 | b9adb4a6 | bellard | |
4551 | eca8f888 | blueswir1 | { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, |
4552 | eca8f888 | blueswir1 | |
4553 | eca8f888 | blueswir1 | { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, |
4554 | eca8f888 | blueswir1 | { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, |
4555 | eca8f888 | blueswir1 | { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, |
4556 | eca8f888 | blueswir1 | |
4557 | ee8ae9e4 | blueswir1 | { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, |
4558 | ee8ae9e4 | blueswir1 | |
4559 | eca8f888 | blueswir1 | { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, |
4560 | eca8f888 | blueswir1 | { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, |
4561 | b9adb4a6 | bellard | |
4562 | b9adb4a6 | bellard | { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, |
4563 | b9adb4a6 | bellard | { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, |
4564 | b9adb4a6 | bellard | |
4565 | eca8f888 | blueswir1 | { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, |
4566 | eca8f888 | blueswir1 | |
4567 | eca8f888 | blueswir1 | { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, |
4568 | eca8f888 | blueswir1 | |
4569 | eca8f888 | blueswir1 | { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, |
4570 | eca8f888 | blueswir1 | { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, |
4571 | eca8f888 | blueswir1 | { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, |
4572 | eca8f888 | blueswir1 | { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, |
4573 | b9adb4a6 | bellard | |
4574 | ee8ae9e4 | blueswir1 | { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, |
4575 | ee8ae9e4 | blueswir1 | |
4576 | b9adb4a6 | bellard | { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, |
4577 | b9adb4a6 | bellard | |
4578 | eca8f888 | blueswir1 | { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, |
4579 | eca8f888 | blueswir1 | |
4580 | eca8f888 | blueswir1 | { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, |
4581 | eca8f888 | blueswir1 | { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, |
4582 | eca8f888 | blueswir1 | |
4583 | eca8f888 | blueswir1 | { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, |
4584 | b9adb4a6 | bellard | |
4585 | eca8f888 | blueswir1 | { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, |
4586 | eca8f888 | blueswir1 | { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, |
4587 | b9adb4a6 | bellard | |
4588 | eca8f888 | blueswir1 | { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, |
4589 | eca8f888 | blueswir1 | |
4590 | ee8ae9e4 | blueswir1 | { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, |
4591 | ee8ae9e4 | blueswir1 | |
4592 | eca8f888 | blueswir1 | { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, |
4593 | b9adb4a6 | bellard | { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
4594 | b9adb4a6 | bellard | { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
4595 | b9adb4a6 | bellard | |
4596 | eca8f888 | blueswir1 | { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, |
4597 | eca8f888 | blueswir1 | |
4598 | eca8f888 | blueswir1 | { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, |
4599 | eca8f888 | blueswir1 | { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, |
4600 | eca8f888 | blueswir1 | { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, |
4601 | eca8f888 | blueswir1 | { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, |
4602 | eca8f888 | blueswir1 | { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, |
4603 | eca8f888 | blueswir1 | { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, |
4604 | eca8f888 | blueswir1 | { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, |
4605 | eca8f888 | blueswir1 | { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, |
4606 | eca8f888 | blueswir1 | { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, |
4607 | eca8f888 | blueswir1 | { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, |
4608 | eca8f888 | blueswir1 | { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, |
4609 | eca8f888 | blueswir1 | { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, |
4610 | eca8f888 | blueswir1 | |
4611 | ee8ae9e4 | blueswir1 | /* New load/store left/right index vector instructions that are in the Cell only. */
|
4612 | ee8ae9e4 | blueswir1 | { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, |
4613 | ee8ae9e4 | blueswir1 | { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, |
4614 | ee8ae9e4 | blueswir1 | { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, |
4615 | ee8ae9e4 | blueswir1 | { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, |
4616 | ee8ae9e4 | blueswir1 | { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, |
4617 | ee8ae9e4 | blueswir1 | { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, |
4618 | ee8ae9e4 | blueswir1 | { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, |
4619 | ee8ae9e4 | blueswir1 | { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, |
4620 | ee8ae9e4 | blueswir1 | |
4621 | eca8f888 | blueswir1 | { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, |
4622 | eca8f888 | blueswir1 | { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
4623 | b9adb4a6 | bellard | |
4624 | eca8f888 | blueswir1 | { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, |
4625 | eca8f888 | blueswir1 | { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
4626 | b9adb4a6 | bellard | |
4627 | eca8f888 | blueswir1 | { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, |
4628 | b9adb4a6 | bellard | |
4629 | eca8f888 | blueswir1 | { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, |
4630 | b9adb4a6 | bellard | |
4631 | eca8f888 | blueswir1 | { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, |
4632 | eca8f888 | blueswir1 | { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, |
4633 | b9adb4a6 | bellard | |
4634 | eca8f888 | blueswir1 | { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, |
4635 | eca8f888 | blueswir1 | { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, |
4636 | b9adb4a6 | bellard | |
4637 | eca8f888 | blueswir1 | { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, |
4638 | b9adb4a6 | bellard | |
4639 | eca8f888 | blueswir1 | { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, |
4640 | b9adb4a6 | bellard | |
4641 | eca8f888 | blueswir1 | { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, |
4642 | b9adb4a6 | bellard | |
4643 | eca8f888 | blueswir1 | { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, |
4644 | b9adb4a6 | bellard | |
4645 | eca8f888 | blueswir1 | { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, |
4646 | b9adb4a6 | bellard | |
4647 | eca8f888 | blueswir1 | { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, |
4648 | b9adb4a6 | bellard | |
4649 | eca8f888 | blueswir1 | { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, |
4650 | b9adb4a6 | bellard | |
4651 | eca8f888 | blueswir1 | { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, |
4652 | b9adb4a6 | bellard | |
4653 | eca8f888 | blueswir1 | { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, |
4654 | eca8f888 | blueswir1 | { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, |
4655 | b9adb4a6 | bellard | |
4656 | eca8f888 | blueswir1 | { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, |
4657 | eca8f888 | blueswir1 | { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, |
4658 | b9adb4a6 | bellard | |
4659 | eca8f888 | blueswir1 | { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, |
4660 | b9adb4a6 | bellard | |
4661 | eca8f888 | blueswir1 | { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, |
4662 | b9adb4a6 | bellard | |
4663 | eca8f888 | blueswir1 | { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, |
4664 | b9adb4a6 | bellard | |
4665 | eca8f888 | blueswir1 | { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, |
4666 | b9adb4a6 | bellard | |
4667 | eca8f888 | blueswir1 | { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, |
4668 | b9adb4a6 | bellard | |
4669 | eca8f888 | blueswir1 | { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, |
4670 | b9adb4a6 | bellard | |
4671 | eca8f888 | blueswir1 | { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, |
4672 | b9adb4a6 | bellard | |
4673 | eca8f888 | blueswir1 | { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, |
4674 | b9adb4a6 | bellard | |
4675 | eca8f888 | blueswir1 | { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, |
4676 | b9adb4a6 | bellard | |
4677 | eca8f888 | blueswir1 | { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, |
4678 | b9adb4a6 | bellard | |
4679 | eca8f888 | blueswir1 | { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, |
4680 | b9adb4a6 | bellard | |
4681 | ee8ae9e4 | blueswir1 | { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, |
4682 | ee8ae9e4 | blueswir1 | |
4683 | eca8f888 | blueswir1 | { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4684 | eca8f888 | blueswir1 | { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4685 | eca8f888 | blueswir1 | { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4686 | eca8f888 | blueswir1 | { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4687 | eca8f888 | blueswir1 | { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4688 | eca8f888 | blueswir1 | { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4689 | eca8f888 | blueswir1 | { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, |
4690 | eca8f888 | blueswir1 | { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, |
4691 | eca8f888 | blueswir1 | { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, |
4692 | eca8f888 | blueswir1 | { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, |
4693 | eca8f888 | blueswir1 | { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, |
4694 | eca8f888 | blueswir1 | { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, |
4695 | eca8f888 | blueswir1 | { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, |
4696 | eca8f888 | blueswir1 | { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, |
4697 | b9adb4a6 | bellard | |
4698 | eca8f888 | blueswir1 | { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, |
4699 | eca8f888 | blueswir1 | |
4700 | eca8f888 | blueswir1 | { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, |
4701 | eca8f888 | blueswir1 | |
4702 | eca8f888 | blueswir1 | { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, |
4703 | b9adb4a6 | bellard | |
4704 | ee8ae9e4 | blueswir1 | { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4705 | ee8ae9e4 | blueswir1 | { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4706 | ee8ae9e4 | blueswir1 | |
4707 | ee8ae9e4 | blueswir1 | { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4708 | ee8ae9e4 | blueswir1 | { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4709 | ee8ae9e4 | blueswir1 | |
4710 | b9adb4a6 | bellard | { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4711 | b9adb4a6 | bellard | { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4712 | b9adb4a6 | bellard | |
4713 | b9adb4a6 | bellard | { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4714 | b9adb4a6 | bellard | { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4715 | b9adb4a6 | bellard | |
4716 | b9adb4a6 | bellard | { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4717 | b9adb4a6 | bellard | { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
4718 | b9adb4a6 | bellard | |
4719 | b9adb4a6 | bellard | { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
4720 | b9adb4a6 | bellard | { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
4721 | b9adb4a6 | bellard | |
4722 | ee8ae9e4 | blueswir1 | { "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4723 | ee8ae9e4 | blueswir1 | { "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4724 | b9adb4a6 | bellard | |
4725 | b9adb4a6 | bellard | { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
4726 | b9adb4a6 | bellard | { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
4727 | b9adb4a6 | bellard | |
4728 | ee8ae9e4 | blueswir1 | { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, |
4729 | ee8ae9e4 | blueswir1 | { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, |
4730 | eca8f888 | blueswir1 | |
4731 | b9adb4a6 | bellard | { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4732 | b9adb4a6 | bellard | { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4733 | b9adb4a6 | bellard | |
4734 | b9adb4a6 | bellard | { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4735 | b9adb4a6 | bellard | { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4736 | b9adb4a6 | bellard | |
4737 | b9adb4a6 | bellard | { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4738 | b9adb4a6 | bellard | { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4739 | b9adb4a6 | bellard | |
4740 | b9adb4a6 | bellard | { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4741 | b9adb4a6 | bellard | { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4742 | b9adb4a6 | bellard | |
4743 | ee8ae9e4 | blueswir1 | { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4744 | ee8ae9e4 | blueswir1 | { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4745 | ee8ae9e4 | blueswir1 | |
4746 | ee8ae9e4 | blueswir1 | { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4747 | ee8ae9e4 | blueswir1 | { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4748 | ee8ae9e4 | blueswir1 | |
4749 | ee8ae9e4 | blueswir1 | { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4750 | ee8ae9e4 | blueswir1 | { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4751 | ee8ae9e4 | blueswir1 | |
4752 | ee8ae9e4 | blueswir1 | { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, |
4753 | ee8ae9e4 | blueswir1 | { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, |
4754 | ee8ae9e4 | blueswir1 | |
4755 | ee8ae9e4 | blueswir1 | { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4756 | ee8ae9e4 | blueswir1 | { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4757 | ee8ae9e4 | blueswir1 | |
4758 | ee8ae9e4 | blueswir1 | { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4759 | ee8ae9e4 | blueswir1 | { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4760 | ee8ae9e4 | blueswir1 | |
4761 | ee8ae9e4 | blueswir1 | { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, |
4762 | ee8ae9e4 | blueswir1 | |
4763 | ee8ae9e4 | blueswir1 | { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, |
4764 | ee8ae9e4 | blueswir1 | { "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, |
4765 | ee8ae9e4 | blueswir1 | { "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } }, |
4766 | ee8ae9e4 | blueswir1 | |
4767 | ee8ae9e4 | blueswir1 | { "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4768 | ee8ae9e4 | blueswir1 | { "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4769 | ee8ae9e4 | blueswir1 | |
4770 | ee8ae9e4 | blueswir1 | { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, |
4771 | ee8ae9e4 | blueswir1 | { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, |
4772 | ee8ae9e4 | blueswir1 | |
4773 | ee8ae9e4 | blueswir1 | { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, |
4774 | ee8ae9e4 | blueswir1 | { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, |
4775 | ee8ae9e4 | blueswir1 | |
4776 | ee8ae9e4 | blueswir1 | { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, |
4777 | ee8ae9e4 | blueswir1 | { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, |
4778 | ee8ae9e4 | blueswir1 | |
4779 | ee8ae9e4 | blueswir1 | { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, |
4780 | ee8ae9e4 | blueswir1 | { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } }, |
4781 | ee8ae9e4 | blueswir1 | |
4782 | ee8ae9e4 | blueswir1 | { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4783 | ee8ae9e4 | blueswir1 | { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4784 | ee8ae9e4 | blueswir1 | |
4785 | ee8ae9e4 | blueswir1 | { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4786 | ee8ae9e4 | blueswir1 | { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4787 | ee8ae9e4 | blueswir1 | |
4788 | ee8ae9e4 | blueswir1 | { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, |
4789 | ee8ae9e4 | blueswir1 | |
4790 | ee8ae9e4 | blueswir1 | { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, |
4791 | ee8ae9e4 | blueswir1 | |
4792 | ee8ae9e4 | blueswir1 | { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, |
4793 | ee8ae9e4 | blueswir1 | { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, |
4794 | ee8ae9e4 | blueswir1 | |
4795 | ee8ae9e4 | blueswir1 | { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, |
4796 | ee8ae9e4 | blueswir1 | { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, |
4797 | ee8ae9e4 | blueswir1 | |
4798 | ee8ae9e4 | blueswir1 | { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, |
4799 | ee8ae9e4 | blueswir1 | { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } }, |
4800 | ee8ae9e4 | blueswir1 | |
4801 | ee8ae9e4 | blueswir1 | { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4802 | ee8ae9e4 | blueswir1 | { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4803 | ee8ae9e4 | blueswir1 | |
4804 | b9adb4a6 | bellard | { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, |
4805 | b9adb4a6 | bellard | |
4806 | b9adb4a6 | bellard | { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, |
4807 | b9adb4a6 | bellard | |
4808 | ee8ae9e4 | blueswir1 | { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, |
4809 | ee8ae9e4 | blueswir1 | |
4810 | eca8f888 | blueswir1 | { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, |
4811 | eca8f888 | blueswir1 | { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, |
4812 | eca8f888 | blueswir1 | { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, |
4813 | eca8f888 | blueswir1 | { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, |
4814 | eca8f888 | blueswir1 | { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, |
4815 | eca8f888 | blueswir1 | { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, |
4816 | eca8f888 | blueswir1 | { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, |
4817 | eca8f888 | blueswir1 | { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, |
4818 | eca8f888 | blueswir1 | { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, |
4819 | eca8f888 | blueswir1 | { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, |
4820 | eca8f888 | blueswir1 | { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, |
4821 | eca8f888 | blueswir1 | { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, |
4822 | b9adb4a6 | bellard | |
4823 | eca8f888 | blueswir1 | { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, |
4824 | b9adb4a6 | bellard | |
4825 | eca8f888 | blueswir1 | { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, |
4826 | b9adb4a6 | bellard | |
4827 | eca8f888 | blueswir1 | { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, |
4828 | b9adb4a6 | bellard | |
4829 | eca8f888 | blueswir1 | { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, |
4830 | eca8f888 | blueswir1 | |
4831 | ee8ae9e4 | blueswir1 | { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4832 | ee8ae9e4 | blueswir1 | { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4833 | ee8ae9e4 | blueswir1 | |
4834 | ee8ae9e4 | blueswir1 | { "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4835 | ee8ae9e4 | blueswir1 | { "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4836 | ee8ae9e4 | blueswir1 | |
4837 | ee8ae9e4 | blueswir1 | { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4838 | ee8ae9e4 | blueswir1 | { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4839 | ee8ae9e4 | blueswir1 | |
4840 | eca8f888 | blueswir1 | { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, |
4841 | eca8f888 | blueswir1 | { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, |
4842 | eca8f888 | blueswir1 | |
4843 | eca8f888 | blueswir1 | { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4844 | b9adb4a6 | bellard | { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, |
4845 | eca8f888 | blueswir1 | { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4846 | b9adb4a6 | bellard | { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, |
4847 | b9adb4a6 | bellard | |
4848 | eca8f888 | blueswir1 | { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4849 | b9adb4a6 | bellard | { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, |
4850 | eca8f888 | blueswir1 | { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, |
4851 | b9adb4a6 | bellard | { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, |
4852 | b9adb4a6 | bellard | |
4853 | eca8f888 | blueswir1 | { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4854 | eca8f888 | blueswir1 | { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4855 | eca8f888 | blueswir1 | { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4856 | eca8f888 | blueswir1 | { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4857 | b9adb4a6 | bellard | |
4858 | eca8f888 | blueswir1 | { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4859 | eca8f888 | blueswir1 | { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4860 | eca8f888 | blueswir1 | { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4861 | eca8f888 | blueswir1 | { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4862 | b9adb4a6 | bellard | |
4863 | eca8f888 | blueswir1 | { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4864 | eca8f888 | blueswir1 | { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4865 | eca8f888 | blueswir1 | { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
4866 | eca8f888 | blueswir1 | { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, |
4867 | b9adb4a6 | bellard | |
4868 | eca8f888 | blueswir1 | { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, |
4869 | eca8f888 | blueswir1 | { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, |
4870 | b9adb4a6 | bellard | |
4871 | b9adb4a6 | bellard | { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4872 | b9adb4a6 | bellard | { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
4873 | b9adb4a6 | bellard | |
4874 | ee8ae9e4 | blueswir1 | { "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, |
4875 | ee8ae9e4 | blueswir1 | { "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, |
4876 | eca8f888 | blueswir1 | |
4877 | eca8f888 | blueswir1 | { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, |
4878 | eca8f888 | blueswir1 | { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, |
4879 | eca8f888 | blueswir1 | { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, |
4880 | eca8f888 | blueswir1 | { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, |
4881 | b9adb4a6 | bellard | |
4882 | ee8ae9e4 | blueswir1 | { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4883 | ee8ae9e4 | blueswir1 | { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, |
4884 | b9adb4a6 | bellard | |
4885 | eca8f888 | blueswir1 | { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4886 | eca8f888 | blueswir1 | { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4887 | eca8f888 | blueswir1 | { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4888 | eca8f888 | blueswir1 | { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4889 | b9adb4a6 | bellard | |
4890 | eca8f888 | blueswir1 | { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4891 | eca8f888 | blueswir1 | { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4892 | eca8f888 | blueswir1 | { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4893 | eca8f888 | blueswir1 | { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4894 | b9adb4a6 | bellard | |
4895 | eca8f888 | blueswir1 | { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4896 | eca8f888 | blueswir1 | { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4897 | eca8f888 | blueswir1 | { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4898 | eca8f888 | blueswir1 | { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4899 | b9adb4a6 | bellard | |
4900 | eca8f888 | blueswir1 | { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4901 | eca8f888 | blueswir1 | { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4902 | eca8f888 | blueswir1 | { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
4903 | eca8f888 | blueswir1 | { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, |
4904 | b9adb4a6 | bellard | |
4905 | eca8f888 | blueswir1 | { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, |
4906 | b9adb4a6 | bellard | |
4907 | ee8ae9e4 | blueswir1 | { "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4908 | ee8ae9e4 | blueswir1 | { "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4909 | ee8ae9e4 | blueswir1 | |
4910 | ee8ae9e4 | blueswir1 | { "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4911 | ee8ae9e4 | blueswir1 | { "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4912 | ee8ae9e4 | blueswir1 | |
4913 | eca8f888 | blueswir1 | { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, |
4914 | eca8f888 | blueswir1 | { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, |
4915 | b9adb4a6 | bellard | |
4916 | eca8f888 | blueswir1 | { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, |
4917 | eca8f888 | blueswir1 | { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, |
4918 | b9adb4a6 | bellard | |
4919 | eca8f888 | blueswir1 | { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, |
4920 | b9adb4a6 | bellard | |
4921 | ee8ae9e4 | blueswir1 | { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4922 | ee8ae9e4 | blueswir1 | { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4923 | ee8ae9e4 | blueswir1 | |
4924 | ee8ae9e4 | blueswir1 | { "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, |
4925 | ee8ae9e4 | blueswir1 | { "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, |
4926 | ee8ae9e4 | blueswir1 | |
4927 | eca8f888 | blueswir1 | { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, |
4928 | eca8f888 | blueswir1 | { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, |
4929 | b9adb4a6 | bellard | |
4930 | eca8f888 | blueswir1 | { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, |
4931 | eca8f888 | blueswir1 | { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, |
4932 | b9adb4a6 | bellard | |
4933 | ee8ae9e4 | blueswir1 | { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4934 | ee8ae9e4 | blueswir1 | { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, |
4935 | ee8ae9e4 | blueswir1 | |
4936 | ee8ae9e4 | blueswir1 | { "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4937 | ee8ae9e4 | blueswir1 | { "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4938 | ee8ae9e4 | blueswir1 | |
4939 | ee8ae9e4 | blueswir1 | { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, |
4940 | ee8ae9e4 | blueswir1 | |
4941 | ee8ae9e4 | blueswir1 | { "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, |
4942 | ee8ae9e4 | blueswir1 | { "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, |
4943 | b9adb4a6 | bellard | |
4944 | eca8f888 | blueswir1 | { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, |
4945 | eca8f888 | blueswir1 | { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, |
4946 | b9adb4a6 | bellard | |
4947 | ee8ae9e4 | blueswir1 | { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, |
4948 | ee8ae9e4 | blueswir1 | { "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } }, |
4949 | ee8ae9e4 | blueswir1 | { "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } }, |
4950 | ee8ae9e4 | blueswir1 | |
4951 | ee8ae9e4 | blueswir1 | { "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4952 | ee8ae9e4 | blueswir1 | { "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, |
4953 | ee8ae9e4 | blueswir1 | |
4954 | ee8ae9e4 | blueswir1 | { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, |
4955 | ee8ae9e4 | blueswir1 | { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } }, |
4956 | ee8ae9e4 | blueswir1 | |
4957 | eca8f888 | blueswir1 | { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, |
4958 | eca8f888 | blueswir1 | { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, |
4959 | b9adb4a6 | bellard | |
4960 | ee8ae9e4 | blueswir1 | { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, |
4961 | ee8ae9e4 | blueswir1 | { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, |
4962 | ee8ae9e4 | blueswir1 | |
4963 | ee8ae9e4 | blueswir1 | { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, |
4964 | ee8ae9e4 | blueswir1 | { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, |
4965 | ee8ae9e4 | blueswir1 | |
4966 | ee8ae9e4 | blueswir1 | { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, |
4967 | ee8ae9e4 | blueswir1 | { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } }, |
4968 | ee8ae9e4 | blueswir1 | |
4969 | eca8f888 | blueswir1 | { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4970 | eca8f888 | blueswir1 | { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4971 | eca8f888 | blueswir1 | { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4972 | eca8f888 | blueswir1 | { "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4973 | eca8f888 | blueswir1 | { "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4974 | eca8f888 | blueswir1 | { "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4975 | eca8f888 | blueswir1 | { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, |
4976 | eca8f888 | blueswir1 | { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, |
4977 | b9adb4a6 | bellard | |
4978 | ee8ae9e4 | blueswir1 | { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4979 | ee8ae9e4 | blueswir1 | { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4980 | ee8ae9e4 | blueswir1 | |
4981 | ee8ae9e4 | blueswir1 | { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4982 | ee8ae9e4 | blueswir1 | { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
4983 | ee8ae9e4 | blueswir1 | |
4984 | eca8f888 | blueswir1 | { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, |
4985 | eca8f888 | blueswir1 | { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, |
4986 | b9adb4a6 | bellard | |
4987 | ee8ae9e4 | blueswir1 | { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, |
4988 | ee8ae9e4 | blueswir1 | |
4989 | ee8ae9e4 | blueswir1 | { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, |
4990 | ee8ae9e4 | blueswir1 | |
4991 | ee8ae9e4 | blueswir1 | { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, |
4992 | ee8ae9e4 | blueswir1 | { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, |
4993 | ee8ae9e4 | blueswir1 | |
4994 | ee8ae9e4 | blueswir1 | { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, |
4995 | ee8ae9e4 | blueswir1 | { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, |
4996 | ee8ae9e4 | blueswir1 | |
4997 | ee8ae9e4 | blueswir1 | { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, |
4998 | ee8ae9e4 | blueswir1 | { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, |
4999 | b9adb4a6 | bellard | |
5000 | eca8f888 | blueswir1 | { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, |
5001 | eca8f888 | blueswir1 | { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, |
5002 | b9adb4a6 | bellard | |
5003 | eca8f888 | blueswir1 | { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, |
5004 | eca8f888 | blueswir1 | { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, |
5005 | eca8f888 | blueswir1 | |
5006 | ee8ae9e4 | blueswir1 | { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, |
5007 | ee8ae9e4 | blueswir1 | { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, |
5008 | ee8ae9e4 | blueswir1 | |
5009 | eca8f888 | blueswir1 | { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, |
5010 | eca8f888 | blueswir1 | { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, |
5011 | b9adb4a6 | bellard | |
5012 | ee8ae9e4 | blueswir1 | { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5013 | ee8ae9e4 | blueswir1 | { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, |
5014 | ee8ae9e4 | blueswir1 | |
5015 | b9adb4a6 | bellard | }; |
5016 | b9adb4a6 | bellard | |
5017 | b9adb4a6 | bellard | const int powerpc_num_opcodes = |
5018 | b9adb4a6 | bellard | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
5019 | b9adb4a6 | bellard | |
5020 | b9adb4a6 | bellard | /* The macro table. This is only used by the assembler. */
|
5021 | b9adb4a6 | bellard | |
5022 | eca8f888 | blueswir1 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
|
5023 | eca8f888 | blueswir1 | when x=0; 32-x when x is between 1 and 31; are negative if x is
|
5024 | eca8f888 | blueswir1 | negative; and are 32 or more otherwise. This is what you want
|
5025 | eca8f888 | blueswir1 | when, for instance, you are emulating a right shift by a
|
5026 | eca8f888 | blueswir1 | rotate-left-and-mask, because the underlying instructions support
|
5027 | eca8f888 | blueswir1 | shifts of size 0 but not shifts of size 32. By comparison, when
|
5028 | eca8f888 | blueswir1 | extracting x bits from some word you want to use just 32-x, because
|
5029 | eca8f888 | blueswir1 | the underlying instructions don't support extracting 0 bits but do
|
5030 | eca8f888 | blueswir1 | support extracting the whole word (32 bits in this case). */
|
5031 | b9adb4a6 | bellard | |
5032 | eca8f888 | blueswir1 | const struct powerpc_macro powerpc_macros[] = { |
5033 | eca8f888 | blueswir1 | { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, |
5034 | eca8f888 | blueswir1 | { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, |
5035 | eca8f888 | blueswir1 | { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, |
5036 | eca8f888 | blueswir1 | { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, |
5037 | eca8f888 | blueswir1 | { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, |
5038 | eca8f888 | blueswir1 | { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, |
5039 | eca8f888 | blueswir1 | { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, |
5040 | eca8f888 | blueswir1 | { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, |
5041 | eca8f888 | blueswir1 | { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, |
5042 | eca8f888 | blueswir1 | { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, |
5043 | eca8f888 | blueswir1 | { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, |
5044 | eca8f888 | blueswir1 | { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, |
5045 | eca8f888 | blueswir1 | { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, |
5046 | eca8f888 | blueswir1 | { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, |
5047 | eca8f888 | blueswir1 | { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, |
5048 | eca8f888 | blueswir1 | { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, |
5049 | eca8f888 | blueswir1 | |
5050 | eca8f888 | blueswir1 | { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, |
5051 | eca8f888 | blueswir1 | { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, |
5052 | eca8f888 | blueswir1 | { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
5053 | eca8f888 | blueswir1 | { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
5054 | eca8f888 | blueswir1 | { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, |
5055 | eca8f888 | blueswir1 | { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, |
5056 | eca8f888 | blueswir1 | { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
5057 | eca8f888 | blueswir1 | { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, |
5058 | eca8f888 | blueswir1 | { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
5059 | eca8f888 | blueswir1 | { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
5060 | eca8f888 | blueswir1 | { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, |
5061 | eca8f888 | blueswir1 | { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, |
5062 | eca8f888 | blueswir1 | { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, |
5063 | eca8f888 | blueswir1 | { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, |
5064 | eca8f888 | blueswir1 | { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5065 | eca8f888 | blueswir1 | { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5066 | eca8f888 | blueswir1 | { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5067 | eca8f888 | blueswir1 | { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
5068 | eca8f888 | blueswir1 | { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, |
5069 | eca8f888 | blueswir1 | { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, |
5070 | eca8f888 | blueswir1 | { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, |
5071 | eca8f888 | blueswir1 | { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, |
5072 | b9adb4a6 | bellard | }; |
5073 | b9adb4a6 | bellard | |
5074 | b9adb4a6 | bellard | const int powerpc_num_macros = |
5075 | b9adb4a6 | bellard | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); |
5076 | b9adb4a6 | bellard | |
5077 | ee8ae9e4 | blueswir1 | |
5078 | eca8f888 | blueswir1 | /* This file provides several disassembler functions, all of which use
|
5079 | eca8f888 | blueswir1 | the disassembler interface defined in dis-asm.h. Several functions
|
5080 | eca8f888 | blueswir1 | are provided because this file handles disassembly for the PowerPC
|
5081 | eca8f888 | blueswir1 | in both big and little endian mode and also for the POWER (RS/6000)
|
5082 | eca8f888 | blueswir1 | chip. */
|
5083 | eca8f888 | blueswir1 | |
5084 | eca8f888 | blueswir1 | static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); |
5085 | eca8f888 | blueswir1 | |
5086 | eca8f888 | blueswir1 | /* Determine which set of machines to disassemble for. PPC403/601 or
|
5087 | eca8f888 | blueswir1 | BookE. For convenience, also disassemble instructions supported
|
5088 | eca8f888 | blueswir1 | by the AltiVec vector unit. */
|
5089 | eca8f888 | blueswir1 | |
5090 | 43ef9eb2 | bellard | static int |
5091 | eca8f888 | blueswir1 | powerpc_dialect (struct disassemble_info *info)
|
5092 | eca8f888 | blueswir1 | { |
5093 | eca8f888 | blueswir1 | int dialect = PPC_OPCODE_PPC;
|
5094 | eca8f888 | blueswir1 | |
5095 | eca8f888 | blueswir1 | if (BFD_DEFAULT_TARGET_SIZE == 64) |
5096 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_64; |
5097 | eca8f888 | blueswir1 | |
5098 | eca8f888 | blueswir1 | if (info->disassembler_options
|
5099 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "booke") != NULL) |
5100 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; |
5101 | eca8f888 | blueswir1 | else if ((info->mach == bfd_mach_ppc_e500) |
5102 | eca8f888 | blueswir1 | || (info->disassembler_options |
5103 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "e500") != NULL)) |
5104 | eca8f888 | blueswir1 | dialect |= (PPC_OPCODE_BOOKE |
5105 | eca8f888 | blueswir1 | | PPC_OPCODE_SPE | PPC_OPCODE_ISEL |
5106 | eca8f888 | blueswir1 | | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK |
5107 | eca8f888 | blueswir1 | | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK |
5108 | eca8f888 | blueswir1 | | PPC_OPCODE_RFMCI); |
5109 | eca8f888 | blueswir1 | else if (info->disassembler_options |
5110 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "efs") != NULL) |
5111 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_EFS; |
5112 | eca8f888 | blueswir1 | else if (info->disassembler_options |
5113 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "e300") != NULL) |
5114 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; |
5115 | ee8ae9e4 | blueswir1 | else if (info->disassembler_options |
5116 | ee8ae9e4 | blueswir1 | && strstr (info->disassembler_options, "440") != NULL) |
5117 | ee8ae9e4 | blueswir1 | dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 |
5118 | ee8ae9e4 | blueswir1 | | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI; |
5119 | eca8f888 | blueswir1 | else
|
5120 | eca8f888 | blueswir1 | dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC |
5121 | eca8f888 | blueswir1 | | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); |
5122 | eca8f888 | blueswir1 | |
5123 | eca8f888 | blueswir1 | if (info->disassembler_options
|
5124 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "power4") != NULL) |
5125 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_POWER4; |
5126 | eca8f888 | blueswir1 | |
5127 | eca8f888 | blueswir1 | if (info->disassembler_options
|
5128 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "power5") != NULL) |
5129 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; |
5130 | eca8f888 | blueswir1 | |
5131 | eca8f888 | blueswir1 | if (info->disassembler_options
|
5132 | ee8ae9e4 | blueswir1 | && strstr (info->disassembler_options, "cell") != NULL) |
5133 | ee8ae9e4 | blueswir1 | dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; |
5134 | ee8ae9e4 | blueswir1 | |
5135 | ee8ae9e4 | blueswir1 | if (info->disassembler_options
|
5136 | ee8ae9e4 | blueswir1 | && strstr (info->disassembler_options, "power6") != NULL) |
5137 | ee8ae9e4 | blueswir1 | dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; |
5138 | ee8ae9e4 | blueswir1 | |
5139 | ee8ae9e4 | blueswir1 | if (info->disassembler_options
|
5140 | eca8f888 | blueswir1 | && strstr (info->disassembler_options, "any") != NULL) |
5141 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_ANY; |
5142 | eca8f888 | blueswir1 | |
5143 | eca8f888 | blueswir1 | if (info->disassembler_options)
|
5144 | eca8f888 | blueswir1 | { |
5145 | eca8f888 | blueswir1 | if (strstr (info->disassembler_options, "32") != NULL) |
5146 | eca8f888 | blueswir1 | dialect &= ~PPC_OPCODE_64; |
5147 | eca8f888 | blueswir1 | else if (strstr (info->disassembler_options, "64") != NULL) |
5148 | eca8f888 | blueswir1 | dialect |= PPC_OPCODE_64; |
5149 | a2458627 | bellard | } |
5150 | eca8f888 | blueswir1 | |
5151 | eca8f888 | blueswir1 | info->private_data = (char *) 0 + dialect; |
5152 | eca8f888 | blueswir1 | return dialect;
|
5153 | eca8f888 | blueswir1 | } |
5154 | eca8f888 | blueswir1 | |
5155 | eca8f888 | blueswir1 | /* Qemu default */
|
5156 | eca8f888 | blueswir1 | int
|
5157 | eca8f888 | blueswir1 | print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
|
5158 | eca8f888 | blueswir1 | { |
5159 | eca8f888 | blueswir1 | int dialect = (char *) info->private_data - (char *) 0; |
5160 | eca8f888 | blueswir1 | return print_insn_powerpc (memaddr, info, 1, dialect); |
5161 | eca8f888 | blueswir1 | } |
5162 | eca8f888 | blueswir1 | |
5163 | eca8f888 | blueswir1 | /* Print a big endian PowerPC instruction. */
|
5164 | eca8f888 | blueswir1 | |
5165 | eca8f888 | blueswir1 | int
|
5166 | eca8f888 | blueswir1 | print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
5167 | eca8f888 | blueswir1 | { |
5168 | eca8f888 | blueswir1 | int dialect = (char *) info->private_data - (char *) 0; |
5169 | eca8f888 | blueswir1 | return print_insn_powerpc (memaddr, info, 1, dialect); |
5170 | eca8f888 | blueswir1 | } |
5171 | eca8f888 | blueswir1 | |
5172 | eca8f888 | blueswir1 | /* Print a little endian PowerPC instruction. */
|
5173 | eca8f888 | blueswir1 | |
5174 | eca8f888 | blueswir1 | int
|
5175 | eca8f888 | blueswir1 | print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
5176 | eca8f888 | blueswir1 | { |
5177 | eca8f888 | blueswir1 | int dialect = (char *) info->private_data - (char *) 0; |
5178 | eca8f888 | blueswir1 | return print_insn_powerpc (memaddr, info, 0, dialect); |
5179 | eca8f888 | blueswir1 | } |
5180 | eca8f888 | blueswir1 | |
5181 | eca8f888 | blueswir1 | /* Print a POWER (RS/6000) instruction. */
|
5182 | eca8f888 | blueswir1 | |
5183 | eca8f888 | blueswir1 | int
|
5184 | eca8f888 | blueswir1 | print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
|
5185 | eca8f888 | blueswir1 | { |
5186 | eca8f888 | blueswir1 | return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); |
5187 | b9adb4a6 | bellard | } |
5188 | b9adb4a6 | bellard | |
5189 | ee8ae9e4 | blueswir1 | /* Extract the operand value from the PowerPC or POWER instruction. */
|
5190 | ee8ae9e4 | blueswir1 | |
5191 | ee8ae9e4 | blueswir1 | static long |
5192 | ee8ae9e4 | blueswir1 | operand_value_powerpc (const struct powerpc_operand *operand, |
5193 | ee8ae9e4 | blueswir1 | unsigned long insn, int dialect) |
5194 | ee8ae9e4 | blueswir1 | { |
5195 | ee8ae9e4 | blueswir1 | long value;
|
5196 | ee8ae9e4 | blueswir1 | int invalid;
|
5197 | ee8ae9e4 | blueswir1 | /* Extract the value from the instruction. */
|
5198 | ee8ae9e4 | blueswir1 | if (operand->extract)
|
5199 | ee8ae9e4 | blueswir1 | value = (*operand->extract) (insn, dialect, &invalid); |
5200 | ee8ae9e4 | blueswir1 | else
|
5201 | ee8ae9e4 | blueswir1 | { |
5202 | ee8ae9e4 | blueswir1 | value = (insn >> operand->shift) & operand->bitm; |
5203 | ee8ae9e4 | blueswir1 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
5204 | ee8ae9e4 | blueswir1 | { |
5205 | ee8ae9e4 | blueswir1 | /* BITM is always some number of zeros followed by some
|
5206 | ee8ae9e4 | blueswir1 | number of ones, followed by some numer of zeros. */
|
5207 | ee8ae9e4 | blueswir1 | unsigned long top = operand->bitm; |
5208 | ee8ae9e4 | blueswir1 | /* top & -top gives the rightmost 1 bit, so this
|
5209 | ee8ae9e4 | blueswir1 | fills in any trailing zeros. */
|
5210 | ee8ae9e4 | blueswir1 | top |= (top & -top) - 1;
|
5211 | ee8ae9e4 | blueswir1 | top &= ~(top >> 1);
|
5212 | ee8ae9e4 | blueswir1 | value = (value ^ top) - top; |
5213 | ee8ae9e4 | blueswir1 | } |
5214 | ee8ae9e4 | blueswir1 | } |
5215 | ee8ae9e4 | blueswir1 | |
5216 | ee8ae9e4 | blueswir1 | return value;
|
5217 | ee8ae9e4 | blueswir1 | } |
5218 | ee8ae9e4 | blueswir1 | |
5219 | ee8ae9e4 | blueswir1 | /* Determine whether the optional operand(s) should be printed. */
|
5220 | ee8ae9e4 | blueswir1 | |
5221 | ee8ae9e4 | blueswir1 | static int |
5222 | ee8ae9e4 | blueswir1 | skip_optional_operands (const unsigned char *opindex, |
5223 | ee8ae9e4 | blueswir1 | unsigned long insn, int dialect) |
5224 | ee8ae9e4 | blueswir1 | { |
5225 | ee8ae9e4 | blueswir1 | const struct powerpc_operand *operand; |
5226 | ee8ae9e4 | blueswir1 | |
5227 | ee8ae9e4 | blueswir1 | for (; *opindex != 0; opindex++) |
5228 | ee8ae9e4 | blueswir1 | { |
5229 | ee8ae9e4 | blueswir1 | operand = &powerpc_operands[*opindex]; |
5230 | ee8ae9e4 | blueswir1 | if ((operand->flags & PPC_OPERAND_NEXT) != 0 |
5231 | ee8ae9e4 | blueswir1 | || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
5232 | ee8ae9e4 | blueswir1 | && operand_value_powerpc (operand, insn, dialect) != 0))
|
5233 | ee8ae9e4 | blueswir1 | return 0; |
5234 | ee8ae9e4 | blueswir1 | } |
5235 | ee8ae9e4 | blueswir1 | |
5236 | ee8ae9e4 | blueswir1 | return 1; |
5237 | ee8ae9e4 | blueswir1 | } |
5238 | ee8ae9e4 | blueswir1 | |
5239 | b9adb4a6 | bellard | /* Print a PowerPC or POWER instruction. */
|
5240 | b9adb4a6 | bellard | |
5241 | 7c08dbf3 | bellard | static int |
5242 | eca8f888 | blueswir1 | print_insn_powerpc (bfd_vma memaddr, |
5243 | eca8f888 | blueswir1 | struct disassemble_info *info,
|
5244 | eca8f888 | blueswir1 | int bigendian,
|
5245 | b9adb4a6 | bellard | int dialect)
|
5246 | b9adb4a6 | bellard | { |
5247 | eca8f888 | blueswir1 | bfd_byte buffer[4];
|
5248 | eca8f888 | blueswir1 | int status;
|
5249 | eca8f888 | blueswir1 | unsigned long insn; |
5250 | b9adb4a6 | bellard | const struct powerpc_opcode *opcode; |
5251 | b9adb4a6 | bellard | const struct powerpc_opcode *opcode_end; |
5252 | eca8f888 | blueswir1 | unsigned long op; |
5253 | eca8f888 | blueswir1 | |
5254 | eca8f888 | blueswir1 | if (dialect == 0) |
5255 | eca8f888 | blueswir1 | dialect = powerpc_dialect (info); |
5256 | eca8f888 | blueswir1 | |
5257 | eca8f888 | blueswir1 | status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
5258 | eca8f888 | blueswir1 | if (status != 0) |
5259 | eca8f888 | blueswir1 | { |
5260 | eca8f888 | blueswir1 | (*info->memory_error_func) (status, memaddr, info); |
5261 | eca8f888 | blueswir1 | return -1; |
5262 | eca8f888 | blueswir1 | } |
5263 | eca8f888 | blueswir1 | |
5264 | eca8f888 | blueswir1 | if (bigendian)
|
5265 | eca8f888 | blueswir1 | insn = bfd_getb32 (buffer); |
5266 | eca8f888 | blueswir1 | else
|
5267 | eca8f888 | blueswir1 | insn = bfd_getl32 (buffer); |
5268 | b9adb4a6 | bellard | |
5269 | b9adb4a6 | bellard | /* Get the major opcode of the instruction. */
|
5270 | b9adb4a6 | bellard | op = PPC_OP (insn); |
5271 | b9adb4a6 | bellard | |
5272 | b9adb4a6 | bellard | /* Find the first match in the opcode table. We could speed this up
|
5273 | b9adb4a6 | bellard | a bit by doing a binary search on the major opcode. */
|
5274 | b9adb4a6 | bellard | opcode_end = powerpc_opcodes + powerpc_num_opcodes; |
5275 | eca8f888 | blueswir1 | again:
|
5276 | b9adb4a6 | bellard | for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
|
5277 | b9adb4a6 | bellard | { |
5278 | eca8f888 | blueswir1 | unsigned long table_op; |
5279 | b9adb4a6 | bellard | const unsigned char *opindex; |
5280 | b9adb4a6 | bellard | const struct powerpc_operand *operand; |
5281 | b9adb4a6 | bellard | int invalid;
|
5282 | b9adb4a6 | bellard | int need_comma;
|
5283 | b9adb4a6 | bellard | int need_paren;
|
5284 | ee8ae9e4 | blueswir1 | int skip_optional;
|
5285 | b9adb4a6 | bellard | |
5286 | b9adb4a6 | bellard | table_op = PPC_OP (opcode->opcode); |
5287 | b9adb4a6 | bellard | if (op < table_op)
|
5288 | eca8f888 | blueswir1 | break;
|
5289 | b9adb4a6 | bellard | if (op > table_op)
|
5290 | eca8f888 | blueswir1 | continue;
|
5291 | b9adb4a6 | bellard | |
5292 | b9adb4a6 | bellard | if ((insn & opcode->mask) != opcode->opcode
|
5293 | b9adb4a6 | bellard | || (opcode->flags & dialect) == 0)
|
5294 | eca8f888 | blueswir1 | continue;
|
5295 | b9adb4a6 | bellard | |
5296 | b9adb4a6 | bellard | /* Make two passes over the operands. First see if any of them
|
5297 | eca8f888 | blueswir1 | have extraction functions, and, if they do, make sure the
|
5298 | eca8f888 | blueswir1 | instruction is valid. */
|
5299 | b9adb4a6 | bellard | invalid = 0;
|
5300 | b9adb4a6 | bellard | for (opindex = opcode->operands; *opindex != 0; opindex++) |
5301 | eca8f888 | blueswir1 | { |
5302 | eca8f888 | blueswir1 | operand = powerpc_operands + *opindex; |
5303 | eca8f888 | blueswir1 | if (operand->extract)
|
5304 | eca8f888 | blueswir1 | (*operand->extract) (insn, dialect, &invalid); |
5305 | eca8f888 | blueswir1 | } |
5306 | b9adb4a6 | bellard | if (invalid)
|
5307 | eca8f888 | blueswir1 | continue;
|
5308 | b9adb4a6 | bellard | |
5309 | b9adb4a6 | bellard | /* The instruction is valid. */
|
5310 | b9adb4a6 | bellard | if (opcode->operands[0] != 0) |
5311 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
|
5312 | eca8f888 | blueswir1 | else
|
5313 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "%s", opcode->name);
|
5314 | b9adb4a6 | bellard | |
5315 | b9adb4a6 | bellard | /* Now extract and print the operands. */
|
5316 | b9adb4a6 | bellard | need_comma = 0;
|
5317 | b9adb4a6 | bellard | need_paren = 0;
|
5318 | ee8ae9e4 | blueswir1 | skip_optional = -1;
|
5319 | b9adb4a6 | bellard | for (opindex = opcode->operands; *opindex != 0; opindex++) |
5320 | eca8f888 | blueswir1 | { |
5321 | eca8f888 | blueswir1 | long value;
|
5322 | eca8f888 | blueswir1 | |
5323 | eca8f888 | blueswir1 | operand = powerpc_operands + *opindex; |
5324 | eca8f888 | blueswir1 | |
5325 | eca8f888 | blueswir1 | /* Operands that are marked FAKE are simply ignored. We
|
5326 | eca8f888 | blueswir1 | already made sure that the extract function considered
|
5327 | eca8f888 | blueswir1 | the instruction to be valid. */
|
5328 | eca8f888 | blueswir1 | if ((operand->flags & PPC_OPERAND_FAKE) != 0) |
5329 | eca8f888 | blueswir1 | continue;
|
5330 | eca8f888 | blueswir1 | |
5331 | ee8ae9e4 | blueswir1 | /* If all of the optional operands have the value zero,
|
5332 | ee8ae9e4 | blueswir1 | then don't print any of them. */
|
5333 | ee8ae9e4 | blueswir1 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
5334 | eca8f888 | blueswir1 | { |
5335 | ee8ae9e4 | blueswir1 | if (skip_optional < 0) |
5336 | ee8ae9e4 | blueswir1 | skip_optional = skip_optional_operands (opindex, insn, |
5337 | ee8ae9e4 | blueswir1 | dialect); |
5338 | ee8ae9e4 | blueswir1 | if (skip_optional)
|
5339 | ee8ae9e4 | blueswir1 | continue;
|
5340 | eca8f888 | blueswir1 | } |
5341 | eca8f888 | blueswir1 | |
5342 | ee8ae9e4 | blueswir1 | value = operand_value_powerpc (operand, insn, dialect); |
5343 | eca8f888 | blueswir1 | |
5344 | eca8f888 | blueswir1 | if (need_comma)
|
5345 | eca8f888 | blueswir1 | { |
5346 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, ",");
|
5347 | eca8f888 | blueswir1 | need_comma = 0;
|
5348 | eca8f888 | blueswir1 | } |
5349 | eca8f888 | blueswir1 | |
5350 | eca8f888 | blueswir1 | /* Print the operand as directed by the flags. */
|
5351 | eca8f888 | blueswir1 | if ((operand->flags & PPC_OPERAND_GPR) != 0 |
5352 | eca8f888 | blueswir1 | || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) |
5353 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "r%ld", value);
|
5354 | eca8f888 | blueswir1 | else if ((operand->flags & PPC_OPERAND_FPR) != 0) |
5355 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "f%ld", value);
|
5356 | eca8f888 | blueswir1 | else if ((operand->flags & PPC_OPERAND_VR) != 0) |
5357 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "v%ld", value);
|
5358 | eca8f888 | blueswir1 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
5359 | eca8f888 | blueswir1 | (*info->print_address_func) (memaddr + value, info); |
5360 | eca8f888 | blueswir1 | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) |
5361 | eca8f888 | blueswir1 | (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
5362 | eca8f888 | blueswir1 | else if ((operand->flags & PPC_OPERAND_CR) == 0 |
5363 | eca8f888 | blueswir1 | || (dialect & PPC_OPCODE_PPC) == 0)
|
5364 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "%ld", value);
|
5365 | eca8f888 | blueswir1 | else
|
5366 | eca8f888 | blueswir1 | { |
5367 | ee8ae9e4 | blueswir1 | if (operand->bitm == 7) |
5368 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "cr%ld", value);
|
5369 | eca8f888 | blueswir1 | else
|
5370 | b9adb4a6 | bellard | { |
5371 | eca8f888 | blueswir1 | static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; |
5372 | eca8f888 | blueswir1 | int cr;
|
5373 | eca8f888 | blueswir1 | int cc;
|
5374 | eca8f888 | blueswir1 | |
5375 | eca8f888 | blueswir1 | cr = value >> 2;
|
5376 | eca8f888 | blueswir1 | if (cr != 0) |
5377 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
|
5378 | eca8f888 | blueswir1 | cc = value & 3;
|
5379 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
5380 | eca8f888 | blueswir1 | } |
5381 | b9adb4a6 | bellard | } |
5382 | b9adb4a6 | bellard | |
5383 | b9adb4a6 | bellard | if (need_paren)
|
5384 | b9adb4a6 | bellard | { |
5385 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, ")");
|
5386 | b9adb4a6 | bellard | need_paren = 0;
|
5387 | b9adb4a6 | bellard | } |
5388 | b9adb4a6 | bellard | |
5389 | b9adb4a6 | bellard | if ((operand->flags & PPC_OPERAND_PARENS) == 0) |
5390 | b9adb4a6 | bellard | need_comma = 1;
|
5391 | b9adb4a6 | bellard | else
|
5392 | b9adb4a6 | bellard | { |
5393 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, "(");
|
5394 | b9adb4a6 | bellard | need_paren = 1;
|
5395 | b9adb4a6 | bellard | } |
5396 | b9adb4a6 | bellard | } |
5397 | b9adb4a6 | bellard | |
5398 | b9adb4a6 | bellard | /* We have found and printed an instruction; return. */
|
5399 | b9adb4a6 | bellard | return 4; |
5400 | b9adb4a6 | bellard | } |
5401 | b9adb4a6 | bellard | |
5402 | eca8f888 | blueswir1 | if ((dialect & PPC_OPCODE_ANY) != 0) |
5403 | eca8f888 | blueswir1 | { |
5404 | eca8f888 | blueswir1 | dialect = ~PPC_OPCODE_ANY; |
5405 | eca8f888 | blueswir1 | goto again;
|
5406 | eca8f888 | blueswir1 | } |
5407 | eca8f888 | blueswir1 | |
5408 | b9adb4a6 | bellard | /* We could not find a match. */
|
5409 | eca8f888 | blueswir1 | (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
|
5410 | b9adb4a6 | bellard | |
5411 | b9adb4a6 | bellard | return 4; |
5412 | b9adb4a6 | bellard | } |