Revision 2dedf314
b/target-sparc/helper.h | ||
---|---|---|
138 | 138 |
DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) |
139 | 139 |
DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) |
140 | 140 |
DEF_HELPER_FLAGS_3(pdist, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) |
141 |
DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64) |
|
142 |
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) |
|
143 |
DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64) |
|
141 | 144 |
#define VIS_HELPER(name) \ |
142 | 145 |
DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE, \ |
143 | 146 |
i64, i64, i64) \ |
b/target-sparc/translate.c | ||
---|---|---|
1739 | 1739 |
gen_store_fpr_D(dc, rd, dst); |
1740 | 1740 |
} |
1741 | 1741 |
|
1742 |
static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, |
|
1743 |
void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) |
|
1744 |
{ |
|
1745 |
TCGv_i64 dst, src1, src2; |
|
1746 |
|
|
1747 |
src1 = gen_load_fpr_D(dc, rs1); |
|
1748 |
src2 = gen_load_fpr_D(dc, rs2); |
|
1749 |
dst = gen_dest_fpr_D(); |
|
1750 |
|
|
1751 |
gen(dst, cpu_gsr, src1, src2); |
|
1752 |
|
|
1753 |
gen_store_fpr_D(dc, rd, dst); |
|
1754 |
} |
|
1755 |
|
|
1742 | 1756 |
static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, |
1743 | 1757 |
void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) |
1744 | 1758 |
{ |
... | ... | |
4072 | 4086 |
gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); |
4073 | 4087 |
break; |
4074 | 4088 |
case 0x03a: /* VIS I fpack32 */ |
4089 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
4090 |
gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); |
|
4091 |
break; |
|
4075 | 4092 |
case 0x03b: /* VIS I fpack16 */ |
4093 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
4094 |
cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
|
4095 |
cpu_dst_32 = gen_dest_fpr_F(); |
|
4096 |
gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); |
|
4097 |
gen_store_fpr_F(dc, rd, cpu_dst_32); |
|
4098 |
break; |
|
4076 | 4099 |
case 0x03d: /* VIS I fpackfix */ |
4077 |
goto illegal_insn; |
|
4100 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
4101 |
cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
|
4102 |
cpu_dst_32 = gen_dest_fpr_F(); |
|
4103 |
gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); |
|
4104 |
gen_store_fpr_F(dc, rd, cpu_dst_32); |
|
4105 |
break; |
|
4078 | 4106 |
case 0x03e: /* VIS I pdist */ |
4079 | 4107 |
CHECK_FPU_FEATURE(dc, VIS1); |
4080 | 4108 |
gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); |
b/target-sparc/vis_helper.c | ||
---|---|---|
417 | 417 |
|
418 | 418 |
return sum; |
419 | 419 |
} |
420 |
|
|
421 |
uint32_t helper_fpack16(uint64_t gsr, uint64_t rs2) |
|
422 |
{ |
|
423 |
int scale = (gsr >> 3) & 0xf; |
|
424 |
uint32_t ret = 0; |
|
425 |
int byte; |
|
426 |
|
|
427 |
for (byte = 0; byte < 4; byte++) { |
|
428 |
uint32_t val; |
|
429 |
int16_t src = rs2 >> (byte * 16); |
|
430 |
int32_t scaled = src << scale; |
|
431 |
int32_t from_fixed = scaled >> 7; |
|
432 |
|
|
433 |
val = (from_fixed < 0 ? 0 : |
|
434 |
from_fixed > 255 ? 255 : from_fixed); |
|
435 |
|
|
436 |
ret |= val << (8 * byte); |
|
437 |
} |
|
438 |
|
|
439 |
return ret; |
|
440 |
} |
|
441 |
|
|
442 |
uint64_t helper_fpack32(uint64_t gsr, uint64_t rs1, uint64_t rs2) |
|
443 |
{ |
|
444 |
int scale = (gsr >> 3) & 0x1f; |
|
445 |
uint64_t ret = 0; |
|
446 |
int word; |
|
447 |
|
|
448 |
ret = (rs1 << 8) & ~(0x000000ff000000ffULL); |
|
449 |
for (word = 0; word < 2; word++) { |
|
450 |
uint64_t val; |
|
451 |
int32_t src = rs2 >> (word * 32); |
|
452 |
int64_t scaled = (int64_t)src << scale; |
|
453 |
int64_t from_fixed = scaled >> 23; |
|
454 |
|
|
455 |
val = (from_fixed < 0 ? 0 : |
|
456 |
(from_fixed > 255) ? 255 : from_fixed); |
|
457 |
|
|
458 |
ret |= val << (32 * word); |
|
459 |
} |
|
460 |
|
|
461 |
return ret; |
|
462 |
} |
|
463 |
|
|
464 |
uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2) |
|
465 |
{ |
|
466 |
int scale = (gsr >> 3) & 0x1f; |
|
467 |
uint32_t ret = 0; |
|
468 |
int word; |
|
469 |
|
|
470 |
for (word = 0; word < 2; word++) { |
|
471 |
uint32_t val; |
|
472 |
int32_t src = rs2 >> (word * 32); |
|
473 |
int64_t scaled = src << scale; |
|
474 |
int64_t from_fixed = scaled >> 16; |
|
475 |
|
|
476 |
val = (from_fixed < -32768 ? -32768 : |
|
477 |
from_fixed > 32767 ? 32767 : from_fixed); |
|
478 |
|
|
479 |
ret |= (val & 0xffff) << (word * 16); |
|
480 |
} |
|
481 |
|
|
482 |
return ret; |
|
483 |
} |
Also available in: Unified diff