Revision 2dedf314 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 1739 | 1739 |
gen_store_fpr_D(dc, rd, dst); |
| 1740 | 1740 |
} |
| 1741 | 1741 |
|
| 1742 |
static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, |
|
| 1743 |
void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) |
|
| 1744 |
{
|
|
| 1745 |
TCGv_i64 dst, src1, src2; |
|
| 1746 |
|
|
| 1747 |
src1 = gen_load_fpr_D(dc, rs1); |
|
| 1748 |
src2 = gen_load_fpr_D(dc, rs2); |
|
| 1749 |
dst = gen_dest_fpr_D(); |
|
| 1750 |
|
|
| 1751 |
gen(dst, cpu_gsr, src1, src2); |
|
| 1752 |
|
|
| 1753 |
gen_store_fpr_D(dc, rd, dst); |
|
| 1754 |
} |
|
| 1755 |
|
|
| 1742 | 1756 |
static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, |
| 1743 | 1757 |
void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) |
| 1744 | 1758 |
{
|
| ... | ... | |
| 4072 | 4086 |
gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); |
| 4073 | 4087 |
break; |
| 4074 | 4088 |
case 0x03a: /* VIS I fpack32 */ |
| 4089 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
| 4090 |
gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); |
|
| 4091 |
break; |
|
| 4075 | 4092 |
case 0x03b: /* VIS I fpack16 */ |
| 4093 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
| 4094 |
cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
|
| 4095 |
cpu_dst_32 = gen_dest_fpr_F(); |
|
| 4096 |
gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); |
|
| 4097 |
gen_store_fpr_F(dc, rd, cpu_dst_32); |
|
| 4098 |
break; |
|
| 4076 | 4099 |
case 0x03d: /* VIS I fpackfix */ |
| 4077 |
goto illegal_insn; |
|
| 4100 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
| 4101 |
cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
|
| 4102 |
cpu_dst_32 = gen_dest_fpr_F(); |
|
| 4103 |
gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); |
|
| 4104 |
gen_store_fpr_F(dc, rd, cpu_dst_32); |
|
| 4105 |
break; |
|
| 4078 | 4106 |
case 0x03e: /* VIS I pdist */ |
| 4079 | 4107 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4080 | 4108 |
gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); |
Also available in: Unified diff