Revision 2e15497c
| b/target-mips/translate.c | ||
|---|---|---|
| 5933 | 5933 |
{
|
| 5934 | 5934 |
const char *opn = "ldst"; |
| 5935 | 5935 |
|
| 5936 |
check_cp0_enabled(ctx); |
|
| 5936 | 5937 |
switch (opc) {
|
| 5937 | 5938 |
case OPC_MFC0: |
| 5938 | 5939 |
if (rt == 0) {
|
| ... | ... | |
| 10121 | 10122 |
#ifndef CONFIG_USER_ONLY |
| 10122 | 10123 |
case MFC0: |
| 10123 | 10124 |
case MFC0 + 32: |
| 10125 |
check_cp0_enabled(ctx); |
|
| 10124 | 10126 |
if (rt == 0) {
|
| 10125 | 10127 |
/* Treat as NOP. */ |
| 10126 | 10128 |
break; |
| ... | ... | |
| 10129 | 10131 |
break; |
| 10130 | 10132 |
case MTC0: |
| 10131 | 10133 |
case MTC0 + 32: |
| 10134 |
check_cp0_enabled(ctx); |
|
| 10132 | 10135 |
{
|
| 10133 | 10136 |
TCGv t0 = tcg_temp_new(); |
| 10134 | 10137 |
|
| ... | ... | |
| 10225 | 10228 |
case 0x05: |
| 10226 | 10229 |
switch (minor) {
|
| 10227 | 10230 |
case RDPGPR: |
| 10231 |
check_cp0_enabled(ctx); |
|
| 10228 | 10232 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 10229 | 10233 |
gen_load_srsgpr(rt, rs); |
| 10230 | 10234 |
break; |
| 10231 | 10235 |
case WRPGPR: |
| 10236 |
check_cp0_enabled(ctx); |
|
| 10232 | 10237 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 10233 | 10238 |
gen_store_srsgpr(rt, rs); |
| 10234 | 10239 |
break; |
| ... | ... | |
| 10269 | 10274 |
case 0x1d: |
| 10270 | 10275 |
switch (minor) {
|
| 10271 | 10276 |
case DI: |
| 10277 |
check_cp0_enabled(ctx); |
|
| 10272 | 10278 |
{
|
| 10273 | 10279 |
TCGv t0 = tcg_temp_new(); |
| 10274 | 10280 |
|
| ... | ... | |
| 10281 | 10287 |
} |
| 10282 | 10288 |
break; |
| 10283 | 10289 |
case EI: |
| 10290 |
check_cp0_enabled(ctx); |
|
| 10284 | 10291 |
{
|
| 10285 | 10292 |
TCGv t0 = tcg_temp_new(); |
| 10286 | 10293 |
|
| ... | ... | |
| 10761 | 10768 |
minor = (ctx->opcode >> 12) & 0xf; |
| 10762 | 10769 |
switch (minor) {
|
| 10763 | 10770 |
case CACHE: |
| 10771 |
check_cp0_enabled(ctx); |
|
| 10764 | 10772 |
/* Treat as no-op. */ |
| 10765 | 10773 |
break; |
| 10766 | 10774 |
case LWC2: |
| ... | ... | |
| 12211 | 12219 |
gen_st_cond(ctx, op, rt, rs, imm); |
| 12212 | 12220 |
break; |
| 12213 | 12221 |
case OPC_CACHE: |
| 12222 |
check_cp0_enabled(ctx); |
|
| 12214 | 12223 |
check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); |
| 12215 | 12224 |
/* Treat as NOP. */ |
| 12216 | 12225 |
break; |
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