Revision 2e2f4ade target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 1405 | 1405 |
{
|
| 1406 | 1406 |
switch (fccno) {
|
| 1407 | 1407 |
case 0: |
| 1408 |
gen_helper_fcmps(r_rs1, r_rs2); |
|
| 1408 |
gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
|
|
| 1409 | 1409 |
break; |
| 1410 | 1410 |
case 1: |
| 1411 |
gen_helper_fcmps_fcc1(r_rs1, r_rs2); |
|
| 1411 |
gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
|
|
| 1412 | 1412 |
break; |
| 1413 | 1413 |
case 2: |
| 1414 |
gen_helper_fcmps_fcc2(r_rs1, r_rs2); |
|
| 1414 |
gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
|
|
| 1415 | 1415 |
break; |
| 1416 | 1416 |
case 3: |
| 1417 |
gen_helper_fcmps_fcc3(r_rs1, r_rs2); |
|
| 1417 |
gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
|
|
| 1418 | 1418 |
break; |
| 1419 | 1419 |
} |
| 1420 | 1420 |
} |
| ... | ... | |
| 1423 | 1423 |
{
|
| 1424 | 1424 |
switch (fccno) {
|
| 1425 | 1425 |
case 0: |
| 1426 |
gen_helper_fcmpd(); |
|
| 1426 |
gen_helper_fcmpd(cpu_env);
|
|
| 1427 | 1427 |
break; |
| 1428 | 1428 |
case 1: |
| 1429 |
gen_helper_fcmpd_fcc1(); |
|
| 1429 |
gen_helper_fcmpd_fcc1(cpu_env);
|
|
| 1430 | 1430 |
break; |
| 1431 | 1431 |
case 2: |
| 1432 |
gen_helper_fcmpd_fcc2(); |
|
| 1432 |
gen_helper_fcmpd_fcc2(cpu_env);
|
|
| 1433 | 1433 |
break; |
| 1434 | 1434 |
case 3: |
| 1435 |
gen_helper_fcmpd_fcc3(); |
|
| 1435 |
gen_helper_fcmpd_fcc3(cpu_env);
|
|
| 1436 | 1436 |
break; |
| 1437 | 1437 |
} |
| 1438 | 1438 |
} |
| ... | ... | |
| 1441 | 1441 |
{
|
| 1442 | 1442 |
switch (fccno) {
|
| 1443 | 1443 |
case 0: |
| 1444 |
gen_helper_fcmpq(); |
|
| 1444 |
gen_helper_fcmpq(cpu_env);
|
|
| 1445 | 1445 |
break; |
| 1446 | 1446 |
case 1: |
| 1447 |
gen_helper_fcmpq_fcc1(); |
|
| 1447 |
gen_helper_fcmpq_fcc1(cpu_env);
|
|
| 1448 | 1448 |
break; |
| 1449 | 1449 |
case 2: |
| 1450 |
gen_helper_fcmpq_fcc2(); |
|
| 1450 |
gen_helper_fcmpq_fcc2(cpu_env);
|
|
| 1451 | 1451 |
break; |
| 1452 | 1452 |
case 3: |
| 1453 |
gen_helper_fcmpq_fcc3(); |
|
| 1453 |
gen_helper_fcmpq_fcc3(cpu_env);
|
|
| 1454 | 1454 |
break; |
| 1455 | 1455 |
} |
| 1456 | 1456 |
} |
| ... | ... | |
| 1459 | 1459 |
{
|
| 1460 | 1460 |
switch (fccno) {
|
| 1461 | 1461 |
case 0: |
| 1462 |
gen_helper_fcmpes(r_rs1, r_rs2); |
|
| 1462 |
gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
|
|
| 1463 | 1463 |
break; |
| 1464 | 1464 |
case 1: |
| 1465 |
gen_helper_fcmpes_fcc1(r_rs1, r_rs2); |
|
| 1465 |
gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
|
|
| 1466 | 1466 |
break; |
| 1467 | 1467 |
case 2: |
| 1468 |
gen_helper_fcmpes_fcc2(r_rs1, r_rs2); |
|
| 1468 |
gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
|
|
| 1469 | 1469 |
break; |
| 1470 | 1470 |
case 3: |
| 1471 |
gen_helper_fcmpes_fcc3(r_rs1, r_rs2); |
|
| 1471 |
gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
|
|
| 1472 | 1472 |
break; |
| 1473 | 1473 |
} |
| 1474 | 1474 |
} |
| ... | ... | |
| 1477 | 1477 |
{
|
| 1478 | 1478 |
switch (fccno) {
|
| 1479 | 1479 |
case 0: |
| 1480 |
gen_helper_fcmped(); |
|
| 1480 |
gen_helper_fcmped(cpu_env);
|
|
| 1481 | 1481 |
break; |
| 1482 | 1482 |
case 1: |
| 1483 |
gen_helper_fcmped_fcc1(); |
|
| 1483 |
gen_helper_fcmped_fcc1(cpu_env);
|
|
| 1484 | 1484 |
break; |
| 1485 | 1485 |
case 2: |
| 1486 |
gen_helper_fcmped_fcc2(); |
|
| 1486 |
gen_helper_fcmped_fcc2(cpu_env);
|
|
| 1487 | 1487 |
break; |
| 1488 | 1488 |
case 3: |
| 1489 |
gen_helper_fcmped_fcc3(); |
|
| 1489 |
gen_helper_fcmped_fcc3(cpu_env);
|
|
| 1490 | 1490 |
break; |
| 1491 | 1491 |
} |
| 1492 | 1492 |
} |
| ... | ... | |
| 1495 | 1495 |
{
|
| 1496 | 1496 |
switch (fccno) {
|
| 1497 | 1497 |
case 0: |
| 1498 |
gen_helper_fcmpeq(); |
|
| 1498 |
gen_helper_fcmpeq(cpu_env);
|
|
| 1499 | 1499 |
break; |
| 1500 | 1500 |
case 1: |
| 1501 |
gen_helper_fcmpeq_fcc1(); |
|
| 1501 |
gen_helper_fcmpeq_fcc1(cpu_env);
|
|
| 1502 | 1502 |
break; |
| 1503 | 1503 |
case 2: |
| 1504 |
gen_helper_fcmpeq_fcc2(); |
|
| 1504 |
gen_helper_fcmpeq_fcc2(cpu_env);
|
|
| 1505 | 1505 |
break; |
| 1506 | 1506 |
case 3: |
| 1507 |
gen_helper_fcmpeq_fcc3(); |
|
| 1507 |
gen_helper_fcmpeq_fcc3(cpu_env);
|
|
| 1508 | 1508 |
break; |
| 1509 | 1509 |
} |
| 1510 | 1510 |
} |
| ... | ... | |
| 1513 | 1513 |
|
| 1514 | 1514 |
static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
| 1515 | 1515 |
{
|
| 1516 |
gen_helper_fcmps(r_rs1, r_rs2); |
|
| 1516 |
gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
|
|
| 1517 | 1517 |
} |
| 1518 | 1518 |
|
| 1519 | 1519 |
static inline void gen_op_fcmpd(int fccno) |
| 1520 | 1520 |
{
|
| 1521 |
gen_helper_fcmpd(); |
|
| 1521 |
gen_helper_fcmpd(cpu_env);
|
|
| 1522 | 1522 |
} |
| 1523 | 1523 |
|
| 1524 | 1524 |
static inline void gen_op_fcmpq(int fccno) |
| 1525 | 1525 |
{
|
| 1526 |
gen_helper_fcmpq(); |
|
| 1526 |
gen_helper_fcmpq(cpu_env);
|
|
| 1527 | 1527 |
} |
| 1528 | 1528 |
|
| 1529 | 1529 |
static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
| 1530 | 1530 |
{
|
| 1531 |
gen_helper_fcmpes(r_rs1, r_rs2); |
|
| 1531 |
gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
|
|
| 1532 | 1532 |
} |
| 1533 | 1533 |
|
| 1534 | 1534 |
static inline void gen_op_fcmped(int fccno) |
| 1535 | 1535 |
{
|
| 1536 |
gen_helper_fcmped(); |
|
| 1536 |
gen_helper_fcmped(cpu_env);
|
|
| 1537 | 1537 |
} |
| 1538 | 1538 |
|
| 1539 | 1539 |
static inline void gen_op_fcmpeq(int fccno) |
| 1540 | 1540 |
{
|
| 1541 |
gen_helper_fcmpeq(); |
|
| 1541 |
gen_helper_fcmpeq(cpu_env);
|
|
| 1542 | 1542 |
} |
| 1543 | 1543 |
#endif |
| 1544 | 1544 |
|
| ... | ... | |
| 1584 | 1584 |
|
| 1585 | 1585 |
static inline void gen_clear_float_exceptions(void) |
| 1586 | 1586 |
{
|
| 1587 |
gen_helper_clear_float_exceptions(); |
|
| 1587 |
gen_helper_clear_float_exceptions(cpu_env);
|
|
| 1588 | 1588 |
} |
| 1589 | 1589 |
|
| 1590 | 1590 |
/* asi moves */ |
| ... | ... | |
| 2383 | 2383 |
case 0x29: /* fsqrts */ |
| 2384 | 2384 |
CHECK_FPU_FEATURE(dc, FSQRT); |
| 2385 | 2385 |
gen_clear_float_exceptions(); |
| 2386 |
gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
|
| 2387 |
gen_helper_check_ieee_exceptions(); |
|
| 2386 |
gen_helper_fsqrts(cpu_tmp32, cpu_env, cpu_fpr[rs2]);
|
|
| 2387 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2388 | 2388 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2389 | 2389 |
gen_update_fprs_dirty(rd); |
| 2390 | 2390 |
break; |
| ... | ... | |
| 2392 | 2392 |
CHECK_FPU_FEATURE(dc, FSQRT); |
| 2393 | 2393 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2394 | 2394 |
gen_clear_float_exceptions(); |
| 2395 |
gen_helper_fsqrtd(); |
|
| 2396 |
gen_helper_check_ieee_exceptions(); |
|
| 2395 |
gen_helper_fsqrtd(cpu_env);
|
|
| 2396 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2397 | 2397 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2398 | 2398 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2399 | 2399 |
break; |
| ... | ... | |
| 2401 | 2401 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2402 | 2402 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2403 | 2403 |
gen_clear_float_exceptions(); |
| 2404 |
gen_helper_fsqrtq(); |
|
| 2405 |
gen_helper_check_ieee_exceptions(); |
|
| 2404 |
gen_helper_fsqrtq(cpu_env);
|
|
| 2405 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2406 | 2406 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2407 | 2407 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2408 | 2408 |
break; |
| 2409 | 2409 |
case 0x41: /* fadds */ |
| 2410 | 2410 |
gen_clear_float_exceptions(); |
| 2411 |
gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2412 |
gen_helper_check_ieee_exceptions(); |
|
| 2411 |
gen_helper_fadds(cpu_tmp32, cpu_env, cpu_fpr[rs1], |
|
| 2412 |
cpu_fpr[rs2]); |
|
| 2413 |
gen_helper_check_ieee_exceptions(cpu_env); |
|
| 2413 | 2414 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2414 | 2415 |
gen_update_fprs_dirty(rd); |
| 2415 | 2416 |
break; |
| ... | ... | |
| 2417 | 2418 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2418 | 2419 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2419 | 2420 |
gen_clear_float_exceptions(); |
| 2420 |
gen_helper_faddd(); |
|
| 2421 |
gen_helper_check_ieee_exceptions(); |
|
| 2421 |
gen_helper_faddd(cpu_env);
|
|
| 2422 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2422 | 2423 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2423 | 2424 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2424 | 2425 |
break; |
| ... | ... | |
| 2427 | 2428 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2428 | 2429 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2429 | 2430 |
gen_clear_float_exceptions(); |
| 2430 |
gen_helper_faddq(); |
|
| 2431 |
gen_helper_check_ieee_exceptions(); |
|
| 2431 |
gen_helper_faddq(cpu_env);
|
|
| 2432 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2432 | 2433 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2433 | 2434 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2434 | 2435 |
break; |
| 2435 | 2436 |
case 0x45: /* fsubs */ |
| 2436 | 2437 |
gen_clear_float_exceptions(); |
| 2437 |
gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2438 |
gen_helper_check_ieee_exceptions(); |
|
| 2438 |
gen_helper_fsubs(cpu_tmp32, cpu_env, cpu_fpr[rs1], |
|
| 2439 |
cpu_fpr[rs2]); |
|
| 2440 |
gen_helper_check_ieee_exceptions(cpu_env); |
|
| 2439 | 2441 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2440 | 2442 |
gen_update_fprs_dirty(rd); |
| 2441 | 2443 |
break; |
| ... | ... | |
| 2443 | 2445 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2444 | 2446 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2445 | 2447 |
gen_clear_float_exceptions(); |
| 2446 |
gen_helper_fsubd(); |
|
| 2447 |
gen_helper_check_ieee_exceptions(); |
|
| 2448 |
gen_helper_fsubd(cpu_env);
|
|
| 2449 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2448 | 2450 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2449 | 2451 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2450 | 2452 |
break; |
| ... | ... | |
| 2453 | 2455 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2454 | 2456 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2455 | 2457 |
gen_clear_float_exceptions(); |
| 2456 |
gen_helper_fsubq(); |
|
| 2457 |
gen_helper_check_ieee_exceptions(); |
|
| 2458 |
gen_helper_fsubq(cpu_env);
|
|
| 2459 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2458 | 2460 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2459 | 2461 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2460 | 2462 |
break; |
| 2461 | 2463 |
case 0x49: /* fmuls */ |
| 2462 | 2464 |
CHECK_FPU_FEATURE(dc, FMUL); |
| 2463 | 2465 |
gen_clear_float_exceptions(); |
| 2464 |
gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2465 |
gen_helper_check_ieee_exceptions(); |
|
| 2466 |
gen_helper_fmuls(cpu_tmp32, cpu_env, cpu_fpr[rs1], |
|
| 2467 |
cpu_fpr[rs2]); |
|
| 2468 |
gen_helper_check_ieee_exceptions(cpu_env); |
|
| 2466 | 2469 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2467 | 2470 |
gen_update_fprs_dirty(rd); |
| 2468 | 2471 |
break; |
| ... | ... | |
| 2471 | 2474 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2472 | 2475 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2473 | 2476 |
gen_clear_float_exceptions(); |
| 2474 |
gen_helper_fmuld(); |
|
| 2475 |
gen_helper_check_ieee_exceptions(); |
|
| 2477 |
gen_helper_fmuld(cpu_env);
|
|
| 2478 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2476 | 2479 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2477 | 2480 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2478 | 2481 |
break; |
| ... | ... | |
| 2482 | 2485 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2483 | 2486 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2484 | 2487 |
gen_clear_float_exceptions(); |
| 2485 |
gen_helper_fmulq(); |
|
| 2486 |
gen_helper_check_ieee_exceptions(); |
|
| 2488 |
gen_helper_fmulq(cpu_env);
|
|
| 2489 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2487 | 2490 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2488 | 2491 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2489 | 2492 |
break; |
| 2490 | 2493 |
case 0x4d: /* fdivs */ |
| 2491 | 2494 |
gen_clear_float_exceptions(); |
| 2492 |
gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2493 |
gen_helper_check_ieee_exceptions(); |
|
| 2495 |
gen_helper_fdivs(cpu_tmp32, cpu_env, cpu_fpr[rs1], |
|
| 2496 |
cpu_fpr[rs2]); |
|
| 2497 |
gen_helper_check_ieee_exceptions(cpu_env); |
|
| 2494 | 2498 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2495 | 2499 |
gen_update_fprs_dirty(rd); |
| 2496 | 2500 |
break; |
| ... | ... | |
| 2498 | 2502 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2499 | 2503 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2500 | 2504 |
gen_clear_float_exceptions(); |
| 2501 |
gen_helper_fdivd(); |
|
| 2502 |
gen_helper_check_ieee_exceptions(); |
|
| 2505 |
gen_helper_fdivd(cpu_env);
|
|
| 2506 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2503 | 2507 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2504 | 2508 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2505 | 2509 |
break; |
| ... | ... | |
| 2508 | 2512 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2509 | 2513 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2510 | 2514 |
gen_clear_float_exceptions(); |
| 2511 |
gen_helper_fdivq(); |
|
| 2512 |
gen_helper_check_ieee_exceptions(); |
|
| 2515 |
gen_helper_fdivq(cpu_env);
|
|
| 2516 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2513 | 2517 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2514 | 2518 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2515 | 2519 |
break; |
| 2516 | 2520 |
case 0x69: /* fsmuld */ |
| 2517 | 2521 |
CHECK_FPU_FEATURE(dc, FSMULD); |
| 2518 | 2522 |
gen_clear_float_exceptions(); |
| 2519 |
gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2520 |
gen_helper_check_ieee_exceptions(); |
|
| 2523 |
gen_helper_fsmuld(cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
|
|
| 2524 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2521 | 2525 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2522 | 2526 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2523 | 2527 |
break; |
| ... | ... | |
| 2526 | 2530 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2527 | 2531 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2528 | 2532 |
gen_clear_float_exceptions(); |
| 2529 |
gen_helper_fdmulq(); |
|
| 2530 |
gen_helper_check_ieee_exceptions(); |
|
| 2533 |
gen_helper_fdmulq(cpu_env);
|
|
| 2534 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2531 | 2535 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2532 | 2536 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2533 | 2537 |
break; |
| 2534 | 2538 |
case 0xc4: /* fitos */ |
| 2535 | 2539 |
gen_clear_float_exceptions(); |
| 2536 |
gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
|
| 2537 |
gen_helper_check_ieee_exceptions(); |
|
| 2540 |
gen_helper_fitos(cpu_tmp32, cpu_env, cpu_fpr[rs2]);
|
|
| 2541 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2538 | 2542 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2539 | 2543 |
gen_update_fprs_dirty(rd); |
| 2540 | 2544 |
break; |
| 2541 | 2545 |
case 0xc6: /* fdtos */ |
| 2542 | 2546 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2543 | 2547 |
gen_clear_float_exceptions(); |
| 2544 |
gen_helper_fdtos(cpu_tmp32); |
|
| 2545 |
gen_helper_check_ieee_exceptions(); |
|
| 2548 |
gen_helper_fdtos(cpu_tmp32, cpu_env);
|
|
| 2549 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2546 | 2550 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2547 | 2551 |
gen_update_fprs_dirty(rd); |
| 2548 | 2552 |
break; |
| ... | ... | |
| 2550 | 2554 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2551 | 2555 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2552 | 2556 |
gen_clear_float_exceptions(); |
| 2553 |
gen_helper_fqtos(cpu_tmp32); |
|
| 2554 |
gen_helper_check_ieee_exceptions(); |
|
| 2557 |
gen_helper_fqtos(cpu_tmp32, cpu_env);
|
|
| 2558 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2555 | 2559 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2556 | 2560 |
gen_update_fprs_dirty(rd); |
| 2557 | 2561 |
break; |
| 2558 | 2562 |
case 0xc8: /* fitod */ |
| 2559 |
gen_helper_fitod(cpu_fpr[rs2]); |
|
| 2563 |
gen_helper_fitod(cpu_env, cpu_fpr[rs2]);
|
|
| 2560 | 2564 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2561 | 2565 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2562 | 2566 |
break; |
| 2563 | 2567 |
case 0xc9: /* fstod */ |
| 2564 |
gen_helper_fstod(cpu_fpr[rs2]); |
|
| 2568 |
gen_helper_fstod(cpu_env, cpu_fpr[rs2]);
|
|
| 2565 | 2569 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2566 | 2570 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2567 | 2571 |
break; |
| ... | ... | |
| 2569 | 2573 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2570 | 2574 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2571 | 2575 |
gen_clear_float_exceptions(); |
| 2572 |
gen_helper_fqtod(); |
|
| 2573 |
gen_helper_check_ieee_exceptions(); |
|
| 2576 |
gen_helper_fqtod(cpu_env);
|
|
| 2577 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2574 | 2578 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2575 | 2579 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2576 | 2580 |
break; |
| 2577 | 2581 |
case 0xcc: /* fitoq */ |
| 2578 | 2582 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2579 |
gen_helper_fitoq(cpu_fpr[rs2]); |
|
| 2583 |
gen_helper_fitoq(cpu_env, cpu_fpr[rs2]);
|
|
| 2580 | 2584 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2581 | 2585 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2582 | 2586 |
break; |
| 2583 | 2587 |
case 0xcd: /* fstoq */ |
| 2584 | 2588 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2585 |
gen_helper_fstoq(cpu_fpr[rs2]); |
|
| 2589 |
gen_helper_fstoq(cpu_env, cpu_fpr[rs2]);
|
|
| 2586 | 2590 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2587 | 2591 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2588 | 2592 |
break; |
| 2589 | 2593 |
case 0xce: /* fdtoq */ |
| 2590 | 2594 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2591 | 2595 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2592 |
gen_helper_fdtoq(); |
|
| 2596 |
gen_helper_fdtoq(cpu_env);
|
|
| 2593 | 2597 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2594 | 2598 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2595 | 2599 |
break; |
| 2596 | 2600 |
case 0xd1: /* fstoi */ |
| 2597 | 2601 |
gen_clear_float_exceptions(); |
| 2598 |
gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
|
| 2599 |
gen_helper_check_ieee_exceptions(); |
|
| 2602 |
gen_helper_fstoi(cpu_tmp32, cpu_env, cpu_fpr[rs2]);
|
|
| 2603 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2600 | 2604 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2601 | 2605 |
gen_update_fprs_dirty(rd); |
| 2602 | 2606 |
break; |
| 2603 | 2607 |
case 0xd2: /* fdtoi */ |
| 2604 | 2608 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2605 | 2609 |
gen_clear_float_exceptions(); |
| 2606 |
gen_helper_fdtoi(cpu_tmp32); |
|
| 2607 |
gen_helper_check_ieee_exceptions(); |
|
| 2610 |
gen_helper_fdtoi(cpu_tmp32, cpu_env);
|
|
| 2611 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2608 | 2612 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2609 | 2613 |
gen_update_fprs_dirty(rd); |
| 2610 | 2614 |
break; |
| ... | ... | |
| 2612 | 2616 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2613 | 2617 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2614 | 2618 |
gen_clear_float_exceptions(); |
| 2615 |
gen_helper_fqtoi(cpu_tmp32); |
|
| 2616 |
gen_helper_check_ieee_exceptions(); |
|
| 2619 |
gen_helper_fqtoi(cpu_tmp32, cpu_env);
|
|
| 2620 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2617 | 2621 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2618 | 2622 |
gen_update_fprs_dirty(rd); |
| 2619 | 2623 |
break; |
| ... | ... | |
| 2637 | 2641 |
break; |
| 2638 | 2642 |
case 0x6: /* V9 fnegd */ |
| 2639 | 2643 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2640 |
gen_helper_fnegd(); |
|
| 2644 |
gen_helper_fnegd(cpu_env);
|
|
| 2641 | 2645 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2642 | 2646 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2643 | 2647 |
break; |
| 2644 | 2648 |
case 0x7: /* V9 fnegq */ |
| 2645 | 2649 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2646 | 2650 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2647 |
gen_helper_fnegq(); |
|
| 2651 |
gen_helper_fnegq(cpu_env);
|
|
| 2648 | 2652 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2649 | 2653 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2650 | 2654 |
break; |
| 2651 | 2655 |
case 0xa: /* V9 fabsd */ |
| 2652 | 2656 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2653 |
gen_helper_fabsd(); |
|
| 2657 |
gen_helper_fabsd(cpu_env);
|
|
| 2654 | 2658 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2655 | 2659 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2656 | 2660 |
break; |
| 2657 | 2661 |
case 0xb: /* V9 fabsq */ |
| 2658 | 2662 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2659 | 2663 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2660 |
gen_helper_fabsq(); |
|
| 2664 |
gen_helper_fabsq(cpu_env);
|
|
| 2661 | 2665 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2662 | 2666 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2663 | 2667 |
break; |
| 2664 | 2668 |
case 0x81: /* V9 fstox */ |
| 2665 | 2669 |
gen_clear_float_exceptions(); |
| 2666 |
gen_helper_fstox(cpu_fpr[rs2]); |
|
| 2667 |
gen_helper_check_ieee_exceptions(); |
|
| 2670 |
gen_helper_fstox(cpu_env, cpu_fpr[rs2]);
|
|
| 2671 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2668 | 2672 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2669 | 2673 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2670 | 2674 |
break; |
| 2671 | 2675 |
case 0x82: /* V9 fdtox */ |
| 2672 | 2676 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2673 | 2677 |
gen_clear_float_exceptions(); |
| 2674 |
gen_helper_fdtox(); |
|
| 2675 |
gen_helper_check_ieee_exceptions(); |
|
| 2678 |
gen_helper_fdtox(cpu_env);
|
|
| 2679 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2676 | 2680 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2677 | 2681 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2678 | 2682 |
break; |
| ... | ... | |
| 2680 | 2684 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2681 | 2685 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2682 | 2686 |
gen_clear_float_exceptions(); |
| 2683 |
gen_helper_fqtox(); |
|
| 2684 |
gen_helper_check_ieee_exceptions(); |
|
| 2687 |
gen_helper_fqtox(cpu_env);
|
|
| 2688 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2685 | 2689 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2686 | 2690 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2687 | 2691 |
break; |
| 2688 | 2692 |
case 0x84: /* V9 fxtos */ |
| 2689 | 2693 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2690 | 2694 |
gen_clear_float_exceptions(); |
| 2691 |
gen_helper_fxtos(cpu_tmp32); |
|
| 2692 |
gen_helper_check_ieee_exceptions(); |
|
| 2695 |
gen_helper_fxtos(cpu_tmp32, cpu_env);
|
|
| 2696 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2693 | 2697 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2694 | 2698 |
gen_update_fprs_dirty(rd); |
| 2695 | 2699 |
break; |
| 2696 | 2700 |
case 0x88: /* V9 fxtod */ |
| 2697 | 2701 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2698 | 2702 |
gen_clear_float_exceptions(); |
| 2699 |
gen_helper_fxtod(); |
|
| 2700 |
gen_helper_check_ieee_exceptions(); |
|
| 2703 |
gen_helper_fxtod(cpu_env);
|
|
| 2704 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2701 | 2705 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2702 | 2706 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 2703 | 2707 |
break; |
| ... | ... | |
| 2705 | 2709 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2706 | 2710 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2707 | 2711 |
gen_clear_float_exceptions(); |
| 2708 |
gen_helper_fxtoq(); |
|
| 2709 |
gen_helper_check_ieee_exceptions(); |
|
| 2712 |
gen_helper_fxtoq(cpu_env);
|
|
| 2713 |
gen_helper_check_ieee_exceptions(cpu_env);
|
|
| 2710 | 2714 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2711 | 2715 |
gen_update_fprs_dirty(QFPREG(rd)); |
| 2712 | 2716 |
break; |
| ... | ... | |
| 3828 | 3832 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3829 | 3833 |
cpu_src1 = get_src1(insn, cpu_src1); |
| 3830 | 3834 |
gen_movl_reg_TN(rs2, cpu_src2); |
| 3831 |
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
|
| 3835 |
gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2);
|
|
| 3832 | 3836 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3833 | 3837 |
break; |
| 3834 | 3838 |
case 0x012: /* VIS I array16 */ |
| 3835 | 3839 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3836 | 3840 |
cpu_src1 = get_src1(insn, cpu_src1); |
| 3837 | 3841 |
gen_movl_reg_TN(rs2, cpu_src2); |
| 3838 |
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
|
| 3842 |
gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2);
|
|
| 3839 | 3843 |
tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); |
| 3840 | 3844 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3841 | 3845 |
break; |
| ... | ... | |
| 3843 | 3847 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3844 | 3848 |
cpu_src1 = get_src1(insn, cpu_src1); |
| 3845 | 3849 |
gen_movl_reg_TN(rs2, cpu_src2); |
| 3846 |
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
|
| 3850 |
gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2);
|
|
| 3847 | 3851 |
tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); |
| 3848 | 3852 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3849 | 3853 |
break; |
| ... | ... | |
| 3851 | 3855 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3852 | 3856 |
cpu_src1 = get_src1(insn, cpu_src1); |
| 3853 | 3857 |
gen_movl_reg_TN(rs2, cpu_src2); |
| 3854 |
gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); |
|
| 3858 |
gen_helper_alignaddr(cpu_dst, cpu_env, cpu_src1, cpu_src2);
|
|
| 3855 | 3859 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3856 | 3860 |
break; |
| 3857 | 3861 |
case 0x019: /* VIS II bmask */ |
| ... | ... | |
| 3862 | 3866 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3863 | 3867 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3864 | 3868 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3865 |
gen_helper_fcmple16(cpu_dst); |
|
| 3869 |
gen_helper_fcmple16(cpu_dst, cpu_env);
|
|
| 3866 | 3870 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3867 | 3871 |
break; |
| 3868 | 3872 |
case 0x022: /* VIS I fcmpne16 */ |
| 3869 | 3873 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3870 | 3874 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3871 | 3875 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3872 |
gen_helper_fcmpne16(cpu_dst); |
|
| 3876 |
gen_helper_fcmpne16(cpu_dst, cpu_env);
|
|
| 3873 | 3877 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3874 | 3878 |
break; |
| 3875 | 3879 |
case 0x024: /* VIS I fcmple32 */ |
| 3876 | 3880 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3877 | 3881 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3878 | 3882 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3879 |
gen_helper_fcmple32(cpu_dst); |
|
| 3883 |
gen_helper_fcmple32(cpu_dst, cpu_env);
|
|
| 3880 | 3884 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3881 | 3885 |
break; |
| 3882 | 3886 |
case 0x026: /* VIS I fcmpne32 */ |
| 3883 | 3887 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3884 | 3888 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3885 | 3889 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3886 |
gen_helper_fcmpne32(cpu_dst); |
|
| 3890 |
gen_helper_fcmpne32(cpu_dst, cpu_env);
|
|
| 3887 | 3891 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3888 | 3892 |
break; |
| 3889 | 3893 |
case 0x028: /* VIS I fcmpgt16 */ |
| 3890 | 3894 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3891 | 3895 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3892 | 3896 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3893 |
gen_helper_fcmpgt16(cpu_dst); |
|
| 3897 |
gen_helper_fcmpgt16(cpu_dst, cpu_env);
|
|
| 3894 | 3898 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3895 | 3899 |
break; |
| 3896 | 3900 |
case 0x02a: /* VIS I fcmpeq16 */ |
| 3897 | 3901 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3898 | 3902 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3899 | 3903 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3900 |
gen_helper_fcmpeq16(cpu_dst); |
|
| 3904 |
gen_helper_fcmpeq16(cpu_dst, cpu_env);
|
|
| 3901 | 3905 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3902 | 3906 |
break; |
| 3903 | 3907 |
case 0x02c: /* VIS I fcmpgt32 */ |
| 3904 | 3908 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3905 | 3909 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3906 | 3910 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3907 |
gen_helper_fcmpgt32(cpu_dst); |
|
| 3911 |
gen_helper_fcmpgt32(cpu_dst, cpu_env);
|
|
| 3908 | 3912 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3909 | 3913 |
break; |
| 3910 | 3914 |
case 0x02e: /* VIS I fcmpeq32 */ |
| 3911 | 3915 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3912 | 3916 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3913 | 3917 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3914 |
gen_helper_fcmpeq32(cpu_dst); |
|
| 3918 |
gen_helper_fcmpeq32(cpu_dst, cpu_env);
|
|
| 3915 | 3919 |
gen_movl_TN_reg(rd, cpu_dst); |
| 3916 | 3920 |
break; |
| 3917 | 3921 |
case 0x031: /* VIS I fmul8x16 */ |
| 3918 | 3922 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3919 | 3923 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3920 | 3924 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3921 |
gen_helper_fmul8x16(); |
|
| 3925 |
gen_helper_fmul8x16(cpu_env);
|
|
| 3922 | 3926 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3923 | 3927 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3924 | 3928 |
break; |
| ... | ... | |
| 3926 | 3930 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3927 | 3931 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3928 | 3932 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3929 |
gen_helper_fmul8x16au(); |
|
| 3933 |
gen_helper_fmul8x16au(cpu_env);
|
|
| 3930 | 3934 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3931 | 3935 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3932 | 3936 |
break; |
| ... | ... | |
| 3934 | 3938 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3935 | 3939 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3936 | 3940 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3937 |
gen_helper_fmul8x16al(); |
|
| 3941 |
gen_helper_fmul8x16al(cpu_env);
|
|
| 3938 | 3942 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3939 | 3943 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3940 | 3944 |
break; |
| ... | ... | |
| 3942 | 3946 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3943 | 3947 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3944 | 3948 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3945 |
gen_helper_fmul8sux16(); |
|
| 3949 |
gen_helper_fmul8sux16(cpu_env);
|
|
| 3946 | 3950 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3947 | 3951 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3948 | 3952 |
break; |
| ... | ... | |
| 3950 | 3954 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3951 | 3955 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3952 | 3956 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3953 |
gen_helper_fmul8ulx16(); |
|
| 3957 |
gen_helper_fmul8ulx16(cpu_env);
|
|
| 3954 | 3958 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3955 | 3959 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3956 | 3960 |
break; |
| ... | ... | |
| 3958 | 3962 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3959 | 3963 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3960 | 3964 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3961 |
gen_helper_fmuld8sux16(); |
|
| 3965 |
gen_helper_fmuld8sux16(cpu_env);
|
|
| 3962 | 3966 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3963 | 3967 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3964 | 3968 |
break; |
| ... | ... | |
| 3966 | 3970 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3967 | 3971 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3968 | 3972 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3969 |
gen_helper_fmuld8ulx16(); |
|
| 3973 |
gen_helper_fmuld8ulx16(cpu_env);
|
|
| 3970 | 3974 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3971 | 3975 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3972 | 3976 |
break; |
| ... | ... | |
| 3980 | 3984 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3981 | 3985 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3982 | 3986 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3983 |
gen_helper_faligndata(); |
|
| 3987 |
gen_helper_faligndata(cpu_env);
|
|
| 3984 | 3988 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3985 | 3989 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3986 | 3990 |
break; |
| ... | ... | |
| 3988 | 3992 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3989 | 3993 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3990 | 3994 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3991 |
gen_helper_fpmerge(); |
|
| 3995 |
gen_helper_fpmerge(cpu_env);
|
|
| 3992 | 3996 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3993 | 3997 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 3994 | 3998 |
break; |
| ... | ... | |
| 3999 | 4003 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4000 | 4004 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 4001 | 4005 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 4002 |
gen_helper_fexpand(); |
|
| 4006 |
gen_helper_fexpand(cpu_env);
|
|
| 4003 | 4007 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4004 | 4008 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 4005 | 4009 |
break; |
| ... | ... | |
| 4007 | 4011 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4008 | 4012 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 4009 | 4013 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 4010 |
gen_helper_fpadd16(); |
|
| 4014 |
gen_helper_fpadd16(cpu_env);
|
|
| 4011 | 4015 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4012 | 4016 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 4013 | 4017 |
break; |
| 4014 | 4018 |
case 0x051: /* VIS I fpadd16s */ |
| 4015 | 4019 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4016 |
gen_helper_fpadd16s(cpu_fpr[rd], |
|
| 4020 |
gen_helper_fpadd16s(cpu_env, cpu_fpr[rd],
|
|
| 4017 | 4021 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4018 | 4022 |
gen_update_fprs_dirty(rd); |
| 4019 | 4023 |
break; |
| ... | ... | |
| 4021 | 4025 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4022 | 4026 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 4023 | 4027 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 4024 |
gen_helper_fpadd32(); |
|
| 4028 |
gen_helper_fpadd32(cpu_env);
|
|
| 4025 | 4029 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4026 | 4030 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 4027 | 4031 |
break; |
| 4028 | 4032 |
case 0x053: /* VIS I fpadd32s */ |
| 4029 | 4033 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4030 |
gen_helper_fpadd32s(cpu_fpr[rd], |
|
| 4034 |
gen_helper_fpadd32s(cpu_env, cpu_fpr[rd],
|
|
| 4031 | 4035 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4032 | 4036 |
gen_update_fprs_dirty(rd); |
| 4033 | 4037 |
break; |
| ... | ... | |
| 4035 | 4039 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4036 | 4040 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 4037 | 4041 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 4038 |
gen_helper_fpsub16(); |
|
| 4042 |
gen_helper_fpsub16(cpu_env);
|
|
| 4039 | 4043 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4040 | 4044 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 4041 | 4045 |
break; |
| 4042 | 4046 |
case 0x055: /* VIS I fpsub16s */ |
| 4043 | 4047 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4044 |
gen_helper_fpsub16s(cpu_fpr[rd], |
|
| 4048 |
gen_helper_fpsub16s(cpu_env, cpu_fpr[rd],
|
|
| 4045 | 4049 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4046 | 4050 |
gen_update_fprs_dirty(rd); |
| 4047 | 4051 |
break; |
| ... | ... | |
| 4049 | 4053 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4050 | 4054 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 4051 | 4055 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 4052 |
gen_helper_fpsub32(); |
|
| 4056 |
gen_helper_fpsub32(cpu_env);
|
|
| 4053 | 4057 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4054 | 4058 |
gen_update_fprs_dirty(DFPREG(rd)); |
| 4055 | 4059 |
break; |
| 4056 | 4060 |
case 0x057: /* VIS I fpsub32s */ |
| 4057 | 4061 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4058 |
gen_helper_fpsub32s(cpu_fpr[rd], |
|
| 4062 |
gen_helper_fpsub32s(cpu_env, cpu_fpr[rd],
|
|
| 4059 | 4063 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4060 | 4064 |
gen_update_fprs_dirty(rd); |
| 4061 | 4065 |
break; |
| ... | ... | |
| 4659 | 4663 |
gen_address_mask(dc, cpu_addr); |
| 4660 | 4664 |
if (rd == 1) {
|
| 4661 | 4665 |
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
| 4662 |
gen_helper_ldxfsr(cpu_tmp64); |
|
| 4666 |
gen_helper_ldxfsr(cpu_env, cpu_tmp64);
|
|
| 4663 | 4667 |
} else {
|
| 4664 | 4668 |
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
| 4665 | 4669 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
| 4666 |
gen_helper_ldfsr(cpu_tmp32); |
|
| 4670 |
gen_helper_ldfsr(cpu_env, cpu_tmp32);
|
|
| 4667 | 4671 |
} |
| 4668 | 4672 |
#else |
| 4669 | 4673 |
{
|
| 4670 | 4674 |
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
| 4671 |
gen_helper_ldfsr(cpu_tmp32); |
|
| 4675 |
gen_helper_ldfsr(cpu_env, cpu_tmp32);
|
|
| 4672 | 4676 |
} |
| 4673 | 4677 |
#endif |
| 4674 | 4678 |
break; |
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