Revision 2e4d7e3e
| b/target-arm/cpu-qom.h | ||
|---|---|---|
| 75 | 75 |
uint32_t mvfr1; |
| 76 | 76 |
uint32_t ctr; |
| 77 | 77 |
uint32_t reset_sctlr; |
| 78 |
uint32_t id_pfr0; |
|
| 79 |
uint32_t id_pfr1; |
|
| 80 |
uint32_t id_dfr0; |
|
| 81 |
uint32_t id_afr0; |
|
| 82 |
uint32_t id_mmfr0; |
|
| 83 |
uint32_t id_mmfr1; |
|
| 84 |
uint32_t id_mmfr2; |
|
| 85 |
uint32_t id_mmfr3; |
|
| 86 |
uint32_t id_isar0; |
|
| 87 |
uint32_t id_isar1; |
|
| 88 |
uint32_t id_isar2; |
|
| 89 |
uint32_t id_isar3; |
|
| 90 |
uint32_t id_isar4; |
|
| 91 |
uint32_t id_isar5; |
|
| 78 | 92 |
} ARMCPU; |
| 79 | 93 |
|
| 80 | 94 |
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) |
| b/target-arm/cpu.c | ||
|---|---|---|
| 130 | 130 |
static void arm1136_r2_initfn(Object *obj) |
| 131 | 131 |
{
|
| 132 | 132 |
ARMCPU *cpu = ARM_CPU(obj); |
| 133 |
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
|
| 134 |
* older core than plain "arm1136". In particular this does not |
|
| 135 |
* have the v6K features. |
|
| 136 |
* These ID register values are correct for 1136 but may be wrong |
|
| 137 |
* for 1136_r2 (in particular r0p2 does not actually implement most |
|
| 138 |
* of the ID registers). |
|
| 139 |
*/ |
|
| 133 | 140 |
set_feature(&cpu->env, ARM_FEATURE_V6); |
| 134 | 141 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 135 | 142 |
cpu->midr = ARM_CPUID_ARM1136_R2; |
| ... | ... | |
| 138 | 145 |
cpu->mvfr1 = 0x00000000; |
| 139 | 146 |
cpu->ctr = 0x1dd20d2; |
| 140 | 147 |
cpu->reset_sctlr = 0x00050078; |
| 148 |
cpu->id_pfr0 = 0x111; |
|
| 149 |
cpu->id_pfr1 = 0x1; |
|
| 150 |
cpu->id_dfr0 = 0x2; |
|
| 151 |
cpu->id_afr0 = 0x3; |
|
| 152 |
cpu->id_mmfr0 = 0x01130003; |
|
| 153 |
cpu->id_mmfr1 = 0x10030302; |
|
| 154 |
cpu->id_mmfr2 = 0x01222110; |
|
| 155 |
cpu->id_isar0 = 0x00140011; |
|
| 156 |
cpu->id_isar1 = 0x12002111; |
|
| 157 |
cpu->id_isar2 = 0x11231111; |
|
| 158 |
cpu->id_isar3 = 0x01102131; |
|
| 159 |
cpu->id_isar4 = 0x141; |
|
| 141 | 160 |
} |
| 142 | 161 |
|
| 143 | 162 |
static void arm1136_initfn(Object *obj) |
| ... | ... | |
| 152 | 171 |
cpu->mvfr1 = 0x00000000; |
| 153 | 172 |
cpu->ctr = 0x1dd20d2; |
| 154 | 173 |
cpu->reset_sctlr = 0x00050078; |
| 174 |
cpu->id_pfr0 = 0x111; |
|
| 175 |
cpu->id_pfr1 = 0x1; |
|
| 176 |
cpu->id_dfr0 = 0x2; |
|
| 177 |
cpu->id_afr0 = 0x3; |
|
| 178 |
cpu->id_mmfr0 = 0x01130003; |
|
| 179 |
cpu->id_mmfr1 = 0x10030302; |
|
| 180 |
cpu->id_mmfr2 = 0x01222110; |
|
| 181 |
cpu->id_isar0 = 0x00140011; |
|
| 182 |
cpu->id_isar1 = 0x12002111; |
|
| 183 |
cpu->id_isar2 = 0x11231111; |
|
| 184 |
cpu->id_isar3 = 0x01102131; |
|
| 185 |
cpu->id_isar4 = 0x141; |
|
| 155 | 186 |
} |
| 156 | 187 |
|
| 157 | 188 |
static void arm1176_initfn(Object *obj) |
| ... | ... | |
| 166 | 197 |
cpu->mvfr1 = 0x00000000; |
| 167 | 198 |
cpu->ctr = 0x1dd20d2; |
| 168 | 199 |
cpu->reset_sctlr = 0x00050078; |
| 200 |
cpu->id_pfr0 = 0x111; |
|
| 201 |
cpu->id_pfr1 = 0x11; |
|
| 202 |
cpu->id_dfr0 = 0x33; |
|
| 203 |
cpu->id_afr0 = 0; |
|
| 204 |
cpu->id_mmfr0 = 0x01130003; |
|
| 205 |
cpu->id_mmfr1 = 0x10030302; |
|
| 206 |
cpu->id_mmfr2 = 0x01222100; |
|
| 207 |
cpu->id_isar0 = 0x0140011; |
|
| 208 |
cpu->id_isar1 = 0x12002111; |
|
| 209 |
cpu->id_isar2 = 0x11231121; |
|
| 210 |
cpu->id_isar3 = 0x01102131; |
|
| 211 |
cpu->id_isar4 = 0x01141; |
|
| 169 | 212 |
} |
| 170 | 213 |
|
| 171 | 214 |
static void arm11mpcore_initfn(Object *obj) |
| ... | ... | |
| 179 | 222 |
cpu->mvfr0 = 0x11111111; |
| 180 | 223 |
cpu->mvfr1 = 0x00000000; |
| 181 | 224 |
cpu->ctr = 0x1dd20d2; |
| 225 |
cpu->id_pfr0 = 0x111; |
|
| 226 |
cpu->id_pfr1 = 0x1; |
|
| 227 |
cpu->id_dfr0 = 0; |
|
| 228 |
cpu->id_afr0 = 0x2; |
|
| 229 |
cpu->id_mmfr0 = 0x01100103; |
|
| 230 |
cpu->id_mmfr1 = 0x10020302; |
|
| 231 |
cpu->id_mmfr2 = 0x01222000; |
|
| 232 |
cpu->id_isar0 = 0x00100011; |
|
| 233 |
cpu->id_isar1 = 0x12002111; |
|
| 234 |
cpu->id_isar2 = 0x11221011; |
|
| 235 |
cpu->id_isar3 = 0x01102131; |
|
| 236 |
cpu->id_isar4 = 0x141; |
|
| 182 | 237 |
} |
| 183 | 238 |
|
| 184 | 239 |
static void cortex_m3_initfn(Object *obj) |
| ... | ... | |
| 202 | 257 |
cpu->mvfr1 = 0x00011100; |
| 203 | 258 |
cpu->ctr = 0x82048004; |
| 204 | 259 |
cpu->reset_sctlr = 0x00c50078; |
| 260 |
cpu->id_pfr0 = 0x1031; |
|
| 261 |
cpu->id_pfr1 = 0x11; |
|
| 262 |
cpu->id_dfr0 = 0x400; |
|
| 263 |
cpu->id_afr0 = 0; |
|
| 264 |
cpu->id_mmfr0 = 0x31100003; |
|
| 265 |
cpu->id_mmfr1 = 0x20000000; |
|
| 266 |
cpu->id_mmfr2 = 0x01202000; |
|
| 267 |
cpu->id_mmfr3 = 0x11; |
|
| 268 |
cpu->id_isar0 = 0x00101111; |
|
| 269 |
cpu->id_isar1 = 0x12112111; |
|
| 270 |
cpu->id_isar2 = 0x21232031; |
|
| 271 |
cpu->id_isar3 = 0x11112131; |
|
| 272 |
cpu->id_isar4 = 0x00111142; |
|
| 205 | 273 |
} |
| 206 | 274 |
|
| 207 | 275 |
static void cortex_a9_initfn(Object *obj) |
| ... | ... | |
| 223 | 291 |
cpu->mvfr1 = 0x01111111; |
| 224 | 292 |
cpu->ctr = 0x80038003; |
| 225 | 293 |
cpu->reset_sctlr = 0x00c50078; |
| 294 |
cpu->id_pfr0 = 0x1031; |
|
| 295 |
cpu->id_pfr1 = 0x11; |
|
| 296 |
cpu->id_dfr0 = 0x000; |
|
| 297 |
cpu->id_afr0 = 0; |
|
| 298 |
cpu->id_mmfr0 = 0x00100103; |
|
| 299 |
cpu->id_mmfr1 = 0x20000000; |
|
| 300 |
cpu->id_mmfr2 = 0x01230000; |
|
| 301 |
cpu->id_mmfr3 = 0x00002111; |
|
| 302 |
cpu->id_isar0 = 0x00101111; |
|
| 303 |
cpu->id_isar1 = 0x13112111; |
|
| 304 |
cpu->id_isar2 = 0x21232041; |
|
| 305 |
cpu->id_isar3 = 0x11112131; |
|
| 306 |
cpu->id_isar4 = 0x00111142; |
|
| 226 | 307 |
} |
| 227 | 308 |
|
| 228 | 309 |
static void cortex_a15_initfn(Object *obj) |
| ... | ... | |
| 242 | 323 |
cpu->mvfr1 = 0x11111111; |
| 243 | 324 |
cpu->ctr = 0x8444c004; |
| 244 | 325 |
cpu->reset_sctlr = 0x00c50078; |
| 326 |
cpu->id_pfr0 = 0x00001131; |
|
| 327 |
cpu->id_pfr1 = 0x00011011; |
|
| 328 |
cpu->id_dfr0 = 0x02010555; |
|
| 329 |
cpu->id_afr0 = 0x00000000; |
|
| 330 |
cpu->id_mmfr0 = 0x10201105; |
|
| 331 |
cpu->id_mmfr1 = 0x20000000; |
|
| 332 |
cpu->id_mmfr2 = 0x01240000; |
|
| 333 |
cpu->id_mmfr3 = 0x02102211; |
|
| 334 |
cpu->id_isar0 = 0x02101110; |
|
| 335 |
cpu->id_isar1 = 0x13112111; |
|
| 336 |
cpu->id_isar2 = 0x21232041; |
|
| 337 |
cpu->id_isar3 = 0x11112131; |
|
| 338 |
cpu->id_isar4 = 0x10011142; |
|
| 245 | 339 |
} |
| 246 | 340 |
|
| 247 | 341 |
static void ti925t_initfn(Object *obj) |
| b/target-arm/helper.c | ||
|---|---|---|
| 7 | 7 |
#endif |
| 8 | 8 |
#include "sysemu.h" |
| 9 | 9 |
|
| 10 |
static uint32_t cortexa15_cp15_c0_c1[8] = {
|
|
| 11 |
0x00001131, 0x00011011, 0x02010555, 0x00000000, |
|
| 12 |
0x10201105, 0x20000000, 0x01240000, 0x02102211 |
|
| 13 |
}; |
|
| 14 |
|
|
| 15 |
static uint32_t cortexa15_cp15_c0_c2[8] = {
|
|
| 16 |
0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0 |
|
| 17 |
}; |
|
| 18 |
|
|
| 19 |
static uint32_t cortexa9_cp15_c0_c1[8] = |
|
| 20 |
{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
|
|
| 21 |
|
|
| 22 |
static uint32_t cortexa9_cp15_c0_c2[8] = |
|
| 23 |
{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
|
|
| 24 |
|
|
| 25 |
static uint32_t cortexa8_cp15_c0_c1[8] = |
|
| 26 |
{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
|
|
| 27 |
|
|
| 28 |
static uint32_t cortexa8_cp15_c0_c2[8] = |
|
| 29 |
{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
|
|
| 30 |
|
|
| 31 |
static uint32_t mpcore_cp15_c0_c1[8] = |
|
| 32 |
{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
|
|
| 33 |
|
|
| 34 |
static uint32_t mpcore_cp15_c0_c2[8] = |
|
| 35 |
{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
|
|
| 36 |
|
|
| 37 |
static uint32_t arm1136_cp15_c0_c1[8] = |
|
| 38 |
{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
|
|
| 39 |
|
|
| 40 |
static uint32_t arm1136_cp15_c0_c2[8] = |
|
| 41 |
{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
|
|
| 42 |
|
|
| 43 |
static uint32_t arm1176_cp15_c0_c1[8] = |
|
| 44 |
{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
|
|
| 45 |
|
|
| 46 |
static uint32_t arm1176_cp15_c0_c2[8] = |
|
| 47 |
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
|
|
| 48 |
|
|
| 49 | 10 |
static void cpu_reset_model_id(CPUARMState *env, uint32_t id) |
| 50 | 11 |
{
|
| 51 | 12 |
switch (id) {
|
| ... | ... | |
| 58 | 19 |
case ARM_CPUID_ARM1136: |
| 59 | 20 |
/* This is the 1136 r1, which is a v6K core */ |
| 60 | 21 |
case ARM_CPUID_ARM1136_R2: |
| 61 |
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
|
| 62 |
* older core than plain "arm1136". In particular this does not |
|
| 63 |
* have the v6K features. |
|
| 64 |
*/ |
|
| 65 |
/* These ID register values are correct for 1136 but may be wrong |
|
| 66 |
* for 1136_r2 (in particular r0p2 does not actually implement most |
|
| 67 |
* of the ID registers). |
|
| 68 |
*/ |
|
| 69 |
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); |
|
| 70 |
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); |
|
| 71 | 22 |
break; |
| 72 | 23 |
case ARM_CPUID_ARM1176: |
| 73 |
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); |
|
| 74 |
memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); |
|
| 75 | 24 |
break; |
| 76 | 25 |
case ARM_CPUID_ARM11MPCORE: |
| 77 |
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); |
|
| 78 |
memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); |
|
| 79 | 26 |
break; |
| 80 | 27 |
case ARM_CPUID_CORTEXA8: |
| 81 |
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); |
|
| 82 |
memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); |
|
| 83 | 28 |
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; |
| 84 | 29 |
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ |
| 85 | 30 |
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ |
| 86 | 31 |
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ |
| 87 | 32 |
break; |
| 88 | 33 |
case ARM_CPUID_CORTEXA9: |
| 89 |
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); |
|
| 90 |
memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); |
|
| 91 | 34 |
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; |
| 92 | 35 |
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ |
| 93 | 36 |
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ |
| 94 | 37 |
break; |
| 95 | 38 |
case ARM_CPUID_CORTEXA15: |
| 96 |
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); |
|
| 97 |
memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t)); |
|
| 98 | 39 |
env->cp15.c0_clid = 0x0a200023; |
| 99 | 40 |
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ |
| 100 | 41 |
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ |
| ... | ... | |
| 159 | 100 |
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
| 160 | 101 |
env->cp15.c0_cachetype = cpu->ctr; |
| 161 | 102 |
env->cp15.c1_sys = cpu->reset_sctlr; |
| 103 |
env->cp15.c0_c1[0] = cpu->id_pfr0; |
|
| 104 |
env->cp15.c0_c1[1] = cpu->id_pfr1; |
|
| 105 |
env->cp15.c0_c1[2] = cpu->id_dfr0; |
|
| 106 |
env->cp15.c0_c1[3] = cpu->id_afr0; |
|
| 107 |
env->cp15.c0_c1[4] = cpu->id_mmfr0; |
|
| 108 |
env->cp15.c0_c1[5] = cpu->id_mmfr1; |
|
| 109 |
env->cp15.c0_c1[6] = cpu->id_mmfr2; |
|
| 110 |
env->cp15.c0_c1[7] = cpu->id_mmfr3; |
|
| 111 |
env->cp15.c0_c2[0] = cpu->id_isar0; |
|
| 112 |
env->cp15.c0_c2[1] = cpu->id_isar1; |
|
| 113 |
env->cp15.c0_c2[2] = cpu->id_isar2; |
|
| 114 |
env->cp15.c0_c2[3] = cpu->id_isar3; |
|
| 115 |
env->cp15.c0_c2[4] = cpu->id_isar4; |
|
| 116 |
env->cp15.c0_c2[5] = cpu->id_isar5; |
|
| 162 | 117 |
|
| 163 | 118 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
| 164 | 119 |
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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