root / exec-all.h @ 2e70f6ef
History | View | Annotate | Download (14.2 kB)
1 | d4e8164f | bellard | /*
|
---|---|---|---|
2 | d4e8164f | bellard | * internal execution defines for qemu
|
3 | 5fafdf24 | ths | *
|
4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | d4e8164f | bellard | *
|
6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
|
7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
|
9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | d4e8164f | bellard | *
|
11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
|
12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | d4e8164f | bellard | * Lesser General Public License for more details.
|
15 | d4e8164f | bellard | *
|
16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
|
18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | d4e8164f | bellard | */
|
20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
|
22 | cb7cca1a | aurel32 | #define DEBUG_DISAS
|
23 | b346ff46 | bellard | |
24 | b346ff46 | bellard | /* is_jmp field values */
|
25 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
26 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
27 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
28 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
29 | b346ff46 | bellard | |
30 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
31 | b346ff46 | bellard | |
32 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
|
33 | e83a8673 | edgar_igl | #define MAX_OP_PER_INSTR 64 |
34 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
|
35 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
36 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
37 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
|
38 | b346ff46 | bellard | |
39 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
|
40 | a208e54a | pbrook | single op may require several host instructions and regirster reloads.
|
41 | a208e54a | pbrook | For now take a wild guess at 128 bytes, which should allow at least
|
42 | a208e54a | pbrook | a couple of fixup instructions per argument. */
|
43 | a208e54a | pbrook | #define TCG_MAX_OP_SIZE 128 |
44 | a208e54a | pbrook | |
45 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
|
46 | b346ff46 | bellard | |
47 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
|
48 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
|
49 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
|
50 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
|
51 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
|
52 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
53 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
|
54 | b346ff46 | bellard | |
55 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
56 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
57 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
58 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
59 | 3b46e624 | ths | |
60 | b346ff46 | bellard | extern FILE *logfile;
|
61 | b346ff46 | bellard | extern int loglevel; |
62 | b346ff46 | bellard | |
63 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
64 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
65 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
66 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc); |
67 | d2856f1a | aurel32 | |
68 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
69 | 57fec1fe | bellard | void cpu_gen_init(void); |
70 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
71 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
|
72 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
73 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
74 | 58fe2f10 | bellard | void *puc);
|
75 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
76 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
77 | 58fe2f10 | bellard | void *puc);
|
78 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
79 | 2e70f6ef | pbrook | void cpu_io_recompile(CPUState *env, void *retaddr); |
80 | 2e70f6ef | pbrook | TranslationBlock *tb_gen_code(CPUState *env, |
81 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
|
82 | 2e70f6ef | pbrook | int cflags);
|
83 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
|
84 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
85 | 00f82b8a | aurel32 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
|
86 | 2e12669a | bellard | int is_cpu_write_access);
|
87 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
|
88 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
|
89 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
90 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
|
91 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
92 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
93 | 4d7a0880 | blueswir1 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
94 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
95 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
96 | 84b7b8e7 | bellard | { |
97 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
|
98 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
99 | 4d7a0880 | blueswir1 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
|
100 | 84b7b8e7 | bellard | } |
101 | d4e8164f | bellard | |
102 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
103 | d4e8164f | bellard | |
104 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
105 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
106 | 4390df51 | bellard | |
107 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
108 | d4e8164f | bellard | |
109 | 4390df51 | bellard | /* estimated block size for TB allocation */
|
110 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
|
111 | 4390df51 | bellard | according to the host CPU */
|
112 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
|
113 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
114 | 4390df51 | bellard | #else
|
115 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
116 | 4390df51 | bellard | #endif
|
117 | 4390df51 | bellard | |
118 | 811d4cf4 | balrog | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
|
119 | 4390df51 | bellard | #define USE_DIRECT_JUMP
|
120 | 4390df51 | bellard | #endif
|
121 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
|
122 | d4e8164f | bellard | #define USE_DIRECT_JUMP
|
123 | d4e8164f | bellard | #endif
|
124 | d4e8164f | bellard | |
125 | 2e70f6ef | pbrook | struct TranslationBlock {
|
126 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
|
127 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
|
128 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
|
129 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
|
130 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
|
131 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
|
132 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
133 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
134 | 58fe2f10 | bellard | |
135 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
|
136 | 4390df51 | bellard | /* next matching tb for physical address. */
|
137 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
|
138 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
|
139 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
|
140 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
141 | 5fafdf24 | ths | target_ulong page_addr[2];
|
142 | 4390df51 | bellard | |
143 | d4e8164f | bellard | /* the following data are used to directly call another TB from
|
144 | d4e8164f | bellard | the code of this one. */
|
145 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
146 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
|
147 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
148 | d4e8164f | bellard | #else
|
149 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
150 | d4e8164f | bellard | #endif
|
151 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
|
152 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
|
153 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
|
154 | d4e8164f | bellard | jmp_first */
|
155 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
156 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
|
157 | 2e70f6ef | pbrook | uint32_t icount; |
158 | 2e70f6ef | pbrook | }; |
159 | d4e8164f | bellard | |
160 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
161 | b362e5e0 | pbrook | { |
162 | b362e5e0 | pbrook | target_ulong tmp; |
163 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
164 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
|
165 | b362e5e0 | pbrook | } |
166 | b362e5e0 | pbrook | |
167 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
168 | d4e8164f | bellard | { |
169 | b362e5e0 | pbrook | target_ulong tmp; |
170 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
171 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
|
172 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
173 | d4e8164f | bellard | } |
174 | d4e8164f | bellard | |
175 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
176 | 4390df51 | bellard | { |
177 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
178 | 4390df51 | bellard | } |
179 | 4390df51 | bellard | |
180 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
181 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
|
182 | 0124311e | bellard | void tb_flush(CPUState *env);
|
183 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
|
184 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
185 | 2e70f6ef | pbrook | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
|
186 | d4e8164f | bellard | |
187 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
|
188 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
|
189 | 26a5f13b | bellard | extern int code_gen_max_blocks; |
190 | d4e8164f | bellard | |
191 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
|
192 | 4390df51 | bellard | |
193 | 4390df51 | bellard | #if defined(__powerpc__)
|
194 | 0a878c47 | malc | static inline void flush_icache_range(unsigned long start, unsigned long stop); |
195 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
196 | d4e8164f | bellard | { |
197 | 0a878c47 | malc | /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */
|
198 | 0a878c47 | malc | uint32_t *ptr; |
199 | 932a6909 | bellard | long disp = addr - jmp_addr;
|
200 | 0a878c47 | malc | unsigned long patch_size; |
201 | d4e8164f | bellard | |
202 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
203 | 932a6909 | bellard | |
204 | 932a6909 | bellard | if ((disp << 6) >> 6 != disp) { |
205 | 0a878c47 | malc | ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */ |
206 | 0a878c47 | malc | ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */ |
207 | 0a878c47 | malc | ptr[2] = 0x7c0903a6; /* mtctr 0 */ |
208 | 0a878c47 | malc | ptr[3] = 0x4e800420; /* brctr */ |
209 | 0a878c47 | malc | patch_size = 16;
|
210 | 932a6909 | bellard | } else {
|
211 | 932a6909 | bellard | /* patch the branch destination */
|
212 | 0a878c47 | malc | if (disp != 16) { |
213 | 0a878c47 | malc | *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */ |
214 | 0a878c47 | malc | patch_size = 4;
|
215 | 0a878c47 | malc | } else {
|
216 | 0a878c47 | malc | ptr[0] = 0x60000000; /* nop */ |
217 | 0a878c47 | malc | ptr[1] = 0x60000000; |
218 | 0a878c47 | malc | ptr[2] = 0x60000000; |
219 | 0a878c47 | malc | ptr[3] = 0x60000000; |
220 | 0a878c47 | malc | patch_size = 16;
|
221 | 0a878c47 | malc | } |
222 | 932a6909 | bellard | } |
223 | d4e8164f | bellard | /* flush icache */
|
224 | 0a878c47 | malc | flush_icache_range(jmp_addr, jmp_addr + patch_size); |
225 | d4e8164f | bellard | } |
226 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
|
227 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
228 | 4390df51 | bellard | { |
229 | 4390df51 | bellard | /* patch the branch destination */
|
230 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
|
231 | 1235fc06 | ths | /* no need to flush icache explicitly */
|
232 | 4390df51 | bellard | } |
233 | 811d4cf4 | balrog | #elif defined(__arm__)
|
234 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
235 | 811d4cf4 | balrog | { |
236 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
237 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
238 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
239 | 811d4cf4 | balrog | |
240 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
|
241 | 811d4cf4 | balrog | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; |
242 | 811d4cf4 | balrog | |
243 | 811d4cf4 | balrog | /* flush icache */
|
244 | 811d4cf4 | balrog | _beg = jmp_addr; |
245 | 811d4cf4 | balrog | _end = jmp_addr + 4;
|
246 | 811d4cf4 | balrog | _flg = 0;
|
247 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
248 | 811d4cf4 | balrog | } |
249 | 4390df51 | bellard | #endif
|
250 | d4e8164f | bellard | |
251 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
252 | 4cbb86e1 | bellard | int n, unsigned long addr) |
253 | 4cbb86e1 | bellard | { |
254 | 4cbb86e1 | bellard | unsigned long offset; |
255 | 4cbb86e1 | bellard | |
256 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
257 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
258 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
|
259 | 4cbb86e1 | bellard | if (offset != 0xffff) |
260 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
261 | 4cbb86e1 | bellard | } |
262 | 4cbb86e1 | bellard | |
263 | d4e8164f | bellard | #else
|
264 | d4e8164f | bellard | |
265 | d4e8164f | bellard | /* set the jump target */
|
266 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
267 | d4e8164f | bellard | int n, unsigned long addr) |
268 | d4e8164f | bellard | { |
269 | 95f7652d | bellard | tb->tb_next[n] = addr; |
270 | d4e8164f | bellard | } |
271 | d4e8164f | bellard | |
272 | d4e8164f | bellard | #endif
|
273 | d4e8164f | bellard | |
274 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
275 | d4e8164f | bellard | TranslationBlock *tb_next) |
276 | d4e8164f | bellard | { |
277 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
|
278 | cf25629d | bellard | if (!tb->jmp_next[n]) {
|
279 | cf25629d | bellard | /* patch the native jump address */
|
280 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
281 | 3b46e624 | ths | |
282 | cf25629d | bellard | /* add in TB jmp circular list */
|
283 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
284 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
|
285 | cf25629d | bellard | } |
286 | d4e8164f | bellard | } |
287 | d4e8164f | bellard | |
288 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
289 | a513fe19 | bellard | |
290 | d4e8164f | bellard | #ifndef offsetof
|
291 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
292 | d4e8164f | bellard | #endif
|
293 | d4e8164f | bellard | |
294 | d549f7d9 | bellard | #if defined(_WIN32)
|
295 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
296 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
297 | d549f7d9 | bellard | #elif defined(__APPLE__)
|
298 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
299 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
300 | d549f7d9 | bellard | #else
|
301 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
302 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
303 | d549f7d9 | bellard | #endif
|
304 | d549f7d9 | bellard | |
305 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
|
306 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
307 | 75913b72 | bellard | |
308 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
309 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
310 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
311 | 33417e70 | bellard | |
312 | d5975363 | pbrook | #include "qemu-lock.h" |
313 | d4e8164f | bellard | |
314 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
315 | d4e8164f | bellard | |
316 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
317 | 6e59c1db | bellard | |
318 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
319 | 6e59c1db | bellard | |
320 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
321 | 6e59c1db | bellard | void *retaddr);
|
322 | 6e59c1db | bellard | |
323 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
324 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
325 | 6e59c1db | bellard | #define env cpu_single_env
|
326 | 6e59c1db | bellard | |
327 | 6e59c1db | bellard | #define DATA_SIZE 1 |
328 | 6e59c1db | bellard | #include "softmmu_header.h" |
329 | 6e59c1db | bellard | |
330 | 6e59c1db | bellard | #define DATA_SIZE 2 |
331 | 6e59c1db | bellard | #include "softmmu_header.h" |
332 | 6e59c1db | bellard | |
333 | 6e59c1db | bellard | #define DATA_SIZE 4 |
334 | 6e59c1db | bellard | #include "softmmu_header.h" |
335 | 6e59c1db | bellard | |
336 | c27004ec | bellard | #define DATA_SIZE 8 |
337 | c27004ec | bellard | #include "softmmu_header.h" |
338 | c27004ec | bellard | |
339 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
340 | 6e59c1db | bellard | #undef MEMSUFFIX
|
341 | 6e59c1db | bellard | #undef env
|
342 | 6e59c1db | bellard | |
343 | 6e59c1db | bellard | #endif
|
344 | 4390df51 | bellard | |
345 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
346 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
347 | 4390df51 | bellard | { |
348 | 4390df51 | bellard | return addr;
|
349 | 4390df51 | bellard | } |
350 | 4390df51 | bellard | #else
|
351 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
352 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
353 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
354 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
355 | 4390df51 | bellard | { |
356 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
|
357 | 4390df51 | bellard | |
358 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
359 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
360 | 4d7a0880 | blueswir1 | if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
|
361 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
362 | c27004ec | bellard | ldub_code(addr); |
363 | c27004ec | bellard | } |
364 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
365 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
366 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
367 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
368 | 6c36d3fa | blueswir1 | #else
|
369 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
370 | 6c36d3fa | blueswir1 | #endif
|
371 | 4390df51 | bellard | } |
372 | 4d7a0880 | blueswir1 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
373 | 4390df51 | bellard | } |
374 | 2e70f6ef | pbrook | |
375 | 2e70f6ef | pbrook | /* Deterministic execution requires that IO only be performaed on the last
|
376 | 2e70f6ef | pbrook | instruction of a TB so that interrupts take effect immediately. */
|
377 | 2e70f6ef | pbrook | static inline int can_do_io(CPUState *env) |
378 | 2e70f6ef | pbrook | { |
379 | 2e70f6ef | pbrook | if (!use_icount)
|
380 | 2e70f6ef | pbrook | return 1; |
381 | 2e70f6ef | pbrook | |
382 | 2e70f6ef | pbrook | /* If not executing code then assume we are ok. */
|
383 | 2e70f6ef | pbrook | if (!env->current_tb)
|
384 | 2e70f6ef | pbrook | return 1; |
385 | 2e70f6ef | pbrook | |
386 | 2e70f6ef | pbrook | return env->can_do_io != 0; |
387 | 2e70f6ef | pbrook | } |
388 | 4390df51 | bellard | #endif
|
389 | 9df217a3 | bellard | |
390 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
391 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
392 | f32fc648 | bellard | |
393 | da260249 | bellard | #define MSR_QPI_COMMBASE 0xfabe0010 |
394 | da260249 | bellard | |
395 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
396 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
397 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
398 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
399 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
400 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
401 | da260249 | bellard | void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
|
402 | da260249 | bellard | ram_addr_t phys_offset); |
403 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
404 | f32fc648 | bellard | void kqemu_record_dump(void); |
405 | 9df217a3 | bellard | |
406 | da260249 | bellard | extern uint32_t kqemu_comm_base;
|
407 | da260249 | bellard | |
408 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
409 | 9df217a3 | bellard | { |
410 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
411 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
412 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
413 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
414 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
415 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
416 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
417 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
418 | 9df217a3 | bellard | } |
419 | 9df217a3 | bellard | |
420 | 9df217a3 | bellard | #endif |