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/*
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* i386 CPUID helper functions
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "kvm.h" |
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#include "qemu-option.h" |
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#include "qemu-config.h" |
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#include "qapi/qapi-visit-core.h" |
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#include "arch_init.h" |
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#include "hyperv.h" |
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#include "hw/hw.h" |
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#if defined(CONFIG_KVM)
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#include <linux/kvm_para.h> |
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#endif
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/* feature flags taken from "Intel Processor Identification and the CPUID
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* Instruction" and AMD's "CPUID Specification". In cases of disagreement
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* between feature naming conventions, aliases may be added.
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*/
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static const char *feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8", "apic", NULL, "sep", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, |
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NULL, "ds" /* Intel dts */, "acpi", "mmx", |
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"fxsr", "sse", "sse2", "ss", |
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"ht" /* Intel htt */, "tm", "ia64", "pbe", |
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}; |
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static const char *ext_feature_name[] = { |
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"pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor", |
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"ds_cpl", "vmx", "smx", "est", |
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"tm2", "ssse3", "cid", NULL, |
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"fma", "cx16", "xtpr", "pdcm", |
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NULL, "pcid", "dca", "sse4.1|sse4_1", |
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"sse4.2|sse4_2", "x2apic", "movbe", "popcnt", |
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"tsc-deadline", "aes", "xsave", "osxsave", |
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"avx", NULL, NULL, "hypervisor", |
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}; |
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static const char *ext2_feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", NULL, NULL /* Linux mp */, |
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"nx|xd", NULL, "mmxext", "mmx", |
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"fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp", |
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NULL, "lm|i64", "3dnowext", "3dnow", |
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}; |
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static const char *ext3_feature_name[] = { |
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"lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, |
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"cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", |
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"3dnowprefetch", "osvw", "ibs", "xop", |
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"skinit", "wdt", NULL, NULL, |
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"fma4", NULL, "cvt16", "nodeid_msr", |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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static const char *kvm_feature_name[] = { |
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"kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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}; |
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static const char *svm_feature_name[] = { |
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"npt", "lbrv", "svm_lock", "nrip_save", |
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"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", |
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NULL, NULL, "pause_filter", NULL, |
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"pfthreshold", NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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/* collects per-function cpuid data
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*/
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typedef struct model_features_t { |
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uint32_t *guest_feat; |
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uint32_t *host_feat; |
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uint32_t check_feat; |
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const char **flag_names; |
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uint32_t cpuid; |
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} model_features_t; |
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int check_cpuid = 0; |
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int enforce_cpuid = 0; |
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void host_cpuid(uint32_t function, uint32_t count,
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uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) |
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{ |
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#if defined(CONFIG_KVM)
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uint32_t vec[4];
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#ifdef __x86_64__
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asm volatile("cpuid" |
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: "=a"(vec[0]), "=b"(vec[1]), |
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"=c"(vec[2]), "=d"(vec[3]) |
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: "0"(function), "c"(count) : "cc"); |
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#else
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asm volatile("pusha \n\t" |
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"cpuid \n\t"
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"mov %%eax, 0(%2) \n\t"
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"mov %%ebx, 4(%2) \n\t"
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"mov %%ecx, 8(%2) \n\t"
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"mov %%edx, 12(%2) \n\t"
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"popa"
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: : "a"(function), "c"(count), "S"(vec) |
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: "memory", "cc"); |
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#endif
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if (eax)
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*eax = vec[0];
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if (ebx)
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*ebx = vec[1];
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if (ecx)
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*ecx = vec[2];
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if (edx)
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*edx = vec[3];
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#endif
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} |
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#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) |
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/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
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* a substring. ex if !NULL points to the first char after a substring,
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* otherwise the string is assumed to sized by a terminating nul.
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* Return lexical ordering of *s1:*s2.
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*/
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static int sstrcmp(const char *s1, const char *e1, const char *s2, |
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const char *e2) |
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{ |
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for (;;) {
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if (!*s1 || !*s2 || *s1 != *s2)
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return (*s1 - *s2);
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++s1, ++s2; |
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if (s1 == e1 && s2 == e2)
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return (0); |
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else if (s1 == e1) |
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return (*s2);
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else if (s2 == e2) |
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return (*s1);
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} |
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} |
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/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
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* '|' delimited (possibly empty) strings in which case search for a match
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* within the alternatives proceeds left to right. Return 0 for success,
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* non-zero otherwise.
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*/
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static int altcmp(const char *s, const char *e, const char *altstr) |
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{ |
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const char *p, *q; |
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for (q = p = altstr; ; ) {
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while (*p && *p != '|') |
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++p; |
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if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
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return (0); |
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if (!*p)
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return (1); |
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else
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q = ++p; |
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} |
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} |
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/* search featureset for flag *[s..e), if found set corresponding bit in
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* *pval and return true, otherwise return false
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*/
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static bool lookup_feature(uint32_t *pval, const char *s, const char *e, |
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const char **featureset) |
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{ |
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uint32_t mask; |
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const char **ppc; |
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bool found = false; |
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for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) { |
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if (*ppc && !altcmp(s, e, *ppc)) {
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*pval |= mask; |
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found = true;
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} |
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} |
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return found;
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} |
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static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, |
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uint32_t *ext_features, |
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uint32_t *ext2_features, |
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uint32_t *ext3_features, |
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uint32_t *kvm_features, |
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uint32_t *svm_features) |
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{ |
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if (!lookup_feature(features, flagname, NULL, feature_name) && |
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!lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
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!lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
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!lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
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!lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
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!lookup_feature(svm_features, flagname, NULL, svm_feature_name))
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fprintf(stderr, "CPU feature %s not found\n", flagname);
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} |
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typedef struct x86_def_t { |
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struct x86_def_t *next;
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const char *name; |
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uint32_t level; |
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uint32_t vendor1, vendor2, vendor3; |
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int family;
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int model;
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int stepping;
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int tsc_khz;
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uint32_t features, ext_features, ext2_features, ext3_features; |
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uint32_t kvm_features, svm_features; |
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uint32_t xlevel; |
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char model_id[48]; |
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int vendor_override;
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uint32_t flags; |
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/* Store the results of Centaur's CPUID instructions */
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uint32_t ext4_features; |
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uint32_t xlevel2; |
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/* The feature bits on CPUID[EAX=7,ECX=0].EBX */
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uint32_t cpuid_7_0_ebx_features; |
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} x86_def_t; |
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) |
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#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_FXSR) |
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#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
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#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ |
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CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ |
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CPUID_PAE | CPUID_SEP | CPUID_APIC) |
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#define EXT2_FEATURE_MASK 0x0183F3FF |
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#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
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CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ |
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ |
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CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) |
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/* partly implemented:
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CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
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CPUID_PSE36 (needed for Solaris) */
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/* missing:
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CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
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#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
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CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ |
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CPUID_EXT_HYPERVISOR) |
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/* missing:
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CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
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CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
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#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
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CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ |
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) |
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/* missing:
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CPUID_EXT2_PDPE1GB */
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) |
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#define TCG_SVM_FEATURES 0 |
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/* maintains list of cpu model definitions
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*/
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static x86_def_t *x86_defs = {NULL}; |
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/* built-in cpu model definitions (deprecated)
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*/
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static x86_def_t builtin_x86_defs[] = {
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{ |
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.name = "qemu64",
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.level = 4,
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 6,
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.model = 2,
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.stepping = 3,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.xlevel = 0x8000000A,
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}, |
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{ |
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.name = "phenom",
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.level = 5,
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 16,
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.model = 2,
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.stepping = 3,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36 | CPUID_VME | CPUID_HT, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | |
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CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | |
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | |
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CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, |
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/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
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CPUID_EXT3_CR8LEG,
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CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV, |
340 |
.xlevel = 0x8000001A,
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.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
|
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}, |
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{ |
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.name = "core2duo",
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.level = 10,
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.family = 6,
|
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.model = 15,
|
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.stepping = 11,
|
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.features = PPRO_FEATURES | |
350 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | |
352 |
CPUID_HT | CPUID_TM | CPUID_PBE, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
354 |
CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST | |
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CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, |
356 |
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
357 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
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.xlevel = 0x80000008,
|
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.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
|
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}, |
361 |
{ |
362 |
.name = "kvm64",
|
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.level = 5,
|
364 |
.vendor1 = CPUID_VENDOR_INTEL_1, |
365 |
.vendor2 = CPUID_VENDOR_INTEL_2, |
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.vendor3 = CPUID_VENDOR_INTEL_3, |
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.family = 15,
|
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.model = 6,
|
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.stepping = 1,
|
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/* Missing: CPUID_VME, CPUID_HT */
|
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.features = PPRO_FEATURES | |
372 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
373 |
CPUID_PSE36, |
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/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
|
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, |
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/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
|
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
379 |
/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
|
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CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
|
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CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
|
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
|
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.ext3_features = 0,
|
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.xlevel = 0x80000008,
|
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.model_id = "Common KVM processor"
|
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}, |
387 |
{ |
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.name = "qemu32",
|
389 |
.level = 4,
|
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.family = 6,
|
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.model = 3,
|
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.stepping = 3,
|
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.features = PPRO_FEATURES, |
394 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, |
395 |
.xlevel = 0x80000004,
|
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}, |
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{ |
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.name = "kvm32",
|
399 |
.level = 5,
|
400 |
.family = 15,
|
401 |
.model = 6,
|
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.stepping = 1,
|
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.features = PPRO_FEATURES | |
404 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, |
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.ext_features = CPUID_EXT_SSE3, |
406 |
.ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK, |
407 |
.ext3_features = 0,
|
408 |
.xlevel = 0x80000008,
|
409 |
.model_id = "Common 32-bit KVM processor"
|
410 |
}, |
411 |
{ |
412 |
.name = "coreduo",
|
413 |
.level = 10,
|
414 |
.family = 6,
|
415 |
.model = 14,
|
416 |
.stepping = 8,
|
417 |
.features = PPRO_FEATURES | CPUID_VME | |
418 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI | |
419 |
CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, |
420 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX | |
421 |
CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, |
422 |
.ext2_features = CPUID_EXT2_NX, |
423 |
.xlevel = 0x80000008,
|
424 |
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
|
425 |
}, |
426 |
{ |
427 |
.name = "486",
|
428 |
.level = 1,
|
429 |
.family = 4,
|
430 |
.model = 0,
|
431 |
.stepping = 0,
|
432 |
.features = I486_FEATURES, |
433 |
.xlevel = 0,
|
434 |
}, |
435 |
{ |
436 |
.name = "pentium",
|
437 |
.level = 1,
|
438 |
.family = 5,
|
439 |
.model = 4,
|
440 |
.stepping = 3,
|
441 |
.features = PENTIUM_FEATURES, |
442 |
.xlevel = 0,
|
443 |
}, |
444 |
{ |
445 |
.name = "pentium2",
|
446 |
.level = 2,
|
447 |
.family = 6,
|
448 |
.model = 5,
|
449 |
.stepping = 2,
|
450 |
.features = PENTIUM2_FEATURES, |
451 |
.xlevel = 0,
|
452 |
}, |
453 |
{ |
454 |
.name = "pentium3",
|
455 |
.level = 2,
|
456 |
.family = 6,
|
457 |
.model = 7,
|
458 |
.stepping = 3,
|
459 |
.features = PENTIUM3_FEATURES, |
460 |
.xlevel = 0,
|
461 |
}, |
462 |
{ |
463 |
.name = "athlon",
|
464 |
.level = 2,
|
465 |
.vendor1 = CPUID_VENDOR_AMD_1, |
466 |
.vendor2 = CPUID_VENDOR_AMD_2, |
467 |
.vendor3 = CPUID_VENDOR_AMD_3, |
468 |
.family = 6,
|
469 |
.model = 2,
|
470 |
.stepping = 3,
|
471 |
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, |
472 |
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
473 |
.xlevel = 0x80000008,
|
474 |
}, |
475 |
{ |
476 |
.name = "n270",
|
477 |
/* original is on level 10 */
|
478 |
.level = 5,
|
479 |
.family = 6,
|
480 |
.model = 28,
|
481 |
.stepping = 2,
|
482 |
.features = PPRO_FEATURES | |
483 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS | |
484 |
CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, |
485 |
/* Some CPUs got no CPUID_SEP */
|
486 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
487 |
CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR, |
488 |
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX, |
489 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
490 |
.xlevel = 0x8000000A,
|
491 |
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
|
492 |
}, |
493 |
}; |
494 |
|
495 |
static int cpu_x86_fill_model_id(char *str) |
496 |
{ |
497 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
498 |
int i;
|
499 |
|
500 |
for (i = 0; i < 3; i++) { |
501 |
host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); |
502 |
memcpy(str + i * 16 + 0, &eax, 4); |
503 |
memcpy(str + i * 16 + 4, &ebx, 4); |
504 |
memcpy(str + i * 16 + 8, &ecx, 4); |
505 |
memcpy(str + i * 16 + 12, &edx, 4); |
506 |
} |
507 |
return 0; |
508 |
} |
509 |
|
510 |
static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) |
511 |
{ |
512 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
513 |
|
514 |
x86_cpu_def->name = "host";
|
515 |
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); |
516 |
x86_cpu_def->level = eax; |
517 |
x86_cpu_def->vendor1 = ebx; |
518 |
x86_cpu_def->vendor2 = edx; |
519 |
x86_cpu_def->vendor3 = ecx; |
520 |
|
521 |
host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); |
522 |
x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); |
523 |
x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); |
524 |
x86_cpu_def->stepping = eax & 0x0F;
|
525 |
x86_cpu_def->ext_features = ecx; |
526 |
x86_cpu_def->features = edx; |
527 |
|
528 |
if (kvm_enabled() && x86_cpu_def->level >= 7) { |
529 |
x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX); |
530 |
} else {
|
531 |
x86_cpu_def->cpuid_7_0_ebx_features = 0;
|
532 |
} |
533 |
|
534 |
host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); |
535 |
x86_cpu_def->xlevel = eax; |
536 |
|
537 |
host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); |
538 |
x86_cpu_def->ext2_features = edx; |
539 |
x86_cpu_def->ext3_features = ecx; |
540 |
cpu_x86_fill_model_id(x86_cpu_def->model_id); |
541 |
x86_cpu_def->vendor_override = 0;
|
542 |
|
543 |
/* Call Centaur's CPUID instruction. */
|
544 |
if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
|
545 |
x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 && |
546 |
x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) { |
547 |
host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); |
548 |
if (eax >= 0xC0000001) { |
549 |
/* Support VIA max extended level */
|
550 |
x86_cpu_def->xlevel2 = eax; |
551 |
host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); |
552 |
x86_cpu_def->ext4_features = edx; |
553 |
} |
554 |
} |
555 |
|
556 |
/*
|
557 |
* Every SVM feature requires emulation support in KVM - so we can't just
|
558 |
* read the host features here. KVM might even support SVM features not
|
559 |
* available on the host hardware. Just set all bits and mask out the
|
560 |
* unsupported ones later.
|
561 |
*/
|
562 |
x86_cpu_def->svm_features = -1;
|
563 |
|
564 |
return 0; |
565 |
} |
566 |
|
567 |
static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) |
568 |
{ |
569 |
int i;
|
570 |
|
571 |
for (i = 0; i < 32; ++i) |
572 |
if (1 << i & mask) { |
573 |
fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
|
574 |
" flag '%s' [0x%08x]\n",
|
575 |
f->cpuid >> 16, f->cpuid & 0xffff, |
576 |
f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
|
577 |
break;
|
578 |
} |
579 |
return 0; |
580 |
} |
581 |
|
582 |
/* best effort attempt to inform user requested cpu flags aren't making
|
583 |
* their way to the guest. Note: ft[].check_feat ideally should be
|
584 |
* specified via a guest_def field to suppress report of extraneous flags.
|
585 |
*/
|
586 |
static int check_features_against_host(x86_def_t *guest_def) |
587 |
{ |
588 |
x86_def_t host_def; |
589 |
uint32_t mask; |
590 |
int rv, i;
|
591 |
struct model_features_t ft[] = {
|
592 |
{&guest_def->features, &host_def.features, |
593 |
~0, feature_name, 0x00000000}, |
594 |
{&guest_def->ext_features, &host_def.ext_features, |
595 |
~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
|
596 |
{&guest_def->ext2_features, &host_def.ext2_features, |
597 |
~PPRO_FEATURES, ext2_feature_name, 0x80000000},
|
598 |
{&guest_def->ext3_features, &host_def.ext3_features, |
599 |
~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
|
600 |
|
601 |
cpu_x86_fill_host(&host_def); |
602 |
for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) |
603 |
for (mask = 1; mask; mask <<= 1) |
604 |
if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
|
605 |
!(*ft[i].host_feat & mask)) { |
606 |
unavailable_host_feature(&ft[i], mask); |
607 |
rv = 1;
|
608 |
} |
609 |
return rv;
|
610 |
} |
611 |
|
612 |
static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque, |
613 |
const char *name, Error **errp) |
614 |
{ |
615 |
X86CPU *cpu = X86_CPU(obj); |
616 |
CPUX86State *env = &cpu->env; |
617 |
int64_t value; |
618 |
|
619 |
value = (env->cpuid_version >> 8) & 0xf; |
620 |
if (value == 0xf) { |
621 |
value += (env->cpuid_version >> 20) & 0xff; |
622 |
} |
623 |
visit_type_int(v, &value, name, errp); |
624 |
} |
625 |
|
626 |
static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque, |
627 |
const char *name, Error **errp) |
628 |
{ |
629 |
X86CPU *cpu = X86_CPU(obj); |
630 |
CPUX86State *env = &cpu->env; |
631 |
const int64_t min = 0; |
632 |
const int64_t max = 0xff + 0xf; |
633 |
int64_t value; |
634 |
|
635 |
visit_type_int(v, &value, name, errp); |
636 |
if (error_is_set(errp)) {
|
637 |
return;
|
638 |
} |
639 |
if (value < min || value > max) {
|
640 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
641 |
name ? name : "null", value, min, max);
|
642 |
return;
|
643 |
} |
644 |
|
645 |
env->cpuid_version &= ~0xff00f00;
|
646 |
if (value > 0x0f) { |
647 |
env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); |
648 |
} else {
|
649 |
env->cpuid_version |= value << 8;
|
650 |
} |
651 |
} |
652 |
|
653 |
static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque, |
654 |
const char *name, Error **errp) |
655 |
{ |
656 |
X86CPU *cpu = X86_CPU(obj); |
657 |
CPUX86State *env = &cpu->env; |
658 |
int64_t value; |
659 |
|
660 |
value = (env->cpuid_version >> 4) & 0xf; |
661 |
value |= ((env->cpuid_version >> 16) & 0xf) << 4; |
662 |
visit_type_int(v, &value, name, errp); |
663 |
} |
664 |
|
665 |
static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque, |
666 |
const char *name, Error **errp) |
667 |
{ |
668 |
X86CPU *cpu = X86_CPU(obj); |
669 |
CPUX86State *env = &cpu->env; |
670 |
const int64_t min = 0; |
671 |
const int64_t max = 0xff; |
672 |
int64_t value; |
673 |
|
674 |
visit_type_int(v, &value, name, errp); |
675 |
if (error_is_set(errp)) {
|
676 |
return;
|
677 |
} |
678 |
if (value < min || value > max) {
|
679 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
680 |
name ? name : "null", value, min, max);
|
681 |
return;
|
682 |
} |
683 |
|
684 |
env->cpuid_version &= ~0xf00f0;
|
685 |
env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); |
686 |
} |
687 |
|
688 |
static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, |
689 |
void *opaque, const char *name, |
690 |
Error **errp) |
691 |
{ |
692 |
X86CPU *cpu = X86_CPU(obj); |
693 |
CPUX86State *env = &cpu->env; |
694 |
int64_t value; |
695 |
|
696 |
value = env->cpuid_version & 0xf;
|
697 |
visit_type_int(v, &value, name, errp); |
698 |
} |
699 |
|
700 |
static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, |
701 |
void *opaque, const char *name, |
702 |
Error **errp) |
703 |
{ |
704 |
X86CPU *cpu = X86_CPU(obj); |
705 |
CPUX86State *env = &cpu->env; |
706 |
const int64_t min = 0; |
707 |
const int64_t max = 0xf; |
708 |
int64_t value; |
709 |
|
710 |
visit_type_int(v, &value, name, errp); |
711 |
if (error_is_set(errp)) {
|
712 |
return;
|
713 |
} |
714 |
if (value < min || value > max) {
|
715 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
716 |
name ? name : "null", value, min, max);
|
717 |
return;
|
718 |
} |
719 |
|
720 |
env->cpuid_version &= ~0xf;
|
721 |
env->cpuid_version |= value & 0xf;
|
722 |
} |
723 |
|
724 |
static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque, |
725 |
const char *name, Error **errp) |
726 |
{ |
727 |
X86CPU *cpu = X86_CPU(obj); |
728 |
|
729 |
visit_type_uint32(v, &cpu->env.cpuid_level, name, errp); |
730 |
} |
731 |
|
732 |
static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque, |
733 |
const char *name, Error **errp) |
734 |
{ |
735 |
X86CPU *cpu = X86_CPU(obj); |
736 |
|
737 |
visit_type_uint32(v, &cpu->env.cpuid_level, name, errp); |
738 |
} |
739 |
|
740 |
static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque, |
741 |
const char *name, Error **errp) |
742 |
{ |
743 |
X86CPU *cpu = X86_CPU(obj); |
744 |
|
745 |
visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp); |
746 |
} |
747 |
|
748 |
static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque, |
749 |
const char *name, Error **errp) |
750 |
{ |
751 |
X86CPU *cpu = X86_CPU(obj); |
752 |
|
753 |
visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp); |
754 |
} |
755 |
|
756 |
static char *x86_cpuid_get_vendor(Object *obj, Error **errp) |
757 |
{ |
758 |
X86CPU *cpu = X86_CPU(obj); |
759 |
CPUX86State *env = &cpu->env; |
760 |
char *value;
|
761 |
int i;
|
762 |
|
763 |
value = (char *)g_malloc(12 + 1); |
764 |
for (i = 0; i < 4; i++) { |
765 |
value[i ] = env->cpuid_vendor1 >> (8 * i);
|
766 |
value[i + 4] = env->cpuid_vendor2 >> (8 * i); |
767 |
value[i + 8] = env->cpuid_vendor3 >> (8 * i); |
768 |
} |
769 |
value[12] = '\0'; |
770 |
return value;
|
771 |
} |
772 |
|
773 |
static void x86_cpuid_set_vendor(Object *obj, const char *value, |
774 |
Error **errp) |
775 |
{ |
776 |
X86CPU *cpu = X86_CPU(obj); |
777 |
CPUX86State *env = &cpu->env; |
778 |
int i;
|
779 |
|
780 |
if (strlen(value) != 12) { |
781 |
error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
|
782 |
"vendor", value);
|
783 |
return;
|
784 |
} |
785 |
|
786 |
env->cpuid_vendor1 = 0;
|
787 |
env->cpuid_vendor2 = 0;
|
788 |
env->cpuid_vendor3 = 0;
|
789 |
for (i = 0; i < 4; i++) { |
790 |
env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
|
791 |
env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); |
792 |
env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); |
793 |
} |
794 |
env->cpuid_vendor_override = 1;
|
795 |
} |
796 |
|
797 |
static char *x86_cpuid_get_model_id(Object *obj, Error **errp) |
798 |
{ |
799 |
X86CPU *cpu = X86_CPU(obj); |
800 |
CPUX86State *env = &cpu->env; |
801 |
char *value;
|
802 |
int i;
|
803 |
|
804 |
value = g_malloc(48 + 1); |
805 |
for (i = 0; i < 48; i++) { |
806 |
value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); |
807 |
} |
808 |
value[48] = '\0'; |
809 |
return value;
|
810 |
} |
811 |
|
812 |
static void x86_cpuid_set_model_id(Object *obj, const char *model_id, |
813 |
Error **errp) |
814 |
{ |
815 |
X86CPU *cpu = X86_CPU(obj); |
816 |
CPUX86State *env = &cpu->env; |
817 |
int c, len, i;
|
818 |
|
819 |
if (model_id == NULL) { |
820 |
model_id = "";
|
821 |
} |
822 |
len = strlen(model_id); |
823 |
memset(env->cpuid_model, 0, 48); |
824 |
for (i = 0; i < 48; i++) { |
825 |
if (i >= len) {
|
826 |
c = '\0';
|
827 |
} else {
|
828 |
c = (uint8_t)model_id[i]; |
829 |
} |
830 |
env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); |
831 |
} |
832 |
} |
833 |
|
834 |
static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque, |
835 |
const char *name, Error **errp) |
836 |
{ |
837 |
X86CPU *cpu = X86_CPU(obj); |
838 |
int64_t value; |
839 |
|
840 |
value = cpu->env.tsc_khz * 1000;
|
841 |
visit_type_int(v, &value, name, errp); |
842 |
} |
843 |
|
844 |
static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque, |
845 |
const char *name, Error **errp) |
846 |
{ |
847 |
X86CPU *cpu = X86_CPU(obj); |
848 |
const int64_t min = 0; |
849 |
const int64_t max = INT64_MAX;
|
850 |
int64_t value; |
851 |
|
852 |
visit_type_int(v, &value, name, errp); |
853 |
if (error_is_set(errp)) {
|
854 |
return;
|
855 |
} |
856 |
if (value < min || value > max) {
|
857 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
858 |
name ? name : "null", value, min, max);
|
859 |
return;
|
860 |
} |
861 |
|
862 |
cpu->env.tsc_khz = value / 1000;
|
863 |
} |
864 |
|
865 |
static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) |
866 |
{ |
867 |
unsigned int i; |
868 |
x86_def_t *def; |
869 |
|
870 |
char *s = g_strdup(cpu_model);
|
871 |
char *featurestr, *name = strtok(s, ","); |
872 |
/* Features to be added*/
|
873 |
uint32_t plus_features = 0, plus_ext_features = 0; |
874 |
uint32_t plus_ext2_features = 0, plus_ext3_features = 0; |
875 |
uint32_t plus_kvm_features = 0, plus_svm_features = 0; |
876 |
/* Features to be removed */
|
877 |
uint32_t minus_features = 0, minus_ext_features = 0; |
878 |
uint32_t minus_ext2_features = 0, minus_ext3_features = 0; |
879 |
uint32_t minus_kvm_features = 0, minus_svm_features = 0; |
880 |
uint32_t numvalue; |
881 |
|
882 |
for (def = x86_defs; def; def = def->next)
|
883 |
if (name && !strcmp(name, def->name))
|
884 |
break;
|
885 |
if (kvm_enabled() && name && strcmp(name, "host") == 0) { |
886 |
cpu_x86_fill_host(x86_cpu_def); |
887 |
} else if (!def) { |
888 |
goto error;
|
889 |
} else {
|
890 |
memcpy(x86_cpu_def, def, sizeof(*def));
|
891 |
} |
892 |
|
893 |
#if defined(CONFIG_KVM)
|
894 |
plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
|
895 |
(1 << KVM_FEATURE_NOP_IO_DELAY) |
|
896 |
(1 << KVM_FEATURE_MMU_OP) |
|
897 |
(1 << KVM_FEATURE_CLOCKSOURCE2) |
|
898 |
(1 << KVM_FEATURE_ASYNC_PF) |
|
899 |
(1 << KVM_FEATURE_STEAL_TIME) |
|
900 |
(1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
|
901 |
#else
|
902 |
plus_kvm_features = 0;
|
903 |
#endif
|
904 |
|
905 |
add_flagname_to_bitmaps("hypervisor", &plus_features,
|
906 |
&plus_ext_features, &plus_ext2_features, &plus_ext3_features, |
907 |
&plus_kvm_features, &plus_svm_features); |
908 |
|
909 |
featurestr = strtok(NULL, ","); |
910 |
|
911 |
while (featurestr) {
|
912 |
char *val;
|
913 |
if (featurestr[0] == '+') { |
914 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features,
|
915 |
&plus_ext_features, &plus_ext2_features, |
916 |
&plus_ext3_features, &plus_kvm_features, |
917 |
&plus_svm_features); |
918 |
} else if (featurestr[0] == '-') { |
919 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features,
|
920 |
&minus_ext_features, &minus_ext2_features, |
921 |
&minus_ext3_features, &minus_kvm_features, |
922 |
&minus_svm_features); |
923 |
} else if ((val = strchr(featurestr, '='))) { |
924 |
*val = 0; val++;
|
925 |
if (!strcmp(featurestr, "family")) { |
926 |
char *err;
|
927 |
numvalue = strtoul(val, &err, 0);
|
928 |
if (!*val || *err || numvalue > 0xff + 0xf) { |
929 |
fprintf(stderr, "bad numerical value %s\n", val);
|
930 |
goto error;
|
931 |
} |
932 |
x86_cpu_def->family = numvalue; |
933 |
} else if (!strcmp(featurestr, "model")) { |
934 |
char *err;
|
935 |
numvalue = strtoul(val, &err, 0);
|
936 |
if (!*val || *err || numvalue > 0xff) { |
937 |
fprintf(stderr, "bad numerical value %s\n", val);
|
938 |
goto error;
|
939 |
} |
940 |
x86_cpu_def->model = numvalue; |
941 |
} else if (!strcmp(featurestr, "stepping")) { |
942 |
char *err;
|
943 |
numvalue = strtoul(val, &err, 0);
|
944 |
if (!*val || *err || numvalue > 0xf) { |
945 |
fprintf(stderr, "bad numerical value %s\n", val);
|
946 |
goto error;
|
947 |
} |
948 |
x86_cpu_def->stepping = numvalue ; |
949 |
} else if (!strcmp(featurestr, "level")) { |
950 |
char *err;
|
951 |
numvalue = strtoul(val, &err, 0);
|
952 |
if (!*val || *err) {
|
953 |
fprintf(stderr, "bad numerical value %s\n", val);
|
954 |
goto error;
|
955 |
} |
956 |
x86_cpu_def->level = numvalue; |
957 |
} else if (!strcmp(featurestr, "xlevel")) { |
958 |
char *err;
|
959 |
numvalue = strtoul(val, &err, 0);
|
960 |
if (!*val || *err) {
|
961 |
fprintf(stderr, "bad numerical value %s\n", val);
|
962 |
goto error;
|
963 |
} |
964 |
if (numvalue < 0x80000000) { |
965 |
numvalue += 0x80000000;
|
966 |
} |
967 |
x86_cpu_def->xlevel = numvalue; |
968 |
} else if (!strcmp(featurestr, "vendor")) { |
969 |
if (strlen(val) != 12) { |
970 |
fprintf(stderr, "vendor string must be 12 chars long\n");
|
971 |
goto error;
|
972 |
} |
973 |
x86_cpu_def->vendor1 = 0;
|
974 |
x86_cpu_def->vendor2 = 0;
|
975 |
x86_cpu_def->vendor3 = 0;
|
976 |
for(i = 0; i < 4; i++) { |
977 |
x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
|
978 |
x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i); |
979 |
x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i); |
980 |
} |
981 |
x86_cpu_def->vendor_override = 1;
|
982 |
} else if (!strcmp(featurestr, "model_id")) { |
983 |
pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
|
984 |
val); |
985 |
} else if (!strcmp(featurestr, "tsc_freq")) { |
986 |
int64_t tsc_freq; |
987 |
char *err;
|
988 |
|
989 |
tsc_freq = strtosz_suffix_unit(val, &err, |
990 |
STRTOSZ_DEFSUFFIX_B, 1000);
|
991 |
if (tsc_freq < 0 || *err) { |
992 |
fprintf(stderr, "bad numerical value %s\n", val);
|
993 |
goto error;
|
994 |
} |
995 |
x86_cpu_def->tsc_khz = tsc_freq / 1000;
|
996 |
} else if (!strcmp(featurestr, "hv_spinlocks")) { |
997 |
char *err;
|
998 |
numvalue = strtoul(val, &err, 0);
|
999 |
if (!*val || *err) {
|
1000 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1001 |
goto error;
|
1002 |
} |
1003 |
hyperv_set_spinlock_retries(numvalue); |
1004 |
} else {
|
1005 |
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
1006 |
goto error;
|
1007 |
} |
1008 |
} else if (!strcmp(featurestr, "check")) { |
1009 |
check_cpuid = 1;
|
1010 |
} else if (!strcmp(featurestr, "enforce")) { |
1011 |
check_cpuid = enforce_cpuid = 1;
|
1012 |
} else if (!strcmp(featurestr, "hv_relaxed")) { |
1013 |
hyperv_enable_relaxed_timing(true);
|
1014 |
} else if (!strcmp(featurestr, "hv_vapic")) { |
1015 |
hyperv_enable_vapic_recommended(true);
|
1016 |
} else {
|
1017 |
fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
|
1018 |
goto error;
|
1019 |
} |
1020 |
featurestr = strtok(NULL, ","); |
1021 |
} |
1022 |
x86_cpu_def->features |= plus_features; |
1023 |
x86_cpu_def->ext_features |= plus_ext_features; |
1024 |
x86_cpu_def->ext2_features |= plus_ext2_features; |
1025 |
x86_cpu_def->ext3_features |= plus_ext3_features; |
1026 |
x86_cpu_def->kvm_features |= plus_kvm_features; |
1027 |
x86_cpu_def->svm_features |= plus_svm_features; |
1028 |
x86_cpu_def->features &= ~minus_features; |
1029 |
x86_cpu_def->ext_features &= ~minus_ext_features; |
1030 |
x86_cpu_def->ext2_features &= ~minus_ext2_features; |
1031 |
x86_cpu_def->ext3_features &= ~minus_ext3_features; |
1032 |
x86_cpu_def->kvm_features &= ~minus_kvm_features; |
1033 |
x86_cpu_def->svm_features &= ~minus_svm_features; |
1034 |
if (check_cpuid) {
|
1035 |
if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
|
1036 |
goto error;
|
1037 |
} |
1038 |
g_free(s); |
1039 |
return 0; |
1040 |
|
1041 |
error:
|
1042 |
g_free(s); |
1043 |
return -1; |
1044 |
} |
1045 |
|
1046 |
/* generate a composite string into buf of all cpuid names in featureset
|
1047 |
* selected by fbits. indicate truncation at bufsize in the event of overflow.
|
1048 |
* if flags, suppress names undefined in featureset.
|
1049 |
*/
|
1050 |
static void listflags(char *buf, int bufsize, uint32_t fbits, |
1051 |
const char **featureset, uint32_t flags) |
1052 |
{ |
1053 |
const char **p = &featureset[31]; |
1054 |
char *q, *b, bit;
|
1055 |
int nc;
|
1056 |
|
1057 |
b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL; |
1058 |
*buf = '\0';
|
1059 |
for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit) |
1060 |
if (fbits & 1 << bit && (*p || !flags)) { |
1061 |
if (*p)
|
1062 |
nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p); |
1063 |
else
|
1064 |
nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit); |
1065 |
if (bufsize <= nc) {
|
1066 |
if (b) {
|
1067 |
memcpy(b, "...", sizeof("...")); |
1068 |
} |
1069 |
return;
|
1070 |
} |
1071 |
q += nc; |
1072 |
bufsize -= nc; |
1073 |
} |
1074 |
} |
1075 |
|
1076 |
/* generate CPU information:
|
1077 |
* -? list model names
|
1078 |
* -?model list model names/IDs
|
1079 |
* -?dump output all model (x86_def_t) data
|
1080 |
* -?cpuid list all recognized cpuid flag names
|
1081 |
*/
|
1082 |
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg) |
1083 |
{ |
1084 |
unsigned char model = !strcmp("?model", optarg); |
1085 |
unsigned char dump = !strcmp("?dump", optarg); |
1086 |
unsigned char cpuid = !strcmp("?cpuid", optarg); |
1087 |
x86_def_t *def; |
1088 |
char buf[256]; |
1089 |
|
1090 |
if (cpuid) {
|
1091 |
(*cpu_fprintf)(f, "Recognized CPUID flags:\n");
|
1092 |
listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1); |
1093 |
(*cpu_fprintf)(f, " f_edx: %s\n", buf);
|
1094 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1); |
1095 |
(*cpu_fprintf)(f, " f_ecx: %s\n", buf);
|
1096 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1); |
1097 |
(*cpu_fprintf)(f, " extf_edx: %s\n", buf);
|
1098 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1); |
1099 |
(*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
|
1100 |
return;
|
1101 |
} |
1102 |
for (def = x86_defs; def; def = def->next) {
|
1103 |
snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name); |
1104 |
if (model || dump) {
|
1105 |
(*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
|
1106 |
} else {
|
1107 |
(*cpu_fprintf)(f, "x86 %16s\n", buf);
|
1108 |
} |
1109 |
if (dump) {
|
1110 |
memcpy(buf, &def->vendor1, sizeof (def->vendor1));
|
1111 |
memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2)); |
1112 |
memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3)); |
1113 |
buf[12] = '\0'; |
1114 |
(*cpu_fprintf)(f, |
1115 |
" family %d model %d stepping %d level %d xlevel 0x%x"
|
1116 |
" vendor \"%s\"\n",
|
1117 |
def->family, def->model, def->stepping, def->level, |
1118 |
def->xlevel, buf); |
1119 |
listflags(buf, sizeof (buf), def->features, feature_name, 0); |
1120 |
(*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
|
1121 |
buf); |
1122 |
listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
|
1123 |
0);
|
1124 |
(*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
|
1125 |
buf); |
1126 |
listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
|
1127 |
0);
|
1128 |
(*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
|
1129 |
def->ext2_features, buf); |
1130 |
listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
|
1131 |
0);
|
1132 |
(*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
|
1133 |
def->ext3_features, buf); |
1134 |
(*cpu_fprintf)(f, "\n");
|
1135 |
} |
1136 |
} |
1137 |
if (kvm_enabled()) {
|
1138 |
(*cpu_fprintf)(f, "x86 %16s\n", "[host]"); |
1139 |
} |
1140 |
} |
1141 |
|
1142 |
CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) |
1143 |
{ |
1144 |
CpuDefinitionInfoList *cpu_list = NULL;
|
1145 |
x86_def_t *def; |
1146 |
|
1147 |
for (def = x86_defs; def; def = def->next) {
|
1148 |
CpuDefinitionInfoList *entry; |
1149 |
CpuDefinitionInfo *info; |
1150 |
|
1151 |
info = g_malloc0(sizeof(*info));
|
1152 |
info->name = g_strdup(def->name); |
1153 |
|
1154 |
entry = g_malloc0(sizeof(*entry));
|
1155 |
entry->value = info; |
1156 |
entry->next = cpu_list; |
1157 |
cpu_list = entry; |
1158 |
} |
1159 |
|
1160 |
return cpu_list;
|
1161 |
} |
1162 |
|
1163 |
int cpu_x86_register(X86CPU *cpu, const char *cpu_model) |
1164 |
{ |
1165 |
CPUX86State *env = &cpu->env; |
1166 |
x86_def_t def1, *def = &def1; |
1167 |
Error *error = NULL;
|
1168 |
|
1169 |
memset(def, 0, sizeof(*def)); |
1170 |
|
1171 |
if (cpu_x86_find_by_name(def, cpu_model) < 0) |
1172 |
return -1; |
1173 |
if (def->vendor1) {
|
1174 |
env->cpuid_vendor1 = def->vendor1; |
1175 |
env->cpuid_vendor2 = def->vendor2; |
1176 |
env->cpuid_vendor3 = def->vendor3; |
1177 |
} else {
|
1178 |
env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; |
1179 |
env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; |
1180 |
env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; |
1181 |
} |
1182 |
env->cpuid_vendor_override = def->vendor_override; |
1183 |
object_property_set_int(OBJECT(cpu), def->level, "level", &error);
|
1184 |
object_property_set_int(OBJECT(cpu), def->family, "family", &error);
|
1185 |
object_property_set_int(OBJECT(cpu), def->model, "model", &error);
|
1186 |
object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
|
1187 |
env->cpuid_features = def->features; |
1188 |
env->cpuid_ext_features = def->ext_features; |
1189 |
env->cpuid_ext2_features = def->ext2_features; |
1190 |
env->cpuid_ext3_features = def->ext3_features; |
1191 |
object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
|
1192 |
env->cpuid_kvm_features = def->kvm_features; |
1193 |
env->cpuid_svm_features = def->svm_features; |
1194 |
env->cpuid_ext4_features = def->ext4_features; |
1195 |
env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features; |
1196 |
env->cpuid_xlevel2 = def->xlevel2; |
1197 |
object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
|
1198 |
"tsc-frequency", &error);
|
1199 |
if (!kvm_enabled()) {
|
1200 |
env->cpuid_features &= TCG_FEATURES; |
1201 |
env->cpuid_ext_features &= TCG_EXT_FEATURES; |
1202 |
env->cpuid_ext2_features &= (TCG_EXT2_FEATURES |
1203 |
#ifdef TARGET_X86_64
|
1204 |
| CPUID_EXT2_SYSCALL | CPUID_EXT2_LM |
1205 |
#endif
|
1206 |
); |
1207 |
env->cpuid_ext3_features &= TCG_EXT3_FEATURES; |
1208 |
env->cpuid_svm_features &= TCG_SVM_FEATURES; |
1209 |
} |
1210 |
object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
|
1211 |
if (error_is_set(&error)) {
|
1212 |
error_free(error); |
1213 |
return -1; |
1214 |
} |
1215 |
return 0; |
1216 |
} |
1217 |
|
1218 |
#if !defined(CONFIG_USER_ONLY)
|
1219 |
/* copy vendor id string to 32 bit register, nul pad as needed
|
1220 |
*/
|
1221 |
static void cpyid(const char *s, uint32_t *id) |
1222 |
{ |
1223 |
char *d = (char *)id; |
1224 |
char i;
|
1225 |
|
1226 |
for (i = sizeof (*id); i--; ) |
1227 |
*d++ = *s ? *s++ : '\0';
|
1228 |
} |
1229 |
|
1230 |
/* interpret radix and convert from string to arbitrary scalar,
|
1231 |
* otherwise flag failure
|
1232 |
*/
|
1233 |
#define setscalar(pval, str, perr) \
|
1234 |
{ \ |
1235 |
char *pend; \
|
1236 |
unsigned long ul; \ |
1237 |
\ |
1238 |
ul = strtoul(str, &pend, 0); \
|
1239 |
*str && !*pend ? (*pval = ul) : (*perr = 1); \
|
1240 |
} |
1241 |
|
1242 |
/* map cpuid options to feature bits, otherwise return failure
|
1243 |
* (option tags in *str are delimited by whitespace)
|
1244 |
*/
|
1245 |
static void setfeatures(uint32_t *pval, const char *str, |
1246 |
const char **featureset, int *perr) |
1247 |
{ |
1248 |
const char *p, *q; |
1249 |
|
1250 |
for (q = p = str; *p || *q; q = p) {
|
1251 |
while (iswhite(*p))
|
1252 |
q = ++p; |
1253 |
while (*p && !iswhite(*p))
|
1254 |
++p; |
1255 |
if (!*q && !*p)
|
1256 |
return;
|
1257 |
if (!lookup_feature(pval, q, p, featureset)) {
|
1258 |
fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
|
1259 |
(int)(p - q), q);
|
1260 |
*perr = 1;
|
1261 |
return;
|
1262 |
} |
1263 |
} |
1264 |
} |
1265 |
|
1266 |
/* map config file options to x86_def_t form
|
1267 |
*/
|
1268 |
static int cpudef_setfield(const char *name, const char *str, void *opaque) |
1269 |
{ |
1270 |
x86_def_t *def = opaque; |
1271 |
int err = 0; |
1272 |
|
1273 |
if (!strcmp(name, "name")) { |
1274 |
g_free((void *)def->name);
|
1275 |
def->name = g_strdup(str); |
1276 |
} else if (!strcmp(name, "model_id")) { |
1277 |
strncpy(def->model_id, str, sizeof (def->model_id));
|
1278 |
} else if (!strcmp(name, "level")) { |
1279 |
setscalar(&def->level, str, &err) |
1280 |
} else if (!strcmp(name, "vendor")) { |
1281 |
cpyid(&str[0], &def->vendor1);
|
1282 |
cpyid(&str[4], &def->vendor2);
|
1283 |
cpyid(&str[8], &def->vendor3);
|
1284 |
} else if (!strcmp(name, "family")) { |
1285 |
setscalar(&def->family, str, &err) |
1286 |
} else if (!strcmp(name, "model")) { |
1287 |
setscalar(&def->model, str, &err) |
1288 |
} else if (!strcmp(name, "stepping")) { |
1289 |
setscalar(&def->stepping, str, &err) |
1290 |
} else if (!strcmp(name, "feature_edx")) { |
1291 |
setfeatures(&def->features, str, feature_name, &err); |
1292 |
} else if (!strcmp(name, "feature_ecx")) { |
1293 |
setfeatures(&def->ext_features, str, ext_feature_name, &err); |
1294 |
} else if (!strcmp(name, "extfeature_edx")) { |
1295 |
setfeatures(&def->ext2_features, str, ext2_feature_name, &err); |
1296 |
} else if (!strcmp(name, "extfeature_ecx")) { |
1297 |
setfeatures(&def->ext3_features, str, ext3_feature_name, &err); |
1298 |
} else if (!strcmp(name, "xlevel")) { |
1299 |
setscalar(&def->xlevel, str, &err) |
1300 |
} else {
|
1301 |
fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
|
1302 |
return (1); |
1303 |
} |
1304 |
if (err) {
|
1305 |
fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
|
1306 |
return (1); |
1307 |
} |
1308 |
return (0); |
1309 |
} |
1310 |
|
1311 |
/* register config file entry as x86_def_t
|
1312 |
*/
|
1313 |
static int cpudef_register(QemuOpts *opts, void *opaque) |
1314 |
{ |
1315 |
x86_def_t *def = g_malloc0(sizeof (x86_def_t));
|
1316 |
|
1317 |
qemu_opt_foreach(opts, cpudef_setfield, def, 1);
|
1318 |
def->next = x86_defs; |
1319 |
x86_defs = def; |
1320 |
return (0); |
1321 |
} |
1322 |
|
1323 |
void cpu_clear_apic_feature(CPUX86State *env)
|
1324 |
{ |
1325 |
env->cpuid_features &= ~CPUID_APIC; |
1326 |
} |
1327 |
|
1328 |
#endif /* !CONFIG_USER_ONLY */ |
1329 |
|
1330 |
/* register "cpudef" models defined in configuration file. Here we first
|
1331 |
* preload any built-in definitions
|
1332 |
*/
|
1333 |
void x86_cpudef_setup(void) |
1334 |
{ |
1335 |
int i, j;
|
1336 |
static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" }; |
1337 |
|
1338 |
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { |
1339 |
builtin_x86_defs[i].next = x86_defs; |
1340 |
builtin_x86_defs[i].flags = 1;
|
1341 |
|
1342 |
/* Look for specific "cpudef" models that */
|
1343 |
/* have the QEMU version in .model_id */
|
1344 |
for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) { |
1345 |
if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) { |
1346 |
pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version "); |
1347 |
pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
|
1348 |
break;
|
1349 |
} |
1350 |
} |
1351 |
|
1352 |
x86_defs = &builtin_x86_defs[i]; |
1353 |
} |
1354 |
#if !defined(CONFIG_USER_ONLY)
|
1355 |
qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0); |
1356 |
#endif
|
1357 |
} |
1358 |
|
1359 |
static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, |
1360 |
uint32_t *ecx, uint32_t *edx) |
1361 |
{ |
1362 |
*ebx = env->cpuid_vendor1; |
1363 |
*edx = env->cpuid_vendor2; |
1364 |
*ecx = env->cpuid_vendor3; |
1365 |
|
1366 |
/* sysenter isn't supported on compatibility mode on AMD, syscall
|
1367 |
* isn't supported in compatibility mode on Intel.
|
1368 |
* Normally we advertise the actual cpu vendor, but you can override
|
1369 |
* this if you want to use KVM's sysenter/syscall emulation
|
1370 |
* in compatibility mode and when doing cross vendor migration
|
1371 |
*/
|
1372 |
if (kvm_enabled() && ! env->cpuid_vendor_override) {
|
1373 |
host_cpuid(0, 0, NULL, ebx, ecx, edx); |
1374 |
} |
1375 |
} |
1376 |
|
1377 |
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
1378 |
uint32_t *eax, uint32_t *ebx, |
1379 |
uint32_t *ecx, uint32_t *edx) |
1380 |
{ |
1381 |
/* test if maximum index reached */
|
1382 |
if (index & 0x80000000) { |
1383 |
if (index > env->cpuid_xlevel) {
|
1384 |
if (env->cpuid_xlevel2 > 0) { |
1385 |
/* Handle the Centaur's CPUID instruction. */
|
1386 |
if (index > env->cpuid_xlevel2) {
|
1387 |
index = env->cpuid_xlevel2; |
1388 |
} else if (index < 0xC0000000) { |
1389 |
index = env->cpuid_xlevel; |
1390 |
} |
1391 |
} else {
|
1392 |
index = env->cpuid_xlevel; |
1393 |
} |
1394 |
} |
1395 |
} else {
|
1396 |
if (index > env->cpuid_level)
|
1397 |
index = env->cpuid_level; |
1398 |
} |
1399 |
|
1400 |
switch(index) {
|
1401 |
case 0: |
1402 |
*eax = env->cpuid_level; |
1403 |
get_cpuid_vendor(env, ebx, ecx, edx); |
1404 |
break;
|
1405 |
case 1: |
1406 |
*eax = env->cpuid_version; |
1407 |
*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ |
1408 |
*ecx = env->cpuid_ext_features; |
1409 |
*edx = env->cpuid_features; |
1410 |
if (env->nr_cores * env->nr_threads > 1) { |
1411 |
*ebx |= (env->nr_cores * env->nr_threads) << 16;
|
1412 |
*edx |= 1 << 28; /* HTT bit */ |
1413 |
} |
1414 |
break;
|
1415 |
case 2: |
1416 |
/* cache info: needed for Pentium Pro compatibility */
|
1417 |
*eax = 1;
|
1418 |
*ebx = 0;
|
1419 |
*ecx = 0;
|
1420 |
*edx = 0x2c307d;
|
1421 |
break;
|
1422 |
case 4: |
1423 |
/* cache info: needed for Core compatibility */
|
1424 |
if (env->nr_cores > 1) { |
1425 |
*eax = (env->nr_cores - 1) << 26; |
1426 |
} else {
|
1427 |
*eax = 0;
|
1428 |
} |
1429 |
switch (count) {
|
1430 |
case 0: /* L1 dcache info */ |
1431 |
*eax |= 0x0000121;
|
1432 |
*ebx = 0x1c0003f;
|
1433 |
*ecx = 0x000003f;
|
1434 |
*edx = 0x0000001;
|
1435 |
break;
|
1436 |
case 1: /* L1 icache info */ |
1437 |
*eax |= 0x0000122;
|
1438 |
*ebx = 0x1c0003f;
|
1439 |
*ecx = 0x000003f;
|
1440 |
*edx = 0x0000001;
|
1441 |
break;
|
1442 |
case 2: /* L2 cache info */ |
1443 |
*eax |= 0x0000143;
|
1444 |
if (env->nr_threads > 1) { |
1445 |
*eax |= (env->nr_threads - 1) << 14; |
1446 |
} |
1447 |
*ebx = 0x3c0003f;
|
1448 |
*ecx = 0x0000fff;
|
1449 |
*edx = 0x0000001;
|
1450 |
break;
|
1451 |
default: /* end of info */ |
1452 |
*eax = 0;
|
1453 |
*ebx = 0;
|
1454 |
*ecx = 0;
|
1455 |
*edx = 0;
|
1456 |
break;
|
1457 |
} |
1458 |
break;
|
1459 |
case 5: |
1460 |
/* mwait info: needed for Core compatibility */
|
1461 |
*eax = 0; /* Smallest monitor-line size in bytes */ |
1462 |
*ebx = 0; /* Largest monitor-line size in bytes */ |
1463 |
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; |
1464 |
*edx = 0;
|
1465 |
break;
|
1466 |
case 6: |
1467 |
/* Thermal and Power Leaf */
|
1468 |
*eax = 0;
|
1469 |
*ebx = 0;
|
1470 |
*ecx = 0;
|
1471 |
*edx = 0;
|
1472 |
break;
|
1473 |
case 7: |
1474 |
/* Structured Extended Feature Flags Enumeration Leaf */
|
1475 |
if (count == 0) { |
1476 |
*eax = 0; /* Maximum ECX value for sub-leaves */ |
1477 |
*ebx = env->cpuid_7_0_ebx; /* Feature flags */
|
1478 |
*ecx = 0; /* Reserved */ |
1479 |
*edx = 0; /* Reserved */ |
1480 |
} else {
|
1481 |
*eax = 0;
|
1482 |
*ebx = 0;
|
1483 |
*ecx = 0;
|
1484 |
*edx = 0;
|
1485 |
} |
1486 |
break;
|
1487 |
case 9: |
1488 |
/* Direct Cache Access Information Leaf */
|
1489 |
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */ |
1490 |
*ebx = 0;
|
1491 |
*ecx = 0;
|
1492 |
*edx = 0;
|
1493 |
break;
|
1494 |
case 0xA: |
1495 |
/* Architectural Performance Monitoring Leaf */
|
1496 |
if (kvm_enabled()) {
|
1497 |
KVMState *s = env->kvm_state; |
1498 |
|
1499 |
*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
|
1500 |
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
|
1501 |
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
|
1502 |
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
|
1503 |
} else {
|
1504 |
*eax = 0;
|
1505 |
*ebx = 0;
|
1506 |
*ecx = 0;
|
1507 |
*edx = 0;
|
1508 |
} |
1509 |
break;
|
1510 |
case 0xD: |
1511 |
/* Processor Extended State */
|
1512 |
if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
|
1513 |
*eax = 0;
|
1514 |
*ebx = 0;
|
1515 |
*ecx = 0;
|
1516 |
*edx = 0;
|
1517 |
break;
|
1518 |
} |
1519 |
if (kvm_enabled()) {
|
1520 |
KVMState *s = env->kvm_state; |
1521 |
|
1522 |
*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
|
1523 |
*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
|
1524 |
*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
|
1525 |
*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
|
1526 |
} else {
|
1527 |
*eax = 0;
|
1528 |
*ebx = 0;
|
1529 |
*ecx = 0;
|
1530 |
*edx = 0;
|
1531 |
} |
1532 |
break;
|
1533 |
case 0x80000000: |
1534 |
*eax = env->cpuid_xlevel; |
1535 |
*ebx = env->cpuid_vendor1; |
1536 |
*edx = env->cpuid_vendor2; |
1537 |
*ecx = env->cpuid_vendor3; |
1538 |
break;
|
1539 |
case 0x80000001: |
1540 |
*eax = env->cpuid_version; |
1541 |
*ebx = 0;
|
1542 |
*ecx = env->cpuid_ext3_features; |
1543 |
*edx = env->cpuid_ext2_features; |
1544 |
|
1545 |
/* The Linux kernel checks for the CMPLegacy bit and
|
1546 |
* discards multiple thread information if it is set.
|
1547 |
* So dont set it here for Intel to make Linux guests happy.
|
1548 |
*/
|
1549 |
if (env->nr_cores * env->nr_threads > 1) { |
1550 |
uint32_t tebx, tecx, tedx; |
1551 |
get_cpuid_vendor(env, &tebx, &tecx, &tedx); |
1552 |
if (tebx != CPUID_VENDOR_INTEL_1 ||
|
1553 |
tedx != CPUID_VENDOR_INTEL_2 || |
1554 |
tecx != CPUID_VENDOR_INTEL_3) { |
1555 |
*ecx |= 1 << 1; /* CmpLegacy bit */ |
1556 |
} |
1557 |
} |
1558 |
break;
|
1559 |
case 0x80000002: |
1560 |
case 0x80000003: |
1561 |
case 0x80000004: |
1562 |
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; |
1563 |
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; |
1564 |
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; |
1565 |
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; |
1566 |
break;
|
1567 |
case 0x80000005: |
1568 |
/* cache info (L1 cache) */
|
1569 |
*eax = 0x01ff01ff;
|
1570 |
*ebx = 0x01ff01ff;
|
1571 |
*ecx = 0x40020140;
|
1572 |
*edx = 0x40020140;
|
1573 |
break;
|
1574 |
case 0x80000006: |
1575 |
/* cache info (L2 cache) */
|
1576 |
*eax = 0;
|
1577 |
*ebx = 0x42004200;
|
1578 |
*ecx = 0x02008140;
|
1579 |
*edx = 0;
|
1580 |
break;
|
1581 |
case 0x80000008: |
1582 |
/* virtual & phys address size in low 2 bytes. */
|
1583 |
/* XXX: This value must match the one used in the MMU code. */
|
1584 |
if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
|
1585 |
/* 64 bit processor */
|
1586 |
/* XXX: The physical address space is limited to 42 bits in exec.c. */
|
1587 |
*eax = 0x00003028; /* 48 bits virtual, 40 bits physical */ |
1588 |
} else {
|
1589 |
if (env->cpuid_features & CPUID_PSE36)
|
1590 |
*eax = 0x00000024; /* 36 bits physical */ |
1591 |
else
|
1592 |
*eax = 0x00000020; /* 32 bits physical */ |
1593 |
} |
1594 |
*ebx = 0;
|
1595 |
*ecx = 0;
|
1596 |
*edx = 0;
|
1597 |
if (env->nr_cores * env->nr_threads > 1) { |
1598 |
*ecx |= (env->nr_cores * env->nr_threads) - 1;
|
1599 |
} |
1600 |
break;
|
1601 |
case 0x8000000A: |
1602 |
if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
|
1603 |
*eax = 0x00000001; /* SVM Revision */ |
1604 |
*ebx = 0x00000010; /* nr of ASIDs */ |
1605 |
*ecx = 0;
|
1606 |
*edx = env->cpuid_svm_features; /* optional features */
|
1607 |
} else {
|
1608 |
*eax = 0;
|
1609 |
*ebx = 0;
|
1610 |
*ecx = 0;
|
1611 |
*edx = 0;
|
1612 |
} |
1613 |
break;
|
1614 |
case 0xC0000000: |
1615 |
*eax = env->cpuid_xlevel2; |
1616 |
*ebx = 0;
|
1617 |
*ecx = 0;
|
1618 |
*edx = 0;
|
1619 |
break;
|
1620 |
case 0xC0000001: |
1621 |
/* Support for VIA CPU's CPUID instruction */
|
1622 |
*eax = env->cpuid_version; |
1623 |
*ebx = 0;
|
1624 |
*ecx = 0;
|
1625 |
*edx = env->cpuid_ext4_features; |
1626 |
break;
|
1627 |
case 0xC0000002: |
1628 |
case 0xC0000003: |
1629 |
case 0xC0000004: |
1630 |
/* Reserved for the future, and now filled with zero */
|
1631 |
*eax = 0;
|
1632 |
*ebx = 0;
|
1633 |
*ecx = 0;
|
1634 |
*edx = 0;
|
1635 |
break;
|
1636 |
default:
|
1637 |
/* reserved values: zero */
|
1638 |
*eax = 0;
|
1639 |
*ebx = 0;
|
1640 |
*ecx = 0;
|
1641 |
*edx = 0;
|
1642 |
break;
|
1643 |
} |
1644 |
} |
1645 |
|
1646 |
/* CPUClass::reset() */
|
1647 |
static void x86_cpu_reset(CPUState *s) |
1648 |
{ |
1649 |
X86CPU *cpu = X86_CPU(s); |
1650 |
X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); |
1651 |
CPUX86State *env = &cpu->env; |
1652 |
int i;
|
1653 |
|
1654 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
1655 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
1656 |
log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
1657 |
} |
1658 |
|
1659 |
xcc->parent_reset(s); |
1660 |
|
1661 |
|
1662 |
memset(env, 0, offsetof(CPUX86State, breakpoints));
|
1663 |
|
1664 |
tlb_flush(env, 1);
|
1665 |
|
1666 |
env->old_exception = -1;
|
1667 |
|
1668 |
/* init to reset state */
|
1669 |
|
1670 |
#ifdef CONFIG_SOFTMMU
|
1671 |
env->hflags |= HF_SOFTMMU_MASK; |
1672 |
#endif
|
1673 |
env->hflags2 |= HF2_GIF_MASK; |
1674 |
|
1675 |
cpu_x86_update_cr0(env, 0x60000010);
|
1676 |
env->a20_mask = ~0x0;
|
1677 |
env->smbase = 0x30000;
|
1678 |
|
1679 |
env->idt.limit = 0xffff;
|
1680 |
env->gdt.limit = 0xffff;
|
1681 |
env->ldt.limit = 0xffff;
|
1682 |
env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
|
1683 |
env->tr.limit = 0xffff;
|
1684 |
env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
|
1685 |
|
1686 |
cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, |
1687 |
DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | |
1688 |
DESC_R_MASK | DESC_A_MASK); |
1689 |
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, |
1690 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1691 |
DESC_A_MASK); |
1692 |
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, |
1693 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1694 |
DESC_A_MASK); |
1695 |
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, |
1696 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1697 |
DESC_A_MASK); |
1698 |
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, |
1699 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1700 |
DESC_A_MASK); |
1701 |
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, |
1702 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1703 |
DESC_A_MASK); |
1704 |
|
1705 |
env->eip = 0xfff0;
|
1706 |
env->regs[R_EDX] = env->cpuid_version; |
1707 |
|
1708 |
env->eflags = 0x2;
|
1709 |
|
1710 |
/* FPU init */
|
1711 |
for (i = 0; i < 8; i++) { |
1712 |
env->fptags[i] = 1;
|
1713 |
} |
1714 |
env->fpuc = 0x37f;
|
1715 |
|
1716 |
env->mxcsr = 0x1f80;
|
1717 |
|
1718 |
env->pat = 0x0007040600070406ULL;
|
1719 |
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; |
1720 |
|
1721 |
memset(env->dr, 0, sizeof(env->dr)); |
1722 |
env->dr[6] = DR6_FIXED_1;
|
1723 |
env->dr[7] = DR7_FIXED_1;
|
1724 |
cpu_breakpoint_remove_all(env, BP_CPU); |
1725 |
cpu_watchpoint_remove_all(env, BP_CPU); |
1726 |
|
1727 |
#if !defined(CONFIG_USER_ONLY)
|
1728 |
/* We hard-wire the BSP to the first CPU. */
|
1729 |
if (env->cpu_index == 0) { |
1730 |
apic_designate_bsp(env->apic_state); |
1731 |
} |
1732 |
|
1733 |
env->halted = !cpu_is_bsp(cpu); |
1734 |
#endif
|
1735 |
} |
1736 |
|
1737 |
#ifndef CONFIG_USER_ONLY
|
1738 |
bool cpu_is_bsp(X86CPU *cpu)
|
1739 |
{ |
1740 |
return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
|
1741 |
} |
1742 |
|
1743 |
/* TODO: remove me, when reset over QOM tree is implemented */
|
1744 |
static void x86_cpu_machine_reset_cb(void *opaque) |
1745 |
{ |
1746 |
X86CPU *cpu = opaque; |
1747 |
cpu_reset(CPU(cpu)); |
1748 |
} |
1749 |
#endif
|
1750 |
|
1751 |
static void mce_init(X86CPU *cpu) |
1752 |
{ |
1753 |
CPUX86State *cenv = &cpu->env; |
1754 |
unsigned int bank; |
1755 |
|
1756 |
if (((cenv->cpuid_version >> 8) & 0xf) >= 6 |
1757 |
&& (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) == |
1758 |
(CPUID_MCE | CPUID_MCA)) { |
1759 |
cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF; |
1760 |
cenv->mcg_ctl = ~(uint64_t)0;
|
1761 |
for (bank = 0; bank < MCE_BANKS_DEF; bank++) { |
1762 |
cenv->mce_banks[bank * 4] = ~(uint64_t)0; |
1763 |
} |
1764 |
} |
1765 |
} |
1766 |
|
1767 |
void x86_cpu_realize(Object *obj, Error **errp)
|
1768 |
{ |
1769 |
X86CPU *cpu = X86_CPU(obj); |
1770 |
|
1771 |
#ifndef CONFIG_USER_ONLY
|
1772 |
qemu_register_reset(x86_cpu_machine_reset_cb, cpu); |
1773 |
#endif
|
1774 |
|
1775 |
mce_init(cpu); |
1776 |
qemu_init_vcpu(&cpu->env); |
1777 |
cpu_reset(CPU(cpu)); |
1778 |
} |
1779 |
|
1780 |
static void x86_cpu_initfn(Object *obj) |
1781 |
{ |
1782 |
X86CPU *cpu = X86_CPU(obj); |
1783 |
CPUX86State *env = &cpu->env; |
1784 |
static int inited; |
1785 |
|
1786 |
cpu_exec_init(env); |
1787 |
|
1788 |
object_property_add(obj, "family", "int", |
1789 |
x86_cpuid_version_get_family, |
1790 |
x86_cpuid_version_set_family, NULL, NULL, NULL); |
1791 |
object_property_add(obj, "model", "int", |
1792 |
x86_cpuid_version_get_model, |
1793 |
x86_cpuid_version_set_model, NULL, NULL, NULL); |
1794 |
object_property_add(obj, "stepping", "int", |
1795 |
x86_cpuid_version_get_stepping, |
1796 |
x86_cpuid_version_set_stepping, NULL, NULL, NULL); |
1797 |
object_property_add(obj, "level", "int", |
1798 |
x86_cpuid_get_level, |
1799 |
x86_cpuid_set_level, NULL, NULL, NULL); |
1800 |
object_property_add(obj, "xlevel", "int", |
1801 |
x86_cpuid_get_xlevel, |
1802 |
x86_cpuid_set_xlevel, NULL, NULL, NULL); |
1803 |
object_property_add_str(obj, "vendor",
|
1804 |
x86_cpuid_get_vendor, |
1805 |
x86_cpuid_set_vendor, NULL);
|
1806 |
object_property_add_str(obj, "model-id",
|
1807 |
x86_cpuid_get_model_id, |
1808 |
x86_cpuid_set_model_id, NULL);
|
1809 |
object_property_add(obj, "tsc-frequency", "int", |
1810 |
x86_cpuid_get_tsc_freq, |
1811 |
x86_cpuid_set_tsc_freq, NULL, NULL, NULL); |
1812 |
|
1813 |
env->cpuid_apic_id = env->cpu_index; |
1814 |
|
1815 |
/* init various static tables used in TCG mode */
|
1816 |
if (tcg_enabled() && !inited) {
|
1817 |
inited = 1;
|
1818 |
optimize_flags_init(); |
1819 |
#ifndef CONFIG_USER_ONLY
|
1820 |
cpu_set_debug_excp_handler(breakpoint_handler); |
1821 |
#endif
|
1822 |
} |
1823 |
} |
1824 |
|
1825 |
static void x86_cpu_common_class_init(ObjectClass *oc, void *data) |
1826 |
{ |
1827 |
X86CPUClass *xcc = X86_CPU_CLASS(oc); |
1828 |
CPUClass *cc = CPU_CLASS(oc); |
1829 |
|
1830 |
xcc->parent_reset = cc->reset; |
1831 |
cc->reset = x86_cpu_reset; |
1832 |
} |
1833 |
|
1834 |
static const TypeInfo x86_cpu_type_info = { |
1835 |
.name = TYPE_X86_CPU, |
1836 |
.parent = TYPE_CPU, |
1837 |
.instance_size = sizeof(X86CPU),
|
1838 |
.instance_init = x86_cpu_initfn, |
1839 |
.abstract = false,
|
1840 |
.class_size = sizeof(X86CPUClass),
|
1841 |
.class_init = x86_cpu_common_class_init, |
1842 |
}; |
1843 |
|
1844 |
static void x86_cpu_register_types(void) |
1845 |
{ |
1846 |
type_register_static(&x86_cpu_type_info); |
1847 |
} |
1848 |
|
1849 |
type_init(x86_cpu_register_types) |