Revision 2f9859fb hw/ppc405_uc.c
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 2111 | 2111 |
{
|
| 2112 | 2112 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
| 2113 | 2113 |
qemu_irq dma_irqs[4]; |
| 2114 |
PowerPCCPU *cpu; |
|
| 2114 | 2115 |
CPUPPCState *env; |
| 2115 | 2116 |
qemu_irq *pic, *irqs; |
| 2116 | 2117 |
|
| 2117 | 2118 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 2118 |
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
|
| 2119 |
cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
|
| 2119 | 2120 |
&clk_setup[PPC405CR_TMR_CLK], sysclk); |
| 2121 |
env = &cpu->env; |
|
| 2120 | 2122 |
/* Memory mapped devices registers */ |
| 2121 | 2123 |
/* PLB arbitrer */ |
| 2122 | 2124 |
ppc4xx_plb_init(env); |
| ... | ... | |
| 2460 | 2462 |
{
|
| 2461 | 2463 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
| 2462 | 2464 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
| 2465 |
PowerPCCPU *cpu; |
|
| 2463 | 2466 |
CPUPPCState *env; |
| 2464 | 2467 |
qemu_irq *pic, *irqs; |
| 2465 | 2468 |
|
| 2466 | 2469 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 2467 | 2470 |
/* init CPUs */ |
| 2468 |
env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
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|
| 2471 |
cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
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|
| 2469 | 2472 |
&tlb_clk_setup, sysclk); |
| 2473 |
env = &cpu->env; |
|
| 2470 | 2474 |
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
| 2471 | 2475 |
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
| 2472 | 2476 |
/* Internal devices init */ |
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