root / tcg / sparc / tcg-target.c @ 301901b5
History | View | Annotate | Download (38.5 kB)
1 | 8289b279 | blueswir1 | /*
|
---|---|---|---|
2 | 8289b279 | blueswir1 | * Tiny Code Generator for QEMU
|
3 | 8289b279 | blueswir1 | *
|
4 | 8289b279 | blueswir1 | * Copyright (c) 2008 Fabrice Bellard
|
5 | 8289b279 | blueswir1 | *
|
6 | 8289b279 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 8289b279 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
|
8 | 8289b279 | blueswir1 | * in the Software without restriction, including without limitation the rights
|
9 | 8289b279 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 8289b279 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
|
11 | 8289b279 | blueswir1 | * furnished to do so, subject to the following conditions:
|
12 | 8289b279 | blueswir1 | *
|
13 | 8289b279 | blueswir1 | * The above copyright notice and this permission notice shall be included in
|
14 | 8289b279 | blueswir1 | * all copies or substantial portions of the Software.
|
15 | 8289b279 | blueswir1 | *
|
16 | 8289b279 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 8289b279 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 8289b279 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 8289b279 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 8289b279 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 8289b279 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 8289b279 | blueswir1 | * THE SOFTWARE.
|
23 | 8289b279 | blueswir1 | */
|
24 | 8289b279 | blueswir1 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
|
26 | 8289b279 | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | 8289b279 | blueswir1 | "%g0",
|
28 | 8289b279 | blueswir1 | "%g1",
|
29 | 8289b279 | blueswir1 | "%g2",
|
30 | 8289b279 | blueswir1 | "%g3",
|
31 | 8289b279 | blueswir1 | "%g4",
|
32 | 8289b279 | blueswir1 | "%g5",
|
33 | 8289b279 | blueswir1 | "%g6",
|
34 | 8289b279 | blueswir1 | "%g7",
|
35 | 8289b279 | blueswir1 | "%o0",
|
36 | 8289b279 | blueswir1 | "%o1",
|
37 | 8289b279 | blueswir1 | "%o2",
|
38 | 8289b279 | blueswir1 | "%o3",
|
39 | 8289b279 | blueswir1 | "%o4",
|
40 | 8289b279 | blueswir1 | "%o5",
|
41 | 8289b279 | blueswir1 | "%o6",
|
42 | 8289b279 | blueswir1 | "%o7",
|
43 | 8289b279 | blueswir1 | "%l0",
|
44 | 8289b279 | blueswir1 | "%l1",
|
45 | 8289b279 | blueswir1 | "%l2",
|
46 | 8289b279 | blueswir1 | "%l3",
|
47 | 8289b279 | blueswir1 | "%l4",
|
48 | 8289b279 | blueswir1 | "%l5",
|
49 | 8289b279 | blueswir1 | "%l6",
|
50 | 8289b279 | blueswir1 | "%l7",
|
51 | 8289b279 | blueswir1 | "%i0",
|
52 | 8289b279 | blueswir1 | "%i1",
|
53 | 8289b279 | blueswir1 | "%i2",
|
54 | 8289b279 | blueswir1 | "%i3",
|
55 | 8289b279 | blueswir1 | "%i4",
|
56 | 8289b279 | blueswir1 | "%i5",
|
57 | 8289b279 | blueswir1 | "%i6",
|
58 | 8289b279 | blueswir1 | "%i7",
|
59 | 8289b279 | blueswir1 | }; |
60 | d4a9eb1f | blueswir1 | #endif
|
61 | 8289b279 | blueswir1 | |
62 | 0954d0d9 | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
63 | 8289b279 | blueswir1 | TCG_REG_L0, |
64 | 8289b279 | blueswir1 | TCG_REG_L1, |
65 | 8289b279 | blueswir1 | TCG_REG_L2, |
66 | 8289b279 | blueswir1 | TCG_REG_L3, |
67 | 8289b279 | blueswir1 | TCG_REG_L4, |
68 | 8289b279 | blueswir1 | TCG_REG_L5, |
69 | 8289b279 | blueswir1 | TCG_REG_L6, |
70 | 8289b279 | blueswir1 | TCG_REG_L7, |
71 | 8289b279 | blueswir1 | TCG_REG_I0, |
72 | 8289b279 | blueswir1 | TCG_REG_I1, |
73 | 8289b279 | blueswir1 | TCG_REG_I2, |
74 | 8289b279 | blueswir1 | TCG_REG_I3, |
75 | 8289b279 | blueswir1 | TCG_REG_I4, |
76 | 8289b279 | blueswir1 | }; |
77 | 8289b279 | blueswir1 | |
78 | 8289b279 | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
79 | 8289b279 | blueswir1 | TCG_REG_O0, |
80 | 8289b279 | blueswir1 | TCG_REG_O1, |
81 | 8289b279 | blueswir1 | TCG_REG_O2, |
82 | 8289b279 | blueswir1 | TCG_REG_O3, |
83 | 8289b279 | blueswir1 | TCG_REG_O4, |
84 | 8289b279 | blueswir1 | TCG_REG_O5, |
85 | 8289b279 | blueswir1 | }; |
86 | 8289b279 | blueswir1 | |
87 | 8289b279 | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
88 | 8289b279 | blueswir1 | TCG_REG_O0, |
89 | 8289b279 | blueswir1 | TCG_REG_O1, |
90 | 8289b279 | blueswir1 | }; |
91 | 8289b279 | blueswir1 | |
92 | 57e49b40 | blueswir1 | static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
93 | f5ef6aac | blueswir1 | { |
94 | 57e49b40 | blueswir1 | return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
95 | 57e49b40 | blueswir1 | >> (sizeof(tcg_target_long) * 8 - bits)) == val; |
96 | 57e49b40 | blueswir1 | } |
97 | 57e49b40 | blueswir1 | |
98 | 57e49b40 | blueswir1 | static inline int check_fit_i32(uint32_t val, unsigned int bits) |
99 | 57e49b40 | blueswir1 | { |
100 | 57e49b40 | blueswir1 | return ((val << (32 - bits)) >> (32 - bits)) == val; |
101 | f5ef6aac | blueswir1 | } |
102 | f5ef6aac | blueswir1 | |
103 | 8289b279 | blueswir1 | static void patch_reloc(uint8_t *code_ptr, int type, |
104 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
105 | 8289b279 | blueswir1 | { |
106 | f54b3f92 | aurel32 | value += addend; |
107 | 8289b279 | blueswir1 | switch (type) {
|
108 | 8289b279 | blueswir1 | case R_SPARC_32:
|
109 | 8289b279 | blueswir1 | if (value != (uint32_t)value)
|
110 | 8289b279 | blueswir1 | tcg_abort(); |
111 | 8289b279 | blueswir1 | *(uint32_t *)code_ptr = value; |
112 | 8289b279 | blueswir1 | break;
|
113 | f5ef6aac | blueswir1 | case R_SPARC_WDISP22:
|
114 | f5ef6aac | blueswir1 | value -= (long)code_ptr;
|
115 | f5ef6aac | blueswir1 | value >>= 2;
|
116 | 57e49b40 | blueswir1 | if (!check_fit_tl(value, 22)) |
117 | f5ef6aac | blueswir1 | tcg_abort(); |
118 | f5ef6aac | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
|
119 | f5ef6aac | blueswir1 | break;
|
120 | 1da92db2 | blueswir1 | case R_SPARC_WDISP19:
|
121 | 1da92db2 | blueswir1 | value -= (long)code_ptr;
|
122 | 1da92db2 | blueswir1 | value >>= 2;
|
123 | 1da92db2 | blueswir1 | if (!check_fit_tl(value, 19)) |
124 | 1da92db2 | blueswir1 | tcg_abort(); |
125 | 1da92db2 | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
|
126 | 1da92db2 | blueswir1 | break;
|
127 | 8289b279 | blueswir1 | default:
|
128 | 8289b279 | blueswir1 | tcg_abort(); |
129 | 8289b279 | blueswir1 | } |
130 | 8289b279 | blueswir1 | } |
131 | 8289b279 | blueswir1 | |
132 | 8289b279 | blueswir1 | /* maximum number of register used for input function arguments */
|
133 | 8289b279 | blueswir1 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
134 | 8289b279 | blueswir1 | { |
135 | 8289b279 | blueswir1 | return 6; |
136 | 8289b279 | blueswir1 | } |
137 | 8289b279 | blueswir1 | |
138 | 8289b279 | blueswir1 | /* parse target specific constraints */
|
139 | 8289b279 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
140 | 8289b279 | blueswir1 | { |
141 | 8289b279 | blueswir1 | const char *ct_str; |
142 | 8289b279 | blueswir1 | |
143 | 8289b279 | blueswir1 | ct_str = *pct_str; |
144 | 8289b279 | blueswir1 | switch (ct_str[0]) { |
145 | 8289b279 | blueswir1 | case 'r': |
146 | 8289b279 | blueswir1 | case 'L': /* qemu_ld/st constraint */ |
147 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_REG; |
148 | 8289b279 | blueswir1 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
149 | 53c37487 | blueswir1 | // Helper args
|
150 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
151 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); |
152 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); |
153 | 8289b279 | blueswir1 | break;
|
154 | 8289b279 | blueswir1 | case 'I': |
155 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S11; |
156 | 8289b279 | blueswir1 | break;
|
157 | 8289b279 | blueswir1 | case 'J': |
158 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S13; |
159 | 8289b279 | blueswir1 | break;
|
160 | 8289b279 | blueswir1 | default:
|
161 | 8289b279 | blueswir1 | return -1; |
162 | 8289b279 | blueswir1 | } |
163 | 8289b279 | blueswir1 | ct_str++; |
164 | 8289b279 | blueswir1 | *pct_str = ct_str; |
165 | 8289b279 | blueswir1 | return 0; |
166 | 8289b279 | blueswir1 | } |
167 | 8289b279 | blueswir1 | |
168 | 8289b279 | blueswir1 | /* test if a constant matches the constraint */
|
169 | 8289b279 | blueswir1 | static inline int tcg_target_const_match(tcg_target_long val, |
170 | 8289b279 | blueswir1 | const TCGArgConstraint *arg_ct)
|
171 | 8289b279 | blueswir1 | { |
172 | 8289b279 | blueswir1 | int ct;
|
173 | 8289b279 | blueswir1 | |
174 | 8289b279 | blueswir1 | ct = arg_ct->ct; |
175 | 8289b279 | blueswir1 | if (ct & TCG_CT_CONST)
|
176 | 8289b279 | blueswir1 | return 1; |
177 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) |
178 | 8289b279 | blueswir1 | return 1; |
179 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) |
180 | 8289b279 | blueswir1 | return 1; |
181 | 8289b279 | blueswir1 | else
|
182 | 8289b279 | blueswir1 | return 0; |
183 | 8289b279 | blueswir1 | } |
184 | 8289b279 | blueswir1 | |
185 | 8289b279 | blueswir1 | #define INSN_OP(x) ((x) << 30) |
186 | 8289b279 | blueswir1 | #define INSN_OP2(x) ((x) << 22) |
187 | 8289b279 | blueswir1 | #define INSN_OP3(x) ((x) << 19) |
188 | 8289b279 | blueswir1 | #define INSN_OPF(x) ((x) << 5) |
189 | 8289b279 | blueswir1 | #define INSN_RD(x) ((x) << 25) |
190 | 8289b279 | blueswir1 | #define INSN_RS1(x) ((x) << 14) |
191 | 8289b279 | blueswir1 | #define INSN_RS2(x) (x)
|
192 | 8384dd67 | blueswir1 | #define INSN_ASI(x) ((x) << 5) |
193 | 8289b279 | blueswir1 | |
194 | 8289b279 | blueswir1 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
195 | 1da92db2 | blueswir1 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
196 | b3db8758 | blueswir1 | #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
197 | 8289b279 | blueswir1 | |
198 | b3db8758 | blueswir1 | #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
199 | cf7c2ca5 | blueswir1 | #define COND_N 0x0 |
200 | cf7c2ca5 | blueswir1 | #define COND_E 0x1 |
201 | cf7c2ca5 | blueswir1 | #define COND_LE 0x2 |
202 | cf7c2ca5 | blueswir1 | #define COND_L 0x3 |
203 | cf7c2ca5 | blueswir1 | #define COND_LEU 0x4 |
204 | cf7c2ca5 | blueswir1 | #define COND_CS 0x5 |
205 | cf7c2ca5 | blueswir1 | #define COND_NEG 0x6 |
206 | cf7c2ca5 | blueswir1 | #define COND_VS 0x7 |
207 | b3db8758 | blueswir1 | #define COND_A 0x8 |
208 | cf7c2ca5 | blueswir1 | #define COND_NE 0x9 |
209 | cf7c2ca5 | blueswir1 | #define COND_G 0xa |
210 | cf7c2ca5 | blueswir1 | #define COND_GE 0xb |
211 | cf7c2ca5 | blueswir1 | #define COND_GU 0xc |
212 | cf7c2ca5 | blueswir1 | #define COND_CC 0xd |
213 | cf7c2ca5 | blueswir1 | #define COND_POS 0xe |
214 | cf7c2ca5 | blueswir1 | #define COND_VC 0xf |
215 | b3db8758 | blueswir1 | #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
216 | 8289b279 | blueswir1 | |
217 | 8289b279 | blueswir1 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
218 | 8289b279 | blueswir1 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
219 | 8289b279 | blueswir1 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
220 | 9a7f3228 | blueswir1 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
221 | 8289b279 | blueswir1 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
222 | f5ef6aac | blueswir1 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
223 | f5ef6aac | blueswir1 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
224 | 8289b279 | blueswir1 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
225 | 8289b279 | blueswir1 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
226 | 8289b279 | blueswir1 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
227 | 8289b279 | blueswir1 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
228 | 8289b279 | blueswir1 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
229 | 8289b279 | blueswir1 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
230 | 8289b279 | blueswir1 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
231 | 8289b279 | blueswir1 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
232 | 8289b279 | blueswir1 | |
233 | 8289b279 | blueswir1 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
234 | 8289b279 | blueswir1 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
235 | 8289b279 | blueswir1 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
236 | 8289b279 | blueswir1 | |
237 | 8289b279 | blueswir1 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
238 | 8289b279 | blueswir1 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
239 | 8289b279 | blueswir1 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
240 | 8289b279 | blueswir1 | |
241 | 8289b279 | blueswir1 | #define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
242 | 8289b279 | blueswir1 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
243 | 8289b279 | blueswir1 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
244 | 8289b279 | blueswir1 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
245 | 8289b279 | blueswir1 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
246 | 8289b279 | blueswir1 | #define CALL INSN_OP(1) |
247 | 8289b279 | blueswir1 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
248 | 8289b279 | blueswir1 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
249 | 8289b279 | blueswir1 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
250 | 8289b279 | blueswir1 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
251 | 8289b279 | blueswir1 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
252 | 8289b279 | blueswir1 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
253 | 8289b279 | blueswir1 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
254 | 8289b279 | blueswir1 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
255 | 8289b279 | blueswir1 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
256 | 8289b279 | blueswir1 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
257 | 8289b279 | blueswir1 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
258 | 8384dd67 | blueswir1 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
259 | 8384dd67 | blueswir1 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
260 | 8384dd67 | blueswir1 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
261 | 8384dd67 | blueswir1 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
262 | 8384dd67 | blueswir1 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
263 | 8384dd67 | blueswir1 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
264 | 8384dd67 | blueswir1 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
265 | 8384dd67 | blueswir1 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
266 | 8384dd67 | blueswir1 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
267 | 8384dd67 | blueswir1 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
268 | 8384dd67 | blueswir1 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
269 | 8384dd67 | blueswir1 | |
270 | 8384dd67 | blueswir1 | #ifndef ASI_PRIMARY_LITTLE
|
271 | 8384dd67 | blueswir1 | #define ASI_PRIMARY_LITTLE 0x88 |
272 | 8384dd67 | blueswir1 | #endif
|
273 | 8289b279 | blueswir1 | |
274 | 26cc915c | blueswir1 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
275 | 26cc915c | blueswir1 | int op)
|
276 | 26cc915c | blueswir1 | { |
277 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
278 | 26cc915c | blueswir1 | INSN_RS2(rs2)); |
279 | 26cc915c | blueswir1 | } |
280 | 26cc915c | blueswir1 | |
281 | 6f41b777 | blueswir1 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, |
282 | 6f41b777 | blueswir1 | uint32_t offset, int op)
|
283 | 26cc915c | blueswir1 | { |
284 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
285 | 26cc915c | blueswir1 | INSN_IMM13(offset)); |
286 | 26cc915c | blueswir1 | } |
287 | 26cc915c | blueswir1 | |
288 | 8289b279 | blueswir1 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
289 | 8289b279 | blueswir1 | { |
290 | 26cc915c | blueswir1 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
291 | 26cc915c | blueswir1 | } |
292 | 26cc915c | blueswir1 | |
293 | 26cc915c | blueswir1 | static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
294 | 26cc915c | blueswir1 | { |
295 | 26cc915c | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
296 | 8289b279 | blueswir1 | } |
297 | 8289b279 | blueswir1 | |
298 | b101234a | blueswir1 | static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
299 | b101234a | blueswir1 | { |
300 | b101234a | blueswir1 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
301 | b101234a | blueswir1 | } |
302 | b101234a | blueswir1 | |
303 | b101234a | blueswir1 | static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) |
304 | 8289b279 | blueswir1 | { |
305 | 6f41b777 | blueswir1 | if (check_fit_tl(arg, 12)) |
306 | b101234a | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
307 | 8289b279 | blueswir1 | else {
|
308 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
309 | 8289b279 | blueswir1 | if (arg & 0x3ff) |
310 | b101234a | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
311 | 8289b279 | blueswir1 | } |
312 | 8289b279 | blueswir1 | } |
313 | 8289b279 | blueswir1 | |
314 | b101234a | blueswir1 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
315 | b101234a | blueswir1 | int ret, tcg_target_long arg)
|
316 | b101234a | blueswir1 | { |
317 | b101234a | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
318 | b101234a | blueswir1 | if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) { |
319 | d795eb86 | blueswir1 | tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32);
|
320 | d795eb86 | blueswir1 | tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
|
321 | b101234a | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
322 | d795eb86 | blueswir1 | tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR); |
323 | 6f41b777 | blueswir1 | } else if (check_fit_tl(arg, 12)) |
324 | 6f41b777 | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
325 | 6f41b777 | blueswir1 | else {
|
326 | 6f41b777 | blueswir1 | tcg_out_sethi(s, ret, arg); |
327 | 6f41b777 | blueswir1 | if (arg & 0x3ff) |
328 | 6f41b777 | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
329 | 6f41b777 | blueswir1 | } |
330 | 6f41b777 | blueswir1 | #else
|
331 | 6f41b777 | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
332 | b101234a | blueswir1 | #endif
|
333 | b101234a | blueswir1 | } |
334 | b101234a | blueswir1 | |
335 | 8289b279 | blueswir1 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
336 | 8289b279 | blueswir1 | tcg_target_long arg) |
337 | 8289b279 | blueswir1 | { |
338 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
339 | 8289b279 | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
340 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
341 | 8289b279 | blueswir1 | } |
342 | 8289b279 | blueswir1 | |
343 | b3db8758 | blueswir1 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
344 | b3db8758 | blueswir1 | tcg_target_long arg) |
345 | b3db8758 | blueswir1 | { |
346 | b101234a | blueswir1 | if (!check_fit_tl(arg, 10)) |
347 | b101234a | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
|
348 | b3db8758 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
349 | b3db8758 | blueswir1 | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
350 | b3db8758 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
351 | b3db8758 | blueswir1 | #else
|
352 | b101234a | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
353 | b101234a | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
354 | b3db8758 | blueswir1 | #endif
|
355 | b3db8758 | blueswir1 | } |
356 | b3db8758 | blueswir1 | |
357 | 8289b279 | blueswir1 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
358 | 8289b279 | blueswir1 | { |
359 | 57e49b40 | blueswir1 | if (check_fit_tl(offset, 13)) |
360 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
361 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
362 | cf7c2ca5 | blueswir1 | else {
|
363 | cf7c2ca5 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
364 | cf7c2ca5 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
365 | cf7c2ca5 | blueswir1 | INSN_RS2(addr)); |
366 | cf7c2ca5 | blueswir1 | } |
367 | 8289b279 | blueswir1 | } |
368 | 8289b279 | blueswir1 | |
369 | 8384dd67 | blueswir1 | static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr, |
370 | 8384dd67 | blueswir1 | int offset, int op, int asi) |
371 | 8384dd67 | blueswir1 | { |
372 | 8384dd67 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
373 | 8384dd67 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
374 | 8384dd67 | blueswir1 | INSN_ASI(asi) | INSN_RS2(addr)); |
375 | 8384dd67 | blueswir1 | } |
376 | 8384dd67 | blueswir1 | |
377 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
378 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
379 | 8289b279 | blueswir1 | { |
380 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
381 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDUW); |
382 | 7d551702 | blueswir1 | else
|
383 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDX); |
384 | 8289b279 | blueswir1 | } |
385 | 8289b279 | blueswir1 | |
386 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
387 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
388 | 8289b279 | blueswir1 | { |
389 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
390 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STW); |
391 | 7d551702 | blueswir1 | else
|
392 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STX); |
393 | 8289b279 | blueswir1 | } |
394 | 8289b279 | blueswir1 | |
395 | 8289b279 | blueswir1 | static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
396 | 8289b279 | blueswir1 | { |
397 | 8289b279 | blueswir1 | if (val == 0 || val == -1) |
398 | 8289b279 | blueswir1 | tcg_out32(s, WRY | INSN_IMM13(val)); |
399 | 8289b279 | blueswir1 | else
|
400 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
401 | 8289b279 | blueswir1 | } |
402 | 8289b279 | blueswir1 | |
403 | 8289b279 | blueswir1 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
404 | 8289b279 | blueswir1 | { |
405 | 8289b279 | blueswir1 | if (val != 0) { |
406 | 57e49b40 | blueswir1 | if (check_fit_tl(val, 13)) |
407 | 8289b279 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
408 | f5ef6aac | blueswir1 | else {
|
409 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val); |
410 | f5ef6aac | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD); |
411 | f5ef6aac | blueswir1 | } |
412 | 8289b279 | blueswir1 | } |
413 | 8289b279 | blueswir1 | } |
414 | 8289b279 | blueswir1 | |
415 | 53c37487 | blueswir1 | static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val) |
416 | 53c37487 | blueswir1 | { |
417 | 53c37487 | blueswir1 | if (val != 0) { |
418 | 53c37487 | blueswir1 | if (check_fit_tl(val, 13)) |
419 | 53c37487 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_AND); |
420 | 53c37487 | blueswir1 | else {
|
421 | 53c37487 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val); |
422 | 53c37487 | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND); |
423 | 53c37487 | blueswir1 | } |
424 | 53c37487 | blueswir1 | } |
425 | 53c37487 | blueswir1 | } |
426 | 53c37487 | blueswir1 | |
427 | 8289b279 | blueswir1 | static inline void tcg_out_nop(TCGContext *s) |
428 | 8289b279 | blueswir1 | { |
429 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_G0, 0);
|
430 | 8289b279 | blueswir1 | } |
431 | 8289b279 | blueswir1 | |
432 | 1da92db2 | blueswir1 | static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index) |
433 | cf7c2ca5 | blueswir1 | { |
434 | cf7c2ca5 | blueswir1 | int32_t val; |
435 | cf7c2ca5 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
436 | cf7c2ca5 | blueswir1 | |
437 | cf7c2ca5 | blueswir1 | if (l->has_value) {
|
438 | cf7c2ca5 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
439 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) |
440 | cf7c2ca5 | blueswir1 | | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); |
441 | f5ef6aac | blueswir1 | } else {
|
442 | f5ef6aac | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
|
443 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0)); |
444 | f5ef6aac | blueswir1 | } |
445 | cf7c2ca5 | blueswir1 | } |
446 | cf7c2ca5 | blueswir1 | |
447 | 1da92db2 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
448 | 1da92db2 | blueswir1 | static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index) |
449 | 1da92db2 | blueswir1 | { |
450 | 1da92db2 | blueswir1 | int32_t val; |
451 | 1da92db2 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
452 | 1da92db2 | blueswir1 | |
453 | 1da92db2 | blueswir1 | if (l->has_value) {
|
454 | 1da92db2 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
455 | 1da92db2 | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | |
456 | 1da92db2 | blueswir1 | (0x5 << 19) | |
457 | 1da92db2 | blueswir1 | INSN_OFF19(l->u.value - (unsigned long)s->code_ptr))); |
458 | 1da92db2 | blueswir1 | } else {
|
459 | 1da92db2 | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
|
460 | 1da92db2 | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | |
461 | 1da92db2 | blueswir1 | (0x5 << 19) | 0)); |
462 | 1da92db2 | blueswir1 | } |
463 | 1da92db2 | blueswir1 | } |
464 | 1da92db2 | blueswir1 | #endif
|
465 | 1da92db2 | blueswir1 | |
466 | cf7c2ca5 | blueswir1 | static const uint8_t tcg_cond_to_bcond[10] = { |
467 | cf7c2ca5 | blueswir1 | [TCG_COND_EQ] = COND_E, |
468 | cf7c2ca5 | blueswir1 | [TCG_COND_NE] = COND_NE, |
469 | cf7c2ca5 | blueswir1 | [TCG_COND_LT] = COND_L, |
470 | cf7c2ca5 | blueswir1 | [TCG_COND_GE] = COND_GE, |
471 | cf7c2ca5 | blueswir1 | [TCG_COND_LE] = COND_LE, |
472 | cf7c2ca5 | blueswir1 | [TCG_COND_GT] = COND_G, |
473 | cf7c2ca5 | blueswir1 | [TCG_COND_LTU] = COND_CS, |
474 | cf7c2ca5 | blueswir1 | [TCG_COND_GEU] = COND_CC, |
475 | cf7c2ca5 | blueswir1 | [TCG_COND_LEU] = COND_LEU, |
476 | cf7c2ca5 | blueswir1 | [TCG_COND_GTU] = COND_GU, |
477 | cf7c2ca5 | blueswir1 | }; |
478 | cf7c2ca5 | blueswir1 | |
479 | 1da92db2 | blueswir1 | static void tcg_out_brcond_i32(TCGContext *s, int cond, |
480 | 1da92db2 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
481 | 1da92db2 | blueswir1 | int label_index)
|
482 | cf7c2ca5 | blueswir1 | { |
483 | cf7c2ca5 | blueswir1 | if (const_arg2 && arg2 == 0) |
484 | 26cc915c | blueswir1 | /* orcc %g0, r, %g0 */
|
485 | 9a7f3228 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC); |
486 | cf7c2ca5 | blueswir1 | else
|
487 | cf7c2ca5 | blueswir1 | /* subcc r1, r2, %g0 */
|
488 | cf7c2ca5 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC); |
489 | 1da92db2 | blueswir1 | tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index); |
490 | cf7c2ca5 | blueswir1 | tcg_out_nop(s); |
491 | cf7c2ca5 | blueswir1 | } |
492 | cf7c2ca5 | blueswir1 | |
493 | 1da92db2 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
494 | 1da92db2 | blueswir1 | static void tcg_out_brcond_i64(TCGContext *s, int cond, |
495 | 1da92db2 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
496 | 1da92db2 | blueswir1 | int label_index)
|
497 | 1da92db2 | blueswir1 | { |
498 | 1da92db2 | blueswir1 | if (const_arg2 && arg2 == 0) |
499 | 1da92db2 | blueswir1 | /* orcc %g0, r, %g0 */
|
500 | 1da92db2 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC); |
501 | 1da92db2 | blueswir1 | else
|
502 | 1da92db2 | blueswir1 | /* subcc r1, r2, %g0 */
|
503 | 1da92db2 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC); |
504 | 1da92db2 | blueswir1 | tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index); |
505 | 1da92db2 | blueswir1 | tcg_out_nop(s); |
506 | 1da92db2 | blueswir1 | } |
507 | 1da92db2 | blueswir1 | #endif
|
508 | 1da92db2 | blueswir1 | |
509 | 7d551702 | blueswir1 | /* Generate global QEMU prologue and epilogue code */
|
510 | 7d551702 | blueswir1 | void tcg_target_qemu_prologue(TCGContext *s)
|
511 | b3db8758 | blueswir1 | { |
512 | b3db8758 | blueswir1 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
513 | b3db8758 | blueswir1 | INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
514 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | |
515 | 7d551702 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
516 | 7d551702 | blueswir1 | tcg_out_nop(s); |
517 | b3db8758 | blueswir1 | } |
518 | b3db8758 | blueswir1 | |
519 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
520 | f5ef6aac | blueswir1 | |
521 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
522 | f5ef6aac | blueswir1 | |
523 | 9a7f3228 | blueswir1 | static const void * const qemu_ld_helpers[4] = { |
524 | f5ef6aac | blueswir1 | __ldb_mmu, |
525 | f5ef6aac | blueswir1 | __ldw_mmu, |
526 | f5ef6aac | blueswir1 | __ldl_mmu, |
527 | f5ef6aac | blueswir1 | __ldq_mmu, |
528 | f5ef6aac | blueswir1 | }; |
529 | f5ef6aac | blueswir1 | |
530 | 9a7f3228 | blueswir1 | static const void * const qemu_st_helpers[4] = { |
531 | f5ef6aac | blueswir1 | __stb_mmu, |
532 | f5ef6aac | blueswir1 | __stw_mmu, |
533 | f5ef6aac | blueswir1 | __stl_mmu, |
534 | f5ef6aac | blueswir1 | __stq_mmu, |
535 | f5ef6aac | blueswir1 | }; |
536 | f5ef6aac | blueswir1 | #endif
|
537 | f5ef6aac | blueswir1 | |
538 | bffe1431 | blueswir1 | #if TARGET_LONG_BITS == 32 |
539 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDUW
|
540 | bffe1431 | blueswir1 | #else
|
541 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDX
|
542 | bffe1431 | blueswir1 | #endif
|
543 | bffe1431 | blueswir1 | |
544 | 9d0efc88 | blueswir1 | #if TARGET_PHYS_ADDR_BITS == 32 |
545 | 9d0efc88 | blueswir1 | #define TARGET_ADDEND_LD_OP LDUW
|
546 | 9d0efc88 | blueswir1 | #else
|
547 | 9d0efc88 | blueswir1 | #define TARGET_ADDEND_LD_OP LDX
|
548 | 9d0efc88 | blueswir1 | #endif
|
549 | 9d0efc88 | blueswir1 | |
550 | bffe1431 | blueswir1 | #ifdef __arch64__
|
551 | bffe1431 | blueswir1 | #define HOST_LD_OP LDX
|
552 | bffe1431 | blueswir1 | #define HOST_ST_OP STX
|
553 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLLX
|
554 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRAX
|
555 | bffe1431 | blueswir1 | #else
|
556 | bffe1431 | blueswir1 | #define HOST_LD_OP LDUW
|
557 | bffe1431 | blueswir1 | #define HOST_ST_OP STW
|
558 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLL
|
559 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRA
|
560 | bffe1431 | blueswir1 | #endif
|
561 | bffe1431 | blueswir1 | |
562 | f5ef6aac | blueswir1 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
563 | f5ef6aac | blueswir1 | int opc)
|
564 | f5ef6aac | blueswir1 | { |
565 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
566 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
567 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
568 | f5ef6aac | blueswir1 | #endif
|
569 | f5ef6aac | blueswir1 | |
570 | f5ef6aac | blueswir1 | data_reg = *args++; |
571 | f5ef6aac | blueswir1 | addr_reg = *args++; |
572 | f5ef6aac | blueswir1 | mem_index = *args; |
573 | f5ef6aac | blueswir1 | s_bits = opc & 3;
|
574 | f5ef6aac | blueswir1 | |
575 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
576 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
577 | 56fc64df | blueswir1 | arg2 = TCG_REG_O2; |
578 | f5ef6aac | blueswir1 | |
579 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
580 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
581 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
582 | f5ef6aac | blueswir1 | SHIFT_SRL); |
583 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
584 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
585 | f5ef6aac | blueswir1 | ARITH_AND); |
586 | f5ef6aac | blueswir1 | |
587 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
588 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
589 | f5ef6aac | blueswir1 | |
590 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
591 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
592 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_read));
|
593 | 53c37487 | blueswir1 | |
594 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
595 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
596 | f5ef6aac | blueswir1 | |
597 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
598 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
599 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
600 | f5ef6aac | blueswir1 | |
601 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
602 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
603 | f5ef6aac | blueswir1 | |
604 | f5ef6aac | blueswir1 | /* will become:
|
605 | 1da92db2 | blueswir1 | be label1
|
606 | 1da92db2 | blueswir1 | or
|
607 | 1da92db2 | blueswir1 | be,pt %xcc label1 */
|
608 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
609 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
610 | f5ef6aac | blueswir1 | |
611 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
612 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
613 | f5ef6aac | blueswir1 | |
614 | bffe1431 | blueswir1 | /* mov */
|
615 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); |
616 | bffe1431 | blueswir1 | |
617 | f5ef6aac | blueswir1 | /* XXX: move that code at the end of the TB */
|
618 | 53c37487 | blueswir1 | /* qemu_ld_helper[s_bits](arg0, arg1) */
|
619 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] |
620 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
621 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
622 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
623 | bffe1431 | blueswir1 | global registers */
|
624 | bffe1431 | blueswir1 | // delay slot
|
625 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
626 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
627 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
628 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
629 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
630 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
631 | f5ef6aac | blueswir1 | |
632 | 53c37487 | blueswir1 | /* data_reg = sign_extend(arg0) */
|
633 | f5ef6aac | blueswir1 | switch(opc) {
|
634 | f5ef6aac | blueswir1 | case 0 | 4: |
635 | 53c37487 | blueswir1 | /* sll arg0, 24/56, data_reg */
|
636 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8, |
637 | bffe1431 | blueswir1 | HOST_SLL_OP); |
638 | 53c37487 | blueswir1 | /* sra data_reg, 24/56, data_reg */
|
639 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
640 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP); |
641 | f5ef6aac | blueswir1 | break;
|
642 | f5ef6aac | blueswir1 | case 1 | 4: |
643 | 53c37487 | blueswir1 | /* sll arg0, 16/48, data_reg */
|
644 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, |
645 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP); |
646 | 53c37487 | blueswir1 | /* sra data_reg, 16/48, data_reg */
|
647 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
648 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP); |
649 | f5ef6aac | blueswir1 | break;
|
650 | f5ef6aac | blueswir1 | case 2 | 4: |
651 | 53c37487 | blueswir1 | /* sll arg0, 32, data_reg */
|
652 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
|
653 | 53c37487 | blueswir1 | /* sra data_reg, 32, data_reg */
|
654 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
|
655 | f5ef6aac | blueswir1 | break;
|
656 | f5ef6aac | blueswir1 | case 0: |
657 | f5ef6aac | blueswir1 | case 1: |
658 | f5ef6aac | blueswir1 | case 2: |
659 | f5ef6aac | blueswir1 | case 3: |
660 | f5ef6aac | blueswir1 | default:
|
661 | f5ef6aac | blueswir1 | /* mov */
|
662 | 53c37487 | blueswir1 | tcg_out_mov(s, data_reg, arg0); |
663 | f5ef6aac | blueswir1 | break;
|
664 | f5ef6aac | blueswir1 | } |
665 | f5ef6aac | blueswir1 | |
666 | f5ef6aac | blueswir1 | /* will become:
|
667 | f5ef6aac | blueswir1 | ba label2 */
|
668 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
669 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
670 | f5ef6aac | blueswir1 | |
671 | 53c37487 | blueswir1 | /* nop (delay slot */
|
672 | 53c37487 | blueswir1 | tcg_out_nop(s); |
673 | 53c37487 | blueswir1 | |
674 | f5ef6aac | blueswir1 | /* label1: */
|
675 | 1da92db2 | blueswir1 | #if TARGET_LONG_BITS == 32 |
676 | 1da92db2 | blueswir1 | /* be label1 */
|
677 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
678 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
679 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
680 | 1da92db2 | blueswir1 | #else
|
681 | 1da92db2 | blueswir1 | /* be,pt %xcc label1 */
|
682 | 1da92db2 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) | |
683 | 1da92db2 | blueswir1 | (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr - |
684 | 1da92db2 | blueswir1 | (unsigned long)label1_ptr)); |
685 | 1da92db2 | blueswir1 | #endif
|
686 | f5ef6aac | blueswir1 | |
687 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
688 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
689 | 9d0efc88 | blueswir1 | offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP); |
690 | 90cbed46 | blueswir1 | |
691 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
692 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
693 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
694 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
695 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
696 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
697 | 90cbed46 | blueswir1 | #else
|
698 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
699 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
700 | 90cbed46 | blueswir1 | #endif
|
701 | 90cbed46 | blueswir1 | |
702 | f5ef6aac | blueswir1 | #else
|
703 | 56fc64df | blueswir1 | arg0 = addr_reg; |
704 | f5ef6aac | blueswir1 | #endif
|
705 | f5ef6aac | blueswir1 | |
706 | f5ef6aac | blueswir1 | switch(opc) {
|
707 | f5ef6aac | blueswir1 | case 0: |
708 | 56fc64df | blueswir1 | /* ldub [arg0], data_reg */
|
709 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
|
710 | f5ef6aac | blueswir1 | break;
|
711 | f5ef6aac | blueswir1 | case 0 | 4: |
712 | 56fc64df | blueswir1 | /* ldsb [arg0], data_reg */
|
713 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
|
714 | f5ef6aac | blueswir1 | break;
|
715 | f5ef6aac | blueswir1 | case 1: |
716 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
717 | 56fc64df | blueswir1 | /* lduh [arg0], data_reg */
|
718 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
|
719 | 8384dd67 | blueswir1 | #else
|
720 | 56fc64df | blueswir1 | /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
721 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
722 | 8384dd67 | blueswir1 | #endif
|
723 | f5ef6aac | blueswir1 | break;
|
724 | f5ef6aac | blueswir1 | case 1 | 4: |
725 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
726 | 56fc64df | blueswir1 | /* ldsh [arg0], data_reg */
|
727 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
|
728 | 8384dd67 | blueswir1 | #else
|
729 | 56fc64df | blueswir1 | /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
730 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
731 | 8384dd67 | blueswir1 | #endif
|
732 | f5ef6aac | blueswir1 | break;
|
733 | f5ef6aac | blueswir1 | case 2: |
734 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
735 | 56fc64df | blueswir1 | /* lduw [arg0], data_reg */
|
736 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
|
737 | 8384dd67 | blueswir1 | #else
|
738 | 56fc64df | blueswir1 | /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
739 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
740 | 8384dd67 | blueswir1 | #endif
|
741 | f5ef6aac | blueswir1 | break;
|
742 | f5ef6aac | blueswir1 | case 2 | 4: |
743 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
744 | 56fc64df | blueswir1 | /* ldsw [arg0], data_reg */
|
745 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
|
746 | 8384dd67 | blueswir1 | #else
|
747 | 56fc64df | blueswir1 | /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
748 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
749 | 8384dd67 | blueswir1 | #endif
|
750 | f5ef6aac | blueswir1 | break;
|
751 | f5ef6aac | blueswir1 | case 3: |
752 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
753 | 56fc64df | blueswir1 | /* ldx [arg0], data_reg */
|
754 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDX);
|
755 | 8384dd67 | blueswir1 | #else
|
756 | 56fc64df | blueswir1 | /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
757 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
758 | 8384dd67 | blueswir1 | #endif
|
759 | f5ef6aac | blueswir1 | break;
|
760 | f5ef6aac | blueswir1 | default:
|
761 | f5ef6aac | blueswir1 | tcg_abort(); |
762 | f5ef6aac | blueswir1 | } |
763 | f5ef6aac | blueswir1 | |
764 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
765 | f5ef6aac | blueswir1 | /* label2: */
|
766 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
767 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
768 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
769 | f5ef6aac | blueswir1 | #endif
|
770 | f5ef6aac | blueswir1 | } |
771 | f5ef6aac | blueswir1 | |
772 | f5ef6aac | blueswir1 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
773 | f5ef6aac | blueswir1 | int opc)
|
774 | f5ef6aac | blueswir1 | { |
775 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
776 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
777 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
778 | f5ef6aac | blueswir1 | #endif
|
779 | f5ef6aac | blueswir1 | |
780 | f5ef6aac | blueswir1 | data_reg = *args++; |
781 | f5ef6aac | blueswir1 | addr_reg = *args++; |
782 | f5ef6aac | blueswir1 | mem_index = *args; |
783 | f5ef6aac | blueswir1 | |
784 | f5ef6aac | blueswir1 | s_bits = opc; |
785 | f5ef6aac | blueswir1 | |
786 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
787 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
788 | 53c37487 | blueswir1 | arg2 = TCG_REG_O2; |
789 | f5ef6aac | blueswir1 | |
790 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
791 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
792 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
793 | f5ef6aac | blueswir1 | SHIFT_SRL); |
794 | 53c37487 | blueswir1 | |
795 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
796 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
797 | f5ef6aac | blueswir1 | ARITH_AND); |
798 | f5ef6aac | blueswir1 | |
799 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
800 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
801 | f5ef6aac | blueswir1 | |
802 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
803 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
804 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_write));
|
805 | f5ef6aac | blueswir1 | |
806 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
807 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
808 | f5ef6aac | blueswir1 | |
809 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
810 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
811 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
812 | 53c37487 | blueswir1 | |
813 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
814 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
815 | f5ef6aac | blueswir1 | |
816 | f5ef6aac | blueswir1 | /* will become:
|
817 | 1da92db2 | blueswir1 | be label1
|
818 | 1da92db2 | blueswir1 | or
|
819 | 1da92db2 | blueswir1 | be,pt %xcc label1 */
|
820 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
821 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
822 | f5ef6aac | blueswir1 | |
823 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
824 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
825 | 53c37487 | blueswir1 | |
826 | 53c37487 | blueswir1 | /* mov */
|
827 | 56fc64df | blueswir1 | tcg_out_mov(s, arg1, data_reg); |
828 | 53c37487 | blueswir1 | |
829 | bffe1431 | blueswir1 | /* mov */
|
830 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); |
831 | bffe1431 | blueswir1 | |
832 | 53c37487 | blueswir1 | /* XXX: move that code at the end of the TB */
|
833 | 53c37487 | blueswir1 | /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
834 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] |
835 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
836 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
837 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
838 | bffe1431 | blueswir1 | global registers */
|
839 | bffe1431 | blueswir1 | // delay slot
|
840 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
841 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
842 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
843 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
844 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
845 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
846 | f5ef6aac | blueswir1 | |
847 | f5ef6aac | blueswir1 | /* will become:
|
848 | f5ef6aac | blueswir1 | ba label2 */
|
849 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
850 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
851 | f5ef6aac | blueswir1 | |
852 | 53c37487 | blueswir1 | /* nop (delay slot) */
|
853 | 53c37487 | blueswir1 | tcg_out_nop(s); |
854 | 53c37487 | blueswir1 | |
855 | 1da92db2 | blueswir1 | #if TARGET_LONG_BITS == 32 |
856 | 1da92db2 | blueswir1 | /* be label1 */
|
857 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
858 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
859 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
860 | 1da92db2 | blueswir1 | #else
|
861 | 1da92db2 | blueswir1 | /* be,pt %xcc label1 */
|
862 | 1da92db2 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) | |
863 | 1da92db2 | blueswir1 | (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr - |
864 | 1da92db2 | blueswir1 | (unsigned long)label1_ptr)); |
865 | 1da92db2 | blueswir1 | #endif
|
866 | f5ef6aac | blueswir1 | |
867 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
868 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
869 | 9d0efc88 | blueswir1 | offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP); |
870 | 53c37487 | blueswir1 | |
871 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
872 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
873 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
874 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
875 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
876 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
877 | 90cbed46 | blueswir1 | #else
|
878 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
879 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
880 | 90cbed46 | blueswir1 | #endif
|
881 | 90cbed46 | blueswir1 | |
882 | f5ef6aac | blueswir1 | #else
|
883 | 56fc64df | blueswir1 | arg0 = addr_reg; |
884 | f5ef6aac | blueswir1 | #endif
|
885 | f5ef6aac | blueswir1 | |
886 | f5ef6aac | blueswir1 | switch(opc) {
|
887 | f5ef6aac | blueswir1 | case 0: |
888 | 56fc64df | blueswir1 | /* stb data_reg, [arg0] */
|
889 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STB);
|
890 | f5ef6aac | blueswir1 | break;
|
891 | f5ef6aac | blueswir1 | case 1: |
892 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
893 | 56fc64df | blueswir1 | /* sth data_reg, [arg0] */
|
894 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STH);
|
895 | 8384dd67 | blueswir1 | #else
|
896 | 56fc64df | blueswir1 | /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
897 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
|
898 | 8384dd67 | blueswir1 | #endif
|
899 | f5ef6aac | blueswir1 | break;
|
900 | f5ef6aac | blueswir1 | case 2: |
901 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
902 | 56fc64df | blueswir1 | /* stw data_reg, [arg0] */
|
903 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STW);
|
904 | 8384dd67 | blueswir1 | #else
|
905 | 56fc64df | blueswir1 | /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
906 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
|
907 | 8384dd67 | blueswir1 | #endif
|
908 | f5ef6aac | blueswir1 | break;
|
909 | f5ef6aac | blueswir1 | case 3: |
910 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
911 | 56fc64df | blueswir1 | /* stx data_reg, [arg0] */
|
912 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STX);
|
913 | 8384dd67 | blueswir1 | #else
|
914 | 56fc64df | blueswir1 | /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
915 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
|
916 | 8384dd67 | blueswir1 | #endif
|
917 | f5ef6aac | blueswir1 | break;
|
918 | f5ef6aac | blueswir1 | default:
|
919 | f5ef6aac | blueswir1 | tcg_abort(); |
920 | f5ef6aac | blueswir1 | } |
921 | f5ef6aac | blueswir1 | |
922 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
923 | f5ef6aac | blueswir1 | /* label2: */
|
924 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
925 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
926 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
927 | f5ef6aac | blueswir1 | #endif
|
928 | f5ef6aac | blueswir1 | } |
929 | f5ef6aac | blueswir1 | |
930 | 8289b279 | blueswir1 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
931 | 8289b279 | blueswir1 | const int *const_args) |
932 | 8289b279 | blueswir1 | { |
933 | 8289b279 | blueswir1 | int c;
|
934 | 8289b279 | blueswir1 | |
935 | 8289b279 | blueswir1 | switch (opc) {
|
936 | 8289b279 | blueswir1 | case INDEX_op_exit_tb:
|
937 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
938 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
939 | 8289b279 | blueswir1 | INSN_IMM13(8));
|
940 | b3db8758 | blueswir1 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
941 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
942 | 8289b279 | blueswir1 | break;
|
943 | 8289b279 | blueswir1 | case INDEX_op_goto_tb:
|
944 | 8289b279 | blueswir1 | if (s->tb_jmp_offset) {
|
945 | 8289b279 | blueswir1 | /* direct jump method */
|
946 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000); |
947 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
948 | cf7c2ca5 | blueswir1 | INSN_IMM13((args[0] & 0x1fff))); |
949 | 8289b279 | blueswir1 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
950 | 8289b279 | blueswir1 | } else {
|
951 | 8289b279 | blueswir1 | /* indirect jump method */
|
952 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
953 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
954 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
955 | 8289b279 | blueswir1 | } |
956 | 53cd9273 | blueswir1 | tcg_out_nop(s); |
957 | 8289b279 | blueswir1 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
958 | 8289b279 | blueswir1 | break;
|
959 | 8289b279 | blueswir1 | case INDEX_op_call:
|
960 | bffe1431 | blueswir1 | if (const_args[0]) |
961 | bffe1431 | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
962 | bffe1431 | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
963 | bffe1431 | blueswir1 | & 0x3fffffff));
|
964 | bffe1431 | blueswir1 | else {
|
965 | bffe1431 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, |
966 | bffe1431 | blueswir1 | (tcg_target_long)(s->tb_next + args[0]));
|
967 | bffe1431 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | |
968 | bffe1431 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
969 | 8289b279 | blueswir1 | } |
970 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
971 | bffe1431 | blueswir1 | global registers */
|
972 | bffe1431 | blueswir1 | // delay slot
|
973 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
974 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
975 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
976 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
977 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
978 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
979 | 8289b279 | blueswir1 | break;
|
980 | 8289b279 | blueswir1 | case INDEX_op_jmp:
|
981 | 8289b279 | blueswir1 | case INDEX_op_br:
|
982 | 1da92db2 | blueswir1 | tcg_out_branch_i32(s, COND_A, args[0]);
|
983 | f5ef6aac | blueswir1 | tcg_out_nop(s); |
984 | 8289b279 | blueswir1 | break;
|
985 | 8289b279 | blueswir1 | case INDEX_op_movi_i32:
|
986 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
987 | 8289b279 | blueswir1 | break;
|
988 | 8289b279 | blueswir1 | |
989 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
990 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
991 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:) \
|
992 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i64:)
|
993 | 8289b279 | blueswir1 | #else
|
994 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
995 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:)
|
996 | 8289b279 | blueswir1 | #endif
|
997 | 8289b279 | blueswir1 | OP_32_64(ld8u); |
998 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
999 | 8289b279 | blueswir1 | break;
|
1000 | 8289b279 | blueswir1 | OP_32_64(ld8s); |
1001 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
1002 | 8289b279 | blueswir1 | break;
|
1003 | 8289b279 | blueswir1 | OP_32_64(ld16u); |
1004 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
1005 | 8289b279 | blueswir1 | break;
|
1006 | 8289b279 | blueswir1 | OP_32_64(ld16s); |
1007 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
1008 | 8289b279 | blueswir1 | break;
|
1009 | 8289b279 | blueswir1 | case INDEX_op_ld_i32:
|
1010 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1011 | 53cd9273 | blueswir1 | case INDEX_op_ld32u_i64:
|
1012 | 8289b279 | blueswir1 | #endif
|
1013 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
1014 | 8289b279 | blueswir1 | break;
|
1015 | 8289b279 | blueswir1 | OP_32_64(st8); |
1016 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
1017 | 8289b279 | blueswir1 | break;
|
1018 | 8289b279 | blueswir1 | OP_32_64(st16); |
1019 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
1020 | 8289b279 | blueswir1 | break;
|
1021 | 8289b279 | blueswir1 | case INDEX_op_st_i32:
|
1022 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1023 | 53cd9273 | blueswir1 | case INDEX_op_st32_i64:
|
1024 | 8289b279 | blueswir1 | #endif
|
1025 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
1026 | 8289b279 | blueswir1 | break;
|
1027 | 53cd9273 | blueswir1 | OP_32_64(add); |
1028 | 53cd9273 | blueswir1 | c = ARITH_ADD; |
1029 | 53cd9273 | blueswir1 | goto gen_arith32;
|
1030 | 8289b279 | blueswir1 | OP_32_64(sub); |
1031 | 8289b279 | blueswir1 | c = ARITH_SUB; |
1032 | 8289b279 | blueswir1 | goto gen_arith32;
|
1033 | 8289b279 | blueswir1 | OP_32_64(and); |
1034 | 8289b279 | blueswir1 | c = ARITH_AND; |
1035 | 8289b279 | blueswir1 | goto gen_arith32;
|
1036 | 8289b279 | blueswir1 | OP_32_64(or); |
1037 | 8289b279 | blueswir1 | c = ARITH_OR; |
1038 | 8289b279 | blueswir1 | goto gen_arith32;
|
1039 | 8289b279 | blueswir1 | OP_32_64(xor); |
1040 | 8289b279 | blueswir1 | c = ARITH_XOR; |
1041 | 8289b279 | blueswir1 | goto gen_arith32;
|
1042 | 8289b279 | blueswir1 | case INDEX_op_shl_i32:
|
1043 | 8289b279 | blueswir1 | c = SHIFT_SLL; |
1044 | 8289b279 | blueswir1 | goto gen_arith32;
|
1045 | 8289b279 | blueswir1 | case INDEX_op_shr_i32:
|
1046 | 8289b279 | blueswir1 | c = SHIFT_SRL; |
1047 | 8289b279 | blueswir1 | goto gen_arith32;
|
1048 | 8289b279 | blueswir1 | case INDEX_op_sar_i32:
|
1049 | 8289b279 | blueswir1 | c = SHIFT_SRA; |
1050 | 8289b279 | blueswir1 | goto gen_arith32;
|
1051 | 8289b279 | blueswir1 | case INDEX_op_mul_i32:
|
1052 | 8289b279 | blueswir1 | c = ARITH_UMUL; |
1053 | 8289b279 | blueswir1 | goto gen_arith32;
|
1054 | 8289b279 | blueswir1 | case INDEX_op_div2_i32:
|
1055 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
1056 | 8289b279 | blueswir1 | c = ARITH_SDIVX; |
1057 | 8289b279 | blueswir1 | goto gen_arith32;
|
1058 | 8289b279 | blueswir1 | #else
|
1059 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
1060 | 8289b279 | blueswir1 | c = ARITH_SDIV; |
1061 | 8289b279 | blueswir1 | goto gen_arith32;
|
1062 | 8289b279 | blueswir1 | #endif
|
1063 | 8289b279 | blueswir1 | case INDEX_op_divu2_i32:
|
1064 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
1065 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1066 | 8289b279 | blueswir1 | goto gen_arith32;
|
1067 | 8289b279 | blueswir1 | #else
|
1068 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
1069 | 8289b279 | blueswir1 | c = ARITH_UDIV; |
1070 | 8289b279 | blueswir1 | goto gen_arith32;
|
1071 | 8289b279 | blueswir1 | #endif
|
1072 | 8289b279 | blueswir1 | |
1073 | 8289b279 | blueswir1 | case INDEX_op_brcond_i32:
|
1074 | 1da92db2 | blueswir1 | tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1], |
1075 | 1da92db2 | blueswir1 | args[3]);
|
1076 | 8289b279 | blueswir1 | break;
|
1077 | 8289b279 | blueswir1 | |
1078 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8u:
|
1079 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0);
|
1080 | 8289b279 | blueswir1 | break;
|
1081 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8s:
|
1082 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0 | 4); |
1083 | 8289b279 | blueswir1 | break;
|
1084 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16u:
|
1085 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1);
|
1086 | 8289b279 | blueswir1 | break;
|
1087 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16s:
|
1088 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1 | 4); |
1089 | 8289b279 | blueswir1 | break;
|
1090 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32u:
|
1091 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2);
|
1092 | 8289b279 | blueswir1 | break;
|
1093 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32s:
|
1094 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2 | 4); |
1095 | 8289b279 | blueswir1 | break;
|
1096 | 8289b279 | blueswir1 | case INDEX_op_qemu_st8:
|
1097 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 0);
|
1098 | 8289b279 | blueswir1 | break;
|
1099 | 8289b279 | blueswir1 | case INDEX_op_qemu_st16:
|
1100 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 1);
|
1101 | 8289b279 | blueswir1 | break;
|
1102 | 8289b279 | blueswir1 | case INDEX_op_qemu_st32:
|
1103 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 2);
|
1104 | 8289b279 | blueswir1 | break;
|
1105 | 8289b279 | blueswir1 | |
1106 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1107 | 8289b279 | blueswir1 | case INDEX_op_movi_i64:
|
1108 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
1109 | 8289b279 | blueswir1 | break;
|
1110 | 53cd9273 | blueswir1 | case INDEX_op_ld32s_i64:
|
1111 | 53cd9273 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
1112 | 53cd9273 | blueswir1 | break;
|
1113 | 8289b279 | blueswir1 | case INDEX_op_ld_i64:
|
1114 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
1115 | 8289b279 | blueswir1 | break;
|
1116 | 8289b279 | blueswir1 | case INDEX_op_st_i64:
|
1117 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
1118 | 8289b279 | blueswir1 | break;
|
1119 | 8289b279 | blueswir1 | case INDEX_op_shl_i64:
|
1120 | 8289b279 | blueswir1 | c = SHIFT_SLLX; |
1121 | 8289b279 | blueswir1 | goto gen_arith32;
|
1122 | 8289b279 | blueswir1 | case INDEX_op_shr_i64:
|
1123 | 8289b279 | blueswir1 | c = SHIFT_SRLX; |
1124 | 8289b279 | blueswir1 | goto gen_arith32;
|
1125 | 8289b279 | blueswir1 | case INDEX_op_sar_i64:
|
1126 | 8289b279 | blueswir1 | c = SHIFT_SRAX; |
1127 | 8289b279 | blueswir1 | goto gen_arith32;
|
1128 | 8289b279 | blueswir1 | case INDEX_op_mul_i64:
|
1129 | 8289b279 | blueswir1 | c = ARITH_MULX; |
1130 | 8289b279 | blueswir1 | goto gen_arith32;
|
1131 | 8289b279 | blueswir1 | case INDEX_op_div2_i64:
|
1132 | 53cd9273 | blueswir1 | c = ARITH_SDIVX; |
1133 | 8289b279 | blueswir1 | goto gen_arith32;
|
1134 | 8289b279 | blueswir1 | case INDEX_op_divu2_i64:
|
1135 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1136 | 8289b279 | blueswir1 | goto gen_arith32;
|
1137 | 8289b279 | blueswir1 | |
1138 | 8289b279 | blueswir1 | case INDEX_op_brcond_i64:
|
1139 | 1da92db2 | blueswir1 | tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1], |
1140 | 1da92db2 | blueswir1 | args[3]);
|
1141 | 8289b279 | blueswir1 | break;
|
1142 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld64:
|
1143 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 3);
|
1144 | 8289b279 | blueswir1 | break;
|
1145 | 8289b279 | blueswir1 | case INDEX_op_qemu_st64:
|
1146 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 3);
|
1147 | 8289b279 | blueswir1 | break;
|
1148 | 8289b279 | blueswir1 | |
1149 | 8289b279 | blueswir1 | #endif
|
1150 | 53cd9273 | blueswir1 | gen_arith32:
|
1151 | 53cd9273 | blueswir1 | if (const_args[2]) { |
1152 | 53cd9273 | blueswir1 | tcg_out_arithi(s, args[0], args[1], args[2], c); |
1153 | 53cd9273 | blueswir1 | } else {
|
1154 | 53cd9273 | blueswir1 | tcg_out_arith(s, args[0], args[1], args[2], c); |
1155 | 53cd9273 | blueswir1 | } |
1156 | 53cd9273 | blueswir1 | break;
|
1157 | 53cd9273 | blueswir1 | |
1158 | 8289b279 | blueswir1 | default:
|
1159 | 8289b279 | blueswir1 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
1160 | 8289b279 | blueswir1 | tcg_abort(); |
1161 | 8289b279 | blueswir1 | } |
1162 | 8289b279 | blueswir1 | } |
1163 | 8289b279 | blueswir1 | |
1164 | 8289b279 | blueswir1 | static const TCGTargetOpDef sparc_op_defs[] = { |
1165 | 8289b279 | blueswir1 | { INDEX_op_exit_tb, { } }, |
1166 | b3db8758 | blueswir1 | { INDEX_op_goto_tb, { } }, |
1167 | 8289b279 | blueswir1 | { INDEX_op_call, { "ri" } },
|
1168 | 8289b279 | blueswir1 | { INDEX_op_jmp, { "ri" } },
|
1169 | 8289b279 | blueswir1 | { INDEX_op_br, { } }, |
1170 | 8289b279 | blueswir1 | |
1171 | 8289b279 | blueswir1 | { INDEX_op_mov_i32, { "r", "r" } }, |
1172 | 8289b279 | blueswir1 | { INDEX_op_movi_i32, { "r" } },
|
1173 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1174 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1175 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1176 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1177 | 8289b279 | blueswir1 | { INDEX_op_ld_i32, { "r", "r" } }, |
1178 | 8289b279 | blueswir1 | { INDEX_op_st8_i32, { "r", "r" } }, |
1179 | 8289b279 | blueswir1 | { INDEX_op_st16_i32, { "r", "r" } }, |
1180 | 8289b279 | blueswir1 | { INDEX_op_st_i32, { "r", "r" } }, |
1181 | 8289b279 | blueswir1 | |
1182 | 53cd9273 | blueswir1 | { INDEX_op_add_i32, { "r", "r", "rJ" } }, |
1183 | 53cd9273 | blueswir1 | { INDEX_op_mul_i32, { "r", "r", "rJ" } }, |
1184 | 8289b279 | blueswir1 | { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } }, |
1185 | 8289b279 | blueswir1 | { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } }, |
1186 | 53cd9273 | blueswir1 | { INDEX_op_sub_i32, { "r", "r", "rJ" } }, |
1187 | 53cd9273 | blueswir1 | { INDEX_op_and_i32, { "r", "r", "rJ" } }, |
1188 | 53cd9273 | blueswir1 | { INDEX_op_or_i32, { "r", "r", "rJ" } }, |
1189 | 53cd9273 | blueswir1 | { INDEX_op_xor_i32, { "r", "r", "rJ" } }, |
1190 | 8289b279 | blueswir1 | |
1191 | 53cd9273 | blueswir1 | { INDEX_op_shl_i32, { "r", "r", "rJ" } }, |
1192 | 53cd9273 | blueswir1 | { INDEX_op_shr_i32, { "r", "r", "rJ" } }, |
1193 | 53cd9273 | blueswir1 | { INDEX_op_sar_i32, { "r", "r", "rJ" } }, |
1194 | 8289b279 | blueswir1 | |
1195 | 8289b279 | blueswir1 | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1196 | 8289b279 | blueswir1 | |
1197 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1198 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1199 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1200 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1201 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1202 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1203 | 8289b279 | blueswir1 | |
1204 | 8289b279 | blueswir1 | { INDEX_op_qemu_st8, { "L", "L" } }, |
1205 | 8289b279 | blueswir1 | { INDEX_op_qemu_st16, { "L", "L" } }, |
1206 | 8289b279 | blueswir1 | { INDEX_op_qemu_st32, { "L", "L" } }, |
1207 | 8289b279 | blueswir1 | |
1208 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1209 | 8289b279 | blueswir1 | { INDEX_op_mov_i64, { "r", "r" } }, |
1210 | 8289b279 | blueswir1 | { INDEX_op_movi_i64, { "r" } },
|
1211 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1212 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1213 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1214 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1215 | 8289b279 | blueswir1 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1216 | 8289b279 | blueswir1 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1217 | 8289b279 | blueswir1 | { INDEX_op_ld_i64, { "r", "r" } }, |
1218 | 8289b279 | blueswir1 | { INDEX_op_st8_i64, { "r", "r" } }, |
1219 | 8289b279 | blueswir1 | { INDEX_op_st16_i64, { "r", "r" } }, |
1220 | 8289b279 | blueswir1 | { INDEX_op_st32_i64, { "r", "r" } }, |
1221 | 8289b279 | blueswir1 | { INDEX_op_st_i64, { "r", "r" } }, |
1222 | 56fc64df | blueswir1 | { INDEX_op_qemu_ld64, { "L", "L" } }, |
1223 | 56fc64df | blueswir1 | { INDEX_op_qemu_st64, { "L", "L" } }, |
1224 | 8289b279 | blueswir1 | |
1225 | 53cd9273 | blueswir1 | { INDEX_op_add_i64, { "r", "r", "rJ" } }, |
1226 | 53cd9273 | blueswir1 | { INDEX_op_mul_i64, { "r", "r", "rJ" } }, |
1227 | 8289b279 | blueswir1 | { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } }, |
1228 | 8289b279 | blueswir1 | { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } }, |
1229 | 53cd9273 | blueswir1 | { INDEX_op_sub_i64, { "r", "r", "rJ" } }, |
1230 | 53cd9273 | blueswir1 | { INDEX_op_and_i64, { "r", "r", "rJ" } }, |
1231 | 53cd9273 | blueswir1 | { INDEX_op_or_i64, { "r", "r", "rJ" } }, |
1232 | 53cd9273 | blueswir1 | { INDEX_op_xor_i64, { "r", "r", "rJ" } }, |
1233 | 8289b279 | blueswir1 | |
1234 | 53cd9273 | blueswir1 | { INDEX_op_shl_i64, { "r", "r", "rJ" } }, |
1235 | 53cd9273 | blueswir1 | { INDEX_op_shr_i64, { "r", "r", "rJ" } }, |
1236 | 53cd9273 | blueswir1 | { INDEX_op_sar_i64, { "r", "r", "rJ" } }, |
1237 | 8289b279 | blueswir1 | |
1238 | 8289b279 | blueswir1 | { INDEX_op_brcond_i64, { "r", "ri" } }, |
1239 | 8289b279 | blueswir1 | #endif
|
1240 | 8289b279 | blueswir1 | { -1 },
|
1241 | 8289b279 | blueswir1 | }; |
1242 | 8289b279 | blueswir1 | |
1243 | 8289b279 | blueswir1 | void tcg_target_init(TCGContext *s)
|
1244 | 8289b279 | blueswir1 | { |
1245 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
1246 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1247 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
1248 | 8289b279 | blueswir1 | #endif
|
1249 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1250 | b3db8758 | blueswir1 | (1 << TCG_REG_G1) |
|
1251 | b3db8758 | blueswir1 | (1 << TCG_REG_G2) |
|
1252 | b3db8758 | blueswir1 | (1 << TCG_REG_G3) |
|
1253 | b3db8758 | blueswir1 | (1 << TCG_REG_G4) |
|
1254 | b3db8758 | blueswir1 | (1 << TCG_REG_G5) |
|
1255 | b3db8758 | blueswir1 | (1 << TCG_REG_G6) |
|
1256 | b3db8758 | blueswir1 | (1 << TCG_REG_G7) |
|
1257 | 8289b279 | blueswir1 | (1 << TCG_REG_O0) |
|
1258 | 8289b279 | blueswir1 | (1 << TCG_REG_O1) |
|
1259 | 8289b279 | blueswir1 | (1 << TCG_REG_O2) |
|
1260 | 8289b279 | blueswir1 | (1 << TCG_REG_O3) |
|
1261 | 8289b279 | blueswir1 | (1 << TCG_REG_O4) |
|
1262 | 8289b279 | blueswir1 | (1 << TCG_REG_O5) |
|
1263 | 8289b279 | blueswir1 | (1 << TCG_REG_O7));
|
1264 | 8289b279 | blueswir1 | |
1265 | 8289b279 | blueswir1 | tcg_regset_clear(s->reserved_regs); |
1266 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
1267 | d795eb86 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1268 | d795eb86 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
|
1269 | d795eb86 | blueswir1 | #endif
|
1270 | 53cd9273 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
1271 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
1272 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
1273 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
1274 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
1275 | 8289b279 | blueswir1 | tcg_add_target_add_op_defs(sparc_op_defs); |
1276 | 8289b279 | blueswir1 | } |