root / hw / tcx.c @ 3023f332
History | View | Annotate | Download (17.2 kB)
1 | 420557e8 | bellard | /*
|
---|---|---|---|
2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
|
3 | 5fafdf24 | ths | *
|
4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
|
12 | 420557e8 | bellard | *
|
13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
|
15 | 420557e8 | bellard | *
|
16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 420557e8 | bellard | * THE SOFTWARE.
|
23 | 420557e8 | bellard | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 94470844 | blueswir1 | #include "pixel_ops.h" |
28 | 420557e8 | bellard | |
29 | 420557e8 | bellard | #define MAXX 1024 |
30 | 420557e8 | bellard | #define MAXY 768 |
31 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
32 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_8 0x081c |
33 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_24 0x1000 |
34 | 8508b89e | blueswir1 | #define TCX_TEC_NREGS 0x1000 |
35 | 420557e8 | bellard | |
36 | 420557e8 | bellard | typedef struct TCXState { |
37 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr; |
38 | 420557e8 | bellard | DisplayState *ds; |
39 | 8d5f07fa | bellard | uint8_t *vram; |
40 | eee0b836 | blueswir1 | uint32_t *vram24, *cplane; |
41 | eee0b836 | blueswir1 | ram_addr_t vram_offset, vram24_offset, cplane_offset; |
42 | eee0b836 | blueswir1 | uint16_t width, height, depth; |
43 | e80cfcfc | bellard | uint8_t r[256], g[256], b[256]; |
44 | 21206a10 | bellard | uint32_t palette[256];
|
45 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
46 | 420557e8 | bellard | } TCXState; |
47 | 420557e8 | bellard | |
48 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename); |
49 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename); |
50 | 97e7df27 | blueswir1 | static void tcx_invalidate_display(void *opaque); |
51 | 97e7df27 | blueswir1 | static void tcx24_invalidate_display(void *opaque); |
52 | 95219897 | pbrook | |
53 | 21206a10 | bellard | static void update_palette_entries(TCXState *s, int start, int end) |
54 | 21206a10 | bellard | { |
55 | 21206a10 | bellard | int i;
|
56 | 21206a10 | bellard | for(i = start; i < end; i++) {
|
57 | 0e1f5a0c | aliguori | switch(ds_get_bits_per_pixel(s->ds)) {
|
58 | 21206a10 | bellard | default:
|
59 | 21206a10 | bellard | case 8: |
60 | 21206a10 | bellard | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
61 | 21206a10 | bellard | break;
|
62 | 21206a10 | bellard | case 15: |
63 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
64 | 21206a10 | bellard | break;
|
65 | 21206a10 | bellard | case 16: |
66 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
67 | 21206a10 | bellard | break;
|
68 | 21206a10 | bellard | case 32: |
69 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
70 | 21206a10 | bellard | break;
|
71 | 21206a10 | bellard | } |
72 | 21206a10 | bellard | } |
73 | 97e7df27 | blueswir1 | if (s->depth == 24) |
74 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
75 | 97e7df27 | blueswir1 | else
|
76 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
77 | 21206a10 | bellard | } |
78 | 21206a10 | bellard | |
79 | 5fafdf24 | ths | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
80 | f930d07e | blueswir1 | const uint8_t *s, int width) |
81 | 420557e8 | bellard | { |
82 | e80cfcfc | bellard | int x;
|
83 | e80cfcfc | bellard | uint8_t val; |
84 | 8bdc2159 | ths | uint32_t *p = (uint32_t *)d; |
85 | e80cfcfc | bellard | |
86 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
87 | f930d07e | blueswir1 | val = *s++; |
88 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
89 | e80cfcfc | bellard | } |
90 | 420557e8 | bellard | } |
91 | 420557e8 | bellard | |
92 | 5fafdf24 | ths | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
93 | f930d07e | blueswir1 | const uint8_t *s, int width) |
94 | e80cfcfc | bellard | { |
95 | e80cfcfc | bellard | int x;
|
96 | e80cfcfc | bellard | uint8_t val; |
97 | 8bdc2159 | ths | uint16_t *p = (uint16_t *)d; |
98 | 8d5f07fa | bellard | |
99 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
100 | f930d07e | blueswir1 | val = *s++; |
101 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
102 | e80cfcfc | bellard | } |
103 | e80cfcfc | bellard | } |
104 | e80cfcfc | bellard | |
105 | 5fafdf24 | ths | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
106 | f930d07e | blueswir1 | const uint8_t *s, int width) |
107 | 420557e8 | bellard | { |
108 | e80cfcfc | bellard | int x;
|
109 | e80cfcfc | bellard | uint8_t val; |
110 | e80cfcfc | bellard | |
111 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
112 | f930d07e | blueswir1 | val = *s++; |
113 | 21206a10 | bellard | *d++ = s1->palette[val]; |
114 | 420557e8 | bellard | } |
115 | 420557e8 | bellard | } |
116 | 420557e8 | bellard | |
117 | 688ea2eb | blueswir1 | /*
|
118 | 688ea2eb | blueswir1 | XXX Could be much more optimal:
|
119 | 688ea2eb | blueswir1 | * detect if line/page/whole screen is in 24 bit mode
|
120 | 688ea2eb | blueswir1 | * if destination is also BGR, use memcpy
|
121 | 688ea2eb | blueswir1 | */
|
122 | eee0b836 | blueswir1 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
123 | eee0b836 | blueswir1 | const uint8_t *s, int width, |
124 | eee0b836 | blueswir1 | const uint32_t *cplane,
|
125 | eee0b836 | blueswir1 | const uint32_t *s24)
|
126 | eee0b836 | blueswir1 | { |
127 | 8927bcfd | aliguori | int x, r, g, b;
|
128 | 688ea2eb | blueswir1 | uint8_t val, *p8; |
129 | eee0b836 | blueswir1 | uint32_t *p = (uint32_t *)d; |
130 | eee0b836 | blueswir1 | uint32_t dval; |
131 | eee0b836 | blueswir1 | |
132 | eee0b836 | blueswir1 | for(x = 0; x < width; x++, s++, s24++) { |
133 | 688ea2eb | blueswir1 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
134 | 688ea2eb | blueswir1 | // 24-bit direct, BGR order
|
135 | 688ea2eb | blueswir1 | p8 = (uint8_t *)s24; |
136 | 688ea2eb | blueswir1 | p8++; |
137 | 688ea2eb | blueswir1 | b = *p8++; |
138 | 688ea2eb | blueswir1 | g = *p8++; |
139 | 688ea2eb | blueswir1 | r = *p8++; |
140 | 8927bcfd | aliguori | dval = rgb_to_pixel32(r, g, b); |
141 | eee0b836 | blueswir1 | } else {
|
142 | eee0b836 | blueswir1 | val = *s; |
143 | eee0b836 | blueswir1 | dval = s1->palette[val]; |
144 | eee0b836 | blueswir1 | } |
145 | eee0b836 | blueswir1 | *p++ = dval; |
146 | eee0b836 | blueswir1 | } |
147 | eee0b836 | blueswir1 | } |
148 | eee0b836 | blueswir1 | |
149 | 22548760 | blueswir1 | static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
150 | eee0b836 | blueswir1 | ram_addr_t cpage) |
151 | eee0b836 | blueswir1 | { |
152 | eee0b836 | blueswir1 | int ret;
|
153 | eee0b836 | blueswir1 | unsigned int off; |
154 | eee0b836 | blueswir1 | |
155 | eee0b836 | blueswir1 | ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
156 | eee0b836 | blueswir1 | for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
157 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
158 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
159 | eee0b836 | blueswir1 | } |
160 | eee0b836 | blueswir1 | return ret;
|
161 | eee0b836 | blueswir1 | } |
162 | eee0b836 | blueswir1 | |
163 | eee0b836 | blueswir1 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
164 | eee0b836 | blueswir1 | ram_addr_t page_max, ram_addr_t page24, |
165 | eee0b836 | blueswir1 | ram_addr_t cpage) |
166 | eee0b836 | blueswir1 | { |
167 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
168 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
169 | eee0b836 | blueswir1 | page_min -= ts->vram_offset; |
170 | eee0b836 | blueswir1 | page_max -= ts->vram_offset; |
171 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page24 + page_min * 4,
|
172 | eee0b836 | blueswir1 | page24 + page_max * 4 + TARGET_PAGE_SIZE,
|
173 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
174 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(cpage + page_min * 4,
|
175 | eee0b836 | blueswir1 | cpage + page_max * 4 + TARGET_PAGE_SIZE,
|
176 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
177 | eee0b836 | blueswir1 | } |
178 | eee0b836 | blueswir1 | |
179 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
|
180 | e80cfcfc | bellard | VGA... */
|
181 | 95219897 | pbrook | static void tcx_update_display(void *opaque) |
182 | 420557e8 | bellard | { |
183 | e80cfcfc | bellard | TCXState *ts = opaque; |
184 | 550be127 | bellard | ram_addr_t page, page_min, page_max; |
185 | 550be127 | bellard | int y, y_start, dd, ds;
|
186 | e80cfcfc | bellard | uint8_t *d, *s; |
187 | b3ceef24 | blueswir1 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
188 | e80cfcfc | bellard | |
189 | 0e1f5a0c | aliguori | if (ds_get_bits_per_pixel(ts->ds) == 0) |
190 | f930d07e | blueswir1 | return;
|
191 | 6f7e9aec | bellard | page = ts->vram_offset; |
192 | e80cfcfc | bellard | y_start = -1;
|
193 | 550be127 | bellard | page_min = 0xffffffff;
|
194 | 550be127 | bellard | page_max = 0;
|
195 | 0e1f5a0c | aliguori | d = ds_get_data(ts->ds); |
196 | 6f7e9aec | bellard | s = ts->vram; |
197 | 0e1f5a0c | aliguori | dd = ds_get_linesize(ts->ds); |
198 | e80cfcfc | bellard | ds = 1024;
|
199 | e80cfcfc | bellard | |
200 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(ts->ds)) {
|
201 | e80cfcfc | bellard | case 32: |
202 | f930d07e | blueswir1 | f = tcx_draw_line32; |
203 | f930d07e | blueswir1 | break;
|
204 | 21206a10 | bellard | case 15: |
205 | 21206a10 | bellard | case 16: |
206 | f930d07e | blueswir1 | f = tcx_draw_line16; |
207 | f930d07e | blueswir1 | break;
|
208 | e80cfcfc | bellard | default:
|
209 | e80cfcfc | bellard | case 8: |
210 | f930d07e | blueswir1 | f = tcx_draw_line8; |
211 | f930d07e | blueswir1 | break;
|
212 | e80cfcfc | bellard | case 0: |
213 | f930d07e | blueswir1 | return;
|
214 | e80cfcfc | bellard | } |
215 | 3b46e624 | ths | |
216 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
217 | f930d07e | blueswir1 | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
|
218 | f930d07e | blueswir1 | if (y_start < 0) |
219 | e80cfcfc | bellard | y_start = y; |
220 | e80cfcfc | bellard | if (page < page_min)
|
221 | e80cfcfc | bellard | page_min = page; |
222 | e80cfcfc | bellard | if (page > page_max)
|
223 | e80cfcfc | bellard | page_max = page; |
224 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
225 | f930d07e | blueswir1 | d += dd; |
226 | f930d07e | blueswir1 | s += ds; |
227 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
228 | f930d07e | blueswir1 | d += dd; |
229 | f930d07e | blueswir1 | s += ds; |
230 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
231 | f930d07e | blueswir1 | d += dd; |
232 | f930d07e | blueswir1 | s += ds; |
233 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
234 | f930d07e | blueswir1 | d += dd; |
235 | f930d07e | blueswir1 | s += ds; |
236 | f930d07e | blueswir1 | } else {
|
237 | e80cfcfc | bellard | if (y_start >= 0) { |
238 | e80cfcfc | bellard | /* flush to display */
|
239 | 5fafdf24 | ths | dpy_update(ts->ds, 0, y_start,
|
240 | 6f7e9aec | bellard | ts->width, y - y_start); |
241 | e80cfcfc | bellard | y_start = -1;
|
242 | e80cfcfc | bellard | } |
243 | f930d07e | blueswir1 | d += dd * 4;
|
244 | f930d07e | blueswir1 | s += ds * 4;
|
245 | f930d07e | blueswir1 | } |
246 | e80cfcfc | bellard | } |
247 | e80cfcfc | bellard | if (y_start >= 0) { |
248 | f930d07e | blueswir1 | /* flush to display */
|
249 | f930d07e | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
250 | f930d07e | blueswir1 | ts->width, y - y_start); |
251 | e80cfcfc | bellard | } |
252 | e80cfcfc | bellard | /* reset modified pages */
|
253 | 550be127 | bellard | if (page_min <= page_max) {
|
254 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
255 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
256 | e80cfcfc | bellard | } |
257 | 420557e8 | bellard | } |
258 | 420557e8 | bellard | |
259 | eee0b836 | blueswir1 | static void tcx24_update_display(void *opaque) |
260 | eee0b836 | blueswir1 | { |
261 | eee0b836 | blueswir1 | TCXState *ts = opaque; |
262 | eee0b836 | blueswir1 | ram_addr_t page, page_min, page_max, cpage, page24; |
263 | eee0b836 | blueswir1 | int y, y_start, dd, ds;
|
264 | eee0b836 | blueswir1 | uint8_t *d, *s; |
265 | eee0b836 | blueswir1 | uint32_t *cptr, *s24; |
266 | eee0b836 | blueswir1 | |
267 | 0e1f5a0c | aliguori | if (ds_get_bits_per_pixel(ts->ds) != 32) |
268 | eee0b836 | blueswir1 | return;
|
269 | eee0b836 | blueswir1 | page = ts->vram_offset; |
270 | eee0b836 | blueswir1 | page24 = ts->vram24_offset; |
271 | eee0b836 | blueswir1 | cpage = ts->cplane_offset; |
272 | eee0b836 | blueswir1 | y_start = -1;
|
273 | eee0b836 | blueswir1 | page_min = 0xffffffff;
|
274 | eee0b836 | blueswir1 | page_max = 0;
|
275 | 0e1f5a0c | aliguori | d = ds_get_data(ts->ds); |
276 | eee0b836 | blueswir1 | s = ts->vram; |
277 | eee0b836 | blueswir1 | s24 = ts->vram24; |
278 | eee0b836 | blueswir1 | cptr = ts->cplane; |
279 | 0e1f5a0c | aliguori | dd = ds_get_linesize(ts->ds); |
280 | eee0b836 | blueswir1 | ds = 1024;
|
281 | eee0b836 | blueswir1 | |
282 | eee0b836 | blueswir1 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
283 | eee0b836 | blueswir1 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
284 | 22548760 | blueswir1 | if (check_dirty(page, page24, cpage)) {
|
285 | eee0b836 | blueswir1 | if (y_start < 0) |
286 | eee0b836 | blueswir1 | y_start = y; |
287 | eee0b836 | blueswir1 | if (page < page_min)
|
288 | eee0b836 | blueswir1 | page_min = page; |
289 | eee0b836 | blueswir1 | if (page > page_max)
|
290 | eee0b836 | blueswir1 | page_max = page; |
291 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
292 | eee0b836 | blueswir1 | d += dd; |
293 | eee0b836 | blueswir1 | s += ds; |
294 | eee0b836 | blueswir1 | cptr += ds; |
295 | eee0b836 | blueswir1 | s24 += ds; |
296 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
297 | eee0b836 | blueswir1 | d += dd; |
298 | eee0b836 | blueswir1 | s += ds; |
299 | eee0b836 | blueswir1 | cptr += ds; |
300 | eee0b836 | blueswir1 | s24 += ds; |
301 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
302 | eee0b836 | blueswir1 | d += dd; |
303 | eee0b836 | blueswir1 | s += ds; |
304 | eee0b836 | blueswir1 | cptr += ds; |
305 | eee0b836 | blueswir1 | s24 += ds; |
306 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
307 | eee0b836 | blueswir1 | d += dd; |
308 | eee0b836 | blueswir1 | s += ds; |
309 | eee0b836 | blueswir1 | cptr += ds; |
310 | eee0b836 | blueswir1 | s24 += ds; |
311 | eee0b836 | blueswir1 | } else {
|
312 | eee0b836 | blueswir1 | if (y_start >= 0) { |
313 | eee0b836 | blueswir1 | /* flush to display */
|
314 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
315 | eee0b836 | blueswir1 | ts->width, y - y_start); |
316 | eee0b836 | blueswir1 | y_start = -1;
|
317 | eee0b836 | blueswir1 | } |
318 | eee0b836 | blueswir1 | d += dd * 4;
|
319 | eee0b836 | blueswir1 | s += ds * 4;
|
320 | eee0b836 | blueswir1 | cptr += ds * 4;
|
321 | eee0b836 | blueswir1 | s24 += ds * 4;
|
322 | eee0b836 | blueswir1 | } |
323 | eee0b836 | blueswir1 | } |
324 | eee0b836 | blueswir1 | if (y_start >= 0) { |
325 | eee0b836 | blueswir1 | /* flush to display */
|
326 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
327 | eee0b836 | blueswir1 | ts->width, y - y_start); |
328 | eee0b836 | blueswir1 | } |
329 | eee0b836 | blueswir1 | /* reset modified pages */
|
330 | eee0b836 | blueswir1 | if (page_min <= page_max) {
|
331 | eee0b836 | blueswir1 | reset_dirty(ts, page_min, page_max, page24, cpage); |
332 | eee0b836 | blueswir1 | } |
333 | eee0b836 | blueswir1 | } |
334 | eee0b836 | blueswir1 | |
335 | 95219897 | pbrook | static void tcx_invalidate_display(void *opaque) |
336 | 420557e8 | bellard | { |
337 | e80cfcfc | bellard | TCXState *s = opaque; |
338 | e80cfcfc | bellard | int i;
|
339 | e80cfcfc | bellard | |
340 | e80cfcfc | bellard | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
341 | f930d07e | blueswir1 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
342 | e80cfcfc | bellard | } |
343 | 420557e8 | bellard | } |
344 | 420557e8 | bellard | |
345 | eee0b836 | blueswir1 | static void tcx24_invalidate_display(void *opaque) |
346 | eee0b836 | blueswir1 | { |
347 | eee0b836 | blueswir1 | TCXState *s = opaque; |
348 | eee0b836 | blueswir1 | int i;
|
349 | eee0b836 | blueswir1 | |
350 | eee0b836 | blueswir1 | tcx_invalidate_display(s); |
351 | eee0b836 | blueswir1 | for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { |
352 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->vram24_offset + i); |
353 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->cplane_offset + i); |
354 | eee0b836 | blueswir1 | } |
355 | eee0b836 | blueswir1 | } |
356 | eee0b836 | blueswir1 | |
357 | e80cfcfc | bellard | static void tcx_save(QEMUFile *f, void *opaque) |
358 | 420557e8 | bellard | { |
359 | 420557e8 | bellard | TCXState *s = opaque; |
360 | 3b46e624 | ths | |
361 | b6c4f71f | blueswir1 | qemu_put_be16s(f, &s->height); |
362 | b6c4f71f | blueswir1 | qemu_put_be16s(f, &s->width); |
363 | b6c4f71f | blueswir1 | qemu_put_be16s(f, &s->depth); |
364 | e80cfcfc | bellard | qemu_put_buffer(f, s->r, 256);
|
365 | e80cfcfc | bellard | qemu_put_buffer(f, s->g, 256);
|
366 | e80cfcfc | bellard | qemu_put_buffer(f, s->b, 256);
|
367 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_index); |
368 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_state); |
369 | 420557e8 | bellard | } |
370 | 420557e8 | bellard | |
371 | e80cfcfc | bellard | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
372 | 420557e8 | bellard | { |
373 | e80cfcfc | bellard | TCXState *s = opaque; |
374 | fda77c2d | blueswir1 | uint32_t dummy; |
375 | fda77c2d | blueswir1 | |
376 | fda77c2d | blueswir1 | if (version_id != 3 && version_id != 4) |
377 | e80cfcfc | bellard | return -EINVAL;
|
378 | e80cfcfc | bellard | |
379 | fda77c2d | blueswir1 | if (version_id == 3) { |
380 | b6c4f71f | blueswir1 | qemu_get_be32s(f, &dummy); |
381 | b6c4f71f | blueswir1 | qemu_get_be32s(f, &dummy); |
382 | b6c4f71f | blueswir1 | qemu_get_be32s(f, &dummy); |
383 | fda77c2d | blueswir1 | } |
384 | b6c4f71f | blueswir1 | qemu_get_be16s(f, &s->height); |
385 | b6c4f71f | blueswir1 | qemu_get_be16s(f, &s->width); |
386 | b6c4f71f | blueswir1 | qemu_get_be16s(f, &s->depth); |
387 | e80cfcfc | bellard | qemu_get_buffer(f, s->r, 256);
|
388 | e80cfcfc | bellard | qemu_get_buffer(f, s->g, 256);
|
389 | e80cfcfc | bellard | qemu_get_buffer(f, s->b, 256);
|
390 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_index); |
391 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_state); |
392 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
393 | 97e7df27 | blueswir1 | if (s->depth == 24) |
394 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
395 | 97e7df27 | blueswir1 | else
|
396 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
397 | 5425a216 | blueswir1 | |
398 | e80cfcfc | bellard | return 0; |
399 | 420557e8 | bellard | } |
400 | 420557e8 | bellard | |
401 | e80cfcfc | bellard | static void tcx_reset(void *opaque) |
402 | 420557e8 | bellard | { |
403 | e80cfcfc | bellard | TCXState *s = opaque; |
404 | e80cfcfc | bellard | |
405 | e80cfcfc | bellard | /* Initialize palette */
|
406 | e80cfcfc | bellard | memset(s->r, 0, 256); |
407 | e80cfcfc | bellard | memset(s->g, 0, 256); |
408 | e80cfcfc | bellard | memset(s->b, 0, 256); |
409 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
410 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
411 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
|
412 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
413 | eee0b836 | blueswir1 | MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
414 | 6f7e9aec | bellard | s->dac_index = 0;
|
415 | 6f7e9aec | bellard | s->dac_state = 0;
|
416 | 6f7e9aec | bellard | } |
417 | 6f7e9aec | bellard | |
418 | 6f7e9aec | bellard | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
419 | 6f7e9aec | bellard | { |
420 | 6f7e9aec | bellard | return 0; |
421 | 6f7e9aec | bellard | } |
422 | 6f7e9aec | bellard | |
423 | 6f7e9aec | bellard | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
424 | 6f7e9aec | bellard | { |
425 | 6f7e9aec | bellard | TCXState *s = opaque; |
426 | 6f7e9aec | bellard | |
427 | e64d7d59 | blueswir1 | switch (addr) {
|
428 | 6f7e9aec | bellard | case 0: |
429 | f930d07e | blueswir1 | s->dac_index = val >> 24;
|
430 | f930d07e | blueswir1 | s->dac_state = 0;
|
431 | f930d07e | blueswir1 | break;
|
432 | e64d7d59 | blueswir1 | case 4: |
433 | f930d07e | blueswir1 | switch (s->dac_state) {
|
434 | f930d07e | blueswir1 | case 0: |
435 | f930d07e | blueswir1 | s->r[s->dac_index] = val >> 24;
|
436 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
437 | f930d07e | blueswir1 | s->dac_state++; |
438 | f930d07e | blueswir1 | break;
|
439 | f930d07e | blueswir1 | case 1: |
440 | f930d07e | blueswir1 | s->g[s->dac_index] = val >> 24;
|
441 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
442 | f930d07e | blueswir1 | s->dac_state++; |
443 | f930d07e | blueswir1 | break;
|
444 | f930d07e | blueswir1 | case 2: |
445 | f930d07e | blueswir1 | s->b[s->dac_index] = val >> 24;
|
446 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
447 | 5c8cdbf8 | blueswir1 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
448 | f930d07e | blueswir1 | default:
|
449 | f930d07e | blueswir1 | s->dac_state = 0;
|
450 | f930d07e | blueswir1 | break;
|
451 | f930d07e | blueswir1 | } |
452 | f930d07e | blueswir1 | break;
|
453 | 6f7e9aec | bellard | default:
|
454 | f930d07e | blueswir1 | break;
|
455 | 6f7e9aec | bellard | } |
456 | 6f7e9aec | bellard | return;
|
457 | 420557e8 | bellard | } |
458 | 420557e8 | bellard | |
459 | 6f7e9aec | bellard | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
460 | 7c560456 | blueswir1 | NULL,
|
461 | 7c560456 | blueswir1 | NULL,
|
462 | 6f7e9aec | bellard | tcx_dac_readl, |
463 | 6f7e9aec | bellard | }; |
464 | 6f7e9aec | bellard | |
465 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
466 | 7c560456 | blueswir1 | NULL,
|
467 | 7c560456 | blueswir1 | NULL,
|
468 | 6f7e9aec | bellard | tcx_dac_writel, |
469 | 6f7e9aec | bellard | }; |
470 | 6f7e9aec | bellard | |
471 | 8508b89e | blueswir1 | static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
472 | 8508b89e | blueswir1 | { |
473 | 8508b89e | blueswir1 | return 0; |
474 | 8508b89e | blueswir1 | } |
475 | 8508b89e | blueswir1 | |
476 | 8508b89e | blueswir1 | static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
477 | 8508b89e | blueswir1 | uint32_t val) |
478 | 8508b89e | blueswir1 | { |
479 | 8508b89e | blueswir1 | } |
480 | 8508b89e | blueswir1 | |
481 | 8508b89e | blueswir1 | static CPUReadMemoryFunc *tcx_dummy_read[3] = { |
482 | 7c560456 | blueswir1 | NULL,
|
483 | 7c560456 | blueswir1 | NULL,
|
484 | 8508b89e | blueswir1 | tcx_dummy_readl, |
485 | 8508b89e | blueswir1 | }; |
486 | 8508b89e | blueswir1 | |
487 | 8508b89e | blueswir1 | static CPUWriteMemoryFunc *tcx_dummy_write[3] = { |
488 | 7c560456 | blueswir1 | NULL,
|
489 | 7c560456 | blueswir1 | NULL,
|
490 | 8508b89e | blueswir1 | tcx_dummy_writel, |
491 | 8508b89e | blueswir1 | }; |
492 | 8508b89e | blueswir1 | |
493 | 3023f332 | aliguori | void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
|
494 | eee0b836 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
495 | eee0b836 | blueswir1 | int depth)
|
496 | 420557e8 | bellard | { |
497 | 420557e8 | bellard | TCXState *s; |
498 | 8508b89e | blueswir1 | int io_memory, dummy_memory;
|
499 | eee0b836 | blueswir1 | int size;
|
500 | 420557e8 | bellard | |
501 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
|
502 | 420557e8 | bellard | if (!s)
|
503 | 95219897 | pbrook | return;
|
504 | 8d5f07fa | bellard | s->addr = addr; |
505 | e80cfcfc | bellard | s->vram_offset = vram_offset; |
506 | 6f7e9aec | bellard | s->width = width; |
507 | 6f7e9aec | bellard | s->height = height; |
508 | eee0b836 | blueswir1 | s->depth = depth; |
509 | eee0b836 | blueswir1 | |
510 | eee0b836 | blueswir1 | // 8-bit plane
|
511 | eee0b836 | blueswir1 | s->vram = vram_base; |
512 | eee0b836 | blueswir1 | size = vram_size; |
513 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
|
514 | eee0b836 | blueswir1 | vram_offset += size; |
515 | eee0b836 | blueswir1 | vram_base += size; |
516 | e80cfcfc | bellard | |
517 | 6f7e9aec | bellard | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
|
518 | 77f193da | blueswir1 | cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
|
519 | 77f193da | blueswir1 | io_memory); |
520 | eee0b836 | blueswir1 | |
521 | 8508b89e | blueswir1 | dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
|
522 | 8508b89e | blueswir1 | s); |
523 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
|
524 | 8508b89e | blueswir1 | dummy_memory); |
525 | eee0b836 | blueswir1 | if (depth == 24) { |
526 | eee0b836 | blueswir1 | // 24-bit plane
|
527 | eee0b836 | blueswir1 | size = vram_size * 4;
|
528 | eee0b836 | blueswir1 | s->vram24 = (uint32_t *)vram_base; |
529 | eee0b836 | blueswir1 | s->vram24_offset = vram_offset; |
530 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
|
531 | eee0b836 | blueswir1 | vram_offset += size; |
532 | eee0b836 | blueswir1 | vram_base += size; |
533 | eee0b836 | blueswir1 | |
534 | eee0b836 | blueswir1 | // Control plane
|
535 | eee0b836 | blueswir1 | size = vram_size * 4;
|
536 | eee0b836 | blueswir1 | s->cplane = (uint32_t *)vram_base; |
537 | eee0b836 | blueswir1 | s->cplane_offset = vram_offset; |
538 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
|
539 | 3023f332 | aliguori | s->ds = graphic_console_init(tcx24_update_display, |
540 | 3023f332 | aliguori | tcx24_invalidate_display, |
541 | 3023f332 | aliguori | tcx24_screen_dump, NULL, s);
|
542 | eee0b836 | blueswir1 | } else {
|
543 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
|
544 | 8508b89e | blueswir1 | dummy_memory); |
545 | 3023f332 | aliguori | s->ds = graphic_console_init(tcx_update_display, |
546 | 3023f332 | aliguori | tcx_invalidate_display, |
547 | 3023f332 | aliguori | tcx_screen_dump, NULL, s);
|
548 | eee0b836 | blueswir1 | } |
549 | f96f4c9d | blueswir1 | // NetBSD writes here even with 8-bit display
|
550 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
|
551 | f96f4c9d | blueswir1 | dummy_memory); |
552 | e80cfcfc | bellard | |
553 | fda77c2d | blueswir1 | register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
554 | e80cfcfc | bellard | qemu_register_reset(tcx_reset, s); |
555 | e80cfcfc | bellard | tcx_reset(s); |
556 | 3023f332 | aliguori | qemu_console_resize(s->ds, width, height); |
557 | 420557e8 | bellard | } |
558 | 420557e8 | bellard | |
559 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename) |
560 | 8d5f07fa | bellard | { |
561 | e80cfcfc | bellard | TCXState *s = opaque; |
562 | 8d5f07fa | bellard | FILE *f; |
563 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
564 | 8d5f07fa | bellard | int y, x;
|
565 | 8d5f07fa | bellard | |
566 | 8d5f07fa | bellard | f = fopen(filename, "wb");
|
567 | 8d5f07fa | bellard | if (!f)
|
568 | e80cfcfc | bellard | return;
|
569 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
570 | 6f7e9aec | bellard | d1 = s->vram; |
571 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
572 | 8d5f07fa | bellard | d = d1; |
573 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
574 | 8d5f07fa | bellard | v = *d; |
575 | e80cfcfc | bellard | fputc(s->r[v], f); |
576 | e80cfcfc | bellard | fputc(s->g[v], f); |
577 | e80cfcfc | bellard | fputc(s->b[v], f); |
578 | 8d5f07fa | bellard | d++; |
579 | 8d5f07fa | bellard | } |
580 | e80cfcfc | bellard | d1 += MAXX; |
581 | 8d5f07fa | bellard | } |
582 | 8d5f07fa | bellard | fclose(f); |
583 | 8d5f07fa | bellard | return;
|
584 | 8d5f07fa | bellard | } |
585 | 8d5f07fa | bellard | |
586 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename) |
587 | eee0b836 | blueswir1 | { |
588 | eee0b836 | blueswir1 | TCXState *s = opaque; |
589 | eee0b836 | blueswir1 | FILE *f; |
590 | eee0b836 | blueswir1 | uint8_t *d, *d1, v; |
591 | eee0b836 | blueswir1 | uint32_t *s24, *cptr, dval; |
592 | eee0b836 | blueswir1 | int y, x;
|
593 | 8d5f07fa | bellard | |
594 | eee0b836 | blueswir1 | f = fopen(filename, "wb");
|
595 | eee0b836 | blueswir1 | if (!f)
|
596 | eee0b836 | blueswir1 | return;
|
597 | eee0b836 | blueswir1 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
598 | eee0b836 | blueswir1 | d1 = s->vram; |
599 | eee0b836 | blueswir1 | s24 = s->vram24; |
600 | eee0b836 | blueswir1 | cptr = s->cplane; |
601 | eee0b836 | blueswir1 | for(y = 0; y < s->height; y++) { |
602 | eee0b836 | blueswir1 | d = d1; |
603 | eee0b836 | blueswir1 | for(x = 0; x < s->width; x++, d++, s24++) { |
604 | eee0b836 | blueswir1 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
605 | eee0b836 | blueswir1 | dval = *s24 & 0x00ffffff;
|
606 | eee0b836 | blueswir1 | fputc((dval >> 16) & 0xff, f); |
607 | eee0b836 | blueswir1 | fputc((dval >> 8) & 0xff, f); |
608 | eee0b836 | blueswir1 | fputc(dval & 0xff, f);
|
609 | eee0b836 | blueswir1 | } else {
|
610 | eee0b836 | blueswir1 | v = *d; |
611 | eee0b836 | blueswir1 | fputc(s->r[v], f); |
612 | eee0b836 | blueswir1 | fputc(s->g[v], f); |
613 | eee0b836 | blueswir1 | fputc(s->b[v], f); |
614 | eee0b836 | blueswir1 | } |
615 | eee0b836 | blueswir1 | } |
616 | eee0b836 | blueswir1 | d1 += MAXX; |
617 | eee0b836 | blueswir1 | } |
618 | eee0b836 | blueswir1 | fclose(f); |
619 | eee0b836 | blueswir1 | return;
|
620 | eee0b836 | blueswir1 | } |