root / hw / ppc_oldworld.c @ 3023f332
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/*
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* QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc_mac.h" |
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#include "nvram.h" |
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#include "pc.h" |
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#include "sysemu.h" |
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#include "net.h" |
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#include "isa.h" |
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#include "pci.h" |
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#include "boards.h" |
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#include "fw_cfg.h" |
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#include "escc.h" |
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#define MAX_IDE_BUS 2 |
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#define VGA_BIOS_SIZE 65536 |
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#define CFG_ADDR 0xf0000510 |
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/* temporary frame buffer OSI calls for the video.x driver. The right
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solution is to modify the driver to use VGA PCI I/Os */
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/* XXX: to be removed. This is no way related to emulation */
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static int vga_osi_call (CPUState *env) |
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{ |
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static int vga_vbl_enabled; |
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int linesize;
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// printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
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/* same handler as PearPC, coming from the original MOL video
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driver. */
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switch(env->gpr[5]) { |
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case 4: |
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break;
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case 28: /* set_vmode */ |
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if (env->gpr[6] != 1 || env->gpr[7] != 0) |
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env->gpr[3] = 1; |
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else
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env->gpr[3] = 0; |
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break;
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case 29: /* get_vmode_info */ |
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if (env->gpr[6] != 0) { |
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if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
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env->gpr[3] = 1; |
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break;
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} |
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} |
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env->gpr[3] = 0; |
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env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
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env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
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env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
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env->gpr[7] = 85 << 16; /* refresh rate */ |
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
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linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
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linesize = (linesize + 3) & ~3; |
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env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
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break;
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case 31: /* set_video power */ |
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env->gpr[3] = 0; |
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break;
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case 39: /* video_ctrl */ |
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if (env->gpr[6] == 0 || env->gpr[6] == 1) |
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vga_vbl_enabled = env->gpr[6];
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env->gpr[3] = 0; |
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break;
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case 47: |
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break;
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case 59: /* set_color */ |
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/* R6 = index, R7 = RGB */
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env->gpr[3] = 0; |
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break;
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case 64: /* get color */ |
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/* R6 = index */
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env->gpr[3] = 0; |
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break;
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case 116: /* set hwcursor */ |
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=" REGX "\n", |
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ppc_dump_gpr(env, 5));
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break;
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} |
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return 1; /* osi_call handled */ |
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} |
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static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, |
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const char *boot_device, |
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const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename, |
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const char *cpu_model) |
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{ |
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CPUState *env = NULL, *envs[MAX_CPUS];
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char buf[1024]; |
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qemu_irq *pic, **heathrow_irqs; |
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nvram_t nvram; |
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m48t59_t *m48t59; |
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int linux_boot, i;
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ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset; |
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
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PCIBus *pci_bus; |
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MacIONVRAMState *nvr; |
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int vga_bios_size, bios_size;
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qemu_irq *dummy_irq; |
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int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
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int escc_mem_index, ide_mem_index[2]; |
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int ppc_boot_device;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
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int index;
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void *fw_cfg;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (cpu_model == NULL) |
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cpu_model = "G3";
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for (i = 0; i < smp_cpus; i++) { |
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env = cpu_init(cpu_model); |
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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} |
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/* Set time-base frequency to 16.6 Mhz */
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cpu_ppc_tb_init(env, 16600000UL);
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env->osi_call = vga_osi_call; |
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qemu_register_reset(&cpu_ppc_reset, env); |
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envs[i] = env; |
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} |
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if (env->nip < 0xFFF80000) { |
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/* Special test for PowerPC 601:
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* the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
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* But the NVRAM is located at 0xFFF04000...
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*/
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cpu_abort(env, "G3 Beige Mac hardware can not handle 1 MB BIOS\n");
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} |
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/* allocate RAM */
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if (ram_size > (2047 << 20)) { |
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fprintf(stderr, |
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"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
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((unsigned int)ram_size / (1 << 20))); |
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exit(1);
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} |
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ram_offset = qemu_ram_alloc(ram_size); |
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cpu_register_physical_memory(0, ram_size, ram_offset);
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/* allocate VGA RAM */
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vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
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/* allocate and load BIOS */
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bios_offset = qemu_ram_alloc(BIOS_SIZE); |
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if (bios_name == NULL) |
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bios_name = PROM_FILENAME; |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
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cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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/* Load OpenBIOS (ELF) */
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bios_size = load_elf(buf, 0, NULL, NULL, NULL); |
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if (bios_size < 0 || bios_size > BIOS_SIZE) { |
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cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
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exit(1);
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} |
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/* allocate and load VGA BIOS */
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vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE); |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
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vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
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if (vga_bios_size < 0) { |
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/* if no bios is present, we can still work */
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fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
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vga_bios_size = 0;
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} else {
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/* set a specific header (XXX: find real Apple format for NDRV
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drivers) */
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phys_ram_base[vga_bios_offset] = 'N';
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phys_ram_base[vga_bios_offset + 1] = 'D'; |
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phys_ram_base[vga_bios_offset + 2] = 'R'; |
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phys_ram_base[vga_bios_offset + 3] = 'V'; |
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cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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vga_bios_size); |
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vga_bios_size += 8;
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} |
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR; |
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/* now we can load the kernel */
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kernel_size = load_elf(kernel_filename, kernel_base - 0xc0000000ULL,
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NULL, NULL, NULL); |
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, kernel_base, |
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ram_size - kernel_base); |
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if (kernel_size < 0) |
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kernel_size = load_image_targphys(kernel_filename, |
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kernel_base, |
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ram_size - kernel_base); |
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if (kernel_size < 0) { |
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cpu_abort(env, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR; |
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initrd_size = load_image(initrd_filename, |
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phys_ram_base + initrd_base); |
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if (initrd_size < 0) { |
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cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} else {
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initrd_base = 0;
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initrd_size = 0;
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} |
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ppc_boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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ppc_boot_device = '\0';
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for (i = 0; boot_device[i] != '\0'; i++) { |
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/* TOFIX: for now, the second IDE channel is not properly
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* used by OHW. The Mac floppy disk are not emulated.
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* For now, OHW cannot boot from the network.
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*/
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#if 0
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if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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break;
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}
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#else
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if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { |
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ppc_boot_device = boot_device[i]; |
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break;
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} |
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#endif
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} |
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if (ppc_boot_device == '\0') { |
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fprintf(stderr, "No valid boot device for G3 Beige machine\n");
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exit(1);
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} |
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} |
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isa_mem_base = 0x80000000;
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/* Register 2 MB of ISA IO space */
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isa_mmio_init(0xfe000000, 0x00200000); |
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/* XXX: we register only 1 output pin for heathrow PIC */
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heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
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heathrow_irqs[0] =
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qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1); |
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/* Connect the heathrow PIC outputs to the 6xx bus */
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for (i = 0; i < smp_cpus; i++) { |
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); |
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heathrow_irqs[i][0] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
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break;
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default:
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cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
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exit(1);
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} |
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} |
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/* init basic PC hardware */
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if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
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exit(1);
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} |
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pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
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pci_bus = pci_grackle_init(0xfec00000, pic);
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pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset, |
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vga_ram_offset, vga_ram_size, |
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vga_bios_offset, vga_bios_size); |
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/* XXX: suppress that */
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dummy_irq = i8259_init(NULL);
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escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], |
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serial_hds[1], ESCC_CLOCK, 4); |
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|
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for(i = 0; i < nb_nics; i++) |
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pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); |
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|
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/* First IDE channel is a CMD646 on the PCI bus */
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|
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if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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fprintf(stderr, "qemu: too many IDE bus\n");
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exit(1);
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} |
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index = drive_get_index(IF_IDE, 0, 0); |
320 |
if (index == -1) |
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hd[0] = NULL; |
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else
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hd[0] = drives_table[index].bdrv;
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index = drive_get_index(IF_IDE, 0, 1); |
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if (index == -1) |
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hd[1] = NULL; |
327 |
else
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hd[1] = drives_table[index].bdrv;
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hd[3] = hd[2] = NULL; |
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pci_cmd646_ide_init(pci_bus, hd, 0);
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/* Second IDE channel is a MAC IDE on the MacIO bus */
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index = drive_get_index(IF_IDE, 1, 0); |
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if (index == -1) |
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hd[0] = NULL; |
336 |
else
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hd[0] = drives_table[index].bdrv;
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index = drive_get_index(IF_IDE, 1, 1); |
339 |
if (index == -1) |
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hd[1] = NULL; |
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else
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hd[1] = drives_table[index].bdrv;
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ide_mem_index[0] = -1; |
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ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]); |
345 |
|
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/* cuda also initialize ADB */
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cuda_init(&cuda_mem_index, pic[0x12]);
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|
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adb_kbd_init(&adb_bus); |
350 |
adb_mouse_init(&adb_bus); |
351 |
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nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
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pmac_format_nvram_partition(nvr, 0x2000);
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|
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dbdma_init(&dbdma_mem_index); |
356 |
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macio_init(pci_bus, 0x0010, 1, pic_mem_index, dbdma_mem_index, |
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cuda_mem_index, nvr, 2, ide_mem_index, escc_mem_index);
|
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|
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if (usb_enabled) {
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usb_ohci_init_pci(pci_bus, 3, -1); |
362 |
} |
363 |
|
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if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
365 |
graphic_depth = 15;
|
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|
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m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
368 |
nvram.opaque = m48t59; |
369 |
nvram.read_fn = &m48t59_read; |
370 |
nvram.write_fn = &m48t59_write; |
371 |
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
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ppc_boot_device, kernel_base, kernel_size, |
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kernel_cmdline, |
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initrd_base, initrd_size, |
375 |
/* XXX: need an option to load a NVRAM image */
|
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0,
|
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graphic_width, graphic_height, graphic_depth); |
378 |
/* No PCI init: the BIOS will do it */
|
379 |
|
380 |
/* Special port to get debug messages from Open-Firmware */
|
381 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
382 |
|
383 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
384 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
385 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
386 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); |
387 |
} |
388 |
|
389 |
QEMUMachine heathrow_machine = { |
390 |
.name = "g3beige",
|
391 |
.desc = "Heathrow based PowerMAC",
|
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.init = ppc_heathrow_init, |
393 |
.ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE, |
394 |
.max_cpus = MAX_CPUS, |
395 |
}; |