Revision 30a8cac1
b/target-arm/helper.c | ||
---|---|---|
824 | 824 |
env->spsr = cpsr_read(env); |
825 | 825 |
/* Clear IT bits. */ |
826 | 826 |
env->condexec_bits = 0; |
827 |
/* Switch to the new mode, and switch to Arm mode. */ |
|
828 |
/* ??? Thumb interrupt handlers not implemented. */ |
|
827 |
/* Switch to the new mode, and to the correct instruction set. */ |
|
829 | 828 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
830 | 829 |
env->uncached_cpsr |= mask; |
831 |
env->thumb = 0; |
|
830 |
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
|
|
832 | 831 |
env->regs[14] = env->regs[15] + offset; |
833 | 832 |
env->regs[15] = addr; |
834 | 833 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
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