root / target-arm / helper.c @ 30b05bba
History | View | Annotate | Download (99.5 kB)
| 1 |
#include "cpu.h" |
|---|---|
| 2 |
#include "gdbstub.h" |
| 3 |
#include "helper.h" |
| 4 |
#include "host-utils.h" |
| 5 |
#include "sysemu.h" |
| 6 |
|
| 7 |
#ifndef CONFIG_USER_ONLY
|
| 8 |
static inline int get_phys_addr(CPUARMState *env, uint32_t address, |
| 9 |
int access_type, int is_user, |
| 10 |
uint32_t *phys_ptr, int *prot,
|
| 11 |
target_ulong *page_size); |
| 12 |
#endif
|
| 13 |
|
| 14 |
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
| 15 |
{
|
| 16 |
int nregs;
|
| 17 |
|
| 18 |
/* VFP data registers are always little-endian. */
|
| 19 |
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
| 20 |
if (reg < nregs) {
|
| 21 |
stfq_le_p(buf, env->vfp.regs[reg]); |
| 22 |
return 8; |
| 23 |
} |
| 24 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
| 25 |
/* Aliases for Q regs. */
|
| 26 |
nregs += 16;
|
| 27 |
if (reg < nregs) {
|
| 28 |
stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); |
| 29 |
stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); |
| 30 |
return 16; |
| 31 |
} |
| 32 |
} |
| 33 |
switch (reg - nregs) {
|
| 34 |
case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; |
| 35 |
case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; |
| 36 |
case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
| 37 |
} |
| 38 |
return 0; |
| 39 |
} |
| 40 |
|
| 41 |
static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
| 42 |
{
|
| 43 |
int nregs;
|
| 44 |
|
| 45 |
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
| 46 |
if (reg < nregs) {
|
| 47 |
env->vfp.regs[reg] = ldfq_le_p(buf); |
| 48 |
return 8; |
| 49 |
} |
| 50 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
| 51 |
nregs += 16;
|
| 52 |
if (reg < nregs) {
|
| 53 |
env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); |
| 54 |
env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); |
| 55 |
return 16; |
| 56 |
} |
| 57 |
} |
| 58 |
switch (reg - nregs) {
|
| 59 |
case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; |
| 60 |
case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; |
| 61 |
case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
| 62 |
} |
| 63 |
return 0; |
| 64 |
} |
| 65 |
|
| 66 |
static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 67 |
{
|
| 68 |
env->cp15.c3 = value; |
| 69 |
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
| 70 |
return 0; |
| 71 |
} |
| 72 |
|
| 73 |
static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 74 |
{
|
| 75 |
if (env->cp15.c13_fcse != value) {
|
| 76 |
/* Unlike real hardware the qemu TLB uses virtual addresses,
|
| 77 |
* not modified virtual addresses, so this causes a TLB flush.
|
| 78 |
*/
|
| 79 |
tlb_flush(env, 1);
|
| 80 |
env->cp15.c13_fcse = value; |
| 81 |
} |
| 82 |
return 0; |
| 83 |
} |
| 84 |
static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 85 |
uint64_t value) |
| 86 |
{
|
| 87 |
if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
|
| 88 |
/* For VMSA (when not using the LPAE long descriptor page table
|
| 89 |
* format) this register includes the ASID, so do a TLB flush.
|
| 90 |
* For PMSA it is purely a process ID and no action is needed.
|
| 91 |
*/
|
| 92 |
tlb_flush(env, 1);
|
| 93 |
} |
| 94 |
env->cp15.c13_context = value; |
| 95 |
return 0; |
| 96 |
} |
| 97 |
|
| 98 |
static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 99 |
uint64_t value) |
| 100 |
{
|
| 101 |
/* Invalidate all (TLBIALL) */
|
| 102 |
tlb_flush(env, 1);
|
| 103 |
return 0; |
| 104 |
} |
| 105 |
|
| 106 |
static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 107 |
uint64_t value) |
| 108 |
{
|
| 109 |
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
|
| 110 |
tlb_flush_page(env, value & TARGET_PAGE_MASK); |
| 111 |
return 0; |
| 112 |
} |
| 113 |
|
| 114 |
static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 115 |
uint64_t value) |
| 116 |
{
|
| 117 |
/* Invalidate by ASID (TLBIASID) */
|
| 118 |
tlb_flush(env, value == 0);
|
| 119 |
return 0; |
| 120 |
} |
| 121 |
|
| 122 |
static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 123 |
uint64_t value) |
| 124 |
{
|
| 125 |
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
|
| 126 |
tlb_flush_page(env, value & TARGET_PAGE_MASK); |
| 127 |
return 0; |
| 128 |
} |
| 129 |
|
| 130 |
static const ARMCPRegInfo cp_reginfo[] = { |
| 131 |
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
|
| 132 |
* version" bits will read as a reserved value, which should cause
|
| 133 |
* Linux to not try to use the debug hardware.
|
| 134 |
*/
|
| 135 |
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 136 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 137 |
/* MMU Domain access control / MPU write buffer control */
|
| 138 |
{ .name = "DACR", .cp = 15,
|
| 139 |
.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
|
| 140 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), |
| 141 |
.resetvalue = 0, .writefn = dacr_write },
|
| 142 |
{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 143 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), |
| 144 |
.resetvalue = 0, .writefn = fcse_write },
|
| 145 |
{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 146 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), |
| 147 |
.resetvalue = 0, .writefn = contextidr_write },
|
| 148 |
/* ??? This covers not just the impdef TLB lockdown registers but also
|
| 149 |
* some v7VMSA registers relating to TEX remap, so it is overly broad.
|
| 150 |
*/
|
| 151 |
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
|
| 152 |
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
| 153 |
/* MMU TLB control. Note that the wildcarding means we cover not just
|
| 154 |
* the unified TLB ops but also the dside/iside/inner-shareable variants.
|
| 155 |
*/
|
| 156 |
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
|
| 157 |
.opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
|
| 158 |
{ .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
|
| 159 |
.opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
|
| 160 |
{ .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
|
| 161 |
.opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
|
| 162 |
{ .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
|
| 163 |
.opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
|
| 164 |
/* Cache maintenance ops; some of this space may be overridden later. */
|
| 165 |
{ .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
|
| 166 |
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
|
| 167 |
.type = ARM_CP_NOP | ARM_CP_OVERRIDE }, |
| 168 |
REGINFO_SENTINEL |
| 169 |
}; |
| 170 |
|
| 171 |
static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
| 172 |
/* Not all pre-v6 cores implemented this WFI, so this is slightly
|
| 173 |
* over-broad.
|
| 174 |
*/
|
| 175 |
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
|
| 176 |
.access = PL1_W, .type = ARM_CP_WFI }, |
| 177 |
REGINFO_SENTINEL |
| 178 |
}; |
| 179 |
|
| 180 |
static const ARMCPRegInfo not_v7_cp_reginfo[] = { |
| 181 |
/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
|
| 182 |
* is UNPREDICTABLE; we choose to NOP as most implementations do).
|
| 183 |
*/
|
| 184 |
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
|
| 185 |
.access = PL1_W, .type = ARM_CP_WFI }, |
| 186 |
/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
|
| 187 |
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
|
| 188 |
* OMAPCP will override this space.
|
| 189 |
*/
|
| 190 |
{ .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 191 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), |
| 192 |
.resetvalue = 0 },
|
| 193 |
{ .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 194 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), |
| 195 |
.resetvalue = 0 },
|
| 196 |
/* v6 doesn't have the cache ID registers but Linux reads them anyway */
|
| 197 |
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
|
| 198 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 199 |
REGINFO_SENTINEL |
| 200 |
}; |
| 201 |
|
| 202 |
static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 203 |
{
|
| 204 |
if (env->cp15.c1_coproc != value) {
|
| 205 |
env->cp15.c1_coproc = value; |
| 206 |
/* ??? Is this safe when called from within a TB? */
|
| 207 |
tb_flush(env); |
| 208 |
} |
| 209 |
return 0; |
| 210 |
} |
| 211 |
|
| 212 |
static const ARMCPRegInfo v6_cp_reginfo[] = { |
| 213 |
/* prefetch by MVA in v6, NOP in v7 */
|
| 214 |
{ .name = "MVA_prefetch",
|
| 215 |
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, |
| 216 |
.access = PL1_W, .type = ARM_CP_NOP }, |
| 217 |
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
|
| 218 |
.access = PL0_W, .type = ARM_CP_NOP }, |
| 219 |
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
|
| 220 |
.access = PL0_W, .type = ARM_CP_NOP }, |
| 221 |
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
|
| 222 |
.access = PL0_W, .type = ARM_CP_NOP }, |
| 223 |
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 224 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
| 225 |
.resetvalue = 0, },
|
| 226 |
/* Watchpoint Fault Address Register : should actually only be present
|
| 227 |
* for 1136, 1176, 11MPCore.
|
| 228 |
*/
|
| 229 |
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 230 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
|
| 231 |
{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 232 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
| 233 |
.resetvalue = 0, .writefn = cpacr_write },
|
| 234 |
REGINFO_SENTINEL |
| 235 |
}; |
| 236 |
|
| 237 |
static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 238 |
uint64_t *value) |
| 239 |
{
|
| 240 |
/* Generic performance monitor register read function for where
|
| 241 |
* user access may be allowed by PMUSERENR.
|
| 242 |
*/
|
| 243 |
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
| 244 |
return EXCP_UDEF;
|
| 245 |
} |
| 246 |
*value = CPREG_FIELD32(env, ri); |
| 247 |
return 0; |
| 248 |
} |
| 249 |
|
| 250 |
static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 251 |
uint64_t value) |
| 252 |
{
|
| 253 |
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
| 254 |
return EXCP_UDEF;
|
| 255 |
} |
| 256 |
/* only the DP, X, D and E bits are writable */
|
| 257 |
env->cp15.c9_pmcr &= ~0x39;
|
| 258 |
env->cp15.c9_pmcr |= (value & 0x39);
|
| 259 |
return 0; |
| 260 |
} |
| 261 |
|
| 262 |
static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 263 |
uint64_t value) |
| 264 |
{
|
| 265 |
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
| 266 |
return EXCP_UDEF;
|
| 267 |
} |
| 268 |
value &= (1 << 31); |
| 269 |
env->cp15.c9_pmcnten |= value; |
| 270 |
return 0; |
| 271 |
} |
| 272 |
|
| 273 |
static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 274 |
uint64_t value) |
| 275 |
{
|
| 276 |
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
| 277 |
return EXCP_UDEF;
|
| 278 |
} |
| 279 |
value &= (1 << 31); |
| 280 |
env->cp15.c9_pmcnten &= ~value; |
| 281 |
return 0; |
| 282 |
} |
| 283 |
|
| 284 |
static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 285 |
uint64_t value) |
| 286 |
{
|
| 287 |
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
| 288 |
return EXCP_UDEF;
|
| 289 |
} |
| 290 |
env->cp15.c9_pmovsr &= ~value; |
| 291 |
return 0; |
| 292 |
} |
| 293 |
|
| 294 |
static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 295 |
uint64_t value) |
| 296 |
{
|
| 297 |
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
| 298 |
return EXCP_UDEF;
|
| 299 |
} |
| 300 |
env->cp15.c9_pmxevtyper = value & 0xff;
|
| 301 |
return 0; |
| 302 |
} |
| 303 |
|
| 304 |
static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 305 |
uint64_t value) |
| 306 |
{
|
| 307 |
env->cp15.c9_pmuserenr = value & 1;
|
| 308 |
return 0; |
| 309 |
} |
| 310 |
|
| 311 |
static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 312 |
uint64_t value) |
| 313 |
{
|
| 314 |
/* We have no event counters so only the C bit can be changed */
|
| 315 |
value &= (1 << 31); |
| 316 |
env->cp15.c9_pminten |= value; |
| 317 |
return 0; |
| 318 |
} |
| 319 |
|
| 320 |
static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 321 |
uint64_t value) |
| 322 |
{
|
| 323 |
value &= (1 << 31); |
| 324 |
env->cp15.c9_pminten &= ~value; |
| 325 |
return 0; |
| 326 |
} |
| 327 |
|
| 328 |
static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 329 |
uint64_t *value) |
| 330 |
{
|
| 331 |
ARMCPU *cpu = arm_env_get_cpu(env); |
| 332 |
*value = cpu->ccsidr[env->cp15.c0_cssel]; |
| 333 |
return 0; |
| 334 |
} |
| 335 |
|
| 336 |
static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 337 |
uint64_t value) |
| 338 |
{
|
| 339 |
env->cp15.c0_cssel = value & 0xf;
|
| 340 |
return 0; |
| 341 |
} |
| 342 |
|
| 343 |
static const ARMCPRegInfo v7_cp_reginfo[] = { |
| 344 |
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
|
| 345 |
* debug components
|
| 346 |
*/
|
| 347 |
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 348 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 349 |
{ .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 350 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 351 |
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
|
| 352 |
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
|
| 353 |
.access = PL1_W, .type = ARM_CP_NOP }, |
| 354 |
/* Performance monitors are implementation defined in v7,
|
| 355 |
* but with an ARM recommended set of registers, which we
|
| 356 |
* follow (although we don't actually implement any counters)
|
| 357 |
*
|
| 358 |
* Performance registers fall into three categories:
|
| 359 |
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
|
| 360 |
* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
|
| 361 |
* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
|
| 362 |
* For the cases controlled by PMUSERENR we must set .access to PL0_RW
|
| 363 |
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
|
| 364 |
*/
|
| 365 |
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
|
| 366 |
.access = PL0_RW, .resetvalue = 0,
|
| 367 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
| 368 |
.readfn = pmreg_read, .writefn = pmcntenset_write }, |
| 369 |
{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
|
| 370 |
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
| 371 |
.readfn = pmreg_read, .writefn = pmcntenclr_write }, |
| 372 |
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
|
| 373 |
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
| 374 |
.readfn = pmreg_read, .writefn = pmovsr_write }, |
| 375 |
/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
|
| 376 |
* respect PMUSERENR.
|
| 377 |
*/
|
| 378 |
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
|
| 379 |
.access = PL0_W, .type = ARM_CP_NOP }, |
| 380 |
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
|
| 381 |
* We choose to RAZ/WI. XXX should respect PMUSERENR.
|
| 382 |
*/
|
| 383 |
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
|
| 384 |
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 385 |
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
|
| 386 |
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
|
| 387 |
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 388 |
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
|
| 389 |
.access = PL0_RW, |
| 390 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), |
| 391 |
.readfn = pmreg_read, .writefn = pmxevtyper_write }, |
| 392 |
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
|
| 393 |
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
|
| 394 |
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 395 |
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
|
| 396 |
.access = PL0_R | PL1_RW, |
| 397 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
| 398 |
.resetvalue = 0,
|
| 399 |
.writefn = pmuserenr_write }, |
| 400 |
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
|
| 401 |
.access = PL1_RW, |
| 402 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
| 403 |
.resetvalue = 0,
|
| 404 |
.writefn = pmintenset_write }, |
| 405 |
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
|
| 406 |
.access = PL1_RW, |
| 407 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
| 408 |
.resetvalue = 0,
|
| 409 |
.writefn = pmintenclr_write }, |
| 410 |
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
|
| 411 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), |
| 412 |
.resetvalue = 0, },
|
| 413 |
{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
|
| 414 |
.access = PL1_R, .readfn = ccsidr_read }, |
| 415 |
{ .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
|
| 416 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), |
| 417 |
.writefn = csselr_write, .resetvalue = 0 },
|
| 418 |
/* Auxiliary ID register: this actually has an IMPDEF value but for now
|
| 419 |
* just RAZ for all cores:
|
| 420 |
*/
|
| 421 |
{ .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
|
| 422 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 423 |
REGINFO_SENTINEL |
| 424 |
}; |
| 425 |
|
| 426 |
static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 427 |
{
|
| 428 |
value &= 1;
|
| 429 |
env->teecr = value; |
| 430 |
return 0; |
| 431 |
} |
| 432 |
|
| 433 |
static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 434 |
uint64_t *value) |
| 435 |
{
|
| 436 |
/* This is a helper function because the user access rights
|
| 437 |
* depend on the value of the TEECR.
|
| 438 |
*/
|
| 439 |
if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
| 440 |
return EXCP_UDEF;
|
| 441 |
} |
| 442 |
*value = env->teehbr; |
| 443 |
return 0; |
| 444 |
} |
| 445 |
|
| 446 |
static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 447 |
uint64_t value) |
| 448 |
{
|
| 449 |
if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
| 450 |
return EXCP_UDEF;
|
| 451 |
} |
| 452 |
env->teehbr = value; |
| 453 |
return 0; |
| 454 |
} |
| 455 |
|
| 456 |
static const ARMCPRegInfo t2ee_cp_reginfo[] = { |
| 457 |
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
|
| 458 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), |
| 459 |
.resetvalue = 0,
|
| 460 |
.writefn = teecr_write }, |
| 461 |
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
|
| 462 |
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), |
| 463 |
.resetvalue = 0,
|
| 464 |
.readfn = teehbr_read, .writefn = teehbr_write }, |
| 465 |
REGINFO_SENTINEL |
| 466 |
}; |
| 467 |
|
| 468 |
static const ARMCPRegInfo v6k_cp_reginfo[] = { |
| 469 |
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 470 |
.access = PL0_RW, |
| 471 |
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls1), |
| 472 |
.resetvalue = 0 },
|
| 473 |
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
|
| 474 |
.access = PL0_R|PL1_W, |
| 475 |
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls2), |
| 476 |
.resetvalue = 0 },
|
| 477 |
{ .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
|
| 478 |
.access = PL1_RW, |
| 479 |
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls3), |
| 480 |
.resetvalue = 0 },
|
| 481 |
REGINFO_SENTINEL |
| 482 |
}; |
| 483 |
|
| 484 |
static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
| 485 |
/* Dummy implementation: RAZ/WI the whole crn=14 space */
|
| 486 |
{ .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
|
| 487 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, |
| 488 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 489 |
REGINFO_SENTINEL |
| 490 |
}; |
| 491 |
|
| 492 |
static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 493 |
{
|
| 494 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
| 495 |
env->cp15.c7_par = value & 0xfffff6ff;
|
| 496 |
} else {
|
| 497 |
env->cp15.c7_par = value & 0xfffff1ff;
|
| 498 |
} |
| 499 |
return 0; |
| 500 |
} |
| 501 |
|
| 502 |
#ifndef CONFIG_USER_ONLY
|
| 503 |
/* get_phys_addr() isn't present for user-mode-only targets */
|
| 504 |
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 505 |
{
|
| 506 |
uint32_t phys_addr; |
| 507 |
target_ulong page_size; |
| 508 |
int prot;
|
| 509 |
int ret, is_user = ri->opc2 & 2; |
| 510 |
int access_type = ri->opc2 & 1; |
| 511 |
|
| 512 |
if (ri->opc2 & 4) { |
| 513 |
/* Other states are only available with TrustZone */
|
| 514 |
return EXCP_UDEF;
|
| 515 |
} |
| 516 |
ret = get_phys_addr(env, value, access_type, is_user, |
| 517 |
&phys_addr, &prot, &page_size); |
| 518 |
if (ret == 0) { |
| 519 |
/* We do not set any attribute bits in the PAR */
|
| 520 |
if (page_size == (1 << 24) |
| 521 |
&& arm_feature(env, ARM_FEATURE_V7)) {
|
| 522 |
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; |
| 523 |
} else {
|
| 524 |
env->cp15.c7_par = phys_addr & 0xfffff000;
|
| 525 |
} |
| 526 |
} else {
|
| 527 |
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) | |
| 528 |
((ret & (12 << 1)) >> 6) | |
| 529 |
((ret & 0xf) << 1) | 1; |
| 530 |
} |
| 531 |
return 0; |
| 532 |
} |
| 533 |
#endif
|
| 534 |
|
| 535 |
static const ARMCPRegInfo vapa_cp_reginfo[] = { |
| 536 |
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
|
| 537 |
.access = PL1_RW, .resetvalue = 0,
|
| 538 |
.fieldoffset = offsetof(CPUARMState, cp15.c7_par), |
| 539 |
.writefn = par_write }, |
| 540 |
#ifndef CONFIG_USER_ONLY
|
| 541 |
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
|
| 542 |
.access = PL1_W, .writefn = ats_write }, |
| 543 |
#endif
|
| 544 |
REGINFO_SENTINEL |
| 545 |
}; |
| 546 |
|
| 547 |
/* Return basic MPU access permission bits. */
|
| 548 |
static uint32_t simple_mpu_ap_bits(uint32_t val)
|
| 549 |
{
|
| 550 |
uint32_t ret; |
| 551 |
uint32_t mask; |
| 552 |
int i;
|
| 553 |
ret = 0;
|
| 554 |
mask = 3;
|
| 555 |
for (i = 0; i < 16; i += 2) { |
| 556 |
ret |= (val >> i) & mask; |
| 557 |
mask <<= 2;
|
| 558 |
} |
| 559 |
return ret;
|
| 560 |
} |
| 561 |
|
| 562 |
/* Pad basic MPU access permission bits to extended format. */
|
| 563 |
static uint32_t extended_mpu_ap_bits(uint32_t val)
|
| 564 |
{
|
| 565 |
uint32_t ret; |
| 566 |
uint32_t mask; |
| 567 |
int i;
|
| 568 |
ret = 0;
|
| 569 |
mask = 3;
|
| 570 |
for (i = 0; i < 16; i += 2) { |
| 571 |
ret |= (val & mask) << i; |
| 572 |
mask <<= 2;
|
| 573 |
} |
| 574 |
return ret;
|
| 575 |
} |
| 576 |
|
| 577 |
static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 578 |
uint64_t value) |
| 579 |
{
|
| 580 |
env->cp15.c5_data = extended_mpu_ap_bits(value); |
| 581 |
return 0; |
| 582 |
} |
| 583 |
|
| 584 |
static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 585 |
uint64_t *value) |
| 586 |
{
|
| 587 |
*value = simple_mpu_ap_bits(env->cp15.c5_data); |
| 588 |
return 0; |
| 589 |
} |
| 590 |
|
| 591 |
static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 592 |
uint64_t value) |
| 593 |
{
|
| 594 |
env->cp15.c5_insn = extended_mpu_ap_bits(value); |
| 595 |
return 0; |
| 596 |
} |
| 597 |
|
| 598 |
static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 599 |
uint64_t *value) |
| 600 |
{
|
| 601 |
*value = simple_mpu_ap_bits(env->cp15.c5_insn); |
| 602 |
return 0; |
| 603 |
} |
| 604 |
|
| 605 |
static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 606 |
uint64_t *value) |
| 607 |
{
|
| 608 |
if (ri->crm > 8) { |
| 609 |
return EXCP_UDEF;
|
| 610 |
} |
| 611 |
*value = env->cp15.c6_region[ri->crm]; |
| 612 |
return 0; |
| 613 |
} |
| 614 |
|
| 615 |
static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 616 |
uint64_t value) |
| 617 |
{
|
| 618 |
if (ri->crm > 8) { |
| 619 |
return EXCP_UDEF;
|
| 620 |
} |
| 621 |
env->cp15.c6_region[ri->crm] = value; |
| 622 |
return 0; |
| 623 |
} |
| 624 |
|
| 625 |
static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
| 626 |
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 627 |
.access = PL1_RW, |
| 628 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
|
| 629 |
.readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
| 630 |
{ .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 631 |
.access = PL1_RW, |
| 632 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
|
| 633 |
.readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
| 634 |
{ .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 635 |
.access = PL1_RW, |
| 636 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
|
| 637 |
{ .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
|
| 638 |
.access = PL1_RW, |
| 639 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
|
| 640 |
{ .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 641 |
.access = PL1_RW, |
| 642 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
|
| 643 |
{ .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 644 |
.access = PL1_RW, |
| 645 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
|
| 646 |
/* Protection region base and size registers */
|
| 647 |
{ .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
|
| 648 |
.opc2 = CP_ANY, .access = PL1_RW, |
| 649 |
.readfn = arm946_prbs_read, .writefn = arm946_prbs_write, }, |
| 650 |
REGINFO_SENTINEL |
| 651 |
}; |
| 652 |
|
| 653 |
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 654 |
uint64_t value) |
| 655 |
{
|
| 656 |
value &= 7;
|
| 657 |
env->cp15.c2_control = value; |
| 658 |
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
|
| 659 |
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
|
| 660 |
return 0; |
| 661 |
} |
| 662 |
|
| 663 |
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
| 664 |
{
|
| 665 |
env->cp15.c2_base_mask = 0xffffc000u;
|
| 666 |
env->cp15.c2_control = 0;
|
| 667 |
env->cp15.c2_mask = 0;
|
| 668 |
} |
| 669 |
|
| 670 |
static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
| 671 |
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 672 |
.access = PL1_RW, |
| 673 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
|
| 674 |
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 675 |
.access = PL1_RW, |
| 676 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
|
| 677 |
{ .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 678 |
.access = PL1_RW, |
| 679 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
|
| 680 |
{ .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 681 |
.access = PL1_RW, |
| 682 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
|
| 683 |
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 684 |
.access = PL1_RW, .writefn = vmsa_ttbcr_write, |
| 685 |
.resetfn = vmsa_ttbcr_reset, |
| 686 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
| 687 |
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 688 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data), |
| 689 |
.resetvalue = 0, },
|
| 690 |
REGINFO_SENTINEL |
| 691 |
}; |
| 692 |
|
| 693 |
static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 694 |
uint64_t value) |
| 695 |
{
|
| 696 |
env->cp15.c15_ticonfig = value & 0xe7;
|
| 697 |
/* The OS_TYPE bit in this register changes the reported CPUID! */
|
| 698 |
env->cp15.c0_cpuid = (value & (1 << 5)) ? |
| 699 |
ARM_CPUID_TI915T : ARM_CPUID_TI925T; |
| 700 |
return 0; |
| 701 |
} |
| 702 |
|
| 703 |
static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 704 |
uint64_t value) |
| 705 |
{
|
| 706 |
env->cp15.c15_threadid = value & 0xffff;
|
| 707 |
return 0; |
| 708 |
} |
| 709 |
|
| 710 |
static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 711 |
uint64_t value) |
| 712 |
{
|
| 713 |
/* Wait-for-interrupt (deprecated) */
|
| 714 |
cpu_interrupt(env, CPU_INTERRUPT_HALT); |
| 715 |
return 0; |
| 716 |
} |
| 717 |
|
| 718 |
static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 719 |
uint64_t value) |
| 720 |
{
|
| 721 |
/* On OMAP there are registers indicating the max/min index of dcache lines
|
| 722 |
* containing a dirty line; cache flush operations have to reset these.
|
| 723 |
*/
|
| 724 |
env->cp15.c15_i_max = 0x000;
|
| 725 |
env->cp15.c15_i_min = 0xff0;
|
| 726 |
return 0; |
| 727 |
} |
| 728 |
|
| 729 |
static const ARMCPRegInfo omap_cp_reginfo[] = { |
| 730 |
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
|
| 731 |
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, |
| 732 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
|
| 733 |
{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 734 |
.access = PL1_RW, .type = ARM_CP_NOP }, |
| 735 |
{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
|
| 736 |
.access = PL1_RW, |
| 737 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
|
| 738 |
.writefn = omap_ticonfig_write }, |
| 739 |
{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
|
| 740 |
.access = PL1_RW, |
| 741 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
|
| 742 |
{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
|
| 743 |
.access = PL1_RW, .resetvalue = 0xff0,
|
| 744 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, |
| 745 |
{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
|
| 746 |
.access = PL1_RW, |
| 747 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
|
| 748 |
.writefn = omap_threadid_write }, |
| 749 |
{ .name = "TI925T_STATUS", .cp = 15, .crn = 15,
|
| 750 |
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, |
| 751 |
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
| 752 |
/* TODO: Peripheral port remap register:
|
| 753 |
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
|
| 754 |
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
|
| 755 |
* when MMU is off.
|
| 756 |
*/
|
| 757 |
{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
|
| 758 |
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
|
| 759 |
.writefn = omap_cachemaint_write }, |
| 760 |
{ .name = "C9", .cp = 15, .crn = 9,
|
| 761 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, |
| 762 |
.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
|
| 763 |
REGINFO_SENTINEL |
| 764 |
}; |
| 765 |
|
| 766 |
static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 767 |
uint64_t value) |
| 768 |
{
|
| 769 |
value &= 0x3fff;
|
| 770 |
if (env->cp15.c15_cpar != value) {
|
| 771 |
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
| 772 |
tb_flush(env); |
| 773 |
env->cp15.c15_cpar = value; |
| 774 |
} |
| 775 |
return 0; |
| 776 |
} |
| 777 |
|
| 778 |
static const ARMCPRegInfo xscale_cp_reginfo[] = { |
| 779 |
{ .name = "XSCALE_CPAR",
|
| 780 |
.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, |
| 781 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
|
| 782 |
.writefn = xscale_cpar_write, }, |
| 783 |
{ .name = "XSCALE_AUXCR",
|
| 784 |
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, |
| 785 |
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), |
| 786 |
.resetvalue = 0, },
|
| 787 |
REGINFO_SENTINEL |
| 788 |
}; |
| 789 |
|
| 790 |
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { |
| 791 |
/* RAZ/WI the whole crn=15 space, when we don't have a more specific
|
| 792 |
* implementation of this implementation-defined space.
|
| 793 |
* Ideally this should eventually disappear in favour of actually
|
| 794 |
* implementing the correct behaviour for all cores.
|
| 795 |
*/
|
| 796 |
{ .name = "C15_IMPDEF", .cp = 15, .crn = 15,
|
| 797 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, |
| 798 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 799 |
REGINFO_SENTINEL |
| 800 |
}; |
| 801 |
|
| 802 |
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
| 803 |
/* Cache status: RAZ because we have no cache so it's always clean */
|
| 804 |
{ .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
|
| 805 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 806 |
REGINFO_SENTINEL |
| 807 |
}; |
| 808 |
|
| 809 |
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { |
| 810 |
/* We never have a a block transfer operation in progress */
|
| 811 |
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
|
| 812 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 813 |
/* The cache ops themselves: these all NOP for QEMU */
|
| 814 |
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
|
| 815 |
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
| 816 |
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
|
| 817 |
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
| 818 |
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
|
| 819 |
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
| 820 |
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
|
| 821 |
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
| 822 |
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
|
| 823 |
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
| 824 |
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
|
| 825 |
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
| 826 |
REGINFO_SENTINEL |
| 827 |
}; |
| 828 |
|
| 829 |
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { |
| 830 |
/* The cache test-and-clean instructions always return (1 << 30)
|
| 831 |
* to indicate that there are no dirty cache lines.
|
| 832 |
*/
|
| 833 |
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
|
| 834 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) }, |
| 835 |
{ .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
|
| 836 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) }, |
| 837 |
REGINFO_SENTINEL |
| 838 |
}; |
| 839 |
|
| 840 |
static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
| 841 |
/* Ignore ReadBuffer accesses */
|
| 842 |
{ .name = "C9_READBUFFER", .cp = 15, .crn = 9,
|
| 843 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, |
| 844 |
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
| 845 |
.resetvalue = 0 },
|
| 846 |
REGINFO_SENTINEL |
| 847 |
}; |
| 848 |
|
| 849 |
static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 850 |
uint64_t *value) |
| 851 |
{
|
| 852 |
uint32_t mpidr = env->cpu_index; |
| 853 |
/* We don't support setting cluster ID ([8..11])
|
| 854 |
* so these bits always RAZ.
|
| 855 |
*/
|
| 856 |
if (arm_feature(env, ARM_FEATURE_V7MP)) {
|
| 857 |
mpidr |= (1 << 31); |
| 858 |
/* Cores which are uniprocessor (non-coherent)
|
| 859 |
* but still implement the MP extensions set
|
| 860 |
* bit 30. (For instance, A9UP.) However we do
|
| 861 |
* not currently model any of those cores.
|
| 862 |
*/
|
| 863 |
} |
| 864 |
*value = mpidr; |
| 865 |
return 0; |
| 866 |
} |
| 867 |
|
| 868 |
static const ARMCPRegInfo mpidr_cp_reginfo[] = { |
| 869 |
{ .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
|
| 870 |
.access = PL1_R, .readfn = mpidr_read }, |
| 871 |
REGINFO_SENTINEL |
| 872 |
}; |
| 873 |
|
| 874 |
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 875 |
{
|
| 876 |
env->cp15.c1_sys = value; |
| 877 |
/* ??? Lots of these bits are not implemented. */
|
| 878 |
/* This may enable/disable the MMU, so do a TLB flush. */
|
| 879 |
tlb_flush(env, 1);
|
| 880 |
return 0; |
| 881 |
} |
| 882 |
|
| 883 |
void register_cp_regs_for_features(ARMCPU *cpu)
|
| 884 |
{
|
| 885 |
/* Register all the coprocessor registers based on feature bits */
|
| 886 |
CPUARMState *env = &cpu->env; |
| 887 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
| 888 |
/* M profile has no coprocessor registers */
|
| 889 |
return;
|
| 890 |
} |
| 891 |
|
| 892 |
define_arm_cp_regs(cpu, cp_reginfo); |
| 893 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
| 894 |
/* The ID registers all have impdef reset values */
|
| 895 |
ARMCPRegInfo v6_idregs[] = {
|
| 896 |
{ .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
|
| 897 |
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, |
| 898 |
.resetvalue = cpu->id_pfr0 }, |
| 899 |
{ .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
|
| 900 |
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, |
| 901 |
.resetvalue = cpu->id_pfr1 }, |
| 902 |
{ .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
|
| 903 |
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, |
| 904 |
.resetvalue = cpu->id_dfr0 }, |
| 905 |
{ .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
|
| 906 |
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, |
| 907 |
.resetvalue = cpu->id_afr0 }, |
| 908 |
{ .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
|
| 909 |
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, |
| 910 |
.resetvalue = cpu->id_mmfr0 }, |
| 911 |
{ .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
|
| 912 |
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, |
| 913 |
.resetvalue = cpu->id_mmfr1 }, |
| 914 |
{ .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
|
| 915 |
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, |
| 916 |
.resetvalue = cpu->id_mmfr2 }, |
| 917 |
{ .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
|
| 918 |
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, |
| 919 |
.resetvalue = cpu->id_mmfr3 }, |
| 920 |
{ .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
|
| 921 |
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, |
| 922 |
.resetvalue = cpu->id_isar0 }, |
| 923 |
{ .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
|
| 924 |
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, |
| 925 |
.resetvalue = cpu->id_isar1 }, |
| 926 |
{ .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
|
| 927 |
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, |
| 928 |
.resetvalue = cpu->id_isar2 }, |
| 929 |
{ .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
|
| 930 |
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, |
| 931 |
.resetvalue = cpu->id_isar3 }, |
| 932 |
{ .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
|
| 933 |
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, |
| 934 |
.resetvalue = cpu->id_isar4 }, |
| 935 |
{ .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
|
| 936 |
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, |
| 937 |
.resetvalue = cpu->id_isar5 }, |
| 938 |
/* 6..7 are as yet unallocated and must RAZ */
|
| 939 |
{ .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
|
| 940 |
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, |
| 941 |
.resetvalue = 0 },
|
| 942 |
{ .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
|
| 943 |
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, |
| 944 |
.resetvalue = 0 },
|
| 945 |
REGINFO_SENTINEL |
| 946 |
}; |
| 947 |
define_arm_cp_regs(cpu, v6_idregs); |
| 948 |
define_arm_cp_regs(cpu, v6_cp_reginfo); |
| 949 |
} else {
|
| 950 |
define_arm_cp_regs(cpu, not_v6_cp_reginfo); |
| 951 |
} |
| 952 |
if (arm_feature(env, ARM_FEATURE_V6K)) {
|
| 953 |
define_arm_cp_regs(cpu, v6k_cp_reginfo); |
| 954 |
} |
| 955 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
| 956 |
/* v7 performance monitor control register: same implementor
|
| 957 |
* field as main ID register, and we implement no event counters.
|
| 958 |
*/
|
| 959 |
ARMCPRegInfo pmcr = {
|
| 960 |
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, |
| 961 |
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
|
| 962 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), |
| 963 |
.readfn = pmreg_read, .writefn = pmcr_write |
| 964 |
}; |
| 965 |
ARMCPRegInfo clidr = {
|
| 966 |
.name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, |
| 967 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
| 968 |
}; |
| 969 |
define_one_arm_cp_reg(cpu, &pmcr); |
| 970 |
define_one_arm_cp_reg(cpu, &clidr); |
| 971 |
define_arm_cp_regs(cpu, v7_cp_reginfo); |
| 972 |
} else {
|
| 973 |
define_arm_cp_regs(cpu, not_v7_cp_reginfo); |
| 974 |
} |
| 975 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
| 976 |
/* These are the MPU registers prior to PMSAv6. Any new
|
| 977 |
* PMSA core later than the ARM946 will require that we
|
| 978 |
* implement the PMSAv6 or PMSAv7 registers, which are
|
| 979 |
* completely different.
|
| 980 |
*/
|
| 981 |
assert(!arm_feature(env, ARM_FEATURE_V6)); |
| 982 |
define_arm_cp_regs(cpu, pmsav5_cp_reginfo); |
| 983 |
} else {
|
| 984 |
define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
| 985 |
} |
| 986 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
| 987 |
define_arm_cp_regs(cpu, t2ee_cp_reginfo); |
| 988 |
} |
| 989 |
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
|
| 990 |
define_arm_cp_regs(cpu, generic_timer_cp_reginfo); |
| 991 |
} |
| 992 |
if (arm_feature(env, ARM_FEATURE_VAPA)) {
|
| 993 |
define_arm_cp_regs(cpu, vapa_cp_reginfo); |
| 994 |
} |
| 995 |
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
|
| 996 |
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); |
| 997 |
} |
| 998 |
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
|
| 999 |
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); |
| 1000 |
} |
| 1001 |
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
|
| 1002 |
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); |
| 1003 |
} |
| 1004 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
| 1005 |
define_arm_cp_regs(cpu, omap_cp_reginfo); |
| 1006 |
} |
| 1007 |
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
|
| 1008 |
define_arm_cp_regs(cpu, strongarm_cp_reginfo); |
| 1009 |
} |
| 1010 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
| 1011 |
define_arm_cp_regs(cpu, xscale_cp_reginfo); |
| 1012 |
} |
| 1013 |
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
|
| 1014 |
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); |
| 1015 |
} |
| 1016 |
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
|
| 1017 |
define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
| 1018 |
} |
| 1019 |
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
|
| 1020 |
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
|
| 1021 |
* be read-only (ie write causes UNDEF exception).
|
| 1022 |
*/
|
| 1023 |
{
|
| 1024 |
ARMCPRegInfo id_cp_reginfo[] = {
|
| 1025 |
/* Note that the MIDR isn't a simple constant register because
|
| 1026 |
* of the TI925 behaviour where writes to another register can
|
| 1027 |
* cause the MIDR value to change.
|
| 1028 |
*/
|
| 1029 |
{ .name = "MIDR",
|
| 1030 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, |
| 1031 |
.access = PL1_R, .resetvalue = cpu->midr, |
| 1032 |
.writefn = arm_cp_write_ignore, |
| 1033 |
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) }, |
| 1034 |
{ .name = "CTR",
|
| 1035 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, |
| 1036 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, |
| 1037 |
{ .name = "TCMTR",
|
| 1038 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, |
| 1039 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1040 |
{ .name = "TLBTR",
|
| 1041 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, |
| 1042 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1043 |
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
|
| 1044 |
{ .name = "DUMMY",
|
| 1045 |
.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, |
| 1046 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1047 |
{ .name = "DUMMY",
|
| 1048 |
.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, |
| 1049 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1050 |
{ .name = "DUMMY",
|
| 1051 |
.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, |
| 1052 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1053 |
{ .name = "DUMMY",
|
| 1054 |
.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, |
| 1055 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1056 |
{ .name = "DUMMY",
|
| 1057 |
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, |
| 1058 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 1059 |
REGINFO_SENTINEL |
| 1060 |
}; |
| 1061 |
ARMCPRegInfo crn0_wi_reginfo = {
|
| 1062 |
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
| 1063 |
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, |
| 1064 |
.type = ARM_CP_NOP | ARM_CP_OVERRIDE |
| 1065 |
}; |
| 1066 |
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
|
| 1067 |
arm_feature(env, ARM_FEATURE_STRONGARM)) {
|
| 1068 |
ARMCPRegInfo *r; |
| 1069 |
/* Register the blanket "writes ignored" value first to cover the
|
| 1070 |
* whole space. Then define the specific ID registers, but update
|
| 1071 |
* their access field to allow write access, so that they ignore
|
| 1072 |
* writes rather than causing them to UNDEF.
|
| 1073 |
*/
|
| 1074 |
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); |
| 1075 |
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
|
| 1076 |
r->access = PL1_RW; |
| 1077 |
define_one_arm_cp_reg(cpu, r); |
| 1078 |
} |
| 1079 |
} else {
|
| 1080 |
/* Just register the standard ID registers (read-only, meaning
|
| 1081 |
* that writes will UNDEF).
|
| 1082 |
*/
|
| 1083 |
define_arm_cp_regs(cpu, id_cp_reginfo); |
| 1084 |
} |
| 1085 |
} |
| 1086 |
|
| 1087 |
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
|
| 1088 |
ARMCPRegInfo auxcr = {
|
| 1089 |
.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, |
| 1090 |
.access = PL1_RW, .type = ARM_CP_CONST, |
| 1091 |
.resetvalue = cpu->reset_auxcr |
| 1092 |
}; |
| 1093 |
define_one_arm_cp_reg(cpu, &auxcr); |
| 1094 |
} |
| 1095 |
|
| 1096 |
/* Generic registers whose values depend on the implementation */
|
| 1097 |
{
|
| 1098 |
ARMCPRegInfo sctlr = {
|
| 1099 |
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, |
| 1100 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), |
| 1101 |
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr |
| 1102 |
}; |
| 1103 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
| 1104 |
/* Normally we would always end the TB on an SCTLR write, but Linux
|
| 1105 |
* arch/arm/mach-pxa/sleep.S expects two instructions following
|
| 1106 |
* an MMU enable to execute from cache. Imitate this behaviour.
|
| 1107 |
*/
|
| 1108 |
sctlr.type |= ARM_CP_SUPPRESS_TB_END; |
| 1109 |
} |
| 1110 |
define_one_arm_cp_reg(cpu, &sctlr); |
| 1111 |
} |
| 1112 |
} |
| 1113 |
|
| 1114 |
ARMCPU *cpu_arm_init(const char *cpu_model) |
| 1115 |
{
|
| 1116 |
ARMCPU *cpu; |
| 1117 |
CPUARMState *env; |
| 1118 |
static int inited = 0; |
| 1119 |
|
| 1120 |
if (!object_class_by_name(cpu_model)) {
|
| 1121 |
return NULL; |
| 1122 |
} |
| 1123 |
cpu = ARM_CPU(object_new(cpu_model)); |
| 1124 |
env = &cpu->env; |
| 1125 |
env->cpu_model_str = cpu_model; |
| 1126 |
arm_cpu_realize(cpu); |
| 1127 |
|
| 1128 |
if (tcg_enabled() && !inited) {
|
| 1129 |
inited = 1;
|
| 1130 |
arm_translate_init(); |
| 1131 |
} |
| 1132 |
|
| 1133 |
cpu_reset(CPU(cpu)); |
| 1134 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
| 1135 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
| 1136 |
51, "arm-neon.xml", 0); |
| 1137 |
} else if (arm_feature(env, ARM_FEATURE_VFP3)) { |
| 1138 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
| 1139 |
35, "arm-vfp3.xml", 0); |
| 1140 |
} else if (arm_feature(env, ARM_FEATURE_VFP)) { |
| 1141 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
| 1142 |
19, "arm-vfp.xml", 0); |
| 1143 |
} |
| 1144 |
qemu_init_vcpu(env); |
| 1145 |
return cpu;
|
| 1146 |
} |
| 1147 |
|
| 1148 |
typedef struct ARMCPUListState { |
| 1149 |
fprintf_function cpu_fprintf; |
| 1150 |
FILE *file; |
| 1151 |
} ARMCPUListState; |
| 1152 |
|
| 1153 |
/* Sort alphabetically by type name, except for "any". */
|
| 1154 |
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
|
| 1155 |
{
|
| 1156 |
ObjectClass *class_a = (ObjectClass *)a; |
| 1157 |
ObjectClass *class_b = (ObjectClass *)b; |
| 1158 |
const char *name_a, *name_b; |
| 1159 |
|
| 1160 |
name_a = object_class_get_name(class_a); |
| 1161 |
name_b = object_class_get_name(class_b); |
| 1162 |
if (strcmp(name_a, "any") == 0) { |
| 1163 |
return 1; |
| 1164 |
} else if (strcmp(name_b, "any") == 0) { |
| 1165 |
return -1; |
| 1166 |
} else {
|
| 1167 |
return strcmp(name_a, name_b);
|
| 1168 |
} |
| 1169 |
} |
| 1170 |
|
| 1171 |
static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
| 1172 |
{
|
| 1173 |
ObjectClass *oc = data; |
| 1174 |
ARMCPUListState *s = user_data; |
| 1175 |
|
| 1176 |
(*s->cpu_fprintf)(s->file, " %s\n",
|
| 1177 |
object_class_get_name(oc)); |
| 1178 |
} |
| 1179 |
|
| 1180 |
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
| 1181 |
{
|
| 1182 |
ARMCPUListState s = {
|
| 1183 |
.file = f, |
| 1184 |
.cpu_fprintf = cpu_fprintf, |
| 1185 |
}; |
| 1186 |
GSList *list; |
| 1187 |
|
| 1188 |
list = object_class_get_list(TYPE_ARM_CPU, false);
|
| 1189 |
list = g_slist_sort(list, arm_cpu_list_compare); |
| 1190 |
(*cpu_fprintf)(f, "Available CPUs:\n");
|
| 1191 |
g_slist_foreach(list, arm_cpu_list_entry, &s); |
| 1192 |
g_slist_free(list); |
| 1193 |
} |
| 1194 |
|
| 1195 |
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
|
| 1196 |
const ARMCPRegInfo *r, void *opaque) |
| 1197 |
{
|
| 1198 |
/* Define implementations of coprocessor registers.
|
| 1199 |
* We store these in a hashtable because typically
|
| 1200 |
* there are less than 150 registers in a space which
|
| 1201 |
* is 16*16*16*8*8 = 262144 in size.
|
| 1202 |
* Wildcarding is supported for the crm, opc1 and opc2 fields.
|
| 1203 |
* If a register is defined twice then the second definition is
|
| 1204 |
* used, so this can be used to define some generic registers and
|
| 1205 |
* then override them with implementation specific variations.
|
| 1206 |
* At least one of the original and the second definition should
|
| 1207 |
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
|
| 1208 |
* against accidental use.
|
| 1209 |
*/
|
| 1210 |
int crm, opc1, opc2;
|
| 1211 |
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
| 1212 |
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; |
| 1213 |
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; |
| 1214 |
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; |
| 1215 |
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; |
| 1216 |
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; |
| 1217 |
/* 64 bit registers have only CRm and Opc1 fields */
|
| 1218 |
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); |
| 1219 |
/* Check that the register definition has enough info to handle
|
| 1220 |
* reads and writes if they are permitted.
|
| 1221 |
*/
|
| 1222 |
if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
|
| 1223 |
if (r->access & PL3_R) {
|
| 1224 |
assert(r->fieldoffset || r->readfn); |
| 1225 |
} |
| 1226 |
if (r->access & PL3_W) {
|
| 1227 |
assert(r->fieldoffset || r->writefn); |
| 1228 |
} |
| 1229 |
} |
| 1230 |
/* Bad type field probably means missing sentinel at end of reg list */
|
| 1231 |
assert(cptype_valid(r->type)); |
| 1232 |
for (crm = crmmin; crm <= crmmax; crm++) {
|
| 1233 |
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
|
| 1234 |
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
|
| 1235 |
uint32_t *key = g_new(uint32_t, 1);
|
| 1236 |
ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
|
| 1237 |
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; |
| 1238 |
*key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2); |
| 1239 |
r2->opaque = opaque; |
| 1240 |
/* Make sure reginfo passed to helpers for wildcarded regs
|
| 1241 |
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
|
| 1242 |
*/
|
| 1243 |
r2->crm = crm; |
| 1244 |
r2->opc1 = opc1; |
| 1245 |
r2->opc2 = opc2; |
| 1246 |
/* Overriding of an existing definition must be explicitly
|
| 1247 |
* requested.
|
| 1248 |
*/
|
| 1249 |
if (!(r->type & ARM_CP_OVERRIDE)) {
|
| 1250 |
ARMCPRegInfo *oldreg; |
| 1251 |
oldreg = g_hash_table_lookup(cpu->cp_regs, key); |
| 1252 |
if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
|
| 1253 |
fprintf(stderr, "Register redefined: cp=%d %d bit "
|
| 1254 |
"crn=%d crm=%d opc1=%d opc2=%d, "
|
| 1255 |
"was %s, now %s\n", r2->cp, 32 + 32 * is64, |
| 1256 |
r2->crn, r2->crm, r2->opc1, r2->opc2, |
| 1257 |
oldreg->name, r2->name); |
| 1258 |
assert(0);
|
| 1259 |
} |
| 1260 |
} |
| 1261 |
g_hash_table_insert(cpu->cp_regs, key, r2); |
| 1262 |
} |
| 1263 |
} |
| 1264 |
} |
| 1265 |
} |
| 1266 |
|
| 1267 |
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
|
| 1268 |
const ARMCPRegInfo *regs, void *opaque) |
| 1269 |
{
|
| 1270 |
/* Define a whole list of registers */
|
| 1271 |
const ARMCPRegInfo *r;
|
| 1272 |
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
|
| 1273 |
define_one_arm_cp_reg_with_opaque(cpu, r, opaque); |
| 1274 |
} |
| 1275 |
} |
| 1276 |
|
| 1277 |
const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
|
| 1278 |
{
|
| 1279 |
return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
|
| 1280 |
} |
| 1281 |
|
| 1282 |
int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
| 1283 |
uint64_t value) |
| 1284 |
{
|
| 1285 |
/* Helper coprocessor write function for write-ignore registers */
|
| 1286 |
return 0; |
| 1287 |
} |
| 1288 |
|
| 1289 |
int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) |
| 1290 |
{
|
| 1291 |
/* Helper coprocessor write function for read-as-zero registers */
|
| 1292 |
*value = 0;
|
| 1293 |
return 0; |
| 1294 |
} |
| 1295 |
|
| 1296 |
static int bad_mode_switch(CPUARMState *env, int mode) |
| 1297 |
{
|
| 1298 |
/* Return true if it is not valid for us to switch to
|
| 1299 |
* this CPU mode (ie all the UNPREDICTABLE cases in
|
| 1300 |
* the ARM ARM CPSRWriteByInstr pseudocode).
|
| 1301 |
*/
|
| 1302 |
switch (mode) {
|
| 1303 |
case ARM_CPU_MODE_USR:
|
| 1304 |
case ARM_CPU_MODE_SYS:
|
| 1305 |
case ARM_CPU_MODE_SVC:
|
| 1306 |
case ARM_CPU_MODE_ABT:
|
| 1307 |
case ARM_CPU_MODE_UND:
|
| 1308 |
case ARM_CPU_MODE_IRQ:
|
| 1309 |
case ARM_CPU_MODE_FIQ:
|
| 1310 |
return 0; |
| 1311 |
default:
|
| 1312 |
return 1; |
| 1313 |
} |
| 1314 |
} |
| 1315 |
|
| 1316 |
uint32_t cpsr_read(CPUARMState *env) |
| 1317 |
{
|
| 1318 |
int ZF;
|
| 1319 |
ZF = (env->ZF == 0);
|
| 1320 |
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | |
| 1321 |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
| 1322 |
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
| 1323 |
| ((env->condexec_bits & 0xfc) << 8) |
| 1324 |
| (env->GE << 16);
|
| 1325 |
} |
| 1326 |
|
| 1327 |
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
| 1328 |
{
|
| 1329 |
if (mask & CPSR_NZCV) {
|
| 1330 |
env->ZF = (~val) & CPSR_Z; |
| 1331 |
env->NF = val; |
| 1332 |
env->CF = (val >> 29) & 1; |
| 1333 |
env->VF = (val << 3) & 0x80000000; |
| 1334 |
} |
| 1335 |
if (mask & CPSR_Q)
|
| 1336 |
env->QF = ((val & CPSR_Q) != 0);
|
| 1337 |
if (mask & CPSR_T)
|
| 1338 |
env->thumb = ((val & CPSR_T) != 0);
|
| 1339 |
if (mask & CPSR_IT_0_1) {
|
| 1340 |
env->condexec_bits &= ~3;
|
| 1341 |
env->condexec_bits |= (val >> 25) & 3; |
| 1342 |
} |
| 1343 |
if (mask & CPSR_IT_2_7) {
|
| 1344 |
env->condexec_bits &= 3;
|
| 1345 |
env->condexec_bits |= (val >> 8) & 0xfc; |
| 1346 |
} |
| 1347 |
if (mask & CPSR_GE) {
|
| 1348 |
env->GE = (val >> 16) & 0xf; |
| 1349 |
} |
| 1350 |
|
| 1351 |
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
| 1352 |
if (bad_mode_switch(env, val & CPSR_M)) {
|
| 1353 |
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
|
| 1354 |
* We choose to ignore the attempt and leave the CPSR M field
|
| 1355 |
* untouched.
|
| 1356 |
*/
|
| 1357 |
mask &= ~CPSR_M; |
| 1358 |
} else {
|
| 1359 |
switch_mode(env, val & CPSR_M); |
| 1360 |
} |
| 1361 |
} |
| 1362 |
mask &= ~CACHED_CPSR_BITS; |
| 1363 |
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
| 1364 |
} |
| 1365 |
|
| 1366 |
/* Sign/zero extend */
|
| 1367 |
uint32_t HELPER(sxtb16)(uint32_t x) |
| 1368 |
{
|
| 1369 |
uint32_t res; |
| 1370 |
res = (uint16_t)(int8_t)x; |
| 1371 |
res |= (uint32_t)(int8_t)(x >> 16) << 16; |
| 1372 |
return res;
|
| 1373 |
} |
| 1374 |
|
| 1375 |
uint32_t HELPER(uxtb16)(uint32_t x) |
| 1376 |
{
|
| 1377 |
uint32_t res; |
| 1378 |
res = (uint16_t)(uint8_t)x; |
| 1379 |
res |= (uint32_t)(uint8_t)(x >> 16) << 16; |
| 1380 |
return res;
|
| 1381 |
} |
| 1382 |
|
| 1383 |
uint32_t HELPER(clz)(uint32_t x) |
| 1384 |
{
|
| 1385 |
return clz32(x);
|
| 1386 |
} |
| 1387 |
|
| 1388 |
int32_t HELPER(sdiv)(int32_t num, int32_t den) |
| 1389 |
{
|
| 1390 |
if (den == 0) |
| 1391 |
return 0; |
| 1392 |
if (num == INT_MIN && den == -1) |
| 1393 |
return INT_MIN;
|
| 1394 |
return num / den;
|
| 1395 |
} |
| 1396 |
|
| 1397 |
uint32_t HELPER(udiv)(uint32_t num, uint32_t den) |
| 1398 |
{
|
| 1399 |
if (den == 0) |
| 1400 |
return 0; |
| 1401 |
return num / den;
|
| 1402 |
} |
| 1403 |
|
| 1404 |
uint32_t HELPER(rbit)(uint32_t x) |
| 1405 |
{
|
| 1406 |
x = ((x & 0xff000000) >> 24) |
| 1407 |
| ((x & 0x00ff0000) >> 8) |
| 1408 |
| ((x & 0x0000ff00) << 8) |
| 1409 |
| ((x & 0x000000ff) << 24); |
| 1410 |
x = ((x & 0xf0f0f0f0) >> 4) |
| 1411 |
| ((x & 0x0f0f0f0f) << 4); |
| 1412 |
x = ((x & 0x88888888) >> 3) |
| 1413 |
| ((x & 0x44444444) >> 1) |
| 1414 |
| ((x & 0x22222222) << 1) |
| 1415 |
| ((x & 0x11111111) << 3); |
| 1416 |
return x;
|
| 1417 |
} |
| 1418 |
|
| 1419 |
uint32_t HELPER(abs)(uint32_t x) |
| 1420 |
{
|
| 1421 |
return ((int32_t)x < 0) ? -x : x; |
| 1422 |
} |
| 1423 |
|
| 1424 |
#if defined(CONFIG_USER_ONLY)
|
| 1425 |
|
| 1426 |
void do_interrupt (CPUARMState *env)
|
| 1427 |
{
|
| 1428 |
env->exception_index = -1;
|
| 1429 |
} |
| 1430 |
|
| 1431 |
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
| 1432 |
int mmu_idx)
|
| 1433 |
{
|
| 1434 |
if (rw == 2) { |
| 1435 |
env->exception_index = EXCP_PREFETCH_ABORT; |
| 1436 |
env->cp15.c6_insn = address; |
| 1437 |
} else {
|
| 1438 |
env->exception_index = EXCP_DATA_ABORT; |
| 1439 |
env->cp15.c6_data = address; |
| 1440 |
} |
| 1441 |
return 1; |
| 1442 |
} |
| 1443 |
|
| 1444 |
void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
|
| 1445 |
{
|
| 1446 |
cpu_abort(env, "cp15 insn %08x\n", insn);
|
| 1447 |
} |
| 1448 |
|
| 1449 |
uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) |
| 1450 |
{
|
| 1451 |
cpu_abort(env, "cp15 insn %08x\n", insn);
|
| 1452 |
} |
| 1453 |
|
| 1454 |
/* These should probably raise undefined insn exceptions. */
|
| 1455 |
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
|
| 1456 |
{
|
| 1457 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
| 1458 |
} |
| 1459 |
|
| 1460 |
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
| 1461 |
{
|
| 1462 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
| 1463 |
return 0; |
| 1464 |
} |
| 1465 |
|
| 1466 |
void switch_mode(CPUARMState *env, int mode) |
| 1467 |
{
|
| 1468 |
if (mode != ARM_CPU_MODE_USR)
|
| 1469 |
cpu_abort(env, "Tried to switch out of user mode\n");
|
| 1470 |
} |
| 1471 |
|
| 1472 |
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
|
| 1473 |
{
|
| 1474 |
cpu_abort(env, "banked r13 write\n");
|
| 1475 |
} |
| 1476 |
|
| 1477 |
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
| 1478 |
{
|
| 1479 |
cpu_abort(env, "banked r13 read\n");
|
| 1480 |
return 0; |
| 1481 |
} |
| 1482 |
|
| 1483 |
#else
|
| 1484 |
|
| 1485 |
/* Map CPU modes onto saved register banks. */
|
| 1486 |
static inline int bank_number(CPUARMState *env, int mode) |
| 1487 |
{
|
| 1488 |
switch (mode) {
|
| 1489 |
case ARM_CPU_MODE_USR:
|
| 1490 |
case ARM_CPU_MODE_SYS:
|
| 1491 |
return 0; |
| 1492 |
case ARM_CPU_MODE_SVC:
|
| 1493 |
return 1; |
| 1494 |
case ARM_CPU_MODE_ABT:
|
| 1495 |
return 2; |
| 1496 |
case ARM_CPU_MODE_UND:
|
| 1497 |
return 3; |
| 1498 |
case ARM_CPU_MODE_IRQ:
|
| 1499 |
return 4; |
| 1500 |
case ARM_CPU_MODE_FIQ:
|
| 1501 |
return 5; |
| 1502 |
} |
| 1503 |
cpu_abort(env, "Bad mode %x\n", mode);
|
| 1504 |
return -1; |
| 1505 |
} |
| 1506 |
|
| 1507 |
void switch_mode(CPUARMState *env, int mode) |
| 1508 |
{
|
| 1509 |
int old_mode;
|
| 1510 |
int i;
|
| 1511 |
|
| 1512 |
old_mode = env->uncached_cpsr & CPSR_M; |
| 1513 |
if (mode == old_mode)
|
| 1514 |
return;
|
| 1515 |
|
| 1516 |
if (old_mode == ARM_CPU_MODE_FIQ) {
|
| 1517 |
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
| 1518 |
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
| 1519 |
} else if (mode == ARM_CPU_MODE_FIQ) { |
| 1520 |
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
| 1521 |
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
| 1522 |
} |
| 1523 |
|
| 1524 |
i = bank_number(env, old_mode); |
| 1525 |
env->banked_r13[i] = env->regs[13];
|
| 1526 |
env->banked_r14[i] = env->regs[14];
|
| 1527 |
env->banked_spsr[i] = env->spsr; |
| 1528 |
|
| 1529 |
i = bank_number(env, mode); |
| 1530 |
env->regs[13] = env->banked_r13[i];
|
| 1531 |
env->regs[14] = env->banked_r14[i];
|
| 1532 |
env->spsr = env->banked_spsr[i]; |
| 1533 |
} |
| 1534 |
|
| 1535 |
static void v7m_push(CPUARMState *env, uint32_t val) |
| 1536 |
{
|
| 1537 |
env->regs[13] -= 4; |
| 1538 |
stl_phys(env->regs[13], val);
|
| 1539 |
} |
| 1540 |
|
| 1541 |
static uint32_t v7m_pop(CPUARMState *env)
|
| 1542 |
{
|
| 1543 |
uint32_t val; |
| 1544 |
val = ldl_phys(env->regs[13]);
|
| 1545 |
env->regs[13] += 4; |
| 1546 |
return val;
|
| 1547 |
} |
| 1548 |
|
| 1549 |
/* Switch to V7M main or process stack pointer. */
|
| 1550 |
static void switch_v7m_sp(CPUARMState *env, int process) |
| 1551 |
{
|
| 1552 |
uint32_t tmp; |
| 1553 |
if (env->v7m.current_sp != process) {
|
| 1554 |
tmp = env->v7m.other_sp; |
| 1555 |
env->v7m.other_sp = env->regs[13];
|
| 1556 |
env->regs[13] = tmp;
|
| 1557 |
env->v7m.current_sp = process; |
| 1558 |
} |
| 1559 |
} |
| 1560 |
|
| 1561 |
static void do_v7m_exception_exit(CPUARMState *env) |
| 1562 |
{
|
| 1563 |
uint32_t type; |
| 1564 |
uint32_t xpsr; |
| 1565 |
|
| 1566 |
type = env->regs[15];
|
| 1567 |
if (env->v7m.exception != 0) |
| 1568 |
armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
| 1569 |
|
| 1570 |
/* Switch to the target stack. */
|
| 1571 |
switch_v7m_sp(env, (type & 4) != 0); |
| 1572 |
/* Pop registers. */
|
| 1573 |
env->regs[0] = v7m_pop(env);
|
| 1574 |
env->regs[1] = v7m_pop(env);
|
| 1575 |
env->regs[2] = v7m_pop(env);
|
| 1576 |
env->regs[3] = v7m_pop(env);
|
| 1577 |
env->regs[12] = v7m_pop(env);
|
| 1578 |
env->regs[14] = v7m_pop(env);
|
| 1579 |
env->regs[15] = v7m_pop(env);
|
| 1580 |
xpsr = v7m_pop(env); |
| 1581 |
xpsr_write(env, xpsr, 0xfffffdff);
|
| 1582 |
/* Undo stack alignment. */
|
| 1583 |
if (xpsr & 0x200) |
| 1584 |
env->regs[13] |= 4; |
| 1585 |
/* ??? The exception return type specifies Thread/Handler mode. However
|
| 1586 |
this is also implied by the xPSR value. Not sure what to do
|
| 1587 |
if there is a mismatch. */
|
| 1588 |
/* ??? Likewise for mismatches between the CONTROL register and the stack
|
| 1589 |
pointer. */
|
| 1590 |
} |
| 1591 |
|
| 1592 |
static void do_interrupt_v7m(CPUARMState *env) |
| 1593 |
{
|
| 1594 |
uint32_t xpsr = xpsr_read(env); |
| 1595 |
uint32_t lr; |
| 1596 |
uint32_t addr; |
| 1597 |
|
| 1598 |
lr = 0xfffffff1;
|
| 1599 |
if (env->v7m.current_sp)
|
| 1600 |
lr |= 4;
|
| 1601 |
if (env->v7m.exception == 0) |
| 1602 |
lr |= 8;
|
| 1603 |
|
| 1604 |
/* For exceptions we just mark as pending on the NVIC, and let that
|
| 1605 |
handle it. */
|
| 1606 |
/* TODO: Need to escalate if the current priority is higher than the
|
| 1607 |
one we're raising. */
|
| 1608 |
switch (env->exception_index) {
|
| 1609 |
case EXCP_UDEF:
|
| 1610 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
| 1611 |
return;
|
| 1612 |
case EXCP_SWI:
|
| 1613 |
env->regs[15] += 2; |
| 1614 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
| 1615 |
return;
|
| 1616 |
case EXCP_PREFETCH_ABORT:
|
| 1617 |
case EXCP_DATA_ABORT:
|
| 1618 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
| 1619 |
return;
|
| 1620 |
case EXCP_BKPT:
|
| 1621 |
if (semihosting_enabled) {
|
| 1622 |
int nr;
|
| 1623 |
nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff; |
| 1624 |
if (nr == 0xab) { |
| 1625 |
env->regs[15] += 2; |
| 1626 |
env->regs[0] = do_arm_semihosting(env);
|
| 1627 |
return;
|
| 1628 |
} |
| 1629 |
} |
| 1630 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
| 1631 |
return;
|
| 1632 |
case EXCP_IRQ:
|
| 1633 |
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
| 1634 |
break;
|
| 1635 |
case EXCP_EXCEPTION_EXIT:
|
| 1636 |
do_v7m_exception_exit(env); |
| 1637 |
return;
|
| 1638 |
default:
|
| 1639 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
| 1640 |
return; /* Never happens. Keep compiler happy. */ |
| 1641 |
} |
| 1642 |
|
| 1643 |
/* Align stack pointer. */
|
| 1644 |
/* ??? Should only do this if Configuration Control Register
|
| 1645 |
STACKALIGN bit is set. */
|
| 1646 |
if (env->regs[13] & 4) { |
| 1647 |
env->regs[13] -= 4; |
| 1648 |
xpsr |= 0x200;
|
| 1649 |
} |
| 1650 |
/* Switch to the handler mode. */
|
| 1651 |
v7m_push(env, xpsr); |
| 1652 |
v7m_push(env, env->regs[15]);
|
| 1653 |
v7m_push(env, env->regs[14]);
|
| 1654 |
v7m_push(env, env->regs[12]);
|
| 1655 |
v7m_push(env, env->regs[3]);
|
| 1656 |
v7m_push(env, env->regs[2]);
|
| 1657 |
v7m_push(env, env->regs[1]);
|
| 1658 |
v7m_push(env, env->regs[0]);
|
| 1659 |
switch_v7m_sp(env, 0);
|
| 1660 |
/* Clear IT bits */
|
| 1661 |
env->condexec_bits = 0;
|
| 1662 |
env->regs[14] = lr;
|
| 1663 |
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
|
| 1664 |
env->regs[15] = addr & 0xfffffffe; |
| 1665 |
env->thumb = addr & 1;
|
| 1666 |
} |
| 1667 |
|
| 1668 |
/* Handle a CPU exception. */
|
| 1669 |
void do_interrupt(CPUARMState *env)
|
| 1670 |
{
|
| 1671 |
uint32_t addr; |
| 1672 |
uint32_t mask; |
| 1673 |
int new_mode;
|
| 1674 |
uint32_t offset; |
| 1675 |
|
| 1676 |
if (IS_M(env)) {
|
| 1677 |
do_interrupt_v7m(env); |
| 1678 |
return;
|
| 1679 |
} |
| 1680 |
/* TODO: Vectored interrupt controller. */
|
| 1681 |
switch (env->exception_index) {
|
| 1682 |
case EXCP_UDEF:
|
| 1683 |
new_mode = ARM_CPU_MODE_UND; |
| 1684 |
addr = 0x04;
|
| 1685 |
mask = CPSR_I; |
| 1686 |
if (env->thumb)
|
| 1687 |
offset = 2;
|
| 1688 |
else
|
| 1689 |
offset = 4;
|
| 1690 |
break;
|
| 1691 |
case EXCP_SWI:
|
| 1692 |
if (semihosting_enabled) {
|
| 1693 |
/* Check for semihosting interrupt. */
|
| 1694 |
if (env->thumb) {
|
| 1695 |
mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff; |
| 1696 |
} else {
|
| 1697 |
mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code) |
| 1698 |
& 0xffffff;
|
| 1699 |
} |
| 1700 |
/* Only intercept calls from privileged modes, to provide some
|
| 1701 |
semblance of security. */
|
| 1702 |
if (((mask == 0x123456 && !env->thumb) |
| 1703 |
|| (mask == 0xab && env->thumb))
|
| 1704 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
|
| 1705 |
env->regs[0] = do_arm_semihosting(env);
|
| 1706 |
return;
|
| 1707 |
} |
| 1708 |
} |
| 1709 |
new_mode = ARM_CPU_MODE_SVC; |
| 1710 |
addr = 0x08;
|
| 1711 |
mask = CPSR_I; |
| 1712 |
/* The PC already points to the next instruction. */
|
| 1713 |
offset = 0;
|
| 1714 |
break;
|
| 1715 |
case EXCP_BKPT:
|
| 1716 |
/* See if this is a semihosting syscall. */
|
| 1717 |
if (env->thumb && semihosting_enabled) {
|
| 1718 |
mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff; |
| 1719 |
if (mask == 0xab |
| 1720 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
|
| 1721 |
env->regs[15] += 2; |
| 1722 |
env->regs[0] = do_arm_semihosting(env);
|
| 1723 |
return;
|
| 1724 |
} |
| 1725 |
} |
| 1726 |
env->cp15.c5_insn = 2;
|
| 1727 |
/* Fall through to prefetch abort. */
|
| 1728 |
case EXCP_PREFETCH_ABORT:
|
| 1729 |
new_mode = ARM_CPU_MODE_ABT; |
| 1730 |
addr = 0x0c;
|
| 1731 |
mask = CPSR_A | CPSR_I; |
| 1732 |
offset = 4;
|
| 1733 |
break;
|
| 1734 |
case EXCP_DATA_ABORT:
|
| 1735 |
new_mode = ARM_CPU_MODE_ABT; |
| 1736 |
addr = 0x10;
|
| 1737 |
mask = CPSR_A | CPSR_I; |
| 1738 |
offset = 8;
|
| 1739 |
break;
|
| 1740 |
case EXCP_IRQ:
|
| 1741 |
new_mode = ARM_CPU_MODE_IRQ; |
| 1742 |
addr = 0x18;
|
| 1743 |
/* Disable IRQ and imprecise data aborts. */
|
| 1744 |
mask = CPSR_A | CPSR_I; |
| 1745 |
offset = 4;
|
| 1746 |
break;
|
| 1747 |
case EXCP_FIQ:
|
| 1748 |
new_mode = ARM_CPU_MODE_FIQ; |
| 1749 |
addr = 0x1c;
|
| 1750 |
/* Disable FIQ, IRQ and imprecise data aborts. */
|
| 1751 |
mask = CPSR_A | CPSR_I | CPSR_F; |
| 1752 |
offset = 4;
|
| 1753 |
break;
|
| 1754 |
default:
|
| 1755 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
| 1756 |
return; /* Never happens. Keep compiler happy. */ |
| 1757 |
} |
| 1758 |
/* High vectors. */
|
| 1759 |
if (env->cp15.c1_sys & (1 << 13)) { |
| 1760 |
addr += 0xffff0000;
|
| 1761 |
} |
| 1762 |
switch_mode (env, new_mode); |
| 1763 |
env->spsr = cpsr_read(env); |
| 1764 |
/* Clear IT bits. */
|
| 1765 |
env->condexec_bits = 0;
|
| 1766 |
/* Switch to the new mode, and to the correct instruction set. */
|
| 1767 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
| 1768 |
env->uncached_cpsr |= mask; |
| 1769 |
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
|
| 1770 |
* and we should just guard the thumb mode on V4 */
|
| 1771 |
if (arm_feature(env, ARM_FEATURE_V4T)) {
|
| 1772 |
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; |
| 1773 |
} |
| 1774 |
env->regs[14] = env->regs[15] + offset; |
| 1775 |
env->regs[15] = addr;
|
| 1776 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 1777 |
} |
| 1778 |
|
| 1779 |
/* Check section/page access permissions.
|
| 1780 |
Returns the page protection flags, or zero if the access is not
|
| 1781 |
permitted. */
|
| 1782 |
static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
| 1783 |
int access_type, int is_user) |
| 1784 |
{
|
| 1785 |
int prot_ro;
|
| 1786 |
|
| 1787 |
if (domain_prot == 3) { |
| 1788 |
return PAGE_READ | PAGE_WRITE;
|
| 1789 |
} |
| 1790 |
|
| 1791 |
if (access_type == 1) |
| 1792 |
prot_ro = 0;
|
| 1793 |
else
|
| 1794 |
prot_ro = PAGE_READ; |
| 1795 |
|
| 1796 |
switch (ap) {
|
| 1797 |
case 0: |
| 1798 |
if (access_type == 1) |
| 1799 |
return 0; |
| 1800 |
switch ((env->cp15.c1_sys >> 8) & 3) { |
| 1801 |
case 1: |
| 1802 |
return is_user ? 0 : PAGE_READ; |
| 1803 |
case 2: |
| 1804 |
return PAGE_READ;
|
| 1805 |
default:
|
| 1806 |
return 0; |
| 1807 |
} |
| 1808 |
case 1: |
| 1809 |
return is_user ? 0 : PAGE_READ | PAGE_WRITE; |
| 1810 |
case 2: |
| 1811 |
if (is_user)
|
| 1812 |
return prot_ro;
|
| 1813 |
else
|
| 1814 |
return PAGE_READ | PAGE_WRITE;
|
| 1815 |
case 3: |
| 1816 |
return PAGE_READ | PAGE_WRITE;
|
| 1817 |
case 4: /* Reserved. */ |
| 1818 |
return 0; |
| 1819 |
case 5: |
| 1820 |
return is_user ? 0 : prot_ro; |
| 1821 |
case 6: |
| 1822 |
return prot_ro;
|
| 1823 |
case 7: |
| 1824 |
if (!arm_feature (env, ARM_FEATURE_V6K))
|
| 1825 |
return 0; |
| 1826 |
return prot_ro;
|
| 1827 |
default:
|
| 1828 |
abort(); |
| 1829 |
} |
| 1830 |
} |
| 1831 |
|
| 1832 |
static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
|
| 1833 |
{
|
| 1834 |
uint32_t table; |
| 1835 |
|
| 1836 |
if (address & env->cp15.c2_mask)
|
| 1837 |
table = env->cp15.c2_base1 & 0xffffc000;
|
| 1838 |
else
|
| 1839 |
table = env->cp15.c2_base0 & env->cp15.c2_base_mask; |
| 1840 |
|
| 1841 |
table |= (address >> 18) & 0x3ffc; |
| 1842 |
return table;
|
| 1843 |
} |
| 1844 |
|
| 1845 |
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
| 1846 |
int is_user, uint32_t *phys_ptr, int *prot, |
| 1847 |
target_ulong *page_size) |
| 1848 |
{
|
| 1849 |
int code;
|
| 1850 |
uint32_t table; |
| 1851 |
uint32_t desc; |
| 1852 |
int type;
|
| 1853 |
int ap;
|
| 1854 |
int domain;
|
| 1855 |
int domain_prot;
|
| 1856 |
uint32_t phys_addr; |
| 1857 |
|
| 1858 |
/* Pagetable walk. */
|
| 1859 |
/* Lookup l1 descriptor. */
|
| 1860 |
table = get_level1_table_address(env, address); |
| 1861 |
desc = ldl_phys(table); |
| 1862 |
type = (desc & 3);
|
| 1863 |
domain = (desc >> 5) & 0x0f; |
| 1864 |
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
| 1865 |
if (type == 0) { |
| 1866 |
/* Section translation fault. */
|
| 1867 |
code = 5;
|
| 1868 |
goto do_fault;
|
| 1869 |
} |
| 1870 |
if (domain_prot == 0 || domain_prot == 2) { |
| 1871 |
if (type == 2) |
| 1872 |
code = 9; /* Section domain fault. */ |
| 1873 |
else
|
| 1874 |
code = 11; /* Page domain fault. */ |
| 1875 |
goto do_fault;
|
| 1876 |
} |
| 1877 |
if (type == 2) { |
| 1878 |
/* 1Mb section. */
|
| 1879 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
| 1880 |
ap = (desc >> 10) & 3; |
| 1881 |
code = 13;
|
| 1882 |
*page_size = 1024 * 1024; |
| 1883 |
} else {
|
| 1884 |
/* Lookup l2 entry. */
|
| 1885 |
if (type == 1) { |
| 1886 |
/* Coarse pagetable. */
|
| 1887 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
| 1888 |
} else {
|
| 1889 |
/* Fine pagetable. */
|
| 1890 |
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); |
| 1891 |
} |
| 1892 |
desc = ldl_phys(table); |
| 1893 |
switch (desc & 3) { |
| 1894 |
case 0: /* Page translation fault. */ |
| 1895 |
code = 7;
|
| 1896 |
goto do_fault;
|
| 1897 |
case 1: /* 64k page. */ |
| 1898 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
| 1899 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
| 1900 |
*page_size = 0x10000;
|
| 1901 |
break;
|
| 1902 |
case 2: /* 4k page. */ |
| 1903 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
| 1904 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
| 1905 |
*page_size = 0x1000;
|
| 1906 |
break;
|
| 1907 |
case 3: /* 1k page. */ |
| 1908 |
if (type == 1) { |
| 1909 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
| 1910 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
| 1911 |
} else {
|
| 1912 |
/* Page translation fault. */
|
| 1913 |
code = 7;
|
| 1914 |
goto do_fault;
|
| 1915 |
} |
| 1916 |
} else {
|
| 1917 |
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); |
| 1918 |
} |
| 1919 |
ap = (desc >> 4) & 3; |
| 1920 |
*page_size = 0x400;
|
| 1921 |
break;
|
| 1922 |
default:
|
| 1923 |
/* Never happens, but compiler isn't smart enough to tell. */
|
| 1924 |
abort(); |
| 1925 |
} |
| 1926 |
code = 15;
|
| 1927 |
} |
| 1928 |
*prot = check_ap(env, ap, domain_prot, access_type, is_user); |
| 1929 |
if (!*prot) {
|
| 1930 |
/* Access permission fault. */
|
| 1931 |
goto do_fault;
|
| 1932 |
} |
| 1933 |
*prot |= PAGE_EXEC; |
| 1934 |
*phys_ptr = phys_addr; |
| 1935 |
return 0; |
| 1936 |
do_fault:
|
| 1937 |
return code | (domain << 4); |
| 1938 |
} |
| 1939 |
|
| 1940 |
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
| 1941 |
int is_user, uint32_t *phys_ptr, int *prot, |
| 1942 |
target_ulong *page_size) |
| 1943 |
{
|
| 1944 |
int code;
|
| 1945 |
uint32_t table; |
| 1946 |
uint32_t desc; |
| 1947 |
uint32_t xn; |
| 1948 |
int type;
|
| 1949 |
int ap;
|
| 1950 |
int domain;
|
| 1951 |
int domain_prot;
|
| 1952 |
uint32_t phys_addr; |
| 1953 |
|
| 1954 |
/* Pagetable walk. */
|
| 1955 |
/* Lookup l1 descriptor. */
|
| 1956 |
table = get_level1_table_address(env, address); |
| 1957 |
desc = ldl_phys(table); |
| 1958 |
type = (desc & 3);
|
| 1959 |
if (type == 0) { |
| 1960 |
/* Section translation fault. */
|
| 1961 |
code = 5;
|
| 1962 |
domain = 0;
|
| 1963 |
goto do_fault;
|
| 1964 |
} else if (type == 2 && (desc & (1 << 18))) { |
| 1965 |
/* Supersection. */
|
| 1966 |
domain = 0;
|
| 1967 |
} else {
|
| 1968 |
/* Section or page. */
|
| 1969 |
domain = (desc >> 5) & 0x0f; |
| 1970 |
} |
| 1971 |
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
| 1972 |
if (domain_prot == 0 || domain_prot == 2) { |
| 1973 |
if (type == 2) |
| 1974 |
code = 9; /* Section domain fault. */ |
| 1975 |
else
|
| 1976 |
code = 11; /* Page domain fault. */ |
| 1977 |
goto do_fault;
|
| 1978 |
} |
| 1979 |
if (type == 2) { |
| 1980 |
if (desc & (1 << 18)) { |
| 1981 |
/* Supersection. */
|
| 1982 |
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); |
| 1983 |
*page_size = 0x1000000;
|
| 1984 |
} else {
|
| 1985 |
/* Section. */
|
| 1986 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
| 1987 |
*page_size = 0x100000;
|
| 1988 |
} |
| 1989 |
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
| 1990 |
xn = desc & (1 << 4); |
| 1991 |
code = 13;
|
| 1992 |
} else {
|
| 1993 |
/* Lookup l2 entry. */
|
| 1994 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
| 1995 |
desc = ldl_phys(table); |
| 1996 |
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
| 1997 |
switch (desc & 3) { |
| 1998 |
case 0: /* Page translation fault. */ |
| 1999 |
code = 7;
|
| 2000 |
goto do_fault;
|
| 2001 |
case 1: /* 64k page. */ |
| 2002 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
| 2003 |
xn = desc & (1 << 15); |
| 2004 |
*page_size = 0x10000;
|
| 2005 |
break;
|
| 2006 |
case 2: case 3: /* 4k page. */ |
| 2007 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
| 2008 |
xn = desc & 1;
|
| 2009 |
*page_size = 0x1000;
|
| 2010 |
break;
|
| 2011 |
default:
|
| 2012 |
/* Never happens, but compiler isn't smart enough to tell. */
|
| 2013 |
abort(); |
| 2014 |
} |
| 2015 |
code = 15;
|
| 2016 |
} |
| 2017 |
if (domain_prot == 3) { |
| 2018 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 2019 |
} else {
|
| 2020 |
if (xn && access_type == 2) |
| 2021 |
goto do_fault;
|
| 2022 |
|
| 2023 |
/* The simplified model uses AP[0] as an access control bit. */
|
| 2024 |
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) { |
| 2025 |
/* Access flag fault. */
|
| 2026 |
code = (code == 15) ? 6 : 3; |
| 2027 |
goto do_fault;
|
| 2028 |
} |
| 2029 |
*prot = check_ap(env, ap, domain_prot, access_type, is_user); |
| 2030 |
if (!*prot) {
|
| 2031 |
/* Access permission fault. */
|
| 2032 |
goto do_fault;
|
| 2033 |
} |
| 2034 |
if (!xn) {
|
| 2035 |
*prot |= PAGE_EXEC; |
| 2036 |
} |
| 2037 |
} |
| 2038 |
*phys_ptr = phys_addr; |
| 2039 |
return 0; |
| 2040 |
do_fault:
|
| 2041 |
return code | (domain << 4); |
| 2042 |
} |
| 2043 |
|
| 2044 |
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type, |
| 2045 |
int is_user, uint32_t *phys_ptr, int *prot) |
| 2046 |
{
|
| 2047 |
int n;
|
| 2048 |
uint32_t mask; |
| 2049 |
uint32_t base; |
| 2050 |
|
| 2051 |
*phys_ptr = address; |
| 2052 |
for (n = 7; n >= 0; n--) { |
| 2053 |
base = env->cp15.c6_region[n]; |
| 2054 |
if ((base & 1) == 0) |
| 2055 |
continue;
|
| 2056 |
mask = 1 << ((base >> 1) & 0x1f); |
| 2057 |
/* Keep this shift separate from the above to avoid an
|
| 2058 |
(undefined) << 32. */
|
| 2059 |
mask = (mask << 1) - 1; |
| 2060 |
if (((base ^ address) & ~mask) == 0) |
| 2061 |
break;
|
| 2062 |
} |
| 2063 |
if (n < 0) |
| 2064 |
return 2; |
| 2065 |
|
| 2066 |
if (access_type == 2) { |
| 2067 |
mask = env->cp15.c5_insn; |
| 2068 |
} else {
|
| 2069 |
mask = env->cp15.c5_data; |
| 2070 |
} |
| 2071 |
mask = (mask >> (n * 4)) & 0xf; |
| 2072 |
switch (mask) {
|
| 2073 |
case 0: |
| 2074 |
return 1; |
| 2075 |
case 1: |
| 2076 |
if (is_user)
|
| 2077 |
return 1; |
| 2078 |
*prot = PAGE_READ | PAGE_WRITE; |
| 2079 |
break;
|
| 2080 |
case 2: |
| 2081 |
*prot = PAGE_READ; |
| 2082 |
if (!is_user)
|
| 2083 |
*prot |= PAGE_WRITE; |
| 2084 |
break;
|
| 2085 |
case 3: |
| 2086 |
*prot = PAGE_READ | PAGE_WRITE; |
| 2087 |
break;
|
| 2088 |
case 5: |
| 2089 |
if (is_user)
|
| 2090 |
return 1; |
| 2091 |
*prot = PAGE_READ; |
| 2092 |
break;
|
| 2093 |
case 6: |
| 2094 |
*prot = PAGE_READ; |
| 2095 |
break;
|
| 2096 |
default:
|
| 2097 |
/* Bad permission. */
|
| 2098 |
return 1; |
| 2099 |
} |
| 2100 |
*prot |= PAGE_EXEC; |
| 2101 |
return 0; |
| 2102 |
} |
| 2103 |
|
| 2104 |
static inline int get_phys_addr(CPUARMState *env, uint32_t address, |
| 2105 |
int access_type, int is_user, |
| 2106 |
uint32_t *phys_ptr, int *prot,
|
| 2107 |
target_ulong *page_size) |
| 2108 |
{
|
| 2109 |
/* Fast Context Switch Extension. */
|
| 2110 |
if (address < 0x02000000) |
| 2111 |
address += env->cp15.c13_fcse; |
| 2112 |
|
| 2113 |
if ((env->cp15.c1_sys & 1) == 0) { |
| 2114 |
/* MMU/MPU disabled. */
|
| 2115 |
*phys_ptr = address; |
| 2116 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 2117 |
*page_size = TARGET_PAGE_SIZE; |
| 2118 |
return 0; |
| 2119 |
} else if (arm_feature(env, ARM_FEATURE_MPU)) { |
| 2120 |
*page_size = TARGET_PAGE_SIZE; |
| 2121 |
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
|
| 2122 |
prot); |
| 2123 |
} else if (env->cp15.c1_sys & (1 << 23)) { |
| 2124 |
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
|
| 2125 |
prot, page_size); |
| 2126 |
} else {
|
| 2127 |
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
|
| 2128 |
prot, page_size); |
| 2129 |
} |
| 2130 |
} |
| 2131 |
|
| 2132 |
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
|
| 2133 |
int access_type, int mmu_idx) |
| 2134 |
{
|
| 2135 |
uint32_t phys_addr; |
| 2136 |
target_ulong page_size; |
| 2137 |
int prot;
|
| 2138 |
int ret, is_user;
|
| 2139 |
|
| 2140 |
is_user = mmu_idx == MMU_USER_IDX; |
| 2141 |
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
| 2142 |
&page_size); |
| 2143 |
if (ret == 0) { |
| 2144 |
/* Map a single [sub]page. */
|
| 2145 |
phys_addr &= ~(uint32_t)0x3ff;
|
| 2146 |
address &= ~(uint32_t)0x3ff;
|
| 2147 |
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); |
| 2148 |
return 0; |
| 2149 |
} |
| 2150 |
|
| 2151 |
if (access_type == 2) { |
| 2152 |
env->cp15.c5_insn = ret; |
| 2153 |
env->cp15.c6_insn = address; |
| 2154 |
env->exception_index = EXCP_PREFETCH_ABORT; |
| 2155 |
} else {
|
| 2156 |
env->cp15.c5_data = ret; |
| 2157 |
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
| 2158 |
env->cp15.c5_data |= (1 << 11); |
| 2159 |
env->cp15.c6_data = address; |
| 2160 |
env->exception_index = EXCP_DATA_ABORT; |
| 2161 |
} |
| 2162 |
return 1; |
| 2163 |
} |
| 2164 |
|
| 2165 |
target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) |
| 2166 |
{
|
| 2167 |
uint32_t phys_addr; |
| 2168 |
target_ulong page_size; |
| 2169 |
int prot;
|
| 2170 |
int ret;
|
| 2171 |
|
| 2172 |
ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size); |
| 2173 |
|
| 2174 |
if (ret != 0) |
| 2175 |
return -1; |
| 2176 |
|
| 2177 |
return phys_addr;
|
| 2178 |
} |
| 2179 |
|
| 2180 |
void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
|
| 2181 |
{
|
| 2182 |
int op1;
|
| 2183 |
int op2;
|
| 2184 |
int crm;
|
| 2185 |
|
| 2186 |
op1 = (insn >> 21) & 7; |
| 2187 |
op2 = (insn >> 5) & 7; |
| 2188 |
crm = insn & 0xf;
|
| 2189 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
| 2190 |
cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
|
| 2191 |
(insn >> 16) & 0xf, crm, op1, op2); |
| 2192 |
} |
| 2193 |
|
| 2194 |
uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) |
| 2195 |
{
|
| 2196 |
int op1;
|
| 2197 |
int op2;
|
| 2198 |
int crm;
|
| 2199 |
|
| 2200 |
op1 = (insn >> 21) & 7; |
| 2201 |
op2 = (insn >> 5) & 7; |
| 2202 |
crm = insn & 0xf;
|
| 2203 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
| 2204 |
cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
|
| 2205 |
(insn >> 16) & 0xf, crm, op1, op2); |
| 2206 |
return 0; |
| 2207 |
} |
| 2208 |
|
| 2209 |
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
|
| 2210 |
{
|
| 2211 |
if ((env->uncached_cpsr & CPSR_M) == mode) {
|
| 2212 |
env->regs[13] = val;
|
| 2213 |
} else {
|
| 2214 |
env->banked_r13[bank_number(env, mode)] = val; |
| 2215 |
} |
| 2216 |
} |
| 2217 |
|
| 2218 |
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
| 2219 |
{
|
| 2220 |
if ((env->uncached_cpsr & CPSR_M) == mode) {
|
| 2221 |
return env->regs[13]; |
| 2222 |
} else {
|
| 2223 |
return env->banked_r13[bank_number(env, mode)];
|
| 2224 |
} |
| 2225 |
} |
| 2226 |
|
| 2227 |
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
| 2228 |
{
|
| 2229 |
switch (reg) {
|
| 2230 |
case 0: /* APSR */ |
| 2231 |
return xpsr_read(env) & 0xf8000000; |
| 2232 |
case 1: /* IAPSR */ |
| 2233 |
return xpsr_read(env) & 0xf80001ff; |
| 2234 |
case 2: /* EAPSR */ |
| 2235 |
return xpsr_read(env) & 0xff00fc00; |
| 2236 |
case 3: /* xPSR */ |
| 2237 |
return xpsr_read(env) & 0xff00fdff; |
| 2238 |
case 5: /* IPSR */ |
| 2239 |
return xpsr_read(env) & 0x000001ff; |
| 2240 |
case 6: /* EPSR */ |
| 2241 |
return xpsr_read(env) & 0x0700fc00; |
| 2242 |
case 7: /* IEPSR */ |
| 2243 |
return xpsr_read(env) & 0x0700edff; |
| 2244 |
case 8: /* MSP */ |
| 2245 |
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; |
| 2246 |
case 9: /* PSP */ |
| 2247 |
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; |
| 2248 |
case 16: /* PRIMASK */ |
| 2249 |
return (env->uncached_cpsr & CPSR_I) != 0; |
| 2250 |
case 17: /* BASEPRI */ |
| 2251 |
case 18: /* BASEPRI_MAX */ |
| 2252 |
return env->v7m.basepri;
|
| 2253 |
case 19: /* FAULTMASK */ |
| 2254 |
return (env->uncached_cpsr & CPSR_F) != 0; |
| 2255 |
case 20: /* CONTROL */ |
| 2256 |
return env->v7m.control;
|
| 2257 |
default:
|
| 2258 |
/* ??? For debugging only. */
|
| 2259 |
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
|
| 2260 |
return 0; |
| 2261 |
} |
| 2262 |
} |
| 2263 |
|
| 2264 |
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
|
| 2265 |
{
|
| 2266 |
switch (reg) {
|
| 2267 |
case 0: /* APSR */ |
| 2268 |
xpsr_write(env, val, 0xf8000000);
|
| 2269 |
break;
|
| 2270 |
case 1: /* IAPSR */ |
| 2271 |
xpsr_write(env, val, 0xf8000000);
|
| 2272 |
break;
|
| 2273 |
case 2: /* EAPSR */ |
| 2274 |
xpsr_write(env, val, 0xfe00fc00);
|
| 2275 |
break;
|
| 2276 |
case 3: /* xPSR */ |
| 2277 |
xpsr_write(env, val, 0xfe00fc00);
|
| 2278 |
break;
|
| 2279 |
case 5: /* IPSR */ |
| 2280 |
/* IPSR bits are readonly. */
|
| 2281 |
break;
|
| 2282 |
case 6: /* EPSR */ |
| 2283 |
xpsr_write(env, val, 0x0600fc00);
|
| 2284 |
break;
|
| 2285 |
case 7: /* IEPSR */ |
| 2286 |
xpsr_write(env, val, 0x0600fc00);
|
| 2287 |
break;
|
| 2288 |
case 8: /* MSP */ |
| 2289 |
if (env->v7m.current_sp)
|
| 2290 |
env->v7m.other_sp = val; |
| 2291 |
else
|
| 2292 |
env->regs[13] = val;
|
| 2293 |
break;
|
| 2294 |
case 9: /* PSP */ |
| 2295 |
if (env->v7m.current_sp)
|
| 2296 |
env->regs[13] = val;
|
| 2297 |
else
|
| 2298 |
env->v7m.other_sp = val; |
| 2299 |
break;
|
| 2300 |
case 16: /* PRIMASK */ |
| 2301 |
if (val & 1) |
| 2302 |
env->uncached_cpsr |= CPSR_I; |
| 2303 |
else
|
| 2304 |
env->uncached_cpsr &= ~CPSR_I; |
| 2305 |
break;
|
| 2306 |
case 17: /* BASEPRI */ |
| 2307 |
env->v7m.basepri = val & 0xff;
|
| 2308 |
break;
|
| 2309 |
case 18: /* BASEPRI_MAX */ |
| 2310 |
val &= 0xff;
|
| 2311 |
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) |
| 2312 |
env->v7m.basepri = val; |
| 2313 |
break;
|
| 2314 |
case 19: /* FAULTMASK */ |
| 2315 |
if (val & 1) |
| 2316 |
env->uncached_cpsr |= CPSR_F; |
| 2317 |
else
|
| 2318 |
env->uncached_cpsr &= ~CPSR_F; |
| 2319 |
break;
|
| 2320 |
case 20: /* CONTROL */ |
| 2321 |
env->v7m.control = val & 3;
|
| 2322 |
switch_v7m_sp(env, (val & 2) != 0); |
| 2323 |
break;
|
| 2324 |
default:
|
| 2325 |
/* ??? For debugging only. */
|
| 2326 |
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
|
| 2327 |
return;
|
| 2328 |
} |
| 2329 |
} |
| 2330 |
|
| 2331 |
#endif
|
| 2332 |
|
| 2333 |
/* Note that signed overflow is undefined in C. The following routines are
|
| 2334 |
careful to use unsigned types where modulo arithmetic is required.
|
| 2335 |
Failure to do so _will_ break on newer gcc. */
|
| 2336 |
|
| 2337 |
/* Signed saturating arithmetic. */
|
| 2338 |
|
| 2339 |
/* Perform 16-bit signed saturating addition. */
|
| 2340 |
static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
| 2341 |
{
|
| 2342 |
uint16_t res; |
| 2343 |
|
| 2344 |
res = a + b; |
| 2345 |
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { |
| 2346 |
if (a & 0x8000) |
| 2347 |
res = 0x8000;
|
| 2348 |
else
|
| 2349 |
res = 0x7fff;
|
| 2350 |
} |
| 2351 |
return res;
|
| 2352 |
} |
| 2353 |
|
| 2354 |
/* Perform 8-bit signed saturating addition. */
|
| 2355 |
static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
| 2356 |
{
|
| 2357 |
uint8_t res; |
| 2358 |
|
| 2359 |
res = a + b; |
| 2360 |
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { |
| 2361 |
if (a & 0x80) |
| 2362 |
res = 0x80;
|
| 2363 |
else
|
| 2364 |
res = 0x7f;
|
| 2365 |
} |
| 2366 |
return res;
|
| 2367 |
} |
| 2368 |
|
| 2369 |
/* Perform 16-bit signed saturating subtraction. */
|
| 2370 |
static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
| 2371 |
{
|
| 2372 |
uint16_t res; |
| 2373 |
|
| 2374 |
res = a - b; |
| 2375 |
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { |
| 2376 |
if (a & 0x8000) |
| 2377 |
res = 0x8000;
|
| 2378 |
else
|
| 2379 |
res = 0x7fff;
|
| 2380 |
} |
| 2381 |
return res;
|
| 2382 |
} |
| 2383 |
|
| 2384 |
/* Perform 8-bit signed saturating subtraction. */
|
| 2385 |
static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
| 2386 |
{
|
| 2387 |
uint8_t res; |
| 2388 |
|
| 2389 |
res = a - b; |
| 2390 |
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { |
| 2391 |
if (a & 0x80) |
| 2392 |
res = 0x80;
|
| 2393 |
else
|
| 2394 |
res = 0x7f;
|
| 2395 |
} |
| 2396 |
return res;
|
| 2397 |
} |
| 2398 |
|
| 2399 |
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); |
| 2400 |
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); |
| 2401 |
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); |
| 2402 |
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); |
| 2403 |
#define PFX q
|
| 2404 |
|
| 2405 |
#include "op_addsub.h" |
| 2406 |
|
| 2407 |
/* Unsigned saturating arithmetic. */
|
| 2408 |
static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
| 2409 |
{
|
| 2410 |
uint16_t res; |
| 2411 |
res = a + b; |
| 2412 |
if (res < a)
|
| 2413 |
res = 0xffff;
|
| 2414 |
return res;
|
| 2415 |
} |
| 2416 |
|
| 2417 |
static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
| 2418 |
{
|
| 2419 |
if (a > b)
|
| 2420 |
return a - b;
|
| 2421 |
else
|
| 2422 |
return 0; |
| 2423 |
} |
| 2424 |
|
| 2425 |
static inline uint8_t add8_usat(uint8_t a, uint8_t b) |
| 2426 |
{
|
| 2427 |
uint8_t res; |
| 2428 |
res = a + b; |
| 2429 |
if (res < a)
|
| 2430 |
res = 0xff;
|
| 2431 |
return res;
|
| 2432 |
} |
| 2433 |
|
| 2434 |
static inline uint8_t sub8_usat(uint8_t a, uint8_t b) |
| 2435 |
{
|
| 2436 |
if (a > b)
|
| 2437 |
return a - b;
|
| 2438 |
else
|
| 2439 |
return 0; |
| 2440 |
} |
| 2441 |
|
| 2442 |
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); |
| 2443 |
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); |
| 2444 |
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); |
| 2445 |
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); |
| 2446 |
#define PFX uq
|
| 2447 |
|
| 2448 |
#include "op_addsub.h" |
| 2449 |
|
| 2450 |
/* Signed modulo arithmetic. */
|
| 2451 |
#define SARITH16(a, b, n, op) do { \ |
| 2452 |
int32_t sum; \ |
| 2453 |
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
| 2454 |
RESULT(sum, n, 16); \
|
| 2455 |
if (sum >= 0) \ |
| 2456 |
ge |= 3 << (n * 2); \ |
| 2457 |
} while(0) |
| 2458 |
|
| 2459 |
#define SARITH8(a, b, n, op) do { \ |
| 2460 |
int32_t sum; \ |
| 2461 |
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
| 2462 |
RESULT(sum, n, 8); \
|
| 2463 |
if (sum >= 0) \ |
| 2464 |
ge |= 1 << n; \
|
| 2465 |
} while(0) |
| 2466 |
|
| 2467 |
|
| 2468 |
#define ADD16(a, b, n) SARITH16(a, b, n, +)
|
| 2469 |
#define SUB16(a, b, n) SARITH16(a, b, n, -)
|
| 2470 |
#define ADD8(a, b, n) SARITH8(a, b, n, +)
|
| 2471 |
#define SUB8(a, b, n) SARITH8(a, b, n, -)
|
| 2472 |
#define PFX s
|
| 2473 |
#define ARITH_GE
|
| 2474 |
|
| 2475 |
#include "op_addsub.h" |
| 2476 |
|
| 2477 |
/* Unsigned modulo arithmetic. */
|
| 2478 |
#define ADD16(a, b, n) do { \ |
| 2479 |
uint32_t sum; \ |
| 2480 |
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ |
| 2481 |
RESULT(sum, n, 16); \
|
| 2482 |
if ((sum >> 16) == 1) \ |
| 2483 |
ge |= 3 << (n * 2); \ |
| 2484 |
} while(0) |
| 2485 |
|
| 2486 |
#define ADD8(a, b, n) do { \ |
| 2487 |
uint32_t sum; \ |
| 2488 |
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ |
| 2489 |
RESULT(sum, n, 8); \
|
| 2490 |
if ((sum >> 8) == 1) \ |
| 2491 |
ge |= 1 << n; \
|
| 2492 |
} while(0) |
| 2493 |
|
| 2494 |
#define SUB16(a, b, n) do { \ |
| 2495 |
uint32_t sum; \ |
| 2496 |
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ |
| 2497 |
RESULT(sum, n, 16); \
|
| 2498 |
if ((sum >> 16) == 0) \ |
| 2499 |
ge |= 3 << (n * 2); \ |
| 2500 |
} while(0) |
| 2501 |
|
| 2502 |
#define SUB8(a, b, n) do { \ |
| 2503 |
uint32_t sum; \ |
| 2504 |
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ |
| 2505 |
RESULT(sum, n, 8); \
|
| 2506 |
if ((sum >> 8) == 0) \ |
| 2507 |
ge |= 1 << n; \
|
| 2508 |
} while(0) |
| 2509 |
|
| 2510 |
#define PFX u
|
| 2511 |
#define ARITH_GE
|
| 2512 |
|
| 2513 |
#include "op_addsub.h" |
| 2514 |
|
| 2515 |
/* Halved signed arithmetic. */
|
| 2516 |
#define ADD16(a, b, n) \
|
| 2517 |
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) |
| 2518 |
#define SUB16(a, b, n) \
|
| 2519 |
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) |
| 2520 |
#define ADD8(a, b, n) \
|
| 2521 |
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) |
| 2522 |
#define SUB8(a, b, n) \
|
| 2523 |
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) |
| 2524 |
#define PFX sh
|
| 2525 |
|
| 2526 |
#include "op_addsub.h" |
| 2527 |
|
| 2528 |
/* Halved unsigned arithmetic. */
|
| 2529 |
#define ADD16(a, b, n) \
|
| 2530 |
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
| 2531 |
#define SUB16(a, b, n) \
|
| 2532 |
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
| 2533 |
#define ADD8(a, b, n) \
|
| 2534 |
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
| 2535 |
#define SUB8(a, b, n) \
|
| 2536 |
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
| 2537 |
#define PFX uh
|
| 2538 |
|
| 2539 |
#include "op_addsub.h" |
| 2540 |
|
| 2541 |
static inline uint8_t do_usad(uint8_t a, uint8_t b) |
| 2542 |
{
|
| 2543 |
if (a > b)
|
| 2544 |
return a - b;
|
| 2545 |
else
|
| 2546 |
return b - a;
|
| 2547 |
} |
| 2548 |
|
| 2549 |
/* Unsigned sum of absolute byte differences. */
|
| 2550 |
uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
| 2551 |
{
|
| 2552 |
uint32_t sum; |
| 2553 |
sum = do_usad(a, b); |
| 2554 |
sum += do_usad(a >> 8, b >> 8); |
| 2555 |
sum += do_usad(a >> 16, b >>16); |
| 2556 |
sum += do_usad(a >> 24, b >> 24); |
| 2557 |
return sum;
|
| 2558 |
} |
| 2559 |
|
| 2560 |
/* For ARMv6 SEL instruction. */
|
| 2561 |
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) |
| 2562 |
{
|
| 2563 |
uint32_t mask; |
| 2564 |
|
| 2565 |
mask = 0;
|
| 2566 |
if (flags & 1) |
| 2567 |
mask |= 0xff;
|
| 2568 |
if (flags & 2) |
| 2569 |
mask |= 0xff00;
|
| 2570 |
if (flags & 4) |
| 2571 |
mask |= 0xff0000;
|
| 2572 |
if (flags & 8) |
| 2573 |
mask |= 0xff000000;
|
| 2574 |
return (a & mask) | (b & ~mask);
|
| 2575 |
} |
| 2576 |
|
| 2577 |
uint32_t HELPER(logicq_cc)(uint64_t val) |
| 2578 |
{
|
| 2579 |
return (val >> 32) | (val != 0); |
| 2580 |
} |
| 2581 |
|
| 2582 |
/* VFP support. We follow the convention used for VFP instrunctions:
|
| 2583 |
Single precition routines have a "s" suffix, double precision a
|
| 2584 |
"d" suffix. */
|
| 2585 |
|
| 2586 |
/* Convert host exception flags to vfp form. */
|
| 2587 |
static inline int vfp_exceptbits_from_host(int host_bits) |
| 2588 |
{
|
| 2589 |
int target_bits = 0; |
| 2590 |
|
| 2591 |
if (host_bits & float_flag_invalid)
|
| 2592 |
target_bits |= 1;
|
| 2593 |
if (host_bits & float_flag_divbyzero)
|
| 2594 |
target_bits |= 2;
|
| 2595 |
if (host_bits & float_flag_overflow)
|
| 2596 |
target_bits |= 4;
|
| 2597 |
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
|
| 2598 |
target_bits |= 8;
|
| 2599 |
if (host_bits & float_flag_inexact)
|
| 2600 |
target_bits |= 0x10;
|
| 2601 |
if (host_bits & float_flag_input_denormal)
|
| 2602 |
target_bits |= 0x80;
|
| 2603 |
return target_bits;
|
| 2604 |
} |
| 2605 |
|
| 2606 |
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
| 2607 |
{
|
| 2608 |
int i;
|
| 2609 |
uint32_t fpscr; |
| 2610 |
|
| 2611 |
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
|
| 2612 |
| (env->vfp.vec_len << 16)
|
| 2613 |
| (env->vfp.vec_stride << 20);
|
| 2614 |
i = get_float_exception_flags(&env->vfp.fp_status); |
| 2615 |
i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
| 2616 |
fpscr |= vfp_exceptbits_from_host(i); |
| 2617 |
return fpscr;
|
| 2618 |
} |
| 2619 |
|
| 2620 |
uint32_t vfp_get_fpscr(CPUARMState *env) |
| 2621 |
{
|
| 2622 |
return HELPER(vfp_get_fpscr)(env);
|
| 2623 |
} |
| 2624 |
|
| 2625 |
/* Convert vfp exception flags to target form. */
|
| 2626 |
static inline int vfp_exceptbits_to_host(int target_bits) |
| 2627 |
{
|
| 2628 |
int host_bits = 0; |
| 2629 |
|
| 2630 |
if (target_bits & 1) |
| 2631 |
host_bits |= float_flag_invalid; |
| 2632 |
if (target_bits & 2) |
| 2633 |
host_bits |= float_flag_divbyzero; |
| 2634 |
if (target_bits & 4) |
| 2635 |
host_bits |= float_flag_overflow; |
| 2636 |
if (target_bits & 8) |
| 2637 |
host_bits |= float_flag_underflow; |
| 2638 |
if (target_bits & 0x10) |
| 2639 |
host_bits |= float_flag_inexact; |
| 2640 |
if (target_bits & 0x80) |
| 2641 |
host_bits |= float_flag_input_denormal; |
| 2642 |
return host_bits;
|
| 2643 |
} |
| 2644 |
|
| 2645 |
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
|
| 2646 |
{
|
| 2647 |
int i;
|
| 2648 |
uint32_t changed; |
| 2649 |
|
| 2650 |
changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
| 2651 |
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
|
| 2652 |
env->vfp.vec_len = (val >> 16) & 7; |
| 2653 |
env->vfp.vec_stride = (val >> 20) & 3; |
| 2654 |
|
| 2655 |
changed ^= val; |
| 2656 |
if (changed & (3 << 22)) { |
| 2657 |
i = (val >> 22) & 3; |
| 2658 |
switch (i) {
|
| 2659 |
case 0: |
| 2660 |
i = float_round_nearest_even; |
| 2661 |
break;
|
| 2662 |
case 1: |
| 2663 |
i = float_round_up; |
| 2664 |
break;
|
| 2665 |
case 2: |
| 2666 |
i = float_round_down; |
| 2667 |
break;
|
| 2668 |
case 3: |
| 2669 |
i = float_round_to_zero; |
| 2670 |
break;
|
| 2671 |
} |
| 2672 |
set_float_rounding_mode(i, &env->vfp.fp_status); |
| 2673 |
} |
| 2674 |
if (changed & (1 << 24)) { |
| 2675 |
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
| 2676 |
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
| 2677 |
} |
| 2678 |
if (changed & (1 << 25)) |
| 2679 |
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); |
| 2680 |
|
| 2681 |
i = vfp_exceptbits_to_host(val); |
| 2682 |
set_float_exception_flags(i, &env->vfp.fp_status); |
| 2683 |
set_float_exception_flags(0, &env->vfp.standard_fp_status);
|
| 2684 |
} |
| 2685 |
|
| 2686 |
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
|
| 2687 |
{
|
| 2688 |
HELPER(vfp_set_fpscr)(env, val); |
| 2689 |
} |
| 2690 |
|
| 2691 |
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
|
| 2692 |
|
| 2693 |
#define VFP_BINOP(name) \
|
| 2694 |
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
|
| 2695 |
{ \
|
| 2696 |
float_status *fpst = fpstp; \ |
| 2697 |
return float32_ ## name(a, b, fpst); \ |
| 2698 |
} \ |
| 2699 |
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
|
| 2700 |
{ \
|
| 2701 |
float_status *fpst = fpstp; \ |
| 2702 |
return float64_ ## name(a, b, fpst); \ |
| 2703 |
} |
| 2704 |
VFP_BINOP(add) |
| 2705 |
VFP_BINOP(sub) |
| 2706 |
VFP_BINOP(mul) |
| 2707 |
VFP_BINOP(div) |
| 2708 |
#undef VFP_BINOP
|
| 2709 |
|
| 2710 |
float32 VFP_HELPER(neg, s)(float32 a) |
| 2711 |
{
|
| 2712 |
return float32_chs(a);
|
| 2713 |
} |
| 2714 |
|
| 2715 |
float64 VFP_HELPER(neg, d)(float64 a) |
| 2716 |
{
|
| 2717 |
return float64_chs(a);
|
| 2718 |
} |
| 2719 |
|
| 2720 |
float32 VFP_HELPER(abs, s)(float32 a) |
| 2721 |
{
|
| 2722 |
return float32_abs(a);
|
| 2723 |
} |
| 2724 |
|
| 2725 |
float64 VFP_HELPER(abs, d)(float64 a) |
| 2726 |
{
|
| 2727 |
return float64_abs(a);
|
| 2728 |
} |
| 2729 |
|
| 2730 |
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
| 2731 |
{
|
| 2732 |
return float32_sqrt(a, &env->vfp.fp_status);
|
| 2733 |
} |
| 2734 |
|
| 2735 |
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
| 2736 |
{
|
| 2737 |
return float64_sqrt(a, &env->vfp.fp_status);
|
| 2738 |
} |
| 2739 |
|
| 2740 |
/* XXX: check quiet/signaling case */
|
| 2741 |
#define DO_VFP_cmp(p, type) \
|
| 2742 |
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
|
| 2743 |
{ \
|
| 2744 |
uint32_t flags; \ |
| 2745 |
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ |
| 2746 |
case 0: flags = 0x6; break; \ |
| 2747 |
case -1: flags = 0x8; break; \ |
| 2748 |
case 1: flags = 0x2; break; \ |
| 2749 |
default: case 2: flags = 0x3; break; \ |
| 2750 |
} \ |
| 2751 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
| 2752 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
| 2753 |
} \ |
| 2754 |
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
|
| 2755 |
{ \
|
| 2756 |
uint32_t flags; \ |
| 2757 |
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ |
| 2758 |
case 0: flags = 0x6; break; \ |
| 2759 |
case -1: flags = 0x8; break; \ |
| 2760 |
case 1: flags = 0x2; break; \ |
| 2761 |
default: case 2: flags = 0x3; break; \ |
| 2762 |
} \ |
| 2763 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
| 2764 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
| 2765 |
} |
| 2766 |
DO_VFP_cmp(s, float32) |
| 2767 |
DO_VFP_cmp(d, float64) |
| 2768 |
#undef DO_VFP_cmp
|
| 2769 |
|
| 2770 |
/* Integer to float and float to integer conversions */
|
| 2771 |
|
| 2772 |
#define CONV_ITOF(name, fsz, sign) \
|
| 2773 |
float##fsz HELPER(name)(uint32_t x, void *fpstp) \ |
| 2774 |
{ \
|
| 2775 |
float_status *fpst = fpstp; \ |
| 2776 |
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
| 2777 |
} |
| 2778 |
|
| 2779 |
#define CONV_FTOI(name, fsz, sign, round) \
|
| 2780 |
uint32_t HELPER(name)(float##fsz x, void *fpstp) \ |
| 2781 |
{ \
|
| 2782 |
float_status *fpst = fpstp; \ |
| 2783 |
if (float##fsz##_is_any_nan(x)) { \ |
| 2784 |
float_raise(float_flag_invalid, fpst); \ |
| 2785 |
return 0; \ |
| 2786 |
} \ |
| 2787 |
return float##fsz##_to_##sign##int32##round(x, fpst); \ |
| 2788 |
} |
| 2789 |
|
| 2790 |
#define FLOAT_CONVS(name, p, fsz, sign) \
|
| 2791 |
CONV_ITOF(vfp_##name##to##p, fsz, sign) \ |
| 2792 |
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ |
| 2793 |
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) |
| 2794 |
|
| 2795 |
FLOAT_CONVS(si, s, 32, )
|
| 2796 |
FLOAT_CONVS(si, d, 64, )
|
| 2797 |
FLOAT_CONVS(ui, s, 32, u)
|
| 2798 |
FLOAT_CONVS(ui, d, 64, u)
|
| 2799 |
|
| 2800 |
#undef CONV_ITOF
|
| 2801 |
#undef CONV_FTOI
|
| 2802 |
#undef FLOAT_CONVS
|
| 2803 |
|
| 2804 |
/* floating point conversion */
|
| 2805 |
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
| 2806 |
{
|
| 2807 |
float64 r = float32_to_float64(x, &env->vfp.fp_status); |
| 2808 |
/* ARM requires that S<->D conversion of any kind of NaN generates
|
| 2809 |
* a quiet NaN by forcing the most significant frac bit to 1.
|
| 2810 |
*/
|
| 2811 |
return float64_maybe_silence_nan(r);
|
| 2812 |
} |
| 2813 |
|
| 2814 |
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
| 2815 |
{
|
| 2816 |
float32 r = float64_to_float32(x, &env->vfp.fp_status); |
| 2817 |
/* ARM requires that S<->D conversion of any kind of NaN generates
|
| 2818 |
* a quiet NaN by forcing the most significant frac bit to 1.
|
| 2819 |
*/
|
| 2820 |
return float32_maybe_silence_nan(r);
|
| 2821 |
} |
| 2822 |
|
| 2823 |
/* VFP3 fixed point conversion. */
|
| 2824 |
#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
|
| 2825 |
float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \ |
| 2826 |
void *fpstp) \
|
| 2827 |
{ \
|
| 2828 |
float_status *fpst = fpstp; \ |
| 2829 |
float##fsz tmp; \ |
| 2830 |
tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \ |
| 2831 |
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
| 2832 |
} \ |
| 2833 |
uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \ |
| 2834 |
void *fpstp) \
|
| 2835 |
{ \
|
| 2836 |
float_status *fpst = fpstp; \ |
| 2837 |
float##fsz tmp; \ |
| 2838 |
if (float##fsz##_is_any_nan(x)) { \ |
| 2839 |
float_raise(float_flag_invalid, fpst); \ |
| 2840 |
return 0; \ |
| 2841 |
} \ |
| 2842 |
tmp = float##fsz##_scalbn(x, shift, fpst); \ |
| 2843 |
return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \ |
| 2844 |
} |
| 2845 |
|
| 2846 |
VFP_CONV_FIX(sh, d, 64, int16, )
|
| 2847 |
VFP_CONV_FIX(sl, d, 64, int32, )
|
| 2848 |
VFP_CONV_FIX(uh, d, 64, uint16, u)
|
| 2849 |
VFP_CONV_FIX(ul, d, 64, uint32, u)
|
| 2850 |
VFP_CONV_FIX(sh, s, 32, int16, )
|
| 2851 |
VFP_CONV_FIX(sl, s, 32, int32, )
|
| 2852 |
VFP_CONV_FIX(uh, s, 32, uint16, u)
|
| 2853 |
VFP_CONV_FIX(ul, s, 32, uint32, u)
|
| 2854 |
#undef VFP_CONV_FIX
|
| 2855 |
|
| 2856 |
/* Half precision conversions. */
|
| 2857 |
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
|
| 2858 |
{
|
| 2859 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
| 2860 |
float32 r = float16_to_float32(make_float16(a), ieee, s); |
| 2861 |
if (ieee) {
|
| 2862 |
return float32_maybe_silence_nan(r);
|
| 2863 |
} |
| 2864 |
return r;
|
| 2865 |
} |
| 2866 |
|
| 2867 |
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
|
| 2868 |
{
|
| 2869 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
| 2870 |
float16 r = float32_to_float16(a, ieee, s); |
| 2871 |
if (ieee) {
|
| 2872 |
r = float16_maybe_silence_nan(r); |
| 2873 |
} |
| 2874 |
return float16_val(r);
|
| 2875 |
} |
| 2876 |
|
| 2877 |
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
| 2878 |
{
|
| 2879 |
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
|
| 2880 |
} |
| 2881 |
|
| 2882 |
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
| 2883 |
{
|
| 2884 |
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
|
| 2885 |
} |
| 2886 |
|
| 2887 |
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
| 2888 |
{
|
| 2889 |
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
|
| 2890 |
} |
| 2891 |
|
| 2892 |
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
| 2893 |
{
|
| 2894 |
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
|
| 2895 |
} |
| 2896 |
|
| 2897 |
#define float32_two make_float32(0x40000000) |
| 2898 |
#define float32_three make_float32(0x40400000) |
| 2899 |
#define float32_one_point_five make_float32(0x3fc00000) |
| 2900 |
|
| 2901 |
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
| 2902 |
{
|
| 2903 |
float_status *s = &env->vfp.standard_fp_status; |
| 2904 |
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
| 2905 |
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
|
| 2906 |
if (!(float32_is_zero(a) || float32_is_zero(b))) {
|
| 2907 |
float_raise(float_flag_input_denormal, s); |
| 2908 |
} |
| 2909 |
return float32_two;
|
| 2910 |
} |
| 2911 |
return float32_sub(float32_two, float32_mul(a, b, s), s);
|
| 2912 |
} |
| 2913 |
|
| 2914 |
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
| 2915 |
{
|
| 2916 |
float_status *s = &env->vfp.standard_fp_status; |
| 2917 |
float32 product; |
| 2918 |
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
| 2919 |
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
|
| 2920 |
if (!(float32_is_zero(a) || float32_is_zero(b))) {
|
| 2921 |
float_raise(float_flag_input_denormal, s); |
| 2922 |
} |
| 2923 |
return float32_one_point_five;
|
| 2924 |
} |
| 2925 |
product = float32_mul(a, b, s); |
| 2926 |
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
|
| 2927 |
} |
| 2928 |
|
| 2929 |
/* NEON helpers. */
|
| 2930 |
|
| 2931 |
/* Constants 256 and 512 are used in some helpers; we avoid relying on
|
| 2932 |
* int->float conversions at run-time. */
|
| 2933 |
#define float64_256 make_float64(0x4070000000000000LL) |
| 2934 |
#define float64_512 make_float64(0x4080000000000000LL) |
| 2935 |
|
| 2936 |
/* The algorithm that must be used to calculate the estimate
|
| 2937 |
* is specified by the ARM ARM.
|
| 2938 |
*/
|
| 2939 |
static float64 recip_estimate(float64 a, CPUARMState *env)
|
| 2940 |
{
|
| 2941 |
/* These calculations mustn't set any fp exception flags,
|
| 2942 |
* so we use a local copy of the fp_status.
|
| 2943 |
*/
|
| 2944 |
float_status dummy_status = env->vfp.standard_fp_status; |
| 2945 |
float_status *s = &dummy_status; |
| 2946 |
/* q = (int)(a * 512.0) */
|
| 2947 |
float64 q = float64_mul(float64_512, a, s); |
| 2948 |
int64_t q_int = float64_to_int64_round_to_zero(q, s); |
| 2949 |
|
| 2950 |
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
|
| 2951 |
q = int64_to_float64(q_int, s); |
| 2952 |
q = float64_add(q, float64_half, s); |
| 2953 |
q = float64_div(q, float64_512, s); |
| 2954 |
q = float64_div(float64_one, q, s); |
| 2955 |
|
| 2956 |
/* s = (int)(256.0 * r + 0.5) */
|
| 2957 |
q = float64_mul(q, float64_256, s); |
| 2958 |
q = float64_add(q, float64_half, s); |
| 2959 |
q_int = float64_to_int64_round_to_zero(q, s); |
| 2960 |
|
| 2961 |
/* return (double)s / 256.0 */
|
| 2962 |
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
| 2963 |
} |
| 2964 |
|
| 2965 |
float32 HELPER(recpe_f32)(float32 a, CPUARMState *env) |
| 2966 |
{
|
| 2967 |
float_status *s = &env->vfp.standard_fp_status; |
| 2968 |
float64 f64; |
| 2969 |
uint32_t val32 = float32_val(a); |
| 2970 |
|
| 2971 |
int result_exp;
|
| 2972 |
int a_exp = (val32 & 0x7f800000) >> 23; |
| 2973 |
int sign = val32 & 0x80000000; |
| 2974 |
|
| 2975 |
if (float32_is_any_nan(a)) {
|
| 2976 |
if (float32_is_signaling_nan(a)) {
|
| 2977 |
float_raise(float_flag_invalid, s); |
| 2978 |
} |
| 2979 |
return float32_default_nan;
|
| 2980 |
} else if (float32_is_infinity(a)) { |
| 2981 |
return float32_set_sign(float32_zero, float32_is_neg(a));
|
| 2982 |
} else if (float32_is_zero_or_denormal(a)) { |
| 2983 |
if (!float32_is_zero(a)) {
|
| 2984 |
float_raise(float_flag_input_denormal, s); |
| 2985 |
} |
| 2986 |
float_raise(float_flag_divbyzero, s); |
| 2987 |
return float32_set_sign(float32_infinity, float32_is_neg(a));
|
| 2988 |
} else if (a_exp >= 253) { |
| 2989 |
float_raise(float_flag_underflow, s); |
| 2990 |
return float32_set_sign(float32_zero, float32_is_neg(a));
|
| 2991 |
} |
| 2992 |
|
| 2993 |
f64 = make_float64((0x3feULL << 52) |
| 2994 |
| ((int64_t)(val32 & 0x7fffff) << 29)); |
| 2995 |
|
| 2996 |
result_exp = 253 - a_exp;
|
| 2997 |
|
| 2998 |
f64 = recip_estimate(f64, env); |
| 2999 |
|
| 3000 |
val32 = sign |
| 3001 |
| ((result_exp & 0xff) << 23) |
| 3002 |
| ((float64_val(f64) >> 29) & 0x7fffff); |
| 3003 |
return make_float32(val32);
|
| 3004 |
} |
| 3005 |
|
| 3006 |
/* The algorithm that must be used to calculate the estimate
|
| 3007 |
* is specified by the ARM ARM.
|
| 3008 |
*/
|
| 3009 |
static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
|
| 3010 |
{
|
| 3011 |
/* These calculations mustn't set any fp exception flags,
|
| 3012 |
* so we use a local copy of the fp_status.
|
| 3013 |
*/
|
| 3014 |
float_status dummy_status = env->vfp.standard_fp_status; |
| 3015 |
float_status *s = &dummy_status; |
| 3016 |
float64 q; |
| 3017 |
int64_t q_int; |
| 3018 |
|
| 3019 |
if (float64_lt(a, float64_half, s)) {
|
| 3020 |
/* range 0.25 <= a < 0.5 */
|
| 3021 |
|
| 3022 |
/* a in units of 1/512 rounded down */
|
| 3023 |
/* q0 = (int)(a * 512.0); */
|
| 3024 |
q = float64_mul(float64_512, a, s); |
| 3025 |
q_int = float64_to_int64_round_to_zero(q, s); |
| 3026 |
|
| 3027 |
/* reciprocal root r */
|
| 3028 |
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
|
| 3029 |
q = int64_to_float64(q_int, s); |
| 3030 |
q = float64_add(q, float64_half, s); |
| 3031 |
q = float64_div(q, float64_512, s); |
| 3032 |
q = float64_sqrt(q, s); |
| 3033 |
q = float64_div(float64_one, q, s); |
| 3034 |
} else {
|
| 3035 |
/* range 0.5 <= a < 1.0 */
|
| 3036 |
|
| 3037 |
/* a in units of 1/256 rounded down */
|
| 3038 |
/* q1 = (int)(a * 256.0); */
|
| 3039 |
q = float64_mul(float64_256, a, s); |
| 3040 |
int64_t q_int = float64_to_int64_round_to_zero(q, s); |
| 3041 |
|
| 3042 |
/* reciprocal root r */
|
| 3043 |
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
|
| 3044 |
q = int64_to_float64(q_int, s); |
| 3045 |
q = float64_add(q, float64_half, s); |
| 3046 |
q = float64_div(q, float64_256, s); |
| 3047 |
q = float64_sqrt(q, s); |
| 3048 |
q = float64_div(float64_one, q, s); |
| 3049 |
} |
| 3050 |
/* r in units of 1/256 rounded to nearest */
|
| 3051 |
/* s = (int)(256.0 * r + 0.5); */
|
| 3052 |
|
| 3053 |
q = float64_mul(q, float64_256,s ); |
| 3054 |
q = float64_add(q, float64_half, s); |
| 3055 |
q_int = float64_to_int64_round_to_zero(q, s); |
| 3056 |
|
| 3057 |
/* return (double)s / 256.0;*/
|
| 3058 |
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
| 3059 |
} |
| 3060 |
|
| 3061 |
float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env) |
| 3062 |
{
|
| 3063 |
float_status *s = &env->vfp.standard_fp_status; |
| 3064 |
int result_exp;
|
| 3065 |
float64 f64; |
| 3066 |
uint32_t val; |
| 3067 |
uint64_t val64; |
| 3068 |
|
| 3069 |
val = float32_val(a); |
| 3070 |
|
| 3071 |
if (float32_is_any_nan(a)) {
|
| 3072 |
if (float32_is_signaling_nan(a)) {
|
| 3073 |
float_raise(float_flag_invalid, s); |
| 3074 |
} |
| 3075 |
return float32_default_nan;
|
| 3076 |
} else if (float32_is_zero_or_denormal(a)) { |
| 3077 |
if (!float32_is_zero(a)) {
|
| 3078 |
float_raise(float_flag_input_denormal, s); |
| 3079 |
} |
| 3080 |
float_raise(float_flag_divbyzero, s); |
| 3081 |
return float32_set_sign(float32_infinity, float32_is_neg(a));
|
| 3082 |
} else if (float32_is_neg(a)) { |
| 3083 |
float_raise(float_flag_invalid, s); |
| 3084 |
return float32_default_nan;
|
| 3085 |
} else if (float32_is_infinity(a)) { |
| 3086 |
return float32_zero;
|
| 3087 |
} |
| 3088 |
|
| 3089 |
/* Normalize to a double-precision value between 0.25 and 1.0,
|
| 3090 |
* preserving the parity of the exponent. */
|
| 3091 |
if ((val & 0x800000) == 0) { |
| 3092 |
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) |
| 3093 |
| (0x3feULL << 52) |
| 3094 |
| ((uint64_t)(val & 0x7fffff) << 29)); |
| 3095 |
} else {
|
| 3096 |
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) |
| 3097 |
| (0x3fdULL << 52) |
| 3098 |
| ((uint64_t)(val & 0x7fffff) << 29)); |
| 3099 |
} |
| 3100 |
|
| 3101 |
result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2; |
| 3102 |
|
| 3103 |
f64 = recip_sqrt_estimate(f64, env); |
| 3104 |
|
| 3105 |
val64 = float64_val(f64); |
| 3106 |
|
| 3107 |
val = ((result_exp & 0xff) << 23) |
| 3108 |
| ((val64 >> 29) & 0x7fffff); |
| 3109 |
return make_float32(val);
|
| 3110 |
} |
| 3111 |
|
| 3112 |
uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env) |
| 3113 |
{
|
| 3114 |
float64 f64; |
| 3115 |
|
| 3116 |
if ((a & 0x80000000) == 0) { |
| 3117 |
return 0xffffffff; |
| 3118 |
} |
| 3119 |
|
| 3120 |
f64 = make_float64((0x3feULL << 52) |
| 3121 |
| ((int64_t)(a & 0x7fffffff) << 21)); |
| 3122 |
|
| 3123 |
f64 = recip_estimate (f64, env); |
| 3124 |
|
| 3125 |
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); |
| 3126 |
} |
| 3127 |
|
| 3128 |
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env) |
| 3129 |
{
|
| 3130 |
float64 f64; |
| 3131 |
|
| 3132 |
if ((a & 0xc0000000) == 0) { |
| 3133 |
return 0xffffffff; |
| 3134 |
} |
| 3135 |
|
| 3136 |
if (a & 0x80000000) { |
| 3137 |
f64 = make_float64((0x3feULL << 52) |
| 3138 |
| ((uint64_t)(a & 0x7fffffff) << 21)); |
| 3139 |
} else { /* bits 31-30 == '01' */ |
| 3140 |
f64 = make_float64((0x3fdULL << 52) |
| 3141 |
| ((uint64_t)(a & 0x3fffffff) << 22)); |
| 3142 |
} |
| 3143 |
|
| 3144 |
f64 = recip_sqrt_estimate(f64, env); |
| 3145 |
|
| 3146 |
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); |
| 3147 |
} |
| 3148 |
|
| 3149 |
/* VFPv4 fused multiply-accumulate */
|
| 3150 |
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
|
| 3151 |
{
|
| 3152 |
float_status *fpst = fpstp; |
| 3153 |
return float32_muladd(a, b, c, 0, fpst); |
| 3154 |
} |
| 3155 |
|
| 3156 |
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
|
| 3157 |
{
|
| 3158 |
float_status *fpst = fpstp; |
| 3159 |
return float64_muladd(a, b, c, 0, fpst); |
| 3160 |
} |