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/*
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* QEMU M48T59 NVRAM emulation for PPC PREP platform
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*
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* Copyright (c) 2003-2004 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "m48t59.h" |
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
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#else
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#define NVRAM_PRINTF(fmt, args...) do { } while (0) |
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#endif
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struct m48t59_t {
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/* Hardware parameters */
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int IRQ;
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int mem_index;
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uint32_t mem_base; |
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uint32_t io_base; |
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uint16_t size; |
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/* RTC management */
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time_t time_offset; |
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time_t stop_time; |
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/* Alarm & watchdog */
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time_t alarm; |
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t lock; |
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uint16_t addr; |
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uint8_t *buffer; |
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}; |
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/* Fake timer functions */
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/* Generic helpers for BCD */
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static inline uint8_t toBCD (uint8_t value) |
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{ |
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return (((value / 10) % 10) << 4) | (value % 10); |
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} |
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static inline uint8_t fromBCD (uint8_t BCD) |
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{ |
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return ((BCD >> 4) * 10) + (BCD & 0x0F); |
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} |
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/* RTC management helpers */
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static void get_time (m48t59_t *NVRAM, struct tm *tm) |
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{ |
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time_t t; |
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t = time(NULL) + NVRAM->time_offset;
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#ifdef _WIN32
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memcpy(tm,localtime(&t),sizeof(*tm));
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#else
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localtime_r (&t, tm) ; |
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#endif
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} |
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static void set_time (m48t59_t *NVRAM, struct tm *tm) |
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{ |
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time_t now, new_time; |
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new_time = mktime(tm); |
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now = time(NULL);
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NVRAM->time_offset = new_time - now; |
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} |
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/* Alarm management */
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static void alarm_cb (void *opaque) |
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{ |
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struct tm tm, tm_now;
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uint64_t next_time; |
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m48t59_t *NVRAM = opaque; |
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pic_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a month */
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get_time(NVRAM, &tm_now); |
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memcpy(&tm, &tm_now, sizeof(struct tm)); |
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tm.tm_mon++; |
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if (tm.tm_mon == 13) { |
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tm.tm_mon = 1;
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tm.tm_year++; |
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} |
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next_time = mktime(&tm); |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a day */
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next_time = 24 * 60 * 60 + mktime(&tm_now); |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once an hour */
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next_time = 60 * 60 + mktime(&tm_now); |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a minute */
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next_time = 60 + mktime(&tm_now);
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} else {
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/* Repeat once a second */
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next_time = 1 + mktime(&tm_now);
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} |
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qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
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pic_set_irq(NVRAM->IRQ, 0);
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} |
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static void get_alarm (m48t59_t *NVRAM, struct tm *tm) |
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{ |
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#ifdef _WIN32
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memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
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#else
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localtime_r (&NVRAM->alarm, tm); |
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#endif
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} |
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static void set_alarm (m48t59_t *NVRAM, struct tm *tm) |
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{ |
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NVRAM->alarm = mktime(tm); |
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if (NVRAM->alrm_timer != NULL) { |
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qemu_del_timer(NVRAM->alrm_timer); |
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NVRAM->alrm_timer = NULL;
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} |
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if (NVRAM->alarm - time(NULL) > 0) |
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qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
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} |
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/* Watchdog management */
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static void watchdog_cb (void *opaque) |
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{ |
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m48t59_t *NVRAM = opaque; |
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NVRAM->buffer[0x1FF0] |= 0x80; |
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if (NVRAM->buffer[0x1FF7] & 0x80) { |
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NVRAM->buffer[0x1FF7] = 0x00; |
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NVRAM->buffer[0x1FFC] &= ~0x40; |
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request(); |
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} else {
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pic_set_irq(NVRAM->IRQ, 1);
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pic_set_irq(NVRAM->IRQ, 0);
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} |
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} |
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static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
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{ |
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uint64_t interval; /* in 1/16 seconds */
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if (NVRAM->wd_timer != NULL) { |
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qemu_del_timer(NVRAM->wd_timer); |
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NVRAM->wd_timer = NULL;
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} |
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NVRAM->buffer[0x1FF0] &= ~0x80; |
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if (value != 0) { |
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
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((interval * 1000) >> 4)); |
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} |
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} |
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/* Direct access to NVRAM */
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void m48t59_write (m48t59_t *NVRAM, uint32_t val)
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{ |
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struct tm tm;
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int tmp;
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if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000) |
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
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switch (NVRAM->addr) {
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case 0x1FF0: |
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/* flags register : read-only */
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break;
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case 0x1FF1: |
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/* unused */
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break;
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case 0x1FF2: |
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/* alarm seconds */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_sec = tmp; |
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM, &tm); |
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} |
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break;
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case 0x1FF3: |
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/* alarm minutes */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_min = tmp; |
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM, &tm); |
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} |
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break;
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case 0x1FF4: |
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/* alarm hours */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_hour = tmp; |
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM, &tm); |
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} |
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break;
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case 0x1FF5: |
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/* alarm date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_mday = tmp; |
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM, &tm); |
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} |
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break;
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case 0x1FF6: |
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7: |
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val); |
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break;
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case 0x1FF8: |
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/* control */
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NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90; |
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break;
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case 0x1FF9: |
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/* seconds (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
263 |
tm.tm_sec = tmp; |
264 |
set_time(NVRAM, &tm); |
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} |
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if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) { |
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if (val & 0x80) { |
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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} |
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} |
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NVRAM->buffer[0x1FF9] = val & 0x80; |
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break;
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case 0x1FFA: |
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/* minutes (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
281 |
tm.tm_min = tmp; |
282 |
set_time(NVRAM, &tm); |
283 |
} |
284 |
break;
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case 0x1FFB: |
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/* hours (BCD) */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
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get_time(NVRAM, &tm); |
290 |
tm.tm_hour = tmp; |
291 |
set_time(NVRAM, &tm); |
292 |
} |
293 |
break;
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case 0x1FFC: |
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/* day of the week / century */
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tmp = fromBCD(val & 0x07);
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get_time(NVRAM, &tm); |
298 |
tm.tm_wday = tmp; |
299 |
set_time(NVRAM, &tm); |
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NVRAM->buffer[0x1FFC] = val & 0x40; |
301 |
break;
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case 0x1FFD: |
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/* date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) { |
306 |
get_time(NVRAM, &tm); |
307 |
tm.tm_mday = tmp; |
308 |
set_time(NVRAM, &tm); |
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} |
310 |
break;
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case 0x1FFE: |
312 |
/* month */
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tmp = fromBCD(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) { |
315 |
get_time(NVRAM, &tm); |
316 |
tm.tm_mon = tmp - 1;
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set_time(NVRAM, &tm); |
318 |
} |
319 |
break;
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case 0x1FFF: |
321 |
/* year */
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322 |
tmp = fromBCD(val); |
323 |
if (tmp >= 0 && tmp <= 99) { |
324 |
get_time(NVRAM, &tm); |
325 |
tm.tm_year = fromBCD(val); |
326 |
set_time(NVRAM, &tm); |
327 |
} |
328 |
break;
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default:
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/* Check lock registers state */
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331 |
if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1)) |
332 |
break;
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if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2)) |
334 |
break;
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if (NVRAM->addr < 0x1FF0 || |
336 |
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
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NVRAM->buffer[NVRAM->addr] = val & 0xFF;
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} |
339 |
break;
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} |
341 |
} |
342 |
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uint32_t m48t59_read (m48t59_t *NVRAM) |
344 |
{ |
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struct tm tm;
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uint32_t retval = 0xFF;
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347 |
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348 |
switch (NVRAM->addr) {
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case 0x1FF0: |
350 |
/* flags register */
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goto do_read;
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case 0x1FF1: |
353 |
/* unused */
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retval = 0;
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break;
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356 |
case 0x1FF2: |
357 |
/* alarm seconds */
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goto do_read;
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case 0x1FF3: |
360 |
/* alarm minutes */
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goto do_read;
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362 |
case 0x1FF4: |
363 |
/* alarm hours */
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364 |
goto do_read;
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365 |
case 0x1FF5: |
366 |
/* alarm date */
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367 |
goto do_read;
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368 |
case 0x1FF6: |
369 |
/* interrupts */
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370 |
goto do_read;
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371 |
case 0x1FF7: |
372 |
/* A read resets the watchdog */
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373 |
set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
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goto do_read;
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case 0x1FF8: |
376 |
/* control */
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377 |
goto do_read;
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378 |
case 0x1FF9: |
379 |
/* seconds (BCD) */
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380 |
get_time(NVRAM, &tm); |
381 |
retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec); |
382 |
break;
|
383 |
case 0x1FFA: |
384 |
/* minutes (BCD) */
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385 |
get_time(NVRAM, &tm); |
386 |
retval = toBCD(tm.tm_min); |
387 |
break;
|
388 |
case 0x1FFB: |
389 |
/* hours (BCD) */
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390 |
get_time(NVRAM, &tm); |
391 |
retval = toBCD(tm.tm_hour); |
392 |
break;
|
393 |
case 0x1FFC: |
394 |
/* day of the week / century */
|
395 |
get_time(NVRAM, &tm); |
396 |
retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
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397 |
break;
|
398 |
case 0x1FFD: |
399 |
/* date */
|
400 |
get_time(NVRAM, &tm); |
401 |
retval = toBCD(tm.tm_mday); |
402 |
break;
|
403 |
case 0x1FFE: |
404 |
/* month */
|
405 |
get_time(NVRAM, &tm); |
406 |
retval = toBCD(tm.tm_mon + 1);
|
407 |
break;
|
408 |
case 0x1FFF: |
409 |
/* year */
|
410 |
get_time(NVRAM, &tm); |
411 |
retval = toBCD(tm.tm_year); |
412 |
break;
|
413 |
default:
|
414 |
/* Check lock registers state */
|
415 |
if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1)) |
416 |
break;
|
417 |
if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2)) |
418 |
break;
|
419 |
if (NVRAM->addr < 0x1FF0 || |
420 |
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
421 |
do_read:
|
422 |
retval = NVRAM->buffer[NVRAM->addr]; |
423 |
} |
424 |
break;
|
425 |
} |
426 |
if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000) |
427 |
NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
|
428 |
|
429 |
return retval;
|
430 |
} |
431 |
|
432 |
void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
|
433 |
{ |
434 |
NVRAM->addr = addr; |
435 |
} |
436 |
|
437 |
void m48t59_toggle_lock (m48t59_t *NVRAM, int lock) |
438 |
{ |
439 |
NVRAM->lock ^= 1 << lock;
|
440 |
} |
441 |
|
442 |
/* IO access to NVRAM */
|
443 |
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
444 |
{ |
445 |
m48t59_t *NVRAM = opaque; |
446 |
|
447 |
addr -= NVRAM->io_base; |
448 |
NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
|
449 |
switch (addr) {
|
450 |
case 0: |
451 |
NVRAM->addr &= ~0x00FF;
|
452 |
NVRAM->addr |= val; |
453 |
break;
|
454 |
case 1: |
455 |
NVRAM->addr &= ~0xFF00;
|
456 |
NVRAM->addr |= val << 8;
|
457 |
break;
|
458 |
case 3: |
459 |
m48t59_write(NVRAM, val); |
460 |
NVRAM->addr = 0x0000;
|
461 |
break;
|
462 |
default:
|
463 |
break;
|
464 |
} |
465 |
} |
466 |
|
467 |
static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
468 |
{ |
469 |
m48t59_t *NVRAM = opaque; |
470 |
uint32_t retval; |
471 |
|
472 |
addr -= NVRAM->io_base; |
473 |
switch (addr) {
|
474 |
case 3: |
475 |
retval = m48t59_read(NVRAM); |
476 |
break;
|
477 |
default:
|
478 |
retval = -1;
|
479 |
break;
|
480 |
} |
481 |
NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
482 |
|
483 |
return retval;
|
484 |
} |
485 |
|
486 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
487 |
{ |
488 |
m48t59_t *NVRAM = opaque; |
489 |
|
490 |
addr -= NVRAM->mem_base; |
491 |
if (addr < 0x1FF0) |
492 |
NVRAM->buffer[addr] = value; |
493 |
} |
494 |
|
495 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
496 |
{ |
497 |
m48t59_t *NVRAM = opaque; |
498 |
|
499 |
addr -= NVRAM->mem_base; |
500 |
if (addr < 0x1FF0) { |
501 |
NVRAM->buffer[addr] = value >> 8;
|
502 |
NVRAM->buffer[addr + 1] = value;
|
503 |
} |
504 |
} |
505 |
|
506 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
507 |
{ |
508 |
m48t59_t *NVRAM = opaque; |
509 |
|
510 |
addr -= NVRAM->mem_base; |
511 |
if (addr < 0x1FF0) { |
512 |
NVRAM->buffer[addr] = value >> 24;
|
513 |
NVRAM->buffer[addr + 1] = value >> 16; |
514 |
NVRAM->buffer[addr + 2] = value >> 8; |
515 |
NVRAM->buffer[addr + 3] = value;
|
516 |
} |
517 |
} |
518 |
|
519 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
520 |
{ |
521 |
m48t59_t *NVRAM = opaque; |
522 |
uint32_t retval = 0;
|
523 |
|
524 |
addr -= NVRAM->mem_base; |
525 |
if (addr < 0x1FF0) |
526 |
retval = NVRAM->buffer[addr]; |
527 |
|
528 |
return retval;
|
529 |
} |
530 |
|
531 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
532 |
{ |
533 |
m48t59_t *NVRAM = opaque; |
534 |
uint32_t retval = 0;
|
535 |
|
536 |
addr -= NVRAM->mem_base; |
537 |
if (addr < 0x1FF0) { |
538 |
retval = NVRAM->buffer[addr] << 8;
|
539 |
retval |= NVRAM->buffer[addr + 1];
|
540 |
} |
541 |
|
542 |
return retval;
|
543 |
} |
544 |
|
545 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
546 |
{ |
547 |
m48t59_t *NVRAM = opaque; |
548 |
uint32_t retval = 0;
|
549 |
|
550 |
addr -= NVRAM->mem_base; |
551 |
if (addr < 0x1FF0) { |
552 |
retval = NVRAM->buffer[addr] << 24;
|
553 |
retval |= NVRAM->buffer[addr + 1] << 16; |
554 |
retval |= NVRAM->buffer[addr + 2] << 8; |
555 |
retval |= NVRAM->buffer[addr + 3];
|
556 |
} |
557 |
|
558 |
return retval;
|
559 |
} |
560 |
|
561 |
static CPUWriteMemoryFunc *nvram_write[] = {
|
562 |
&nvram_writeb, |
563 |
&nvram_writew, |
564 |
&nvram_writel, |
565 |
}; |
566 |
|
567 |
static CPUReadMemoryFunc *nvram_read[] = {
|
568 |
&nvram_readb, |
569 |
&nvram_readw, |
570 |
&nvram_readl, |
571 |
}; |
572 |
/* Initialisation routine */
|
573 |
m48t59_t *m48t59_init (int IRQ, uint32_t mem_base,
|
574 |
uint32_t io_base, uint16_t size) |
575 |
{ |
576 |
m48t59_t *s; |
577 |
|
578 |
s = qemu_mallocz(sizeof(m48t59_t));
|
579 |
if (!s)
|
580 |
return NULL; |
581 |
s->buffer = qemu_mallocz(size); |
582 |
if (!s->buffer) {
|
583 |
qemu_free(s); |
584 |
return NULL; |
585 |
} |
586 |
s->IRQ = IRQ; |
587 |
s->size = size; |
588 |
s->mem_base = mem_base; |
589 |
s->io_base = io_base; |
590 |
s->addr = 0;
|
591 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
592 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
593 |
if (mem_base != 0) { |
594 |
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
595 |
cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
|
596 |
} |
597 |
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
598 |
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
599 |
s->lock = 0;
|
600 |
|
601 |
return s;
|
602 |
} |