root / hw / spapr_pci.c @ 3204db98
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1 | 3384f95c | David Gibson | /*
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2 | 3384f95c | David Gibson | * QEMU sPAPR PCI host originated from Uninorth PCI host
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3 | 3384f95c | David Gibson | *
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4 | 3384f95c | David Gibson | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
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5 | 3384f95c | David Gibson | * Copyright (C) 2011 David Gibson, IBM Corporation.
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6 | 3384f95c | David Gibson | *
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7 | 3384f95c | David Gibson | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 3384f95c | David Gibson | * of this software and associated documentation files (the "Software"), to deal
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9 | 3384f95c | David Gibson | * in the Software without restriction, including without limitation the rights
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10 | 3384f95c | David Gibson | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 3384f95c | David Gibson | * copies of the Software, and to permit persons to whom the Software is
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12 | 3384f95c | David Gibson | * furnished to do so, subject to the following conditions:
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13 | 3384f95c | David Gibson | *
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14 | 3384f95c | David Gibson | * The above copyright notice and this permission notice shall be included in
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15 | 3384f95c | David Gibson | * all copies or substantial portions of the Software.
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16 | 3384f95c | David Gibson | *
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17 | 3384f95c | David Gibson | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 3384f95c | David Gibson | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 3384f95c | David Gibson | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 3384f95c | David Gibson | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 3384f95c | David Gibson | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 3384f95c | David Gibson | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 3384f95c | David Gibson | * THE SOFTWARE.
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24 | 3384f95c | David Gibson | */
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25 | 3384f95c | David Gibson | #include "hw.h" |
26 | 3384f95c | David Gibson | #include "pci.h" |
27 | 3384f95c | David Gibson | #include "pci_host.h" |
28 | 3384f95c | David Gibson | #include "hw/spapr.h" |
29 | 3384f95c | David Gibson | #include "hw/spapr_pci.h" |
30 | 3384f95c | David Gibson | #include "exec-memory.h" |
31 | 3384f95c | David Gibson | #include <libfdt.h> |
32 | 3384f95c | David Gibson | |
33 | 3384f95c | David Gibson | #include "hw/pci_internals.h" |
34 | 3384f95c | David Gibson | |
35 | 3384f95c | David Gibson | static const uint32_t bars[] = { |
36 | 3384f95c | David Gibson | PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, |
37 | 3384f95c | David Gibson | PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, |
38 | 3384f95c | David Gibson | PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5 |
39 | 3384f95c | David Gibson | /*, PCI_ROM_ADDRESS*/
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40 | 3384f95c | David Gibson | }; |
41 | 3384f95c | David Gibson | |
42 | 3384f95c | David Gibson | static PCIDevice *find_dev(sPAPREnvironment *spapr,
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43 | 3384f95c | David Gibson | uint64_t buid, uint32_t config_addr) |
44 | 3384f95c | David Gibson | { |
45 | 3384f95c | David Gibson | DeviceState *qdev; |
46 | 3384f95c | David Gibson | int devfn = (config_addr >> 8) & 0xFF; |
47 | 3384f95c | David Gibson | sPAPRPHBState *phb; |
48 | 3384f95c | David Gibson | |
49 | 3384f95c | David Gibson | QLIST_FOREACH(phb, &spapr->phbs, list) { |
50 | 3384f95c | David Gibson | if (phb->buid != buid) {
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51 | 3384f95c | David Gibson | continue;
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52 | 3384f95c | David Gibson | } |
53 | 3384f95c | David Gibson | |
54 | 3a26360d | Anthony Liguori | QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) { |
55 | 3384f95c | David Gibson | PCIDevice *dev = (PCIDevice *)qdev; |
56 | 3384f95c | David Gibson | if (dev->devfn == devfn) {
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57 | 3384f95c | David Gibson | return dev;
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58 | 3384f95c | David Gibson | } |
59 | 3384f95c | David Gibson | } |
60 | 3384f95c | David Gibson | } |
61 | 3384f95c | David Gibson | |
62 | 3384f95c | David Gibson | return NULL; |
63 | 3384f95c | David Gibson | } |
64 | 3384f95c | David Gibson | |
65 | 3384f95c | David Gibson | static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr, |
66 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
67 | 3384f95c | David Gibson | target_ulong args, |
68 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
69 | 3384f95c | David Gibson | { |
70 | 3384f95c | David Gibson | uint32_t val, size, addr; |
71 | 3384f95c | David Gibson | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); |
72 | 3384f95c | David Gibson | PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
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73 | 3384f95c | David Gibson | |
74 | 3384f95c | David Gibson | if (!dev) {
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75 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
76 | 3384f95c | David Gibson | return;
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77 | 3384f95c | David Gibson | } |
78 | 3384f95c | David Gibson | size = rtas_ld(args, 3);
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79 | 3384f95c | David Gibson | addr = rtas_ld(args, 0) & 0xFF; |
80 | 3384f95c | David Gibson | val = pci_default_read_config(dev, addr, size); |
81 | 3384f95c | David Gibson | rtas_st(rets, 0, 0); |
82 | 3384f95c | David Gibson | rtas_st(rets, 1, val);
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83 | 3384f95c | David Gibson | } |
84 | 3384f95c | David Gibson | |
85 | 3384f95c | David Gibson | static void rtas_read_pci_config(sPAPREnvironment *spapr, |
86 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
87 | 3384f95c | David Gibson | target_ulong args, |
88 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
89 | 3384f95c | David Gibson | { |
90 | 3384f95c | David Gibson | uint32_t val, size, addr; |
91 | 3384f95c | David Gibson | PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0)); |
92 | 3384f95c | David Gibson | |
93 | 3384f95c | David Gibson | if (!dev) {
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94 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
95 | 3384f95c | David Gibson | return;
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96 | 3384f95c | David Gibson | } |
97 | 3384f95c | David Gibson | size = rtas_ld(args, 1);
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98 | 3384f95c | David Gibson | addr = rtas_ld(args, 0) & 0xFF; |
99 | 3384f95c | David Gibson | val = pci_default_read_config(dev, addr, size); |
100 | 3384f95c | David Gibson | rtas_st(rets, 0, 0); |
101 | 3384f95c | David Gibson | rtas_st(rets, 1, val);
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102 | 3384f95c | David Gibson | } |
103 | 3384f95c | David Gibson | |
104 | 3384f95c | David Gibson | static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr, |
105 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
106 | 3384f95c | David Gibson | target_ulong args, |
107 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
108 | 3384f95c | David Gibson | { |
109 | 3384f95c | David Gibson | uint32_t val, size, addr; |
110 | 3384f95c | David Gibson | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); |
111 | 3384f95c | David Gibson | PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
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112 | 3384f95c | David Gibson | |
113 | 3384f95c | David Gibson | if (!dev) {
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114 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
115 | 3384f95c | David Gibson | return;
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116 | 3384f95c | David Gibson | } |
117 | 3384f95c | David Gibson | val = rtas_ld(args, 4);
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118 | 3384f95c | David Gibson | size = rtas_ld(args, 3);
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119 | 3384f95c | David Gibson | addr = rtas_ld(args, 0) & 0xFF; |
120 | 3384f95c | David Gibson | pci_default_write_config(dev, addr, val, size); |
121 | 3384f95c | David Gibson | rtas_st(rets, 0, 0); |
122 | 3384f95c | David Gibson | } |
123 | 3384f95c | David Gibson | |
124 | 3384f95c | David Gibson | static void rtas_write_pci_config(sPAPREnvironment *spapr, |
125 | 3384f95c | David Gibson | uint32_t token, uint32_t nargs, |
126 | 3384f95c | David Gibson | target_ulong args, |
127 | 3384f95c | David Gibson | uint32_t nret, target_ulong rets) |
128 | 3384f95c | David Gibson | { |
129 | 3384f95c | David Gibson | uint32_t val, size, addr; |
130 | 3384f95c | David Gibson | PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0)); |
131 | 3384f95c | David Gibson | |
132 | 3384f95c | David Gibson | if (!dev) {
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133 | 3384f95c | David Gibson | rtas_st(rets, 0, -1); |
134 | 3384f95c | David Gibson | return;
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135 | 3384f95c | David Gibson | } |
136 | 3384f95c | David Gibson | val = rtas_ld(args, 2);
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137 | 3384f95c | David Gibson | size = rtas_ld(args, 1);
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138 | 3384f95c | David Gibson | addr = rtas_ld(args, 0) & 0xFF; |
139 | 3384f95c | David Gibson | pci_default_write_config(dev, addr, val, size); |
140 | 3384f95c | David Gibson | rtas_st(rets, 0, 0); |
141 | 3384f95c | David Gibson | } |
142 | 3384f95c | David Gibson | |
143 | 3384f95c | David Gibson | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
144 | 3384f95c | David Gibson | { |
145 | 3384f95c | David Gibson | /*
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146 | 3384f95c | David Gibson | * Here we need to convert pci_dev + irq_num to some unique value
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147 | 3384f95c | David Gibson | * which is less than number of IRQs on the specific bus (now it
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148 | 3384f95c | David Gibson | * is 16). At the moment irq_num == device_id (number of the
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149 | 3384f95c | David Gibson | * slot?)
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150 | 3384f95c | David Gibson | * FIXME: we should swizzle in fn and irq_num
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151 | 3384f95c | David Gibson | */
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152 | 3384f95c | David Gibson | return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI; |
153 | 3384f95c | David Gibson | } |
154 | 3384f95c | David Gibson | |
155 | 3384f95c | David Gibson | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) |
156 | 3384f95c | David Gibson | { |
157 | 3384f95c | David Gibson | /*
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158 | 3384f95c | David Gibson | * Here we use the number returned by pci_spapr_map_irq to find a
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159 | 3384f95c | David Gibson | * corresponding qemu_irq.
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160 | 3384f95c | David Gibson | */
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161 | 3384f95c | David Gibson | sPAPRPHBState *phb = opaque; |
162 | 3384f95c | David Gibson | |
163 | 3384f95c | David Gibson | qemu_set_irq(phb->lsi_table[irq_num].qirq, level); |
164 | 3384f95c | David Gibson | } |
165 | 3384f95c | David Gibson | |
166 | 3384f95c | David Gibson | static int spapr_phb_init(SysBusDevice *s) |
167 | 3384f95c | David Gibson | { |
168 | 3384f95c | David Gibson | sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s); |
169 | 3384f95c | David Gibson | int i;
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170 | 3384f95c | David Gibson | |
171 | 3384f95c | David Gibson | /* Initialize the LSI table */
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172 | 3384f95c | David Gibson | for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) { |
173 | 3384f95c | David Gibson | qemu_irq qirq; |
174 | 3384f95c | David Gibson | uint32_t num; |
175 | 3384f95c | David Gibson | |
176 | 3384f95c | David Gibson | qirq = spapr_allocate_irq(0, &num);
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177 | 3384f95c | David Gibson | if (!qirq) {
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178 | 3384f95c | David Gibson | return -1; |
179 | 3384f95c | David Gibson | } |
180 | 3384f95c | David Gibson | |
181 | 3384f95c | David Gibson | phb->lsi_table[i].dt_irq = num; |
182 | 3384f95c | David Gibson | phb->lsi_table[i].qirq = qirq; |
183 | 3384f95c | David Gibson | } |
184 | 3384f95c | David Gibson | |
185 | 3384f95c | David Gibson | return 0; |
186 | 3384f95c | David Gibson | } |
187 | 3384f95c | David Gibson | |
188 | 3384f95c | David Gibson | static int spapr_main_pci_host_init(PCIDevice *d) |
189 | 3384f95c | David Gibson | { |
190 | 3384f95c | David Gibson | return 0; |
191 | 3384f95c | David Gibson | } |
192 | 3384f95c | David Gibson | |
193 | 3384f95c | David Gibson | static PCIDeviceInfo spapr_main_pci_host_info = {
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194 | 3384f95c | David Gibson | .qdev.name = "spapr-pci-host-bridge",
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195 | 3384f95c | David Gibson | .qdev.size = sizeof(PCIDevice),
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196 | 3384f95c | David Gibson | .init = spapr_main_pci_host_init, |
197 | 3384f95c | David Gibson | }; |
198 | 3384f95c | David Gibson | |
199 | 3384f95c | David Gibson | static void spapr_register_devices(void) |
200 | 3384f95c | David Gibson | { |
201 | 3384f95c | David Gibson | sysbus_register_dev("spapr-pci-host-bridge", sizeof(sPAPRPHBState), |
202 | 3384f95c | David Gibson | spapr_phb_init); |
203 | 3384f95c | David Gibson | pci_qdev_register(&spapr_main_pci_host_info); |
204 | 3384f95c | David Gibson | } |
205 | 3384f95c | David Gibson | |
206 | 3384f95c | David Gibson | device_init(spapr_register_devices) |
207 | 3384f95c | David Gibson | |
208 | 3384f95c | David Gibson | static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr, |
209 | 3384f95c | David Gibson | unsigned size)
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210 | 3384f95c | David Gibson | { |
211 | 3384f95c | David Gibson | switch (size) {
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212 | 3384f95c | David Gibson | case 1: |
213 | 3384f95c | David Gibson | return cpu_inb(addr);
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214 | 3384f95c | David Gibson | case 2: |
215 | 3384f95c | David Gibson | return cpu_inw(addr);
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216 | 3384f95c | David Gibson | case 4: |
217 | 3384f95c | David Gibson | return cpu_inl(addr);
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218 | 3384f95c | David Gibson | } |
219 | 3384f95c | David Gibson | assert(0);
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220 | 3384f95c | David Gibson | } |
221 | 3384f95c | David Gibson | |
222 | 3384f95c | David Gibson | static void spapr_io_write(void *opaque, target_phys_addr_t addr, |
223 | 3384f95c | David Gibson | uint64_t data, unsigned size)
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224 | 3384f95c | David Gibson | { |
225 | 3384f95c | David Gibson | switch (size) {
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226 | 3384f95c | David Gibson | case 1: |
227 | 3384f95c | David Gibson | cpu_outb(addr, data); |
228 | 3384f95c | David Gibson | return;
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229 | 3384f95c | David Gibson | case 2: |
230 | 3384f95c | David Gibson | cpu_outw(addr, data); |
231 | 3384f95c | David Gibson | return;
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232 | 3384f95c | David Gibson | case 4: |
233 | 3384f95c | David Gibson | cpu_outl(addr, data); |
234 | 3384f95c | David Gibson | return;
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235 | 3384f95c | David Gibson | } |
236 | 3384f95c | David Gibson | assert(0);
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237 | 3384f95c | David Gibson | } |
238 | 3384f95c | David Gibson | |
239 | 3384f95c | David Gibson | static MemoryRegionOps spapr_io_ops = {
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240 | 3384f95c | David Gibson | .endianness = DEVICE_LITTLE_ENDIAN, |
241 | 3384f95c | David Gibson | .read = spapr_io_read, |
242 | 3384f95c | David Gibson | .write = spapr_io_write |
243 | 3384f95c | David Gibson | }; |
244 | 3384f95c | David Gibson | |
245 | 3384f95c | David Gibson | void spapr_create_phb(sPAPREnvironment *spapr,
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246 | 3384f95c | David Gibson | const char *busname, uint64_t buid, |
247 | 3384f95c | David Gibson | uint64_t mem_win_addr, uint64_t mem_win_size, |
248 | 3384f95c | David Gibson | uint64_t io_win_addr) |
249 | 3384f95c | David Gibson | { |
250 | 3384f95c | David Gibson | DeviceState *dev; |
251 | 3384f95c | David Gibson | SysBusDevice *s; |
252 | 3384f95c | David Gibson | sPAPRPHBState *phb; |
253 | 3384f95c | David Gibson | PCIBus *bus; |
254 | 3384f95c | David Gibson | char namebuf[strlen(busname)+11]; |
255 | 3384f95c | David Gibson | |
256 | 3384f95c | David Gibson | dev = qdev_create(NULL, "spapr-pci-host-bridge"); |
257 | 3384f95c | David Gibson | qdev_init_nofail(dev); |
258 | 3384f95c | David Gibson | s = sysbus_from_qdev(dev); |
259 | 3384f95c | David Gibson | phb = FROM_SYSBUS(sPAPRPHBState, s); |
260 | 3384f95c | David Gibson | |
261 | 3384f95c | David Gibson | phb->mem_win_addr = mem_win_addr; |
262 | 3384f95c | David Gibson | |
263 | 3384f95c | David Gibson | sprintf(namebuf, "%s-mem", busname);
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264 | 3384f95c | David Gibson | memory_region_init(&phb->memspace, namebuf, INT64_MAX); |
265 | 3384f95c | David Gibson | |
266 | 3384f95c | David Gibson | sprintf(namebuf, "%s-memwindow", busname);
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267 | 3384f95c | David Gibson | memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace, |
268 | 3384f95c | David Gibson | SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size); |
269 | 3384f95c | David Gibson | memory_region_add_subregion(get_system_memory(), mem_win_addr, |
270 | 3384f95c | David Gibson | &phb->memwindow); |
271 | 3384f95c | David Gibson | |
272 | 3384f95c | David Gibson | phb->io_win_addr = io_win_addr; |
273 | 3384f95c | David Gibson | |
274 | 3384f95c | David Gibson | /* On ppc, we only have MMIO no specific IO space from the CPU
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275 | 3384f95c | David Gibson | * perspective. In theory we ought to be able to embed the PCI IO
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276 | 3384f95c | David Gibson | * memory region direction in the system memory space. However,
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277 | 3384f95c | David Gibson | * if any of the IO BAR subregions use the old_portio mechanism,
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278 | 3384f95c | David Gibson | * that won't be processed properly unless accessed from the
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279 | 3384f95c | David Gibson | * system io address space. This hack to bounce things via
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280 | 3384f95c | David Gibson | * system_io works around the problem until all the users of
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281 | 3384f95c | David Gibson | * old_portion are updated */
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282 | 3384f95c | David Gibson | sprintf(namebuf, "%s-io", busname);
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283 | 3384f95c | David Gibson | memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE); |
284 | 3384f95c | David Gibson | /* FIXME: fix to support multiple PHBs */
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285 | 3384f95c | David Gibson | memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
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286 | 3384f95c | David Gibson | |
287 | 3384f95c | David Gibson | sprintf(namebuf, "%s-iowindow", busname);
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288 | 3384f95c | David Gibson | memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb, |
289 | 3384f95c | David Gibson | namebuf, SPAPR_PCI_IO_WIN_SIZE); |
290 | 3384f95c | David Gibson | memory_region_add_subregion(get_system_memory(), io_win_addr, |
291 | 3384f95c | David Gibson | &phb->iowindow); |
292 | 3384f95c | David Gibson | |
293 | 3384f95c | David Gibson | phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname, |
294 | 3384f95c | David Gibson | pci_spapr_set_irq, |
295 | 3384f95c | David Gibson | pci_spapr_map_irq, |
296 | 3384f95c | David Gibson | phb, |
297 | 3384f95c | David Gibson | &phb->memspace, &phb->iospace, |
298 | 3384f95c | David Gibson | PCI_DEVFN(0, 0), |
299 | 3384f95c | David Gibson | SPAPR_PCI_NUM_LSI); |
300 | 3384f95c | David Gibson | |
301 | 3384f95c | David Gibson | spapr_rtas_register("read-pci-config", rtas_read_pci_config);
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302 | 3384f95c | David Gibson | spapr_rtas_register("write-pci-config", rtas_write_pci_config);
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303 | 3384f95c | David Gibson | spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
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304 | 3384f95c | David Gibson | spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
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305 | 3384f95c | David Gibson | |
306 | 3384f95c | David Gibson | QLIST_INSERT_HEAD(&spapr->phbs, phb, list); |
307 | 3384f95c | David Gibson | |
308 | 3384f95c | David Gibson | /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
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309 | 3384f95c | David Gibson | } |
310 | 3384f95c | David Gibson | |
311 | 3384f95c | David Gibson | /* Macros to operate with address in OF binding to PCI */
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312 | 3384f95c | David Gibson | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) |
313 | 3384f95c | David Gibson | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ |
314 | 3384f95c | David Gibson | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ |
315 | 3384f95c | David Gibson | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ |
316 | 3384f95c | David Gibson | #define b_ss(x) b_x((x), 24, 2) /* the space code */ |
317 | 3384f95c | David Gibson | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ |
318 | 3384f95c | David Gibson | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ |
319 | 3384f95c | David Gibson | #define b_fff(x) b_x((x), 8, 3) /* function number */ |
320 | 3384f95c | David Gibson | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ |
321 | 3384f95c | David Gibson | |
322 | 3384f95c | David Gibson | static uint32_t regtype_to_ss(uint8_t type)
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323 | 3384f95c | David Gibson | { |
324 | 3384f95c | David Gibson | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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325 | 3384f95c | David Gibson | return 3; |
326 | 3384f95c | David Gibson | } |
327 | 3384f95c | David Gibson | if (type == PCI_BASE_ADDRESS_SPACE_IO) {
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328 | 3384f95c | David Gibson | return 1; |
329 | 3384f95c | David Gibson | } |
330 | 3384f95c | David Gibson | return 2; |
331 | 3384f95c | David Gibson | } |
332 | 3384f95c | David Gibson | |
333 | 3384f95c | David Gibson | int spapr_populate_pci_devices(sPAPRPHBState *phb,
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334 | 3384f95c | David Gibson | uint32_t xics_phandle, |
335 | 3384f95c | David Gibson | void *fdt)
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336 | 3384f95c | David Gibson | { |
337 | 3384f95c | David Gibson | PCIBus *bus = phb->host_state.bus; |
338 | 3384f95c | David Gibson | int bus_off, node_off = 0, devid, fn, i, n, devices; |
339 | 3384f95c | David Gibson | DeviceState *qdev; |
340 | 3384f95c | David Gibson | char nodename[256]; |
341 | 3384f95c | David Gibson | struct {
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342 | 3384f95c | David Gibson | uint32_t hi; |
343 | 3384f95c | David Gibson | uint64_t addr; |
344 | 3384f95c | David Gibson | uint64_t size; |
345 | 3384f95c | David Gibson | } __attribute__((packed)) reg[PCI_NUM_REGIONS + 1],
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346 | 3384f95c | David Gibson | assigned_addresses[PCI_NUM_REGIONS]; |
347 | 3384f95c | David Gibson | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
348 | 3384f95c | David Gibson | struct {
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349 | 3384f95c | David Gibson | uint32_t hi; |
350 | 3384f95c | David Gibson | uint64_t child; |
351 | 3384f95c | David Gibson | uint64_t parent; |
352 | 3384f95c | David Gibson | uint64_t size; |
353 | 3384f95c | David Gibson | } __attribute__((packed)) ranges[] = { |
354 | 3384f95c | David Gibson | { |
355 | 3384f95c | David Gibson | cpu_to_be32(b_ss(1)), cpu_to_be64(0), |
356 | 3384f95c | David Gibson | cpu_to_be64(phb->io_win_addr), |
357 | 3384f95c | David Gibson | cpu_to_be64(memory_region_size(&phb->iospace)), |
358 | 3384f95c | David Gibson | }, |
359 | 3384f95c | David Gibson | { |
360 | 3384f95c | David Gibson | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
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361 | 3384f95c | David Gibson | cpu_to_be64(phb->mem_win_addr), |
362 | 3384f95c | David Gibson | cpu_to_be64(memory_region_size(&phb->memwindow)), |
363 | 3384f95c | David Gibson | }, |
364 | 3384f95c | David Gibson | }; |
365 | 3384f95c | David Gibson | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
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366 | 3384f95c | David Gibson | uint32_t interrupt_map_mask[] = { |
367 | 3384f95c | David Gibson | cpu_to_be32(b_ddddd(-1)|b_fff(-1)), 0x0, 0x0, 0x0}; |
368 | 3384f95c | David Gibson | uint32_t interrupt_map[bus->nirq][7];
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369 | 3384f95c | David Gibson | |
370 | 3384f95c | David Gibson | /* Start populating the FDT */
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371 | 3384f95c | David Gibson | sprintf(nodename, "pci@%" PRIx64, phb->buid);
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372 | 3384f95c | David Gibson | bus_off = fdt_add_subnode(fdt, 0, nodename);
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373 | 3384f95c | David Gibson | if (bus_off < 0) { |
374 | 3384f95c | David Gibson | return bus_off;
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375 | 3384f95c | David Gibson | } |
376 | 3384f95c | David Gibson | |
377 | 3384f95c | David Gibson | #define _FDT(exp) \
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378 | 3384f95c | David Gibson | do { \
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379 | 3384f95c | David Gibson | int ret = (exp); \
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380 | 3384f95c | David Gibson | if (ret < 0) { \ |
381 | 3384f95c | David Gibson | return ret; \
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382 | 3384f95c | David Gibson | } \ |
383 | 3384f95c | David Gibson | } while (0) |
384 | 3384f95c | David Gibson | |
385 | 3384f95c | David Gibson | /* Write PHB properties */
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386 | 3384f95c | David Gibson | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); |
387 | 3384f95c | David Gibson | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); |
388 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); |
389 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); |
390 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); |
391 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); |
392 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); |
393 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); |
394 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); |
395 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
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396 | 3384f95c | David Gibson | &interrupt_map_mask, sizeof(interrupt_map_mask)));
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397 | 3384f95c | David Gibson | |
398 | 3384f95c | David Gibson | /* Populate PCI devices and allocate IRQs */
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399 | 3384f95c | David Gibson | devices = 0;
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400 | 3a26360d | Anthony Liguori | QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) { |
401 | 3384f95c | David Gibson | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
402 | 3384f95c | David Gibson | int irq_index = pci_spapr_map_irq(dev, 0); |
403 | 3384f95c | David Gibson | uint32_t *irqmap = interrupt_map[devices]; |
404 | 3384f95c | David Gibson | uint8_t *config = dev->config; |
405 | 3384f95c | David Gibson | |
406 | 3384f95c | David Gibson | devid = dev->devfn >> 3;
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407 | 3384f95c | David Gibson | fn = dev->devfn & 7;
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408 | 3384f95c | David Gibson | |
409 | 3384f95c | David Gibson | sprintf(nodename, "pci@%u,%u", devid, fn);
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410 | 3384f95c | David Gibson | |
411 | 3384f95c | David Gibson | /* Allocate interrupt from the map */
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412 | 3384f95c | David Gibson | if (devid > bus->nirq) {
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413 | 3384f95c | David Gibson | printf("Unexpected behaviour in spapr_populate_pci_devices,"
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414 | 3384f95c | David Gibson | "wrong devid %u\n", devid);
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415 | 3384f95c | David Gibson | exit(-1);
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416 | 3384f95c | David Gibson | } |
417 | 3384f95c | David Gibson | irqmap[0] = cpu_to_be32(b_ddddd(devid)|b_fff(fn));
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418 | 3384f95c | David Gibson | irqmap[1] = 0; |
419 | 3384f95c | David Gibson | irqmap[2] = 0; |
420 | 3384f95c | David Gibson | irqmap[3] = 0; |
421 | 3384f95c | David Gibson | irqmap[4] = cpu_to_be32(xics_phandle);
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422 | 3384f95c | David Gibson | irqmap[5] = cpu_to_be32(phb->lsi_table[irq_index].dt_irq);
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423 | 3384f95c | David Gibson | irqmap[6] = cpu_to_be32(0x8); |
424 | 3384f95c | David Gibson | |
425 | 3384f95c | David Gibson | /* Add node to FDT */
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426 | 3384f95c | David Gibson | node_off = fdt_add_subnode(fdt, bus_off, nodename); |
427 | 3384f95c | David Gibson | if (node_off < 0) { |
428 | 3384f95c | David Gibson | return node_off;
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429 | 3384f95c | David Gibson | } |
430 | 3384f95c | David Gibson | |
431 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "vendor-id",
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432 | 3384f95c | David Gibson | pci_get_word(&config[PCI_VENDOR_ID]))); |
433 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "device-id",
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434 | 3384f95c | David Gibson | pci_get_word(&config[PCI_DEVICE_ID]))); |
435 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "revision-id",
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436 | 3384f95c | David Gibson | pci_get_byte(&config[PCI_REVISION_ID]))); |
437 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "class-code",
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438 | 3384f95c | David Gibson | pci_get_long(&config[PCI_CLASS_REVISION]) >> 8));
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439 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-id",
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440 | 3384f95c | David Gibson | pci_get_word(&config[PCI_SUBSYSTEM_ID]))); |
441 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-vendor-id",
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442 | 3384f95c | David Gibson | pci_get_word(&config[PCI_SUBSYSTEM_VENDOR_ID]))); |
443 | 3384f95c | David Gibson | |
444 | 3384f95c | David Gibson | /* Config space region comes first */
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445 | 3384f95c | David Gibson | reg[0].hi = cpu_to_be32(
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446 | 3384f95c | David Gibson | b_n(0) |
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447 | 3384f95c | David Gibson | b_p(0) |
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448 | 3384f95c | David Gibson | b_t(0) |
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449 | 3384f95c | David Gibson | b_ss(0/*config*/) | |
450 | 3384f95c | David Gibson | b_bbbbbbbb(0) |
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451 | 3384f95c | David Gibson | b_ddddd(devid) | |
452 | 3384f95c | David Gibson | b_fff(fn)); |
453 | 3384f95c | David Gibson | reg[0].addr = 0; |
454 | 3384f95c | David Gibson | reg[0].size = 0; |
455 | 3384f95c | David Gibson | |
456 | 3384f95c | David Gibson | n = 0;
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457 | 3384f95c | David Gibson | for (i = 0; i < PCI_NUM_REGIONS; ++i) { |
458 | 3384f95c | David Gibson | if (0 == dev->io_regions[i].size) { |
459 | 3384f95c | David Gibson | continue;
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460 | 3384f95c | David Gibson | } |
461 | 3384f95c | David Gibson | |
462 | 3384f95c | David Gibson | reg[n+1].hi = cpu_to_be32(
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463 | 3384f95c | David Gibson | b_n(0) |
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464 | 3384f95c | David Gibson | b_p(0) |
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465 | 3384f95c | David Gibson | b_t(0) |
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466 | 3384f95c | David Gibson | b_ss(regtype_to_ss(dev->io_regions[i].type)) | |
467 | 3384f95c | David Gibson | b_bbbbbbbb(0) |
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468 | 3384f95c | David Gibson | b_ddddd(devid) | |
469 | 3384f95c | David Gibson | b_fff(fn) | |
470 | 3384f95c | David Gibson | b_rrrrrrrr(bars[i])); |
471 | 3384f95c | David Gibson | reg[n+1].addr = 0; |
472 | 3384f95c | David Gibson | reg[n+1].size = cpu_to_be64(dev->io_regions[i].size);
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473 | 3384f95c | David Gibson | |
474 | 3384f95c | David Gibson | assigned_addresses[n].hi = cpu_to_be32( |
475 | 3384f95c | David Gibson | b_n(1) |
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476 | 3384f95c | David Gibson | b_p(0) |
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477 | 3384f95c | David Gibson | b_t(0) |
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478 | 3384f95c | David Gibson | b_ss(regtype_to_ss(dev->io_regions[i].type)) | |
479 | 3384f95c | David Gibson | b_bbbbbbbb(0) |
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480 | 3384f95c | David Gibson | b_ddddd(devid) | |
481 | 3384f95c | David Gibson | b_fff(fn) | |
482 | 3384f95c | David Gibson | b_rrrrrrrr(bars[i])); |
483 | 3384f95c | David Gibson | |
484 | 3384f95c | David Gibson | /*
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485 | 3384f95c | David Gibson | * Writing zeroes to assigned_addresses causes the guest kernel to
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486 | 3384f95c | David Gibson | * reassign BARs
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487 | 3384f95c | David Gibson | */
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488 | 3384f95c | David Gibson | assigned_addresses[n].addr = cpu_to_be64(dev->io_regions[i].addr); |
489 | 3384f95c | David Gibson | assigned_addresses[n].size = reg[n+1].size;
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490 | 3384f95c | David Gibson | |
491 | 3384f95c | David Gibson | ++n; |
492 | 3384f95c | David Gibson | } |
493 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, node_off, "reg", reg, sizeof(reg[0])*(n+1))); |
494 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, node_off, "assigned-addresses",
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495 | 3384f95c | David Gibson | assigned_addresses, |
496 | 3384f95c | David Gibson | sizeof(assigned_addresses[0])*(n))); |
497 | 3384f95c | David Gibson | _FDT(fdt_setprop_cell(fdt, node_off, "interrupts",
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498 | 3384f95c | David Gibson | pci_get_byte(&config[PCI_INTERRUPT_PIN]))); |
499 | 3384f95c | David Gibson | |
500 | 3384f95c | David Gibson | ++devices; |
501 | 3384f95c | David Gibson | } |
502 | 3384f95c | David Gibson | |
503 | 3384f95c | David Gibson | /* Write interrupt map */
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504 | 3384f95c | David Gibson | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
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505 | 3384f95c | David Gibson | devices * sizeof(interrupt_map[0]))); |
506 | 3384f95c | David Gibson | |
507 | 3384f95c | David Gibson | return 0; |
508 | 3384f95c | David Gibson | } |