Revision 32600a30 hw/e1000.c
| b/hw/e1000.c | ||
|---|---|---|
| 857 | 857 |
E1000State *s = opaque; |
| 858 | 858 |
unsigned int index = (addr & 0x1ffff) >> 2; |
| 859 | 859 |
|
| 860 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 861 |
val = bswap32(val); |
|
| 862 |
#endif |
|
| 863 | 860 |
if (index < NWRITEOPS && macreg_writeops[index]) {
|
| 864 | 861 |
macreg_writeops[index](s, index, val); |
| 865 | 862 |
} else if (index < NREADOPS && macreg_readops[index]) {
|
| ... | ... | |
| 894 | 891 |
|
| 895 | 892 |
if (index < NREADOPS && macreg_readops[index]) |
| 896 | 893 |
{
|
| 897 |
uint32_t val = macreg_readops[index](s, index); |
|
| 898 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 899 |
val = bswap32(val); |
|
| 900 |
#endif |
|
| 901 |
return val; |
|
| 894 |
return macreg_readops[index](s, index); |
|
| 902 | 895 |
} |
| 903 | 896 |
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); |
| 904 | 897 |
return 0; |
| ... | ... | |
| 1131 | 1124 |
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 |
| 1132 | 1125 |
|
| 1133 | 1126 |
d->mmio_index = cpu_register_io_memory(e1000_mmio_read, |
| 1134 |
e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
|
|
| 1127 |
e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
|
|
| 1135 | 1128 |
|
| 1136 | 1129 |
pci_register_bar(&d->dev, 0, PNPMMIO_SIZE, |
| 1137 | 1130 |
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map); |
Also available in: Unified diff