root / hw / usb-uhci.c @ 326700e3
History | View | Annotate | Download (34.4 kB)
1 |
/*
|
---|---|
2 |
* USB UHCI controller emulation
|
3 |
*
|
4 |
* Copyright (c) 2005 Fabrice Bellard
|
5 |
*
|
6 |
* Copyright (c) 2008 Max Krasnyansky
|
7 |
* Magor rewrite of the UHCI data structures parser and frame processor
|
8 |
* Support for fully async operation and multiple outstanding transactions
|
9 |
*
|
10 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
11 |
* of this software and associated documentation files (the "Software"), to deal
|
12 |
* in the Software without restriction, including without limitation the rights
|
13 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
14 |
* copies of the Software, and to permit persons to whom the Software is
|
15 |
* furnished to do so, subject to the following conditions:
|
16 |
*
|
17 |
* The above copyright notice and this permission notice shall be included in
|
18 |
* all copies or substantial portions of the Software.
|
19 |
*
|
20 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
21 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
22 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
23 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
24 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
25 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
26 |
* THE SOFTWARE.
|
27 |
*/
|
28 |
#include "hw.h" |
29 |
#include "usb.h" |
30 |
#include "pci.h" |
31 |
#include "qemu-timer.h" |
32 |
#include "usb-uhci.h" |
33 |
#include "iov.h" |
34 |
#include "dma.h" |
35 |
|
36 |
//#define DEBUG
|
37 |
//#define DEBUG_DUMP_DATA
|
38 |
|
39 |
#define UHCI_CMD_FGR (1 << 4) |
40 |
#define UHCI_CMD_EGSM (1 << 3) |
41 |
#define UHCI_CMD_GRESET (1 << 2) |
42 |
#define UHCI_CMD_HCRESET (1 << 1) |
43 |
#define UHCI_CMD_RS (1 << 0) |
44 |
|
45 |
#define UHCI_STS_HCHALTED (1 << 5) |
46 |
#define UHCI_STS_HCPERR (1 << 4) |
47 |
#define UHCI_STS_HSERR (1 << 3) |
48 |
#define UHCI_STS_RD (1 << 2) |
49 |
#define UHCI_STS_USBERR (1 << 1) |
50 |
#define UHCI_STS_USBINT (1 << 0) |
51 |
|
52 |
#define TD_CTRL_SPD (1 << 29) |
53 |
#define TD_CTRL_ERROR_SHIFT 27 |
54 |
#define TD_CTRL_IOS (1 << 25) |
55 |
#define TD_CTRL_IOC (1 << 24) |
56 |
#define TD_CTRL_ACTIVE (1 << 23) |
57 |
#define TD_CTRL_STALL (1 << 22) |
58 |
#define TD_CTRL_BABBLE (1 << 20) |
59 |
#define TD_CTRL_NAK (1 << 19) |
60 |
#define TD_CTRL_TIMEOUT (1 << 18) |
61 |
|
62 |
#define UHCI_PORT_SUSPEND (1 << 12) |
63 |
#define UHCI_PORT_RESET (1 << 9) |
64 |
#define UHCI_PORT_LSDA (1 << 8) |
65 |
#define UHCI_PORT_RD (1 << 6) |
66 |
#define UHCI_PORT_ENC (1 << 3) |
67 |
#define UHCI_PORT_EN (1 << 2) |
68 |
#define UHCI_PORT_CSC (1 << 1) |
69 |
#define UHCI_PORT_CCS (1 << 0) |
70 |
|
71 |
#define UHCI_PORT_READ_ONLY (0x1bb) |
72 |
#define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
|
73 |
|
74 |
#define FRAME_TIMER_FREQ 1000 |
75 |
|
76 |
#define FRAME_MAX_LOOPS 256 |
77 |
|
78 |
#define NB_PORTS 2 |
79 |
|
80 |
#ifdef DEBUG
|
81 |
#define DPRINTF printf
|
82 |
|
83 |
static const char *pid2str(int pid) |
84 |
{ |
85 |
switch (pid) {
|
86 |
case USB_TOKEN_SETUP: return "SETUP"; |
87 |
case USB_TOKEN_IN: return "IN"; |
88 |
case USB_TOKEN_OUT: return "OUT"; |
89 |
} |
90 |
return "?"; |
91 |
} |
92 |
|
93 |
#else
|
94 |
#define DPRINTF(...)
|
95 |
#endif
|
96 |
|
97 |
typedef struct UHCIState UHCIState; |
98 |
|
99 |
/*
|
100 |
* Pending async transaction.
|
101 |
* 'packet' must be the first field because completion
|
102 |
* handler does "(UHCIAsync *) pkt" cast.
|
103 |
*/
|
104 |
typedef struct UHCIAsync { |
105 |
USBPacket packet; |
106 |
QEMUSGList sgl; |
107 |
UHCIState *uhci; |
108 |
QTAILQ_ENTRY(UHCIAsync) next; |
109 |
uint32_t td; |
110 |
uint32_t token; |
111 |
int8_t valid; |
112 |
uint8_t isoc; |
113 |
uint8_t done; |
114 |
} UHCIAsync; |
115 |
|
116 |
typedef struct UHCIPort { |
117 |
USBPort port; |
118 |
uint16_t ctrl; |
119 |
} UHCIPort; |
120 |
|
121 |
struct UHCIState {
|
122 |
PCIDevice dev; |
123 |
MemoryRegion io_bar; |
124 |
USBBus bus; /* Note unused when we're a companion controller */
|
125 |
uint16_t cmd; /* cmd register */
|
126 |
uint16_t status; |
127 |
uint16_t intr; /* interrupt enable register */
|
128 |
uint16_t frnum; /* frame number */
|
129 |
uint32_t fl_base_addr; /* frame list base address */
|
130 |
uint8_t sof_timing; |
131 |
uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
|
132 |
int64_t expire_time; |
133 |
QEMUTimer *frame_timer; |
134 |
UHCIPort ports[NB_PORTS]; |
135 |
|
136 |
/* Interrupts that should be raised at the end of the current frame. */
|
137 |
uint32_t pending_int_mask; |
138 |
|
139 |
/* Active packets */
|
140 |
QTAILQ_HEAD(,UHCIAsync) async_pending; |
141 |
uint8_t num_ports_vmstate; |
142 |
|
143 |
/* Properties */
|
144 |
char *masterbus;
|
145 |
uint32_t firstport; |
146 |
}; |
147 |
|
148 |
typedef struct UHCI_TD { |
149 |
uint32_t link; |
150 |
uint32_t ctrl; /* see TD_CTRL_xxx */
|
151 |
uint32_t token; |
152 |
uint32_t buffer; |
153 |
} UHCI_TD; |
154 |
|
155 |
typedef struct UHCI_QH { |
156 |
uint32_t link; |
157 |
uint32_t el_link; |
158 |
} UHCI_QH; |
159 |
|
160 |
static UHCIAsync *uhci_async_alloc(UHCIState *s)
|
161 |
{ |
162 |
UHCIAsync *async = g_new0(UHCIAsync, 1);
|
163 |
|
164 |
async->uhci = s; |
165 |
usb_packet_init(&async->packet); |
166 |
pci_dma_sglist_init(&async->sgl, &s->dev, 1);
|
167 |
|
168 |
return async;
|
169 |
} |
170 |
|
171 |
static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
172 |
{ |
173 |
usb_packet_cleanup(&async->packet); |
174 |
qemu_sglist_destroy(&async->sgl); |
175 |
g_free(async); |
176 |
} |
177 |
|
178 |
static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
179 |
{ |
180 |
QTAILQ_INSERT_HEAD(&s->async_pending, async, next); |
181 |
} |
182 |
|
183 |
static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
184 |
{ |
185 |
QTAILQ_REMOVE(&s->async_pending, async, next); |
186 |
} |
187 |
|
188 |
static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
189 |
{ |
190 |
DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
|
191 |
async->td, async->token, async->done); |
192 |
|
193 |
if (!async->done)
|
194 |
usb_cancel_packet(&async->packet); |
195 |
uhci_async_free(s, async); |
196 |
} |
197 |
|
198 |
/*
|
199 |
* Mark all outstanding async packets as invalid.
|
200 |
* This is used for canceling them when TDs are removed by the HCD.
|
201 |
*/
|
202 |
static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
|
203 |
{ |
204 |
UHCIAsync *async; |
205 |
|
206 |
QTAILQ_FOREACH(async, &s->async_pending, next) { |
207 |
async->valid--; |
208 |
} |
209 |
return NULL; |
210 |
} |
211 |
|
212 |
/*
|
213 |
* Cancel async packets that are no longer valid
|
214 |
*/
|
215 |
static void uhci_async_validate_end(UHCIState *s) |
216 |
{ |
217 |
UHCIAsync *curr, *n; |
218 |
|
219 |
QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
220 |
if (curr->valid > 0) { |
221 |
continue;
|
222 |
} |
223 |
uhci_async_unlink(s, curr); |
224 |
uhci_async_cancel(s, curr); |
225 |
} |
226 |
} |
227 |
|
228 |
static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
229 |
{ |
230 |
UHCIAsync *curr, *n; |
231 |
|
232 |
QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
233 |
if (!usb_packet_is_inflight(&curr->packet) ||
|
234 |
curr->packet.ep->dev != dev) { |
235 |
continue;
|
236 |
} |
237 |
uhci_async_unlink(s, curr); |
238 |
uhci_async_cancel(s, curr); |
239 |
} |
240 |
} |
241 |
|
242 |
static void uhci_async_cancel_all(UHCIState *s) |
243 |
{ |
244 |
UHCIAsync *curr, *n; |
245 |
|
246 |
QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
247 |
uhci_async_unlink(s, curr); |
248 |
uhci_async_cancel(s, curr); |
249 |
} |
250 |
} |
251 |
|
252 |
static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
|
253 |
{ |
254 |
UHCIAsync *async; |
255 |
UHCIAsync *match = NULL;
|
256 |
int count = 0; |
257 |
|
258 |
/*
|
259 |
* We're looking for the best match here. ie both td addr and token.
|
260 |
* Otherwise we return last good match. ie just token.
|
261 |
* It's ok to match just token because it identifies the transaction
|
262 |
* rather well, token includes: device addr, endpoint, size, etc.
|
263 |
*
|
264 |
* Also since we queue async transactions in reverse order by returning
|
265 |
* last good match we restores the order.
|
266 |
*
|
267 |
* It's expected that we wont have a ton of outstanding transactions.
|
268 |
* If we ever do we'd want to optimize this algorithm.
|
269 |
*/
|
270 |
|
271 |
QTAILQ_FOREACH(async, &s->async_pending, next) { |
272 |
if (async->token == token) {
|
273 |
/* Good match */
|
274 |
match = async; |
275 |
|
276 |
if (async->td == addr) {
|
277 |
/* Best match */
|
278 |
break;
|
279 |
} |
280 |
} |
281 |
count++; |
282 |
} |
283 |
|
284 |
if (count > 64) |
285 |
fprintf(stderr, "uhci: warning lots of async transactions\n");
|
286 |
|
287 |
return match;
|
288 |
} |
289 |
|
290 |
static void uhci_update_irq(UHCIState *s) |
291 |
{ |
292 |
int level;
|
293 |
if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
294 |
((s->status2 & 2) && (s->intr & (1 << 3))) || |
295 |
((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
296 |
((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
297 |
(s->status & UHCI_STS_HSERR) || |
298 |
(s->status & UHCI_STS_HCPERR)) { |
299 |
level = 1;
|
300 |
} else {
|
301 |
level = 0;
|
302 |
} |
303 |
qemu_set_irq(s->dev.irq[3], level);
|
304 |
} |
305 |
|
306 |
static void uhci_reset(void *opaque) |
307 |
{ |
308 |
UHCIState *s = opaque; |
309 |
uint8_t *pci_conf; |
310 |
int i;
|
311 |
UHCIPort *port; |
312 |
|
313 |
DPRINTF("uhci: full reset\n");
|
314 |
|
315 |
pci_conf = s->dev.config; |
316 |
|
317 |
pci_conf[0x6a] = 0x01; /* usb clock */ |
318 |
pci_conf[0x6b] = 0x00; |
319 |
s->cmd = 0;
|
320 |
s->status = 0;
|
321 |
s->status2 = 0;
|
322 |
s->intr = 0;
|
323 |
s->fl_base_addr = 0;
|
324 |
s->sof_timing = 64;
|
325 |
|
326 |
for(i = 0; i < NB_PORTS; i++) { |
327 |
port = &s->ports[i]; |
328 |
port->ctrl = 0x0080;
|
329 |
if (port->port.dev && port->port.dev->attached) {
|
330 |
usb_port_reset(&port->port); |
331 |
} |
332 |
} |
333 |
|
334 |
uhci_async_cancel_all(s); |
335 |
} |
336 |
|
337 |
static void uhci_pre_save(void *opaque) |
338 |
{ |
339 |
UHCIState *s = opaque; |
340 |
|
341 |
uhci_async_cancel_all(s); |
342 |
} |
343 |
|
344 |
static const VMStateDescription vmstate_uhci_port = { |
345 |
.name = "uhci port",
|
346 |
.version_id = 1,
|
347 |
.minimum_version_id = 1,
|
348 |
.minimum_version_id_old = 1,
|
349 |
.fields = (VMStateField []) { |
350 |
VMSTATE_UINT16(ctrl, UHCIPort), |
351 |
VMSTATE_END_OF_LIST() |
352 |
} |
353 |
}; |
354 |
|
355 |
static const VMStateDescription vmstate_uhci = { |
356 |
.name = "uhci",
|
357 |
.version_id = 2,
|
358 |
.minimum_version_id = 1,
|
359 |
.minimum_version_id_old = 1,
|
360 |
.pre_save = uhci_pre_save, |
361 |
.fields = (VMStateField []) { |
362 |
VMSTATE_PCI_DEVICE(dev, UHCIState), |
363 |
VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), |
364 |
VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
|
365 |
vmstate_uhci_port, UHCIPort), |
366 |
VMSTATE_UINT16(cmd, UHCIState), |
367 |
VMSTATE_UINT16(status, UHCIState), |
368 |
VMSTATE_UINT16(intr, UHCIState), |
369 |
VMSTATE_UINT16(frnum, UHCIState), |
370 |
VMSTATE_UINT32(fl_base_addr, UHCIState), |
371 |
VMSTATE_UINT8(sof_timing, UHCIState), |
372 |
VMSTATE_UINT8(status2, UHCIState), |
373 |
VMSTATE_TIMER(frame_timer, UHCIState), |
374 |
VMSTATE_INT64_V(expire_time, UHCIState, 2),
|
375 |
VMSTATE_END_OF_LIST() |
376 |
} |
377 |
}; |
378 |
|
379 |
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
380 |
{ |
381 |
UHCIState *s = opaque; |
382 |
|
383 |
addr &= 0x1f;
|
384 |
switch(addr) {
|
385 |
case 0x0c: |
386 |
s->sof_timing = val; |
387 |
break;
|
388 |
} |
389 |
} |
390 |
|
391 |
static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
392 |
{ |
393 |
UHCIState *s = opaque; |
394 |
uint32_t val; |
395 |
|
396 |
addr &= 0x1f;
|
397 |
switch(addr) {
|
398 |
case 0x0c: |
399 |
val = s->sof_timing; |
400 |
break;
|
401 |
default:
|
402 |
val = 0xff;
|
403 |
break;
|
404 |
} |
405 |
return val;
|
406 |
} |
407 |
|
408 |
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
409 |
{ |
410 |
UHCIState *s = opaque; |
411 |
|
412 |
addr &= 0x1f;
|
413 |
DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
414 |
|
415 |
switch(addr) {
|
416 |
case 0x00: |
417 |
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
418 |
/* start frame processing */
|
419 |
s->expire_time = qemu_get_clock_ns(vm_clock) + |
420 |
(get_ticks_per_sec() / FRAME_TIMER_FREQ); |
421 |
qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
422 |
s->status &= ~UHCI_STS_HCHALTED; |
423 |
} else if (!(val & UHCI_CMD_RS)) { |
424 |
s->status |= UHCI_STS_HCHALTED; |
425 |
} |
426 |
if (val & UHCI_CMD_GRESET) {
|
427 |
UHCIPort *port; |
428 |
int i;
|
429 |
|
430 |
/* send reset on the USB bus */
|
431 |
for(i = 0; i < NB_PORTS; i++) { |
432 |
port = &s->ports[i]; |
433 |
usb_device_reset(port->port.dev); |
434 |
} |
435 |
uhci_reset(s); |
436 |
return;
|
437 |
} |
438 |
if (val & UHCI_CMD_HCRESET) {
|
439 |
uhci_reset(s); |
440 |
return;
|
441 |
} |
442 |
s->cmd = val; |
443 |
break;
|
444 |
case 0x02: |
445 |
s->status &= ~val; |
446 |
/* XXX: the chip spec is not coherent, so we add a hidden
|
447 |
register to distinguish between IOC and SPD */
|
448 |
if (val & UHCI_STS_USBINT)
|
449 |
s->status2 = 0;
|
450 |
uhci_update_irq(s); |
451 |
break;
|
452 |
case 0x04: |
453 |
s->intr = val; |
454 |
uhci_update_irq(s); |
455 |
break;
|
456 |
case 0x06: |
457 |
if (s->status & UHCI_STS_HCHALTED)
|
458 |
s->frnum = val & 0x7ff;
|
459 |
break;
|
460 |
case 0x10 ... 0x1f: |
461 |
{ |
462 |
UHCIPort *port; |
463 |
USBDevice *dev; |
464 |
int n;
|
465 |
|
466 |
n = (addr >> 1) & 7; |
467 |
if (n >= NB_PORTS)
|
468 |
return;
|
469 |
port = &s->ports[n]; |
470 |
dev = port->port.dev; |
471 |
if (dev && dev->attached) {
|
472 |
/* port reset */
|
473 |
if ( (val & UHCI_PORT_RESET) &&
|
474 |
!(port->ctrl & UHCI_PORT_RESET) ) { |
475 |
usb_device_reset(dev); |
476 |
} |
477 |
} |
478 |
port->ctrl &= UHCI_PORT_READ_ONLY; |
479 |
port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
480 |
/* some bits are reset when a '1' is written to them */
|
481 |
port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
482 |
} |
483 |
break;
|
484 |
} |
485 |
} |
486 |
|
487 |
static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
488 |
{ |
489 |
UHCIState *s = opaque; |
490 |
uint32_t val; |
491 |
|
492 |
addr &= 0x1f;
|
493 |
switch(addr) {
|
494 |
case 0x00: |
495 |
val = s->cmd; |
496 |
break;
|
497 |
case 0x02: |
498 |
val = s->status; |
499 |
break;
|
500 |
case 0x04: |
501 |
val = s->intr; |
502 |
break;
|
503 |
case 0x06: |
504 |
val = s->frnum; |
505 |
break;
|
506 |
case 0x10 ... 0x1f: |
507 |
{ |
508 |
UHCIPort *port; |
509 |
int n;
|
510 |
n = (addr >> 1) & 7; |
511 |
if (n >= NB_PORTS)
|
512 |
goto read_default;
|
513 |
port = &s->ports[n]; |
514 |
val = port->ctrl; |
515 |
} |
516 |
break;
|
517 |
default:
|
518 |
read_default:
|
519 |
val = 0xff7f; /* disabled port */ |
520 |
break;
|
521 |
} |
522 |
|
523 |
DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
524 |
|
525 |
return val;
|
526 |
} |
527 |
|
528 |
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
529 |
{ |
530 |
UHCIState *s = opaque; |
531 |
|
532 |
addr &= 0x1f;
|
533 |
DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
534 |
|
535 |
switch(addr) {
|
536 |
case 0x08: |
537 |
s->fl_base_addr = val & ~0xfff;
|
538 |
break;
|
539 |
} |
540 |
} |
541 |
|
542 |
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
543 |
{ |
544 |
UHCIState *s = opaque; |
545 |
uint32_t val; |
546 |
|
547 |
addr &= 0x1f;
|
548 |
switch(addr) {
|
549 |
case 0x08: |
550 |
val = s->fl_base_addr; |
551 |
break;
|
552 |
default:
|
553 |
val = 0xffffffff;
|
554 |
break;
|
555 |
} |
556 |
return val;
|
557 |
} |
558 |
|
559 |
/* signal resume if controller suspended */
|
560 |
static void uhci_resume (void *opaque) |
561 |
{ |
562 |
UHCIState *s = (UHCIState *)opaque; |
563 |
|
564 |
if (!s)
|
565 |
return;
|
566 |
|
567 |
if (s->cmd & UHCI_CMD_EGSM) {
|
568 |
s->cmd |= UHCI_CMD_FGR; |
569 |
s->status |= UHCI_STS_RD; |
570 |
uhci_update_irq(s); |
571 |
} |
572 |
} |
573 |
|
574 |
static void uhci_attach(USBPort *port1) |
575 |
{ |
576 |
UHCIState *s = port1->opaque; |
577 |
UHCIPort *port = &s->ports[port1->index]; |
578 |
|
579 |
/* set connect status */
|
580 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
581 |
|
582 |
/* update speed */
|
583 |
if (port->port.dev->speed == USB_SPEED_LOW) {
|
584 |
port->ctrl |= UHCI_PORT_LSDA; |
585 |
} else {
|
586 |
port->ctrl &= ~UHCI_PORT_LSDA; |
587 |
} |
588 |
|
589 |
uhci_resume(s); |
590 |
} |
591 |
|
592 |
static void uhci_detach(USBPort *port1) |
593 |
{ |
594 |
UHCIState *s = port1->opaque; |
595 |
UHCIPort *port = &s->ports[port1->index]; |
596 |
|
597 |
uhci_async_cancel_device(s, port1->dev); |
598 |
|
599 |
/* set connect status */
|
600 |
if (port->ctrl & UHCI_PORT_CCS) {
|
601 |
port->ctrl &= ~UHCI_PORT_CCS; |
602 |
port->ctrl |= UHCI_PORT_CSC; |
603 |
} |
604 |
/* disable port */
|
605 |
if (port->ctrl & UHCI_PORT_EN) {
|
606 |
port->ctrl &= ~UHCI_PORT_EN; |
607 |
port->ctrl |= UHCI_PORT_ENC; |
608 |
} |
609 |
|
610 |
uhci_resume(s); |
611 |
} |
612 |
|
613 |
static void uhci_child_detach(USBPort *port1, USBDevice *child) |
614 |
{ |
615 |
UHCIState *s = port1->opaque; |
616 |
|
617 |
uhci_async_cancel_device(s, child); |
618 |
} |
619 |
|
620 |
static void uhci_wakeup(USBPort *port1) |
621 |
{ |
622 |
UHCIState *s = port1->opaque; |
623 |
UHCIPort *port = &s->ports[port1->index]; |
624 |
|
625 |
if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
|
626 |
port->ctrl |= UHCI_PORT_RD; |
627 |
uhci_resume(s); |
628 |
} |
629 |
} |
630 |
|
631 |
static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
|
632 |
{ |
633 |
USBDevice *dev; |
634 |
int i;
|
635 |
|
636 |
for (i = 0; i < NB_PORTS; i++) { |
637 |
UHCIPort *port = &s->ports[i]; |
638 |
if (!(port->ctrl & UHCI_PORT_EN)) {
|
639 |
continue;
|
640 |
} |
641 |
dev = usb_find_device(&port->port, addr); |
642 |
if (dev != NULL) { |
643 |
return dev;
|
644 |
} |
645 |
} |
646 |
return NULL; |
647 |
} |
648 |
|
649 |
static void uhci_async_complete(USBPort *port, USBPacket *packet); |
650 |
static void uhci_process_frame(UHCIState *s); |
651 |
|
652 |
/* return -1 if fatal error (frame must be stopped)
|
653 |
0 if TD successful
|
654 |
1 if TD unsuccessful or inactive
|
655 |
*/
|
656 |
static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
657 |
{ |
658 |
int len = 0, max_len, err, ret; |
659 |
uint8_t pid; |
660 |
|
661 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
662 |
pid = td->token & 0xff;
|
663 |
|
664 |
ret = async->packet.result; |
665 |
|
666 |
if (td->ctrl & TD_CTRL_IOS)
|
667 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
668 |
|
669 |
if (ret < 0) |
670 |
goto out;
|
671 |
|
672 |
len = async->packet.result; |
673 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
674 |
|
675 |
/* The NAK bit may have been set by a previous frame, so clear it
|
676 |
here. The docs are somewhat unclear, but win2k relies on this
|
677 |
behavior. */
|
678 |
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
679 |
if (td->ctrl & TD_CTRL_IOC)
|
680 |
*int_mask |= 0x01;
|
681 |
|
682 |
if (pid == USB_TOKEN_IN) {
|
683 |
if (len > max_len) {
|
684 |
ret = USB_RET_BABBLE; |
685 |
goto out;
|
686 |
} |
687 |
|
688 |
if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
689 |
*int_mask |= 0x02;
|
690 |
/* short packet: do not update QH */
|
691 |
DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
692 |
return 1; |
693 |
} |
694 |
} |
695 |
|
696 |
/* success */
|
697 |
return 0; |
698 |
|
699 |
out:
|
700 |
switch(ret) {
|
701 |
case USB_RET_STALL:
|
702 |
td->ctrl |= TD_CTRL_STALL; |
703 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
704 |
s->status |= UHCI_STS_USBERR; |
705 |
if (td->ctrl & TD_CTRL_IOC) {
|
706 |
*int_mask |= 0x01;
|
707 |
} |
708 |
uhci_update_irq(s); |
709 |
return 1; |
710 |
|
711 |
case USB_RET_BABBLE:
|
712 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
713 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
714 |
s->status |= UHCI_STS_USBERR; |
715 |
if (td->ctrl & TD_CTRL_IOC) {
|
716 |
*int_mask |= 0x01;
|
717 |
} |
718 |
uhci_update_irq(s); |
719 |
/* frame interrupted */
|
720 |
return -1; |
721 |
|
722 |
case USB_RET_NAK:
|
723 |
td->ctrl |= TD_CTRL_NAK; |
724 |
if (pid == USB_TOKEN_SETUP)
|
725 |
break;
|
726 |
return 1; |
727 |
|
728 |
case USB_RET_NODEV:
|
729 |
default:
|
730 |
break;
|
731 |
} |
732 |
|
733 |
/* Retry the TD if error count is not zero */
|
734 |
|
735 |
td->ctrl |= TD_CTRL_TIMEOUT; |
736 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
737 |
if (err != 0) { |
738 |
err--; |
739 |
if (err == 0) { |
740 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
741 |
s->status |= UHCI_STS_USBERR; |
742 |
if (td->ctrl & TD_CTRL_IOC)
|
743 |
*int_mask |= 0x01;
|
744 |
uhci_update_irq(s); |
745 |
} |
746 |
} |
747 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
748 |
(err << TD_CTRL_ERROR_SHIFT); |
749 |
return 1; |
750 |
} |
751 |
|
752 |
static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
753 |
{ |
754 |
UHCIAsync *async; |
755 |
int len = 0, max_len; |
756 |
uint8_t pid, isoc; |
757 |
uint32_t token; |
758 |
USBDevice *dev; |
759 |
USBEndpoint *ep; |
760 |
|
761 |
/* Is active ? */
|
762 |
if (!(td->ctrl & TD_CTRL_ACTIVE))
|
763 |
return 1; |
764 |
|
765 |
/* token field is not unique for isochronous requests,
|
766 |
* so use the destination buffer
|
767 |
*/
|
768 |
if (td->ctrl & TD_CTRL_IOS) {
|
769 |
token = td->buffer; |
770 |
isoc = 1;
|
771 |
} else {
|
772 |
token = td->token; |
773 |
isoc = 0;
|
774 |
} |
775 |
|
776 |
async = uhci_async_find_td(s, addr, token); |
777 |
if (async) {
|
778 |
/* Already submitted */
|
779 |
async->valid = 32;
|
780 |
|
781 |
if (!async->done)
|
782 |
return 1; |
783 |
|
784 |
uhci_async_unlink(s, async); |
785 |
goto done;
|
786 |
} |
787 |
|
788 |
/* Allocate new packet */
|
789 |
async = uhci_async_alloc(s); |
790 |
if (!async)
|
791 |
return 1; |
792 |
|
793 |
/* valid needs to be large enough to handle 10 frame delay
|
794 |
* for initial isochronous requests
|
795 |
*/
|
796 |
async->valid = 32;
|
797 |
async->td = addr; |
798 |
async->token = token; |
799 |
async->isoc = isoc; |
800 |
|
801 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
802 |
pid = td->token & 0xff;
|
803 |
|
804 |
dev = uhci_find_device(s, (td->token >> 8) & 0x7f); |
805 |
ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); |
806 |
usb_packet_setup(&async->packet, pid, ep); |
807 |
qemu_sglist_add(&async->sgl, td->buffer, max_len); |
808 |
usb_packet_map(&async->packet, &async->sgl); |
809 |
|
810 |
switch(pid) {
|
811 |
case USB_TOKEN_OUT:
|
812 |
case USB_TOKEN_SETUP:
|
813 |
len = usb_handle_packet(dev, &async->packet); |
814 |
if (len >= 0) |
815 |
len = max_len; |
816 |
break;
|
817 |
|
818 |
case USB_TOKEN_IN:
|
819 |
len = usb_handle_packet(dev, &async->packet); |
820 |
break;
|
821 |
|
822 |
default:
|
823 |
/* invalid pid : frame interrupted */
|
824 |
uhci_async_free(s, async); |
825 |
s->status |= UHCI_STS_HCPERR; |
826 |
uhci_update_irq(s); |
827 |
return -1; |
828 |
} |
829 |
|
830 |
if (len == USB_RET_ASYNC) {
|
831 |
uhci_async_link(s, async); |
832 |
return 2; |
833 |
} |
834 |
|
835 |
async->packet.result = len; |
836 |
|
837 |
done:
|
838 |
len = uhci_complete_td(s, td, async, int_mask); |
839 |
usb_packet_unmap(&async->packet); |
840 |
uhci_async_free(s, async); |
841 |
return len;
|
842 |
} |
843 |
|
844 |
static void uhci_async_complete(USBPort *port, USBPacket *packet) |
845 |
{ |
846 |
UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
847 |
UHCIState *s = async->uhci; |
848 |
|
849 |
DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
850 |
|
851 |
if (async->isoc) {
|
852 |
UHCI_TD td; |
853 |
uint32_t link = async->td; |
854 |
uint32_t int_mask = 0, val;
|
855 |
|
856 |
pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
857 |
le32_to_cpus(&td.link); |
858 |
le32_to_cpus(&td.ctrl); |
859 |
le32_to_cpus(&td.token); |
860 |
le32_to_cpus(&td.buffer); |
861 |
|
862 |
uhci_async_unlink(s, async); |
863 |
uhci_complete_td(s, &td, async, &int_mask); |
864 |
s->pending_int_mask |= int_mask; |
865 |
|
866 |
/* update the status bits of the TD */
|
867 |
val = cpu_to_le32(td.ctrl); |
868 |
pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
869 |
uhci_async_free(s, async); |
870 |
} else {
|
871 |
async->done = 1;
|
872 |
uhci_process_frame(s); |
873 |
} |
874 |
} |
875 |
|
876 |
static int is_valid(uint32_t link) |
877 |
{ |
878 |
return (link & 1) == 0; |
879 |
} |
880 |
|
881 |
static int is_qh(uint32_t link) |
882 |
{ |
883 |
return (link & 2) != 0; |
884 |
} |
885 |
|
886 |
static int depth_first(uint32_t link) |
887 |
{ |
888 |
return (link & 4) != 0; |
889 |
} |
890 |
|
891 |
/* QH DB used for detecting QH loops */
|
892 |
#define UHCI_MAX_QUEUES 128 |
893 |
typedef struct { |
894 |
uint32_t addr[UHCI_MAX_QUEUES]; |
895 |
int count;
|
896 |
} QhDb; |
897 |
|
898 |
static void qhdb_reset(QhDb *db) |
899 |
{ |
900 |
db->count = 0;
|
901 |
} |
902 |
|
903 |
/* Add QH to DB. Returns 1 if already present or DB is full. */
|
904 |
static int qhdb_insert(QhDb *db, uint32_t addr) |
905 |
{ |
906 |
int i;
|
907 |
for (i = 0; i < db->count; i++) |
908 |
if (db->addr[i] == addr)
|
909 |
return 1; |
910 |
|
911 |
if (db->count >= UHCI_MAX_QUEUES)
|
912 |
return 1; |
913 |
|
914 |
db->addr[db->count++] = addr; |
915 |
return 0; |
916 |
} |
917 |
|
918 |
static void uhci_process_frame(UHCIState *s) |
919 |
{ |
920 |
uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
921 |
uint32_t curr_qh, td_count = 0, bytes_count = 0; |
922 |
int cnt, ret;
|
923 |
UHCI_TD td; |
924 |
UHCI_QH qh; |
925 |
QhDb qhdb; |
926 |
|
927 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
928 |
|
929 |
DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
930 |
|
931 |
pci_dma_read(&s->dev, frame_addr, &link, 4);
|
932 |
le32_to_cpus(&link); |
933 |
|
934 |
int_mask = 0;
|
935 |
curr_qh = 0;
|
936 |
|
937 |
qhdb_reset(&qhdb); |
938 |
|
939 |
for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
940 |
if (is_qh(link)) {
|
941 |
/* QH */
|
942 |
|
943 |
if (qhdb_insert(&qhdb, link)) {
|
944 |
/*
|
945 |
* We're going in circles. Which is not a bug because
|
946 |
* HCD is allowed to do that as part of the BW management.
|
947 |
*
|
948 |
* Stop processing here if
|
949 |
* (a) no transaction has been done since we've been
|
950 |
* here last time, or
|
951 |
* (b) we've reached the usb 1.1 bandwidth, which is
|
952 |
* 1280 bytes/frame.
|
953 |
*/
|
954 |
DPRINTF("uhci: detected loop. qh 0x%x\n", link);
|
955 |
if (td_count == 0) { |
956 |
DPRINTF("uhci: no transaction last round, stop\n");
|
957 |
break;
|
958 |
} else if (bytes_count >= 1280) { |
959 |
DPRINTF("uhci: bandwidth limit reached, stop\n");
|
960 |
break;
|
961 |
} else {
|
962 |
td_count = 0;
|
963 |
qhdb_reset(&qhdb); |
964 |
qhdb_insert(&qhdb, link); |
965 |
} |
966 |
} |
967 |
|
968 |
pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
969 |
le32_to_cpus(&qh.link); |
970 |
le32_to_cpus(&qh.el_link); |
971 |
|
972 |
DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
973 |
link, qh.link, qh.el_link); |
974 |
|
975 |
if (!is_valid(qh.el_link)) {
|
976 |
/* QH w/o elements */
|
977 |
curr_qh = 0;
|
978 |
link = qh.link; |
979 |
} else {
|
980 |
/* QH with elements */
|
981 |
curr_qh = link; |
982 |
link = qh.el_link; |
983 |
} |
984 |
continue;
|
985 |
} |
986 |
|
987 |
/* TD */
|
988 |
pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
989 |
le32_to_cpus(&td.link); |
990 |
le32_to_cpus(&td.ctrl); |
991 |
le32_to_cpus(&td.token); |
992 |
le32_to_cpus(&td.buffer); |
993 |
|
994 |
DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
995 |
link, td.link, td.ctrl, td.token, curr_qh); |
996 |
|
997 |
old_td_ctrl = td.ctrl; |
998 |
ret = uhci_handle_td(s, link, &td, &int_mask); |
999 |
if (old_td_ctrl != td.ctrl) {
|
1000 |
/* update the status bits of the TD */
|
1001 |
val = cpu_to_le32(td.ctrl); |
1002 |
pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
1003 |
} |
1004 |
|
1005 |
if (ret < 0) { |
1006 |
/* interrupted frame */
|
1007 |
break;
|
1008 |
} |
1009 |
|
1010 |
if (ret == 2 || ret == 1) { |
1011 |
DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1012 |
link, ret == 2 ? "pend" : "skip", |
1013 |
td.link, td.ctrl, td.token, curr_qh); |
1014 |
|
1015 |
link = curr_qh ? qh.link : td.link; |
1016 |
continue;
|
1017 |
} |
1018 |
|
1019 |
/* completed TD */
|
1020 |
|
1021 |
DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1022 |
link, td.link, td.ctrl, td.token, curr_qh); |
1023 |
|
1024 |
link = td.link; |
1025 |
td_count++; |
1026 |
bytes_count += (td.ctrl & 0x7ff) + 1; |
1027 |
|
1028 |
if (curr_qh) {
|
1029 |
/* update QH element link */
|
1030 |
qh.el_link = link; |
1031 |
val = cpu_to_le32(qh.el_link); |
1032 |
pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); |
1033 |
|
1034 |
if (!depth_first(link)) {
|
1035 |
/* done with this QH */
|
1036 |
|
1037 |
DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
1038 |
curr_qh, qh.link, qh.el_link); |
1039 |
|
1040 |
curr_qh = 0;
|
1041 |
link = qh.link; |
1042 |
} |
1043 |
} |
1044 |
|
1045 |
/* go to the next entry */
|
1046 |
} |
1047 |
|
1048 |
s->pending_int_mask |= int_mask; |
1049 |
} |
1050 |
|
1051 |
static void uhci_frame_timer(void *opaque) |
1052 |
{ |
1053 |
UHCIState *s = opaque; |
1054 |
|
1055 |
/* prepare the timer for the next frame */
|
1056 |
s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1057 |
|
1058 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
1059 |
/* Full stop */
|
1060 |
qemu_del_timer(s->frame_timer); |
1061 |
/* set hchalted bit in status - UHCI11D 2.1.2 */
|
1062 |
s->status |= UHCI_STS_HCHALTED; |
1063 |
|
1064 |
DPRINTF("uhci: halted\n");
|
1065 |
return;
|
1066 |
} |
1067 |
|
1068 |
/* Complete the previous frame */
|
1069 |
if (s->pending_int_mask) {
|
1070 |
s->status2 |= s->pending_int_mask; |
1071 |
s->status |= UHCI_STS_USBINT; |
1072 |
uhci_update_irq(s); |
1073 |
} |
1074 |
s->pending_int_mask = 0;
|
1075 |
|
1076 |
/* Start new frame */
|
1077 |
s->frnum = (s->frnum + 1) & 0x7ff; |
1078 |
|
1079 |
DPRINTF("uhci: new frame #%u\n" , s->frnum);
|
1080 |
|
1081 |
uhci_async_validate_begin(s); |
1082 |
|
1083 |
uhci_process_frame(s); |
1084 |
|
1085 |
uhci_async_validate_end(s); |
1086 |
|
1087 |
qemu_mod_timer(s->frame_timer, s->expire_time); |
1088 |
} |
1089 |
|
1090 |
static const MemoryRegionPortio uhci_portio[] = { |
1091 |
{ 0, 32, 2, .write = uhci_ioport_writew, }, |
1092 |
{ 0, 32, 2, .read = uhci_ioport_readw, }, |
1093 |
{ 0, 32, 4, .write = uhci_ioport_writel, }, |
1094 |
{ 0, 32, 4, .read = uhci_ioport_readl, }, |
1095 |
{ 0, 32, 1, .write = uhci_ioport_writeb, }, |
1096 |
{ 0, 32, 1, .read = uhci_ioport_readb, }, |
1097 |
PORTIO_END_OF_LIST() |
1098 |
}; |
1099 |
|
1100 |
static const MemoryRegionOps uhci_ioport_ops = { |
1101 |
.old_portio = uhci_portio, |
1102 |
}; |
1103 |
|
1104 |
static USBPortOps uhci_port_ops = {
|
1105 |
.attach = uhci_attach, |
1106 |
.detach = uhci_detach, |
1107 |
.child_detach = uhci_child_detach, |
1108 |
.wakeup = uhci_wakeup, |
1109 |
.complete = uhci_async_complete, |
1110 |
}; |
1111 |
|
1112 |
static USBBusOps uhci_bus_ops = {
|
1113 |
}; |
1114 |
|
1115 |
static int usb_uhci_common_initfn(PCIDevice *dev) |
1116 |
{ |
1117 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1118 |
uint8_t *pci_conf = s->dev.config; |
1119 |
int i;
|
1120 |
|
1121 |
pci_conf[PCI_CLASS_PROG] = 0x00;
|
1122 |
/* TODO: reset value should be 0. */
|
1123 |
pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */ |
1124 |
pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
|
1125 |
|
1126 |
if (s->masterbus) {
|
1127 |
USBPort *ports[NB_PORTS]; |
1128 |
for(i = 0; i < NB_PORTS; i++) { |
1129 |
ports[i] = &s->ports[i].port; |
1130 |
} |
1131 |
if (usb_register_companion(s->masterbus, ports, NB_PORTS,
|
1132 |
s->firstport, s, &uhci_port_ops, |
1133 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
|
1134 |
return -1; |
1135 |
} |
1136 |
} else {
|
1137 |
usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); |
1138 |
for (i = 0; i < NB_PORTS; i++) { |
1139 |
usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, |
1140 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1141 |
} |
1142 |
} |
1143 |
s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
1144 |
s->num_ports_vmstate = NB_PORTS; |
1145 |
QTAILQ_INIT(&s->async_pending); |
1146 |
|
1147 |
qemu_register_reset(uhci_reset, s); |
1148 |
|
1149 |
memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); |
1150 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1151 |
to rely on this. */
|
1152 |
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
1153 |
|
1154 |
return 0; |
1155 |
} |
1156 |
|
1157 |
static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1158 |
{ |
1159 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1160 |
uint8_t *pci_conf = s->dev.config; |
1161 |
|
1162 |
/* USB misc control 1/2 */
|
1163 |
pci_set_long(pci_conf + 0x40,0x00001000); |
1164 |
/* PM capability */
|
1165 |
pci_set_long(pci_conf + 0x80,0x00020001); |
1166 |
/* USB legacy support */
|
1167 |
pci_set_long(pci_conf + 0xc0,0x00002000); |
1168 |
|
1169 |
return usb_uhci_common_initfn(dev);
|
1170 |
} |
1171 |
|
1172 |
static int usb_uhci_exit(PCIDevice *dev) |
1173 |
{ |
1174 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1175 |
|
1176 |
memory_region_destroy(&s->io_bar); |
1177 |
return 0; |
1178 |
} |
1179 |
|
1180 |
static Property uhci_properties[] = {
|
1181 |
DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
|
1182 |
DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), |
1183 |
DEFINE_PROP_END_OF_LIST(), |
1184 |
}; |
1185 |
|
1186 |
static void piix3_uhci_class_init(ObjectClass *klass, void *data) |
1187 |
{ |
1188 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1189 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1190 |
|
1191 |
k->init = usb_uhci_common_initfn; |
1192 |
k->exit = usb_uhci_exit; |
1193 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1194 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; |
1195 |
k->revision = 0x01;
|
1196 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1197 |
dc->vmsd = &vmstate_uhci; |
1198 |
dc->props = uhci_properties; |
1199 |
} |
1200 |
|
1201 |
static TypeInfo piix3_uhci_info = {
|
1202 |
.name = "piix3-usb-uhci",
|
1203 |
.parent = TYPE_PCI_DEVICE, |
1204 |
.instance_size = sizeof(UHCIState),
|
1205 |
.class_init = piix3_uhci_class_init, |
1206 |
}; |
1207 |
|
1208 |
static void piix4_uhci_class_init(ObjectClass *klass, void *data) |
1209 |
{ |
1210 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1211 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1212 |
|
1213 |
k->init = usb_uhci_common_initfn; |
1214 |
k->exit = usb_uhci_exit; |
1215 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1216 |
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; |
1217 |
k->revision = 0x01;
|
1218 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1219 |
dc->vmsd = &vmstate_uhci; |
1220 |
dc->props = uhci_properties; |
1221 |
} |
1222 |
|
1223 |
static TypeInfo piix4_uhci_info = {
|
1224 |
.name = "piix4-usb-uhci",
|
1225 |
.parent = TYPE_PCI_DEVICE, |
1226 |
.instance_size = sizeof(UHCIState),
|
1227 |
.class_init = piix4_uhci_class_init, |
1228 |
}; |
1229 |
|
1230 |
static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) |
1231 |
{ |
1232 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1233 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1234 |
|
1235 |
k->init = usb_uhci_vt82c686b_initfn; |
1236 |
k->exit = usb_uhci_exit; |
1237 |
k->vendor_id = PCI_VENDOR_ID_VIA; |
1238 |
k->device_id = PCI_DEVICE_ID_VIA_UHCI; |
1239 |
k->revision = 0x01;
|
1240 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1241 |
dc->vmsd = &vmstate_uhci; |
1242 |
dc->props = uhci_properties; |
1243 |
} |
1244 |
|
1245 |
static TypeInfo vt82c686b_uhci_info = {
|
1246 |
.name = "vt82c686b-usb-uhci",
|
1247 |
.parent = TYPE_PCI_DEVICE, |
1248 |
.instance_size = sizeof(UHCIState),
|
1249 |
.class_init = vt82c686b_uhci_class_init, |
1250 |
}; |
1251 |
|
1252 |
static void ich9_uhci1_class_init(ObjectClass *klass, void *data) |
1253 |
{ |
1254 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1255 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1256 |
|
1257 |
k->init = usb_uhci_common_initfn; |
1258 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1259 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; |
1260 |
k->revision = 0x03;
|
1261 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1262 |
dc->vmsd = &vmstate_uhci; |
1263 |
dc->props = uhci_properties; |
1264 |
} |
1265 |
|
1266 |
static TypeInfo ich9_uhci1_info = {
|
1267 |
.name = "ich9-usb-uhci1",
|
1268 |
.parent = TYPE_PCI_DEVICE, |
1269 |
.instance_size = sizeof(UHCIState),
|
1270 |
.class_init = ich9_uhci1_class_init, |
1271 |
}; |
1272 |
|
1273 |
static void ich9_uhci2_class_init(ObjectClass *klass, void *data) |
1274 |
{ |
1275 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1276 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1277 |
|
1278 |
k->init = usb_uhci_common_initfn; |
1279 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1280 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; |
1281 |
k->revision = 0x03;
|
1282 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1283 |
dc->vmsd = &vmstate_uhci; |
1284 |
dc->props = uhci_properties; |
1285 |
} |
1286 |
|
1287 |
static TypeInfo ich9_uhci2_info = {
|
1288 |
.name = "ich9-usb-uhci2",
|
1289 |
.parent = TYPE_PCI_DEVICE, |
1290 |
.instance_size = sizeof(UHCIState),
|
1291 |
.class_init = ich9_uhci2_class_init, |
1292 |
}; |
1293 |
|
1294 |
static void ich9_uhci3_class_init(ObjectClass *klass, void *data) |
1295 |
{ |
1296 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1297 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1298 |
|
1299 |
k->init = usb_uhci_common_initfn; |
1300 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1301 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; |
1302 |
k->revision = 0x03;
|
1303 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1304 |
dc->vmsd = &vmstate_uhci; |
1305 |
dc->props = uhci_properties; |
1306 |
} |
1307 |
|
1308 |
static TypeInfo ich9_uhci3_info = {
|
1309 |
.name = "ich9-usb-uhci3",
|
1310 |
.parent = TYPE_PCI_DEVICE, |
1311 |
.instance_size = sizeof(UHCIState),
|
1312 |
.class_init = ich9_uhci3_class_init, |
1313 |
}; |
1314 |
|
1315 |
static void uhci_register_types(void) |
1316 |
{ |
1317 |
type_register_static(&piix3_uhci_info); |
1318 |
type_register_static(&piix4_uhci_info); |
1319 |
type_register_static(&vt82c686b_uhci_info); |
1320 |
type_register_static(&ich9_uhci1_info); |
1321 |
type_register_static(&ich9_uhci2_info); |
1322 |
type_register_static(&ich9_uhci3_info); |
1323 |
} |
1324 |
|
1325 |
type_init(uhci_register_types) |
1326 |
|
1327 |
void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1328 |
{ |
1329 |
pci_create_simple(bus, devfn, "piix3-usb-uhci");
|
1330 |
} |
1331 |
|
1332 |
void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1333 |
{ |
1334 |
pci_create_simple(bus, devfn, "piix4-usb-uhci");
|
1335 |
} |
1336 |
|
1337 |
void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) |
1338 |
{ |
1339 |
pci_create_simple(bus, devfn, "vt82c686b-usb-uhci");
|
1340 |
} |