root / target-i386 / cpu.h @ 329e607d
History | View | Annotate | Download (34.8 kB)
1 |
/*
|
---|---|
2 |
* i386 virtual CPU header
|
3 |
*
|
4 |
* Copyright (c) 2003 Fabrice Bellard
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 |
*/
|
19 |
#ifndef CPU_I386_H
|
20 |
#define CPU_I386_H
|
21 |
|
22 |
#include "config.h" |
23 |
#include "qemu-common.h" |
24 |
|
25 |
#ifdef TARGET_X86_64
|
26 |
#define TARGET_LONG_BITS 64 |
27 |
#else
|
28 |
#define TARGET_LONG_BITS 32 |
29 |
#endif
|
30 |
|
31 |
/* target supports implicit self modifying code */
|
32 |
#define TARGET_HAS_SMC
|
33 |
/* support for self modifying code even if the modified instruction is
|
34 |
close to the modifying instruction */
|
35 |
#define TARGET_HAS_PRECISE_SMC
|
36 |
|
37 |
#define TARGET_HAS_ICE 1 |
38 |
|
39 |
#ifdef TARGET_X86_64
|
40 |
#define ELF_MACHINE EM_X86_64
|
41 |
#else
|
42 |
#define ELF_MACHINE EM_386
|
43 |
#endif
|
44 |
|
45 |
#define CPUArchState struct CPUX86State |
46 |
|
47 |
#include "cpu-defs.h" |
48 |
|
49 |
#include "softfloat.h" |
50 |
|
51 |
#define R_EAX 0 |
52 |
#define R_ECX 1 |
53 |
#define R_EDX 2 |
54 |
#define R_EBX 3 |
55 |
#define R_ESP 4 |
56 |
#define R_EBP 5 |
57 |
#define R_ESI 6 |
58 |
#define R_EDI 7 |
59 |
|
60 |
#define R_AL 0 |
61 |
#define R_CL 1 |
62 |
#define R_DL 2 |
63 |
#define R_BL 3 |
64 |
#define R_AH 4 |
65 |
#define R_CH 5 |
66 |
#define R_DH 6 |
67 |
#define R_BH 7 |
68 |
|
69 |
#define R_ES 0 |
70 |
#define R_CS 1 |
71 |
#define R_SS 2 |
72 |
#define R_DS 3 |
73 |
#define R_FS 4 |
74 |
#define R_GS 5 |
75 |
|
76 |
/* segment descriptor fields */
|
77 |
#define DESC_G_MASK (1 << 23) |
78 |
#define DESC_B_SHIFT 22 |
79 |
#define DESC_B_MASK (1 << DESC_B_SHIFT) |
80 |
#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
81 |
#define DESC_L_MASK (1 << DESC_L_SHIFT) |
82 |
#define DESC_AVL_MASK (1 << 20) |
83 |
#define DESC_P_MASK (1 << 15) |
84 |
#define DESC_DPL_SHIFT 13 |
85 |
#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
86 |
#define DESC_S_MASK (1 << 12) |
87 |
#define DESC_TYPE_SHIFT 8 |
88 |
#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
89 |
#define DESC_A_MASK (1 << 8) |
90 |
|
91 |
#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
92 |
#define DESC_C_MASK (1 << 10) /* code: conforming */ |
93 |
#define DESC_R_MASK (1 << 9) /* code: readable */ |
94 |
|
95 |
#define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
96 |
#define DESC_W_MASK (1 << 9) /* data: writable */ |
97 |
|
98 |
#define DESC_TSS_BUSY_MASK (1 << 9) |
99 |
|
100 |
/* eflags masks */
|
101 |
#define CC_C 0x0001 |
102 |
#define CC_P 0x0004 |
103 |
#define CC_A 0x0010 |
104 |
#define CC_Z 0x0040 |
105 |
#define CC_S 0x0080 |
106 |
#define CC_O 0x0800 |
107 |
|
108 |
#define TF_SHIFT 8 |
109 |
#define IOPL_SHIFT 12 |
110 |
#define VM_SHIFT 17 |
111 |
|
112 |
#define TF_MASK 0x00000100 |
113 |
#define IF_MASK 0x00000200 |
114 |
#define DF_MASK 0x00000400 |
115 |
#define IOPL_MASK 0x00003000 |
116 |
#define NT_MASK 0x00004000 |
117 |
#define RF_MASK 0x00010000 |
118 |
#define VM_MASK 0x00020000 |
119 |
#define AC_MASK 0x00040000 |
120 |
#define VIF_MASK 0x00080000 |
121 |
#define VIP_MASK 0x00100000 |
122 |
#define ID_MASK 0x00200000 |
123 |
|
124 |
/* hidden flags - used internally by qemu to represent additional cpu
|
125 |
states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
|
126 |
redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
|
127 |
position to ease oring with eflags. */
|
128 |
/* current cpl */
|
129 |
#define HF_CPL_SHIFT 0 |
130 |
/* true if soft mmu is being used */
|
131 |
#define HF_SOFTMMU_SHIFT 2 |
132 |
/* true if hardware interrupts must be disabled for next instruction */
|
133 |
#define HF_INHIBIT_IRQ_SHIFT 3 |
134 |
/* 16 or 32 segments */
|
135 |
#define HF_CS32_SHIFT 4 |
136 |
#define HF_SS32_SHIFT 5 |
137 |
/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
|
138 |
#define HF_ADDSEG_SHIFT 6 |
139 |
/* copy of CR0.PE (protected mode) */
|
140 |
#define HF_PE_SHIFT 7 |
141 |
#define HF_TF_SHIFT 8 /* must be same as eflags */ |
142 |
#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
143 |
#define HF_EM_SHIFT 10 |
144 |
#define HF_TS_SHIFT 11 |
145 |
#define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
146 |
#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
147 |
#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
148 |
#define HF_RF_SHIFT 16 /* must be same as eflags */ |
149 |
#define HF_VM_SHIFT 17 /* must be same as eflags */ |
150 |
#define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
151 |
#define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
152 |
#define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ |
153 |
#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
154 |
|
155 |
#define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
156 |
#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
157 |
#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
158 |
#define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
159 |
#define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
160 |
#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
161 |
#define HF_PE_MASK (1 << HF_PE_SHIFT) |
162 |
#define HF_TF_MASK (1 << HF_TF_SHIFT) |
163 |
#define HF_MP_MASK (1 << HF_MP_SHIFT) |
164 |
#define HF_EM_MASK (1 << HF_EM_SHIFT) |
165 |
#define HF_TS_MASK (1 << HF_TS_SHIFT) |
166 |
#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
167 |
#define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
168 |
#define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
169 |
#define HF_RF_MASK (1 << HF_RF_SHIFT) |
170 |
#define HF_VM_MASK (1 << HF_VM_SHIFT) |
171 |
#define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
172 |
#define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
173 |
#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) |
174 |
#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
175 |
|
176 |
/* hflags2 */
|
177 |
|
178 |
#define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
179 |
#define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ |
180 |
#define HF2_NMI_SHIFT 2 /* CPU serving NMI */ |
181 |
#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ |
182 |
|
183 |
#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) |
184 |
#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) |
185 |
#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) |
186 |
#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) |
187 |
|
188 |
#define CR0_PE_SHIFT 0 |
189 |
#define CR0_MP_SHIFT 1 |
190 |
|
191 |
#define CR0_PE_MASK (1 << 0) |
192 |
#define CR0_MP_MASK (1 << 1) |
193 |
#define CR0_EM_MASK (1 << 2) |
194 |
#define CR0_TS_MASK (1 << 3) |
195 |
#define CR0_ET_MASK (1 << 4) |
196 |
#define CR0_NE_MASK (1 << 5) |
197 |
#define CR0_WP_MASK (1 << 16) |
198 |
#define CR0_AM_MASK (1 << 18) |
199 |
#define CR0_PG_MASK (1 << 31) |
200 |
|
201 |
#define CR4_VME_MASK (1 << 0) |
202 |
#define CR4_PVI_MASK (1 << 1) |
203 |
#define CR4_TSD_MASK (1 << 2) |
204 |
#define CR4_DE_MASK (1 << 3) |
205 |
#define CR4_PSE_MASK (1 << 4) |
206 |
#define CR4_PAE_MASK (1 << 5) |
207 |
#define CR4_MCE_MASK (1 << 6) |
208 |
#define CR4_PGE_MASK (1 << 7) |
209 |
#define CR4_PCE_MASK (1 << 8) |
210 |
#define CR4_OSFXSR_SHIFT 9 |
211 |
#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) |
212 |
#define CR4_OSXMMEXCPT_MASK (1 << 10) |
213 |
|
214 |
#define DR6_BD (1 << 13) |
215 |
#define DR6_BS (1 << 14) |
216 |
#define DR6_BT (1 << 15) |
217 |
#define DR6_FIXED_1 0xffff0ff0 |
218 |
|
219 |
#define DR7_GD (1 << 13) |
220 |
#define DR7_TYPE_SHIFT 16 |
221 |
#define DR7_LEN_SHIFT 18 |
222 |
#define DR7_FIXED_1 0x00000400 |
223 |
|
224 |
#define PG_PRESENT_BIT 0 |
225 |
#define PG_RW_BIT 1 |
226 |
#define PG_USER_BIT 2 |
227 |
#define PG_PWT_BIT 3 |
228 |
#define PG_PCD_BIT 4 |
229 |
#define PG_ACCESSED_BIT 5 |
230 |
#define PG_DIRTY_BIT 6 |
231 |
#define PG_PSE_BIT 7 |
232 |
#define PG_GLOBAL_BIT 8 |
233 |
#define PG_NX_BIT 63 |
234 |
|
235 |
#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
236 |
#define PG_RW_MASK (1 << PG_RW_BIT) |
237 |
#define PG_USER_MASK (1 << PG_USER_BIT) |
238 |
#define PG_PWT_MASK (1 << PG_PWT_BIT) |
239 |
#define PG_PCD_MASK (1 << PG_PCD_BIT) |
240 |
#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
241 |
#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
242 |
#define PG_PSE_MASK (1 << PG_PSE_BIT) |
243 |
#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
244 |
#define PG_HI_USER_MASK 0x7ff0000000000000LL |
245 |
#define PG_NX_MASK (1LL << PG_NX_BIT) |
246 |
|
247 |
#define PG_ERROR_W_BIT 1 |
248 |
|
249 |
#define PG_ERROR_P_MASK 0x01 |
250 |
#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
251 |
#define PG_ERROR_U_MASK 0x04 |
252 |
#define PG_ERROR_RSVD_MASK 0x08 |
253 |
#define PG_ERROR_I_D_MASK 0x10 |
254 |
|
255 |
#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
256 |
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
257 |
|
258 |
#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
|
259 |
#define MCE_BANKS_DEF 10 |
260 |
|
261 |
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
262 |
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
263 |
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
264 |
|
265 |
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
266 |
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
267 |
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
268 |
#define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
269 |
#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
270 |
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
271 |
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
272 |
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
273 |
#define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
274 |
|
275 |
/* MISC register defines */
|
276 |
#define MCM_ADDR_SEGOFF 0 /* segment offset */ |
277 |
#define MCM_ADDR_LINEAR 1 /* linear address */ |
278 |
#define MCM_ADDR_PHYS 2 /* physical address */ |
279 |
#define MCM_ADDR_MEM 3 /* memory address */ |
280 |
#define MCM_ADDR_GENERIC 7 /* generic */ |
281 |
|
282 |
#define MSR_IA32_TSC 0x10 |
283 |
#define MSR_IA32_APICBASE 0x1b |
284 |
#define MSR_IA32_APICBASE_BSP (1<<8) |
285 |
#define MSR_IA32_APICBASE_ENABLE (1<<11) |
286 |
#define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
287 |
#define MSR_IA32_TSCDEADLINE 0x6e0 |
288 |
|
289 |
#define MSR_MTRRcap 0xfe |
290 |
#define MSR_MTRRcap_VCNT 8 |
291 |
#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) |
292 |
#define MSR_MTRRcap_WC_SUPPORTED (1 << 10) |
293 |
|
294 |
#define MSR_IA32_SYSENTER_CS 0x174 |
295 |
#define MSR_IA32_SYSENTER_ESP 0x175 |
296 |
#define MSR_IA32_SYSENTER_EIP 0x176 |
297 |
|
298 |
#define MSR_MCG_CAP 0x179 |
299 |
#define MSR_MCG_STATUS 0x17a |
300 |
#define MSR_MCG_CTL 0x17b |
301 |
|
302 |
#define MSR_IA32_PERF_STATUS 0x198 |
303 |
|
304 |
#define MSR_IA32_MISC_ENABLE 0x1a0 |
305 |
/* Indicates good rep/movs microcode on some processors: */
|
306 |
#define MSR_IA32_MISC_ENABLE_DEFAULT 1 |
307 |
|
308 |
#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
309 |
#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) |
310 |
|
311 |
#define MSR_MTRRfix64K_00000 0x250 |
312 |
#define MSR_MTRRfix16K_80000 0x258 |
313 |
#define MSR_MTRRfix16K_A0000 0x259 |
314 |
#define MSR_MTRRfix4K_C0000 0x268 |
315 |
#define MSR_MTRRfix4K_C8000 0x269 |
316 |
#define MSR_MTRRfix4K_D0000 0x26a |
317 |
#define MSR_MTRRfix4K_D8000 0x26b |
318 |
#define MSR_MTRRfix4K_E0000 0x26c |
319 |
#define MSR_MTRRfix4K_E8000 0x26d |
320 |
#define MSR_MTRRfix4K_F0000 0x26e |
321 |
#define MSR_MTRRfix4K_F8000 0x26f |
322 |
|
323 |
#define MSR_PAT 0x277 |
324 |
|
325 |
#define MSR_MTRRdefType 0x2ff |
326 |
|
327 |
#define MSR_MC0_CTL 0x400 |
328 |
#define MSR_MC0_STATUS 0x401 |
329 |
#define MSR_MC0_ADDR 0x402 |
330 |
#define MSR_MC0_MISC 0x403 |
331 |
|
332 |
#define MSR_EFER 0xc0000080 |
333 |
|
334 |
#define MSR_EFER_SCE (1 << 0) |
335 |
#define MSR_EFER_LME (1 << 8) |
336 |
#define MSR_EFER_LMA (1 << 10) |
337 |
#define MSR_EFER_NXE (1 << 11) |
338 |
#define MSR_EFER_SVME (1 << 12) |
339 |
#define MSR_EFER_FFXSR (1 << 14) |
340 |
|
341 |
#define MSR_STAR 0xc0000081 |
342 |
#define MSR_LSTAR 0xc0000082 |
343 |
#define MSR_CSTAR 0xc0000083 |
344 |
#define MSR_FMASK 0xc0000084 |
345 |
#define MSR_FSBASE 0xc0000100 |
346 |
#define MSR_GSBASE 0xc0000101 |
347 |
#define MSR_KERNELGSBASE 0xc0000102 |
348 |
#define MSR_TSC_AUX 0xc0000103 |
349 |
|
350 |
#define MSR_VM_HSAVE_PA 0xc0010117 |
351 |
|
352 |
/* cpuid_features bits */
|
353 |
#define CPUID_FP87 (1 << 0) |
354 |
#define CPUID_VME (1 << 1) |
355 |
#define CPUID_DE (1 << 2) |
356 |
#define CPUID_PSE (1 << 3) |
357 |
#define CPUID_TSC (1 << 4) |
358 |
#define CPUID_MSR (1 << 5) |
359 |
#define CPUID_PAE (1 << 6) |
360 |
#define CPUID_MCE (1 << 7) |
361 |
#define CPUID_CX8 (1 << 8) |
362 |
#define CPUID_APIC (1 << 9) |
363 |
#define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
364 |
#define CPUID_MTRR (1 << 12) |
365 |
#define CPUID_PGE (1 << 13) |
366 |
#define CPUID_MCA (1 << 14) |
367 |
#define CPUID_CMOV (1 << 15) |
368 |
#define CPUID_PAT (1 << 16) |
369 |
#define CPUID_PSE36 (1 << 17) |
370 |
#define CPUID_PN (1 << 18) |
371 |
#define CPUID_CLFLUSH (1 << 19) |
372 |
#define CPUID_DTS (1 << 21) |
373 |
#define CPUID_ACPI (1 << 22) |
374 |
#define CPUID_MMX (1 << 23) |
375 |
#define CPUID_FXSR (1 << 24) |
376 |
#define CPUID_SSE (1 << 25) |
377 |
#define CPUID_SSE2 (1 << 26) |
378 |
#define CPUID_SS (1 << 27) |
379 |
#define CPUID_HT (1 << 28) |
380 |
#define CPUID_TM (1 << 29) |
381 |
#define CPUID_IA64 (1 << 30) |
382 |
#define CPUID_PBE (1 << 31) |
383 |
|
384 |
#define CPUID_EXT_SSE3 (1 << 0) |
385 |
#define CPUID_EXT_DTES64 (1 << 2) |
386 |
#define CPUID_EXT_MONITOR (1 << 3) |
387 |
#define CPUID_EXT_DSCPL (1 << 4) |
388 |
#define CPUID_EXT_VMX (1 << 5) |
389 |
#define CPUID_EXT_SMX (1 << 6) |
390 |
#define CPUID_EXT_EST (1 << 7) |
391 |
#define CPUID_EXT_TM2 (1 << 8) |
392 |
#define CPUID_EXT_SSSE3 (1 << 9) |
393 |
#define CPUID_EXT_CID (1 << 10) |
394 |
#define CPUID_EXT_CX16 (1 << 13) |
395 |
#define CPUID_EXT_XTPR (1 << 14) |
396 |
#define CPUID_EXT_PDCM (1 << 15) |
397 |
#define CPUID_EXT_DCA (1 << 18) |
398 |
#define CPUID_EXT_SSE41 (1 << 19) |
399 |
#define CPUID_EXT_SSE42 (1 << 20) |
400 |
#define CPUID_EXT_X2APIC (1 << 21) |
401 |
#define CPUID_EXT_MOVBE (1 << 22) |
402 |
#define CPUID_EXT_POPCNT (1 << 23) |
403 |
#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) |
404 |
#define CPUID_EXT_XSAVE (1 << 26) |
405 |
#define CPUID_EXT_OSXSAVE (1 << 27) |
406 |
#define CPUID_EXT_HYPERVISOR (1 << 31) |
407 |
|
408 |
#define CPUID_EXT2_SYSCALL (1 << 11) |
409 |
#define CPUID_EXT2_MP (1 << 19) |
410 |
#define CPUID_EXT2_NX (1 << 20) |
411 |
#define CPUID_EXT2_MMXEXT (1 << 22) |
412 |
#define CPUID_EXT2_FFXSR (1 << 25) |
413 |
#define CPUID_EXT2_PDPE1GB (1 << 26) |
414 |
#define CPUID_EXT2_RDTSCP (1 << 27) |
415 |
#define CPUID_EXT2_LM (1 << 29) |
416 |
#define CPUID_EXT2_3DNOWEXT (1 << 30) |
417 |
#define CPUID_EXT2_3DNOW (1 << 31) |
418 |
|
419 |
#define CPUID_EXT3_LAHF_LM (1 << 0) |
420 |
#define CPUID_EXT3_CMP_LEG (1 << 1) |
421 |
#define CPUID_EXT3_SVM (1 << 2) |
422 |
#define CPUID_EXT3_EXTAPIC (1 << 3) |
423 |
#define CPUID_EXT3_CR8LEG (1 << 4) |
424 |
#define CPUID_EXT3_ABM (1 << 5) |
425 |
#define CPUID_EXT3_SSE4A (1 << 6) |
426 |
#define CPUID_EXT3_MISALIGNSSE (1 << 7) |
427 |
#define CPUID_EXT3_3DNOWPREFETCH (1 << 8) |
428 |
#define CPUID_EXT3_OSVW (1 << 9) |
429 |
#define CPUID_EXT3_IBS (1 << 10) |
430 |
#define CPUID_EXT3_SKINIT (1 << 12) |
431 |
|
432 |
#define CPUID_SVM_NPT (1 << 0) |
433 |
#define CPUID_SVM_LBRV (1 << 1) |
434 |
#define CPUID_SVM_SVMLOCK (1 << 2) |
435 |
#define CPUID_SVM_NRIPSAVE (1 << 3) |
436 |
#define CPUID_SVM_TSCSCALE (1 << 4) |
437 |
#define CPUID_SVM_VMCBCLEAN (1 << 5) |
438 |
#define CPUID_SVM_FLUSHASID (1 << 6) |
439 |
#define CPUID_SVM_DECODEASSIST (1 << 7) |
440 |
#define CPUID_SVM_PAUSEFILTER (1 << 10) |
441 |
#define CPUID_SVM_PFTHRESHOLD (1 << 12) |
442 |
|
443 |
#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
444 |
#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ |
445 |
#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
446 |
|
447 |
#define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
448 |
#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
449 |
#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
450 |
|
451 |
#define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ |
452 |
#define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ |
453 |
#define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ |
454 |
|
455 |
#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
456 |
#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
457 |
|
458 |
#define EXCP00_DIVZ 0 |
459 |
#define EXCP01_DB 1 |
460 |
#define EXCP02_NMI 2 |
461 |
#define EXCP03_INT3 3 |
462 |
#define EXCP04_INTO 4 |
463 |
#define EXCP05_BOUND 5 |
464 |
#define EXCP06_ILLOP 6 |
465 |
#define EXCP07_PREX 7 |
466 |
#define EXCP08_DBLE 8 |
467 |
#define EXCP09_XERR 9 |
468 |
#define EXCP0A_TSS 10 |
469 |
#define EXCP0B_NOSEG 11 |
470 |
#define EXCP0C_STACK 12 |
471 |
#define EXCP0D_GPF 13 |
472 |
#define EXCP0E_PAGE 14 |
473 |
#define EXCP10_COPR 16 |
474 |
#define EXCP11_ALGN 17 |
475 |
#define EXCP12_MCHK 18 |
476 |
|
477 |
#define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
478 |
for syscall instruction */
|
479 |
|
480 |
/* i386-specific interrupt pending bits. */
|
481 |
#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
|
482 |
#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
|
483 |
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
|
484 |
#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
|
485 |
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
|
486 |
#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
|
487 |
#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
|
488 |
#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3
|
489 |
|
490 |
|
491 |
enum {
|
492 |
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
|
493 |
CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
|
494 |
|
495 |
CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
|
496 |
CC_OP_MULW, |
497 |
CC_OP_MULL, |
498 |
CC_OP_MULQ, |
499 |
|
500 |
CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
501 |
CC_OP_ADDW, |
502 |
CC_OP_ADDL, |
503 |
CC_OP_ADDQ, |
504 |
|
505 |
CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
506 |
CC_OP_ADCW, |
507 |
CC_OP_ADCL, |
508 |
CC_OP_ADCQ, |
509 |
|
510 |
CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
511 |
CC_OP_SUBW, |
512 |
CC_OP_SUBL, |
513 |
CC_OP_SUBQ, |
514 |
|
515 |
CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
516 |
CC_OP_SBBW, |
517 |
CC_OP_SBBL, |
518 |
CC_OP_SBBQ, |
519 |
|
520 |
CC_OP_LOGICB, /* modify all flags, CC_DST = res */
|
521 |
CC_OP_LOGICW, |
522 |
CC_OP_LOGICL, |
523 |
CC_OP_LOGICQ, |
524 |
|
525 |
CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
526 |
CC_OP_INCW, |
527 |
CC_OP_INCL, |
528 |
CC_OP_INCQ, |
529 |
|
530 |
CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
531 |
CC_OP_DECW, |
532 |
CC_OP_DECL, |
533 |
CC_OP_DECQ, |
534 |
|
535 |
CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
|
536 |
CC_OP_SHLW, |
537 |
CC_OP_SHLL, |
538 |
CC_OP_SHLQ, |
539 |
|
540 |
CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
|
541 |
CC_OP_SARW, |
542 |
CC_OP_SARL, |
543 |
CC_OP_SARQ, |
544 |
|
545 |
CC_OP_NB, |
546 |
}; |
547 |
|
548 |
typedef struct SegmentCache { |
549 |
uint32_t selector; |
550 |
target_ulong base; |
551 |
uint32_t limit; |
552 |
uint32_t flags; |
553 |
} SegmentCache; |
554 |
|
555 |
typedef union { |
556 |
uint8_t _b[16];
|
557 |
uint16_t _w[8];
|
558 |
uint32_t _l[4];
|
559 |
uint64_t _q[2];
|
560 |
float32 _s[4];
|
561 |
float64 _d[2];
|
562 |
} XMMReg; |
563 |
|
564 |
typedef union { |
565 |
uint8_t _b[8];
|
566 |
uint16_t _w[4];
|
567 |
uint32_t _l[2];
|
568 |
float32 _s[2];
|
569 |
uint64_t q; |
570 |
} MMXReg; |
571 |
|
572 |
#ifdef HOST_WORDS_BIGENDIAN
|
573 |
#define XMM_B(n) _b[15 - (n)] |
574 |
#define XMM_W(n) _w[7 - (n)] |
575 |
#define XMM_L(n) _l[3 - (n)] |
576 |
#define XMM_S(n) _s[3 - (n)] |
577 |
#define XMM_Q(n) _q[1 - (n)] |
578 |
#define XMM_D(n) _d[1 - (n)] |
579 |
|
580 |
#define MMX_B(n) _b[7 - (n)] |
581 |
#define MMX_W(n) _w[3 - (n)] |
582 |
#define MMX_L(n) _l[1 - (n)] |
583 |
#define MMX_S(n) _s[1 - (n)] |
584 |
#else
|
585 |
#define XMM_B(n) _b[n]
|
586 |
#define XMM_W(n) _w[n]
|
587 |
#define XMM_L(n) _l[n]
|
588 |
#define XMM_S(n) _s[n]
|
589 |
#define XMM_Q(n) _q[n]
|
590 |
#define XMM_D(n) _d[n]
|
591 |
|
592 |
#define MMX_B(n) _b[n]
|
593 |
#define MMX_W(n) _w[n]
|
594 |
#define MMX_L(n) _l[n]
|
595 |
#define MMX_S(n) _s[n]
|
596 |
#endif
|
597 |
#define MMX_Q(n) q
|
598 |
|
599 |
typedef union { |
600 |
floatx80 d __attribute__((aligned(16)));
|
601 |
MMXReg mmx; |
602 |
} FPReg; |
603 |
|
604 |
typedef struct { |
605 |
uint64_t base; |
606 |
uint64_t mask; |
607 |
} MTRRVar; |
608 |
|
609 |
#define CPU_NB_REGS64 16 |
610 |
#define CPU_NB_REGS32 8 |
611 |
|
612 |
#ifdef TARGET_X86_64
|
613 |
#define CPU_NB_REGS CPU_NB_REGS64
|
614 |
#else
|
615 |
#define CPU_NB_REGS CPU_NB_REGS32
|
616 |
#endif
|
617 |
|
618 |
#define NB_MMU_MODES 2 |
619 |
|
620 |
typedef enum TPRAccess { |
621 |
TPR_ACCESS_READ, |
622 |
TPR_ACCESS_WRITE, |
623 |
} TPRAccess; |
624 |
|
625 |
typedef struct CPUX86State { |
626 |
/* standard registers */
|
627 |
target_ulong regs[CPU_NB_REGS]; |
628 |
target_ulong eip; |
629 |
target_ulong eflags; /* eflags register. During CPU emulation, CC
|
630 |
flags and DF are set to zero because they are
|
631 |
stored elsewhere */
|
632 |
|
633 |
/* emulator internal eflags handling */
|
634 |
target_ulong cc_src; |
635 |
target_ulong cc_dst; |
636 |
uint32_t cc_op; |
637 |
int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
638 |
uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
|
639 |
are known at translation time. */
|
640 |
uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
|
641 |
|
642 |
/* segments */
|
643 |
SegmentCache segs[6]; /* selector values */ |
644 |
SegmentCache ldt; |
645 |
SegmentCache tr; |
646 |
SegmentCache gdt; /* only base and limit are used */
|
647 |
SegmentCache idt; /* only base and limit are used */
|
648 |
|
649 |
target_ulong cr[5]; /* NOTE: cr1 is unused */ |
650 |
int32_t a20_mask; |
651 |
|
652 |
/* FPU state */
|
653 |
unsigned int fpstt; /* top of stack index */ |
654 |
uint16_t fpus; |
655 |
uint16_t fpuc; |
656 |
uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
657 |
FPReg fpregs[8];
|
658 |
/* KVM-only so far */
|
659 |
uint16_t fpop; |
660 |
uint64_t fpip; |
661 |
uint64_t fpdp; |
662 |
|
663 |
/* emulator internal variables */
|
664 |
float_status fp_status; |
665 |
floatx80 ft0; |
666 |
|
667 |
float_status mmx_status; /* for 3DNow! float ops */
|
668 |
float_status sse_status; |
669 |
uint32_t mxcsr; |
670 |
XMMReg xmm_regs[CPU_NB_REGS]; |
671 |
XMMReg xmm_t0; |
672 |
MMXReg mmx_t0; |
673 |
target_ulong cc_tmp; /* temporary for rcr/rcl */
|
674 |
|
675 |
/* sysenter registers */
|
676 |
uint32_t sysenter_cs; |
677 |
target_ulong sysenter_esp; |
678 |
target_ulong sysenter_eip; |
679 |
uint64_t efer; |
680 |
uint64_t star; |
681 |
|
682 |
uint64_t vm_hsave; |
683 |
uint64_t vm_vmcb; |
684 |
uint64_t tsc_offset; |
685 |
uint64_t intercept; |
686 |
uint16_t intercept_cr_read; |
687 |
uint16_t intercept_cr_write; |
688 |
uint16_t intercept_dr_read; |
689 |
uint16_t intercept_dr_write; |
690 |
uint32_t intercept_exceptions; |
691 |
uint8_t v_tpr; |
692 |
|
693 |
#ifdef TARGET_X86_64
|
694 |
target_ulong lstar; |
695 |
target_ulong cstar; |
696 |
target_ulong fmask; |
697 |
target_ulong kernelgsbase; |
698 |
#endif
|
699 |
uint64_t system_time_msr; |
700 |
uint64_t wall_clock_msr; |
701 |
uint64_t async_pf_en_msr; |
702 |
|
703 |
uint64_t tsc; |
704 |
uint64_t tsc_deadline; |
705 |
|
706 |
uint64_t mcg_status; |
707 |
uint64_t msr_ia32_misc_enable; |
708 |
|
709 |
/* exception/interrupt handling */
|
710 |
int error_code;
|
711 |
int exception_is_int;
|
712 |
target_ulong exception_next_eip; |
713 |
target_ulong dr[8]; /* debug registers */ |
714 |
union {
|
715 |
CPUBreakpoint *cpu_breakpoint[4];
|
716 |
CPUWatchpoint *cpu_watchpoint[4];
|
717 |
}; /* break/watchpoints for dr[0..3] */
|
718 |
uint32_t smbase; |
719 |
int old_exception; /* exception in flight */ |
720 |
|
721 |
/* KVM states, automatically cleared on reset */
|
722 |
uint8_t nmi_injected; |
723 |
uint8_t nmi_pending; |
724 |
|
725 |
CPU_COMMON |
726 |
|
727 |
uint64_t pat; |
728 |
|
729 |
/* processor features (e.g. for CPUID insn) */
|
730 |
uint32_t cpuid_level; |
731 |
uint32_t cpuid_vendor1; |
732 |
uint32_t cpuid_vendor2; |
733 |
uint32_t cpuid_vendor3; |
734 |
uint32_t cpuid_version; |
735 |
uint32_t cpuid_features; |
736 |
uint32_t cpuid_ext_features; |
737 |
uint32_t cpuid_xlevel; |
738 |
uint32_t cpuid_model[12];
|
739 |
uint32_t cpuid_ext2_features; |
740 |
uint32_t cpuid_ext3_features; |
741 |
uint32_t cpuid_apic_id; |
742 |
int cpuid_vendor_override;
|
743 |
/* Store the results of Centaur's CPUID instructions */
|
744 |
uint32_t cpuid_xlevel2; |
745 |
uint32_t cpuid_ext4_features; |
746 |
/* Flags from CPUID[EAX=7,ECX=0].EBX */
|
747 |
uint32_t cpuid_7_0_ebx; |
748 |
|
749 |
/* MTRRs */
|
750 |
uint64_t mtrr_fixed[11];
|
751 |
uint64_t mtrr_deftype; |
752 |
MTRRVar mtrr_var[8];
|
753 |
|
754 |
/* For KVM */
|
755 |
uint32_t mp_state; |
756 |
int32_t exception_injected; |
757 |
int32_t interrupt_injected; |
758 |
uint8_t soft_interrupt; |
759 |
uint8_t has_error_code; |
760 |
uint32_t sipi_vector; |
761 |
uint32_t cpuid_kvm_features; |
762 |
uint32_t cpuid_svm_features; |
763 |
bool tsc_valid;
|
764 |
int tsc_khz;
|
765 |
void *kvm_xsave_buf;
|
766 |
|
767 |
/* in order to simplify APIC support, we leave this pointer to the
|
768 |
user */
|
769 |
struct DeviceState *apic_state;
|
770 |
|
771 |
uint64_t mcg_cap; |
772 |
uint64_t mcg_ctl; |
773 |
uint64_t mce_banks[MCE_BANKS_DEF*4];
|
774 |
|
775 |
uint64_t tsc_aux; |
776 |
|
777 |
/* vmstate */
|
778 |
uint16_t fpus_vmstate; |
779 |
uint16_t fptag_vmstate; |
780 |
uint16_t fpregs_format_vmstate; |
781 |
|
782 |
uint64_t xstate_bv; |
783 |
XMMReg ymmh_regs[CPU_NB_REGS]; |
784 |
|
785 |
uint64_t xcr0; |
786 |
|
787 |
TPRAccess tpr_access_type; |
788 |
} CPUX86State; |
789 |
|
790 |
#include "cpu-qom.h" |
791 |
|
792 |
X86CPU *cpu_x86_init(const char *cpu_model); |
793 |
int cpu_x86_exec(CPUX86State *s);
|
794 |
void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg); |
795 |
void x86_cpudef_setup(void); |
796 |
int cpu_x86_support_mca_broadcast(CPUX86State *env);
|
797 |
|
798 |
int cpu_get_pic_interrupt(CPUX86State *s);
|
799 |
/* MSDOS compatibility mode FPU exception support */
|
800 |
void cpu_set_ferr(CPUX86State *s);
|
801 |
|
802 |
/* this function must always be used to load data in the segment
|
803 |
cache: it synchronizes the hflags with the segment cache values */
|
804 |
static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
805 |
int seg_reg, unsigned int selector, |
806 |
target_ulong base, |
807 |
unsigned int limit, |
808 |
unsigned int flags) |
809 |
{ |
810 |
SegmentCache *sc; |
811 |
unsigned int new_hflags; |
812 |
|
813 |
sc = &env->segs[seg_reg]; |
814 |
sc->selector = selector; |
815 |
sc->base = base; |
816 |
sc->limit = limit; |
817 |
sc->flags = flags; |
818 |
|
819 |
/* update the hidden flags */
|
820 |
{ |
821 |
if (seg_reg == R_CS) {
|
822 |
#ifdef TARGET_X86_64
|
823 |
if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
|
824 |
/* long mode */
|
825 |
env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
826 |
env->hflags &= ~(HF_ADDSEG_MASK); |
827 |
} else
|
828 |
#endif
|
829 |
{ |
830 |
/* legacy / compatibility case */
|
831 |
new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
832 |
>> (DESC_B_SHIFT - HF_CS32_SHIFT); |
833 |
env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
834 |
new_hflags; |
835 |
} |
836 |
} |
837 |
new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
838 |
>> (DESC_B_SHIFT - HF_SS32_SHIFT); |
839 |
if (env->hflags & HF_CS64_MASK) {
|
840 |
/* zero base assumed for DS, ES and SS in long mode */
|
841 |
} else if (!(env->cr[0] & CR0_PE_MASK) || |
842 |
(env->eflags & VM_MASK) || |
843 |
!(env->hflags & HF_CS32_MASK)) { |
844 |
/* XXX: try to avoid this test. The problem comes from the
|
845 |
fact that is real mode or vm86 mode we only modify the
|
846 |
'base' and 'selector' fields of the segment cache to go
|
847 |
faster. A solution may be to force addseg to one in
|
848 |
translate-i386.c. */
|
849 |
new_hflags |= HF_ADDSEG_MASK; |
850 |
} else {
|
851 |
new_hflags |= ((env->segs[R_DS].base | |
852 |
env->segs[R_ES].base | |
853 |
env->segs[R_SS].base) != 0) <<
|
854 |
HF_ADDSEG_SHIFT; |
855 |
} |
856 |
env->hflags = (env->hflags & |
857 |
~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
858 |
} |
859 |
} |
860 |
|
861 |
static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env, |
862 |
int sipi_vector)
|
863 |
{ |
864 |
env->eip = 0;
|
865 |
cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
|
866 |
sipi_vector << 12,
|
867 |
env->segs[R_CS].limit, |
868 |
env->segs[R_CS].flags); |
869 |
env->halted = 0;
|
870 |
} |
871 |
|
872 |
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
873 |
target_ulong *base, unsigned int *limit, |
874 |
unsigned int *flags); |
875 |
|
876 |
/* wrapper, just in case memory mappings must be changed */
|
877 |
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
878 |
{ |
879 |
#if HF_CPL_MASK == 3 |
880 |
s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
881 |
#else
|
882 |
#error HF_CPL_MASK is hardcoded
|
883 |
#endif
|
884 |
} |
885 |
|
886 |
/* op_helper.c */
|
887 |
/* used for debug or cpu save/restore */
|
888 |
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
|
889 |
floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); |
890 |
|
891 |
/* cpu-exec.c */
|
892 |
/* the following helpers are only usable in user mode simulation as
|
893 |
they can trigger unexpected exceptions */
|
894 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
895 |
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
896 |
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); |
897 |
|
898 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
899 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
900 |
is returned if the signal was handled by the virtual CPU. */
|
901 |
int cpu_x86_signal_handler(int host_signum, void *pinfo, |
902 |
void *puc);
|
903 |
|
904 |
/* cpuid.c */
|
905 |
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
906 |
uint32_t *eax, uint32_t *ebx, |
907 |
uint32_t *ecx, uint32_t *edx); |
908 |
int cpu_x86_register(X86CPU *cpu, const char *cpu_model); |
909 |
void cpu_clear_apic_feature(CPUX86State *env);
|
910 |
void host_cpuid(uint32_t function, uint32_t count,
|
911 |
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); |
912 |
|
913 |
/* helper.c */
|
914 |
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
915 |
int is_write, int mmu_idx); |
916 |
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
|
917 |
void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
918 |
|
919 |
static inline int hw_breakpoint_enabled(unsigned long dr7, int index) |
920 |
{ |
921 |
return (dr7 >> (index * 2)) & 3; |
922 |
} |
923 |
|
924 |
static inline int hw_breakpoint_type(unsigned long dr7, int index) |
925 |
{ |
926 |
return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3; |
927 |
} |
928 |
|
929 |
static inline int hw_breakpoint_len(unsigned long dr7, int index) |
930 |
{ |
931 |
int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3); |
932 |
return (len == 2) ? 8 : len + 1; |
933 |
} |
934 |
|
935 |
void hw_breakpoint_insert(CPUX86State *env, int index); |
936 |
void hw_breakpoint_remove(CPUX86State *env, int index); |
937 |
int check_hw_breakpoints(CPUX86State *env, int force_dr6_update); |
938 |
void breakpoint_handler(CPUX86State *env);
|
939 |
|
940 |
/* will be suppressed */
|
941 |
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
|
942 |
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
|
943 |
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
|
944 |
|
945 |
/* hw/pc.c */
|
946 |
void cpu_smm_update(CPUX86State *env);
|
947 |
uint64_t cpu_get_tsc(CPUX86State *env); |
948 |
|
949 |
/* used to debug */
|
950 |
#define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
951 |
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
952 |
|
953 |
#define TARGET_PAGE_BITS 12 |
954 |
|
955 |
#ifdef TARGET_X86_64
|
956 |
#define TARGET_PHYS_ADDR_SPACE_BITS 52 |
957 |
/* ??? This is really 48 bits, sign-extended, but the only thing
|
958 |
accessible to userland with bit 48 set is the VSYSCALL, and that
|
959 |
is handled via other mechanisms. */
|
960 |
#define TARGET_VIRT_ADDR_SPACE_BITS 47 |
961 |
#else
|
962 |
#define TARGET_PHYS_ADDR_SPACE_BITS 36 |
963 |
#define TARGET_VIRT_ADDR_SPACE_BITS 32 |
964 |
#endif
|
965 |
|
966 |
static inline CPUX86State *cpu_init(const char *cpu_model) |
967 |
{ |
968 |
X86CPU *cpu = cpu_x86_init(cpu_model); |
969 |
if (cpu == NULL) { |
970 |
return NULL; |
971 |
} |
972 |
return &cpu->env;
|
973 |
} |
974 |
|
975 |
#define cpu_exec cpu_x86_exec
|
976 |
#define cpu_gen_code cpu_x86_gen_code
|
977 |
#define cpu_signal_handler cpu_x86_signal_handler
|
978 |
#define cpu_list_id x86_cpu_list
|
979 |
#define cpudef_setup x86_cpudef_setup
|
980 |
|
981 |
#define CPU_SAVE_VERSION 12 |
982 |
|
983 |
/* MMU modes definitions */
|
984 |
#define MMU_MODE0_SUFFIX _kernel
|
985 |
#define MMU_MODE1_SUFFIX _user
|
986 |
#define MMU_USER_IDX 1 |
987 |
static inline int cpu_mmu_index (CPUX86State *env) |
988 |
{ |
989 |
return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; |
990 |
} |
991 |
|
992 |
#undef EAX
|
993 |
#define EAX (env->regs[R_EAX])
|
994 |
#undef ECX
|
995 |
#define ECX (env->regs[R_ECX])
|
996 |
#undef EDX
|
997 |
#define EDX (env->regs[R_EDX])
|
998 |
#undef EBX
|
999 |
#define EBX (env->regs[R_EBX])
|
1000 |
#undef ESP
|
1001 |
#define ESP (env->regs[R_ESP])
|
1002 |
#undef EBP
|
1003 |
#define EBP (env->regs[R_EBP])
|
1004 |
#undef ESI
|
1005 |
#define ESI (env->regs[R_ESI])
|
1006 |
#undef EDI
|
1007 |
#define EDI (env->regs[R_EDI])
|
1008 |
#undef EIP
|
1009 |
#define EIP (env->eip)
|
1010 |
#define DF (env->df)
|
1011 |
|
1012 |
#define CC_SRC (env->cc_src)
|
1013 |
#define CC_DST (env->cc_dst)
|
1014 |
#define CC_OP (env->cc_op)
|
1015 |
|
1016 |
/* n must be a constant to be efficient */
|
1017 |
static inline target_long lshift(target_long x, int n) |
1018 |
{ |
1019 |
if (n >= 0) { |
1020 |
return x << n;
|
1021 |
} else {
|
1022 |
return x >> (-n);
|
1023 |
} |
1024 |
} |
1025 |
|
1026 |
/* float macros */
|
1027 |
#define FT0 (env->ft0)
|
1028 |
#define ST0 (env->fpregs[env->fpstt].d)
|
1029 |
#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
1030 |
#define ST1 ST(1) |
1031 |
|
1032 |
/* translate.c */
|
1033 |
void optimize_flags_init(void); |
1034 |
|
1035 |
#if defined(CONFIG_USER_ONLY)
|
1036 |
static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) |
1037 |
{ |
1038 |
if (newsp)
|
1039 |
env->regs[R_ESP] = newsp; |
1040 |
env->regs[R_EAX] = 0;
|
1041 |
} |
1042 |
#endif
|
1043 |
|
1044 |
#include "cpu-all.h" |
1045 |
#include "svm.h" |
1046 |
|
1047 |
#if !defined(CONFIG_USER_ONLY)
|
1048 |
#include "hw/apic.h" |
1049 |
#endif
|
1050 |
|
1051 |
static inline bool cpu_has_work(CPUX86State *env) |
1052 |
{ |
1053 |
return ((env->interrupt_request & (CPU_INTERRUPT_HARD |
|
1054 |
CPU_INTERRUPT_POLL)) && |
1055 |
(env->eflags & IF_MASK)) || |
1056 |
(env->interrupt_request & (CPU_INTERRUPT_NMI | |
1057 |
CPU_INTERRUPT_INIT | |
1058 |
CPU_INTERRUPT_SIPI | |
1059 |
CPU_INTERRUPT_MCE)); |
1060 |
} |
1061 |
|
1062 |
#include "exec-all.h" |
1063 |
|
1064 |
static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb) |
1065 |
{ |
1066 |
env->eip = tb->pc - tb->cs_base; |
1067 |
} |
1068 |
|
1069 |
static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
1070 |
target_ulong *cs_base, int *flags)
|
1071 |
{ |
1072 |
*cs_base = env->segs[R_CS].base; |
1073 |
*pc = *cs_base + env->eip; |
1074 |
*flags = env->hflags | |
1075 |
(env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); |
1076 |
} |
1077 |
|
1078 |
void do_cpu_init(X86CPU *cpu);
|
1079 |
void do_cpu_sipi(X86CPU *cpu);
|
1080 |
|
1081 |
#define MCE_INJECT_BROADCAST 1 |
1082 |
#define MCE_INJECT_UNCOND_AO 2 |
1083 |
|
1084 |
void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank, |
1085 |
uint64_t status, uint64_t mcg_status, uint64_t addr, |
1086 |
uint64_t misc, int flags);
|
1087 |
|
1088 |
/* excp_helper.c */
|
1089 |
void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
1090 |
void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, |
1091 |
int error_code);
|
1092 |
void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
1093 |
int error_code, int next_eip_addend); |
1094 |
|
1095 |
/* cc_helper.c */
|
1096 |
extern const uint8_t parity_table[256]; |
1097 |
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
|
1098 |
|
1099 |
static inline uint32_t cpu_compute_eflags(CPUX86State *env) |
1100 |
{ |
1101 |
return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK);
|
1102 |
} |
1103 |
|
1104 |
/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
|
1105 |
static inline void cpu_load_eflags(CPUX86State *env, int eflags, |
1106 |
int update_mask)
|
1107 |
{ |
1108 |
CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
1109 |
DF = 1 - (2 * ((eflags >> 10) & 1)); |
1110 |
env->eflags = (env->eflags & ~update_mask) | |
1111 |
(eflags & update_mask) | 0x2;
|
1112 |
} |
1113 |
|
1114 |
/* load efer and update the corresponding hflags. XXX: do consistency
|
1115 |
checks with cpuid bits? */
|
1116 |
static inline void cpu_load_efer(CPUX86State *env, uint64_t val) |
1117 |
{ |
1118 |
env->efer = val; |
1119 |
env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); |
1120 |
if (env->efer & MSR_EFER_LMA) {
|
1121 |
env->hflags |= HF_LMA_MASK; |
1122 |
} |
1123 |
if (env->efer & MSR_EFER_SVME) {
|
1124 |
env->hflags |= HF_SVME_MASK; |
1125 |
} |
1126 |
} |
1127 |
|
1128 |
/* svm_helper.c */
|
1129 |
void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
|
1130 |
uint64_t param); |
1131 |
void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
|
1132 |
|
1133 |
/* op_helper.c */
|
1134 |
void do_interrupt(CPUX86State *env);
|
1135 |
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); |
1136 |
|
1137 |
void do_smm_enter(CPUX86State *env1);
|
1138 |
|
1139 |
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
|
1140 |
|
1141 |
/* temporary wrappers */
|
1142 |
uint32_t cpu_ldub_data(CPUX86State *env, target_ulong ptr); |
1143 |
uint32_t cpu_lduw_data(CPUX86State *env, target_ulong ptr); |
1144 |
uint32_t cpu_ldl_data(CPUX86State *env, target_ulong ptr); |
1145 |
uint64_t cpu_ldq_data(CPUX86State *env, target_ulong ptr); |
1146 |
|
1147 |
void cpu_stb_data(CPUX86State *env, target_ulong ptr, uint32_t data);
|
1148 |
void cpu_stw_data(CPUX86State *env, target_ulong ptr, uint32_t data);
|
1149 |
void cpu_stl_data(CPUX86State *env, target_ulong ptr, uint32_t data);
|
1150 |
void cpu_stq_data(CPUX86State *env, target_ulong ptr, uint64_t data);
|
1151 |
|
1152 |
uint32_t cpu_ldub_kernel(CPUX86State *env, target_ulong ptr); |
1153 |
uint32_t cpu_lduw_kernel(CPUX86State *env, target_ulong ptr); |
1154 |
uint32_t cpu_ldl_kernel(CPUX86State *env, target_ulong ptr); |
1155 |
uint64_t cpu_ldq_kernel(CPUX86State *env, target_ulong ptr); |
1156 |
|
1157 |
void cpu_stb_kernel(CPUX86State *env, target_ulong ptr, uint32_t data);
|
1158 |
void cpu_stw_kernel(CPUX86State *env, target_ulong ptr, uint32_t data);
|
1159 |
void cpu_stl_kernel(CPUX86State *env, target_ulong ptr, uint32_t data);
|
1160 |
void cpu_stq_kernel(CPUX86State *env, target_ulong ptr, uint64_t data);
|
1161 |
|
1162 |
#endif /* CPU_I386_H */ |