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/*
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* QEMU KVM support
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*
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* Copyright (C) 2006-2008 Qumranet Technologies
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* Copyright IBM, Corp. 2008
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <sys/types.h> |
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#include <sys/ioctl.h> |
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#include <sys/mman.h> |
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#include <sys/utsname.h> |
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#include <linux/kvm.h> |
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "kvm.h" |
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#include "cpu.h" |
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#include "gdbstub.h" |
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#include "host-utils.h" |
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#include "hw/pc.h" |
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#include "hw/apic.h" |
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#include "ioport.h" |
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#ifdef CONFIG_KVM_PARA
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#include <linux/kvm_para.h> |
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#endif
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//
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//#define DEBUG_KVM
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#ifdef DEBUG_KVM
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0) |
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#endif
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|
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#define MSR_KVM_WALL_CLOCK 0x11 |
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#define MSR_KVM_SYSTEM_TIME 0x12 |
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#ifndef BUS_MCEERR_AR
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#define BUS_MCEERR_AR 4 |
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#endif
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#ifndef BUS_MCEERR_AO
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#define BUS_MCEERR_AO 5 |
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#endif
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_INFO(SET_TSS_ADDR), |
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KVM_CAP_INFO(EXT_CPUID), |
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KVM_CAP_INFO(MP_STATE), |
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KVM_CAP_LAST_INFO |
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}; |
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|
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static bool has_msr_star; |
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static bool has_msr_hsave_pa; |
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#if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
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static bool has_msr_async_pf_en; |
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#endif
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static int lm_capable_kernel; |
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static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
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{
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struct kvm_cpuid2 *cpuid;
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int r, size;
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size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); |
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cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
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cpuid->nent = max; |
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r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); |
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if (r == 0 && cpuid->nent >= max) { |
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r = -E2BIG; |
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} |
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if (r < 0) { |
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if (r == -E2BIG) {
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qemu_free(cpuid); |
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return NULL; |
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} else {
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fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
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strerror(-r)); |
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exit(1);
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} |
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} |
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return cpuid;
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} |
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|
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uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
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uint32_t index, int reg)
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{
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struct kvm_cpuid2 *cpuid;
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int i, max;
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uint32_t ret = 0;
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uint32_t cpuid_1_edx; |
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max = 1;
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while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { |
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max *= 2;
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} |
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for (i = 0; i < cpuid->nent; ++i) { |
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if (cpuid->entries[i].function == function &&
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cpuid->entries[i].index == index) {
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switch (reg) {
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case R_EAX:
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ret = cpuid->entries[i].eax; |
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break;
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case R_EBX:
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ret = cpuid->entries[i].ebx; |
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break;
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case R_ECX:
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ret = cpuid->entries[i].ecx; |
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break;
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case R_EDX:
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ret = cpuid->entries[i].edx; |
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switch (function) {
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case 1: |
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/* KVM before 2.6.30 misreports the following features */
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ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; |
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break;
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case 0x80000001: |
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/* On Intel, kvm returns cpuid according to the Intel spec,
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* so add missing bits according to the AMD spec:
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*/
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cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
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ret |= cpuid_1_edx & 0x183f7ff;
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break;
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} |
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break;
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} |
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} |
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} |
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qemu_free(cpuid); |
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return ret;
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} |
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#ifdef CONFIG_KVM_PARA
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struct kvm_para_features {
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int cap;
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int feature;
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} para_features[] = {
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{ KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
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{ KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
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{ KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
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#ifdef KVM_CAP_ASYNC_PF
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{ KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
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#endif
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{ -1, -1 }
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}; |
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static int get_para_features(CPUState *env) |
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{
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int i, features = 0; |
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for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
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if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
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features |= (1 << para_features[i].feature);
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} |
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} |
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#ifdef KVM_CAP_ASYNC_PF
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has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF);
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#endif
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return features;
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} |
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#endif /* CONFIG_KVM_PARA */ |
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#ifdef KVM_CAP_MCE
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static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
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int *max_banks)
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{
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int r;
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r = kvm_check_extension(s, KVM_CAP_MCE); |
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if (r > 0) { |
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*max_banks = r; |
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return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
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} |
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return -ENOSYS;
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} |
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static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code) |
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{
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uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
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MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; |
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uint64_t mcg_status = MCG_STATUS_MCIP; |
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if (code == BUS_MCEERR_AR) {
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status |= MCI_STATUS_AR | 0x134;
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mcg_status |= MCG_STATUS_EIPV; |
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} else {
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status |= 0xc0;
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mcg_status |= MCG_STATUS_RIPV; |
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} |
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cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, |
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(MCM_ADDR_PHYS << 6) | 0xc, |
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cpu_x86_support_mca_broadcast(env) ? |
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MCE_INJECT_BROADCAST : 0);
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} |
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#endif /* KVM_CAP_MCE */ |
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static void hardware_memory_error(void) |
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{
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fprintf(stderr, "Hardware memory error!\n");
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exit(1);
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} |
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int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
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{
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#ifdef KVM_CAP_MCE
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ram_addr_t ram_addr; |
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target_phys_addr_t paddr; |
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if ((env->mcg_cap & MCG_SER_P) && addr
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&& (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
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if (qemu_ram_addr_from_host(addr, &ram_addr) ||
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!kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, |
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&paddr)) {
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fprintf(stderr, "Hardware memory error for memory used by "
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"QEMU itself instead of guest system!\n");
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/* Hope we are lucky for AO MCE */
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if (code == BUS_MCEERR_AO) {
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return 0; |
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} else {
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hardware_memory_error(); |
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} |
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} |
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kvm_mce_inject(env, paddr, code); |
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} else
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#endif /* KVM_CAP_MCE */ |
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{
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if (code == BUS_MCEERR_AO) {
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return 0; |
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} else if (code == BUS_MCEERR_AR) { |
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hardware_memory_error(); |
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} else {
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return 1; |
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} |
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} |
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return 0; |
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} |
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|
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int kvm_arch_on_sigbus(int code, void *addr) |
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{
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#ifdef KVM_CAP_MCE
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if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
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ram_addr_t ram_addr; |
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target_phys_addr_t paddr; |
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/* Hope we are lucky for AO MCE */
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if (qemu_ram_addr_from_host(addr, &ram_addr) ||
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!kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, |
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&paddr)) {
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fprintf(stderr, "Hardware memory error for memory used by "
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"QEMU itself instead of guest system!: %p\n", addr);
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return 0; |
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} |
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kvm_mce_inject(first_cpu, paddr, code); |
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} else
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#endif /* KVM_CAP_MCE */ |
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{
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if (code == BUS_MCEERR_AO) {
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return 0; |
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} else if (code == BUS_MCEERR_AR) { |
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hardware_memory_error(); |
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} else {
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return 1; |
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} |
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} |
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return 0; |
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} |
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static int kvm_inject_mce_oldstyle(CPUState *env) |
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{
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#ifdef KVM_CAP_MCE
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if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
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unsigned int bank, bank_num = env->mcg_cap & 0xff; |
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struct kvm_x86_mce mce;
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env->exception_injected = -1;
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/*
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* There must be at least one bank in use if an MCE is pending.
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* Find it and use its values for the event injection.
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*/
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for (bank = 0; bank < bank_num; bank++) { |
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if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { |
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break;
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} |
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} |
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assert(bank < bank_num); |
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|
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mce.bank = bank; |
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mce.status = env->mce_banks[bank * 4 + 1]; |
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mce.mcg_status = env->mcg_status; |
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mce.addr = env->mce_banks[bank * 4 + 2]; |
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mce.misc = env->mce_banks[bank * 4 + 3]; |
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return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
|
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} |
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#endif /* KVM_CAP_MCE */ |
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return 0; |
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} |
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|
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static void cpu_update_state(void *opaque, int running, int reason) |
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{
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CPUState *env = opaque; |
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|
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if (running) {
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env->tsc_valid = false;
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} |
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} |
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|
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int kvm_arch_init_vcpu(CPUState *env)
|
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{
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struct {
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struct kvm_cpuid2 cpuid;
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struct kvm_cpuid_entry2 entries[100]; |
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} __attribute__((packed)) cpuid_data; |
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uint32_t limit, i, j, cpuid_i; |
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uint32_t unused; |
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struct kvm_cpuid_entry2 *c;
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#ifdef CONFIG_KVM_PARA
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uint32_t signature[3];
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#endif
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env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
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|
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i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; |
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env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
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env->cpuid_ext_features |= i; |
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|
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env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
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0, R_EDX);
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env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
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0, R_ECX);
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env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
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0, R_EDX);
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|
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|
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cpuid_i = 0;
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|
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#ifdef CONFIG_KVM_PARA
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/* Paravirtualization CPUIDs */
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memcpy(signature, "KVMKVMKVM\0\0\0", 12); |
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c = &cpuid_data.entries[cpuid_i++]; |
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memset(c, 0, sizeof(*c)); |
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c->function = KVM_CPUID_SIGNATURE; |
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c->eax = 0;
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c->ebx = signature[0];
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c->ecx = signature[1];
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c->edx = signature[2];
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|
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c = &cpuid_data.entries[cpuid_i++]; |
| 363 |
memset(c, 0, sizeof(*c)); |
| 364 |
c->function = KVM_CPUID_FEATURES; |
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c->eax = env->cpuid_kvm_features & get_para_features(env); |
| 366 |
#endif
|
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|
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cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
| 369 |
|
| 370 |
for (i = 0; i <= limit; i++) { |
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c = &cpuid_data.entries[cpuid_i++]; |
| 372 |
|
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switch (i) {
|
| 374 |
case 2: { |
| 375 |
/* Keep reading function 2 till all the input is received */
|
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int times;
|
| 377 |
|
| 378 |
c->function = i; |
| 379 |
c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
| 380 |
KVM_CPUID_FLAG_STATE_READ_NEXT; |
| 381 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
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times = c->eax & 0xff;
|
| 383 |
|
| 384 |
for (j = 1; j < times; ++j) { |
| 385 |
c = &cpuid_data.entries[cpuid_i++]; |
| 386 |
c->function = i; |
| 387 |
c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
| 388 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
| 389 |
} |
| 390 |
break;
|
| 391 |
} |
| 392 |
case 4: |
| 393 |
case 0xb: |
| 394 |
case 0xd: |
| 395 |
for (j = 0; ; j++) { |
| 396 |
c->function = i; |
| 397 |
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
| 398 |
c->index = j; |
| 399 |
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
| 400 |
|
| 401 |
if (i == 4 && c->eax == 0) { |
| 402 |
break;
|
| 403 |
} |
| 404 |
if (i == 0xb && !(c->ecx & 0xff00)) { |
| 405 |
break;
|
| 406 |
} |
| 407 |
if (i == 0xd && c->eax == 0) { |
| 408 |
break;
|
| 409 |
} |
| 410 |
c = &cpuid_data.entries[cpuid_i++]; |
| 411 |
} |
| 412 |
break;
|
| 413 |
default:
|
| 414 |
c->function = i; |
| 415 |
c->flags = 0;
|
| 416 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
| 417 |
break;
|
| 418 |
} |
| 419 |
} |
| 420 |
cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
| 421 |
|
| 422 |
for (i = 0x80000000; i <= limit; i++) { |
| 423 |
c = &cpuid_data.entries[cpuid_i++]; |
| 424 |
|
| 425 |
c->function = i; |
| 426 |
c->flags = 0;
|
| 427 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
| 428 |
} |
| 429 |
|
| 430 |
cpuid_data.cpuid.nent = cpuid_i; |
| 431 |
|
| 432 |
#ifdef KVM_CAP_MCE
|
| 433 |
if (((env->cpuid_version >> 8)&0xF) >= 6 |
| 434 |
&& (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) |
| 435 |
&& kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
|
| 436 |
uint64_t mcg_cap; |
| 437 |
int banks;
|
| 438 |
int ret;
|
| 439 |
|
| 440 |
if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) {
|
| 441 |
perror("kvm_get_mce_cap_supported FAILED");
|
| 442 |
} else {
|
| 443 |
if (banks > MCE_BANKS_DEF)
|
| 444 |
banks = MCE_BANKS_DEF; |
| 445 |
mcg_cap &= MCE_CAP_DEF; |
| 446 |
mcg_cap |= banks; |
| 447 |
ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap); |
| 448 |
if (ret < 0) { |
| 449 |
fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
|
| 450 |
} else {
|
| 451 |
env->mcg_cap = mcg_cap; |
| 452 |
} |
| 453 |
} |
| 454 |
} |
| 455 |
#endif
|
| 456 |
|
| 457 |
qemu_add_vm_change_state_handler(cpu_update_state, env); |
| 458 |
|
| 459 |
return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
|
| 460 |
} |
| 461 |
|
| 462 |
void kvm_arch_reset_vcpu(CPUState *env)
|
| 463 |
{
|
| 464 |
env->exception_injected = -1;
|
| 465 |
env->interrupt_injected = -1;
|
| 466 |
env->xcr0 = 1;
|
| 467 |
if (kvm_irqchip_in_kernel()) {
|
| 468 |
env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : |
| 469 |
KVM_MP_STATE_UNINITIALIZED; |
| 470 |
} else {
|
| 471 |
env->mp_state = KVM_MP_STATE_RUNNABLE; |
| 472 |
} |
| 473 |
} |
| 474 |
|
| 475 |
static int kvm_get_supported_msrs(KVMState *s) |
| 476 |
{
|
| 477 |
static int kvm_supported_msrs; |
| 478 |
int ret = 0; |
| 479 |
|
| 480 |
/* first time */
|
| 481 |
if (kvm_supported_msrs == 0) { |
| 482 |
struct kvm_msr_list msr_list, *kvm_msr_list;
|
| 483 |
|
| 484 |
kvm_supported_msrs = -1;
|
| 485 |
|
| 486 |
/* Obtain MSR list from KVM. These are the MSRs that we must
|
| 487 |
* save/restore */
|
| 488 |
msr_list.nmsrs = 0;
|
| 489 |
ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
| 490 |
if (ret < 0 && ret != -E2BIG) { |
| 491 |
return ret;
|
| 492 |
} |
| 493 |
/* Old kernel modules had a bug and could write beyond the provided
|
| 494 |
memory. Allocate at least a safe amount of 1K. */
|
| 495 |
kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + |
| 496 |
msr_list.nmsrs * |
| 497 |
sizeof(msr_list.indices[0]))); |
| 498 |
|
| 499 |
kvm_msr_list->nmsrs = msr_list.nmsrs; |
| 500 |
ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
| 501 |
if (ret >= 0) { |
| 502 |
int i;
|
| 503 |
|
| 504 |
for (i = 0; i < kvm_msr_list->nmsrs; i++) { |
| 505 |
if (kvm_msr_list->indices[i] == MSR_STAR) {
|
| 506 |
has_msr_star = true;
|
| 507 |
continue;
|
| 508 |
} |
| 509 |
if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
|
| 510 |
has_msr_hsave_pa = true;
|
| 511 |
continue;
|
| 512 |
} |
| 513 |
} |
| 514 |
} |
| 515 |
|
| 516 |
free(kvm_msr_list); |
| 517 |
} |
| 518 |
|
| 519 |
return ret;
|
| 520 |
} |
| 521 |
|
| 522 |
int kvm_arch_init(KVMState *s)
|
| 523 |
{
|
| 524 |
uint64_t identity_base = 0xfffbc000;
|
| 525 |
int ret;
|
| 526 |
struct utsname utsname;
|
| 527 |
|
| 528 |
ret = kvm_get_supported_msrs(s); |
| 529 |
if (ret < 0) { |
| 530 |
return ret;
|
| 531 |
} |
| 532 |
|
| 533 |
uname(&utsname); |
| 534 |
lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; |
| 535 |
|
| 536 |
/*
|
| 537 |
* On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
|
| 538 |
* In order to use vm86 mode, an EPT identity map and a TSS are needed.
|
| 539 |
* Since these must be part of guest physical memory, we need to allocate
|
| 540 |
* them, both by setting their start addresses in the kernel and by
|
| 541 |
* creating a corresponding e820 entry. We need 4 pages before the BIOS.
|
| 542 |
*
|
| 543 |
* Older KVM versions may not support setting the identity map base. In
|
| 544 |
* that case we need to stick with the default, i.e. a 256K maximum BIOS
|
| 545 |
* size.
|
| 546 |
*/
|
| 547 |
#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
|
| 548 |
if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
|
| 549 |
/* Allows up to 16M BIOSes. */
|
| 550 |
identity_base = 0xfeffc000;
|
| 551 |
|
| 552 |
ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); |
| 553 |
if (ret < 0) { |
| 554 |
return ret;
|
| 555 |
} |
| 556 |
} |
| 557 |
#endif
|
| 558 |
/* Set TSS base one page after EPT identity map. */
|
| 559 |
ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
|
| 560 |
if (ret < 0) { |
| 561 |
return ret;
|
| 562 |
} |
| 563 |
|
| 564 |
/* Tell fw_cfg to notify the BIOS to reserve the range. */
|
| 565 |
ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
|
| 566 |
if (ret < 0) { |
| 567 |
fprintf(stderr, "e820_add_entry() table is full\n");
|
| 568 |
return ret;
|
| 569 |
} |
| 570 |
|
| 571 |
return 0; |
| 572 |
} |
| 573 |
|
| 574 |
static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
| 575 |
{
|
| 576 |
lhs->selector = rhs->selector; |
| 577 |
lhs->base = rhs->base; |
| 578 |
lhs->limit = rhs->limit; |
| 579 |
lhs->type = 3;
|
| 580 |
lhs->present = 1;
|
| 581 |
lhs->dpl = 3;
|
| 582 |
lhs->db = 0;
|
| 583 |
lhs->s = 1;
|
| 584 |
lhs->l = 0;
|
| 585 |
lhs->g = 0;
|
| 586 |
lhs->avl = 0;
|
| 587 |
lhs->unusable = 0;
|
| 588 |
} |
| 589 |
|
| 590 |
static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
| 591 |
{
|
| 592 |
unsigned flags = rhs->flags;
|
| 593 |
lhs->selector = rhs->selector; |
| 594 |
lhs->base = rhs->base; |
| 595 |
lhs->limit = rhs->limit; |
| 596 |
lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
|
| 597 |
lhs->present = (flags & DESC_P_MASK) != 0;
|
| 598 |
lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
|
| 599 |
lhs->db = (flags >> DESC_B_SHIFT) & 1;
|
| 600 |
lhs->s = (flags & DESC_S_MASK) != 0;
|
| 601 |
lhs->l = (flags >> DESC_L_SHIFT) & 1;
|
| 602 |
lhs->g = (flags & DESC_G_MASK) != 0;
|
| 603 |
lhs->avl = (flags & DESC_AVL_MASK) != 0;
|
| 604 |
lhs->unusable = 0;
|
| 605 |
} |
| 606 |
|
| 607 |
static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) |
| 608 |
{
|
| 609 |
lhs->selector = rhs->selector; |
| 610 |
lhs->base = rhs->base; |
| 611 |
lhs->limit = rhs->limit; |
| 612 |
lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
| 613 |
(rhs->present * DESC_P_MASK) | |
| 614 |
(rhs->dpl << DESC_DPL_SHIFT) | |
| 615 |
(rhs->db << DESC_B_SHIFT) | |
| 616 |
(rhs->s * DESC_S_MASK) | |
| 617 |
(rhs->l << DESC_L_SHIFT) | |
| 618 |
(rhs->g * DESC_G_MASK) | |
| 619 |
(rhs->avl * DESC_AVL_MASK); |
| 620 |
} |
| 621 |
|
| 622 |
static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) |
| 623 |
{
|
| 624 |
if (set) {
|
| 625 |
*kvm_reg = *qemu_reg; |
| 626 |
} else {
|
| 627 |
*qemu_reg = *kvm_reg; |
| 628 |
} |
| 629 |
} |
| 630 |
|
| 631 |
static int kvm_getput_regs(CPUState *env, int set) |
| 632 |
{
|
| 633 |
struct kvm_regs regs;
|
| 634 |
int ret = 0; |
| 635 |
|
| 636 |
if (!set) {
|
| 637 |
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
| 638 |
if (ret < 0) { |
| 639 |
return ret;
|
| 640 |
} |
| 641 |
} |
| 642 |
|
| 643 |
kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); |
| 644 |
kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); |
| 645 |
kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); |
| 646 |
kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); |
| 647 |
kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); |
| 648 |
kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); |
| 649 |
kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); |
| 650 |
kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); |
| 651 |
#ifdef TARGET_X86_64
|
| 652 |
kvm_getput_reg(®s.r8, &env->regs[8], set);
|
| 653 |
kvm_getput_reg(®s.r9, &env->regs[9], set);
|
| 654 |
kvm_getput_reg(®s.r10, &env->regs[10], set);
|
| 655 |
kvm_getput_reg(®s.r11, &env->regs[11], set);
|
| 656 |
kvm_getput_reg(®s.r12, &env->regs[12], set);
|
| 657 |
kvm_getput_reg(®s.r13, &env->regs[13], set);
|
| 658 |
kvm_getput_reg(®s.r14, &env->regs[14], set);
|
| 659 |
kvm_getput_reg(®s.r15, &env->regs[15], set);
|
| 660 |
#endif
|
| 661 |
|
| 662 |
kvm_getput_reg(®s.rflags, &env->eflags, set); |
| 663 |
kvm_getput_reg(®s.rip, &env->eip, set); |
| 664 |
|
| 665 |
if (set) {
|
| 666 |
ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
| 667 |
} |
| 668 |
|
| 669 |
return ret;
|
| 670 |
} |
| 671 |
|
| 672 |
static int kvm_put_fpu(CPUState *env) |
| 673 |
{
|
| 674 |
struct kvm_fpu fpu;
|
| 675 |
int i;
|
| 676 |
|
| 677 |
memset(&fpu, 0, sizeof fpu); |
| 678 |
fpu.fsw = env->fpus & ~(7 << 11); |
| 679 |
fpu.fsw |= (env->fpstt & 7) << 11; |
| 680 |
fpu.fcw = env->fpuc; |
| 681 |
for (i = 0; i < 8; ++i) { |
| 682 |
fpu.ftwx |= (!env->fptags[i]) << i; |
| 683 |
} |
| 684 |
memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
|
| 685 |
memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
|
| 686 |
fpu.mxcsr = env->mxcsr; |
| 687 |
|
| 688 |
return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
|
| 689 |
} |
| 690 |
|
| 691 |
#ifdef KVM_CAP_XSAVE
|
| 692 |
#define XSAVE_CWD_RIP 2 |
| 693 |
#define XSAVE_CWD_RDP 4 |
| 694 |
#define XSAVE_MXCSR 6 |
| 695 |
#define XSAVE_ST_SPACE 8 |
| 696 |
#define XSAVE_XMM_SPACE 40 |
| 697 |
#define XSAVE_XSTATE_BV 128 |
| 698 |
#define XSAVE_YMMH_SPACE 144 |
| 699 |
#endif
|
| 700 |
|
| 701 |
static int kvm_put_xsave(CPUState *env) |
| 702 |
{
|
| 703 |
#ifdef KVM_CAP_XSAVE
|
| 704 |
int i, r;
|
| 705 |
struct kvm_xsave* xsave;
|
| 706 |
uint16_t cwd, swd, twd, fop; |
| 707 |
|
| 708 |
if (!kvm_has_xsave()) {
|
| 709 |
return kvm_put_fpu(env);
|
| 710 |
} |
| 711 |
|
| 712 |
xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); |
| 713 |
memset(xsave, 0, sizeof(struct kvm_xsave)); |
| 714 |
cwd = swd = twd = fop = 0;
|
| 715 |
swd = env->fpus & ~(7 << 11); |
| 716 |
swd |= (env->fpstt & 7) << 11; |
| 717 |
cwd = env->fpuc; |
| 718 |
for (i = 0; i < 8; ++i) { |
| 719 |
twd |= (!env->fptags[i]) << i; |
| 720 |
} |
| 721 |
xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
| 722 |
xsave->region[1] = (uint32_t)(fop << 16) + twd; |
| 723 |
memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
| 724 |
sizeof env->fpregs);
|
| 725 |
memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, |
| 726 |
sizeof env->xmm_regs);
|
| 727 |
xsave->region[XSAVE_MXCSR] = env->mxcsr; |
| 728 |
*(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; |
| 729 |
memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, |
| 730 |
sizeof env->ymmh_regs);
|
| 731 |
r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
| 732 |
qemu_free(xsave); |
| 733 |
return r;
|
| 734 |
#else
|
| 735 |
return kvm_put_fpu(env);
|
| 736 |
#endif
|
| 737 |
} |
| 738 |
|
| 739 |
static int kvm_put_xcrs(CPUState *env) |
| 740 |
{
|
| 741 |
#ifdef KVM_CAP_XCRS
|
| 742 |
struct kvm_xcrs xcrs;
|
| 743 |
|
| 744 |
if (!kvm_has_xcrs()) {
|
| 745 |
return 0; |
| 746 |
} |
| 747 |
|
| 748 |
xcrs.nr_xcrs = 1;
|
| 749 |
xcrs.flags = 0;
|
| 750 |
xcrs.xcrs[0].xcr = 0; |
| 751 |
xcrs.xcrs[0].value = env->xcr0;
|
| 752 |
return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
|
| 753 |
#else
|
| 754 |
return 0; |
| 755 |
#endif
|
| 756 |
} |
| 757 |
|
| 758 |
static int kvm_put_sregs(CPUState *env) |
| 759 |
{
|
| 760 |
struct kvm_sregs sregs;
|
| 761 |
|
| 762 |
memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
| 763 |
if (env->interrupt_injected >= 0) { |
| 764 |
sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
|
| 765 |
(uint64_t)1 << (env->interrupt_injected % 64); |
| 766 |
} |
| 767 |
|
| 768 |
if ((env->eflags & VM_MASK)) {
|
| 769 |
set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
| 770 |
set_v8086_seg(&sregs.ds, &env->segs[R_DS]); |
| 771 |
set_v8086_seg(&sregs.es, &env->segs[R_ES]); |
| 772 |
set_v8086_seg(&sregs.fs, &env->segs[R_FS]); |
| 773 |
set_v8086_seg(&sregs.gs, &env->segs[R_GS]); |
| 774 |
set_v8086_seg(&sregs.ss, &env->segs[R_SS]); |
| 775 |
} else {
|
| 776 |
set_seg(&sregs.cs, &env->segs[R_CS]); |
| 777 |
set_seg(&sregs.ds, &env->segs[R_DS]); |
| 778 |
set_seg(&sregs.es, &env->segs[R_ES]); |
| 779 |
set_seg(&sregs.fs, &env->segs[R_FS]); |
| 780 |
set_seg(&sregs.gs, &env->segs[R_GS]); |
| 781 |
set_seg(&sregs.ss, &env->segs[R_SS]); |
| 782 |
} |
| 783 |
|
| 784 |
set_seg(&sregs.tr, &env->tr); |
| 785 |
set_seg(&sregs.ldt, &env->ldt); |
| 786 |
|
| 787 |
sregs.idt.limit = env->idt.limit; |
| 788 |
sregs.idt.base = env->idt.base; |
| 789 |
sregs.gdt.limit = env->gdt.limit; |
| 790 |
sregs.gdt.base = env->gdt.base; |
| 791 |
|
| 792 |
sregs.cr0 = env->cr[0];
|
| 793 |
sregs.cr2 = env->cr[2];
|
| 794 |
sregs.cr3 = env->cr[3];
|
| 795 |
sregs.cr4 = env->cr[4];
|
| 796 |
|
| 797 |
sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
| 798 |
sregs.apic_base = cpu_get_apic_base(env->apic_state); |
| 799 |
|
| 800 |
sregs.efer = env->efer; |
| 801 |
|
| 802 |
return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
|
| 803 |
} |
| 804 |
|
| 805 |
static void kvm_msr_entry_set(struct kvm_msr_entry *entry, |
| 806 |
uint32_t index, uint64_t value) |
| 807 |
{
|
| 808 |
entry->index = index; |
| 809 |
entry->data = value; |
| 810 |
} |
| 811 |
|
| 812 |
static int kvm_put_msrs(CPUState *env, int level) |
| 813 |
{
|
| 814 |
struct {
|
| 815 |
struct kvm_msrs info;
|
| 816 |
struct kvm_msr_entry entries[100]; |
| 817 |
} msr_data; |
| 818 |
struct kvm_msr_entry *msrs = msr_data.entries;
|
| 819 |
int n = 0; |
| 820 |
|
| 821 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); |
| 822 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); |
| 823 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); |
| 824 |
if (has_msr_star) {
|
| 825 |
kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
| 826 |
} |
| 827 |
if (has_msr_hsave_pa) {
|
| 828 |
kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
| 829 |
} |
| 830 |
#ifdef TARGET_X86_64
|
| 831 |
if (lm_capable_kernel) {
|
| 832 |
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); |
| 833 |
kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); |
| 834 |
kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); |
| 835 |
kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); |
| 836 |
} |
| 837 |
#endif
|
| 838 |
if (level == KVM_PUT_FULL_STATE) {
|
| 839 |
/*
|
| 840 |
* KVM is yet unable to synchronize TSC values of multiple VCPUs on
|
| 841 |
* writeback. Until this is fixed, we only write the offset to SMP
|
| 842 |
* guests after migration, desynchronizing the VCPUs, but avoiding
|
| 843 |
* huge jump-backs that would occur without any writeback at all.
|
| 844 |
*/
|
| 845 |
if (smp_cpus == 1 || env->tsc != 0) { |
| 846 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); |
| 847 |
} |
| 848 |
} |
| 849 |
/*
|
| 850 |
* The following paravirtual MSRs have side effects on the guest or are
|
| 851 |
* too heavy for normal writeback. Limit them to reset or full state
|
| 852 |
* updates.
|
| 853 |
*/
|
| 854 |
if (level >= KVM_PUT_RESET_STATE) {
|
| 855 |
kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
| 856 |
env->system_time_msr); |
| 857 |
kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); |
| 858 |
#if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
|
| 859 |
if (has_msr_async_pf_en) {
|
| 860 |
kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, |
| 861 |
env->async_pf_en_msr); |
| 862 |
} |
| 863 |
#endif
|
| 864 |
} |
| 865 |
#ifdef KVM_CAP_MCE
|
| 866 |
if (env->mcg_cap) {
|
| 867 |
int i;
|
| 868 |
|
| 869 |
kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
| 870 |
kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); |
| 871 |
for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
| 872 |
kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); |
| 873 |
} |
| 874 |
} |
| 875 |
#endif
|
| 876 |
|
| 877 |
msr_data.info.nmsrs = n; |
| 878 |
|
| 879 |
return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
|
| 880 |
|
| 881 |
} |
| 882 |
|
| 883 |
|
| 884 |
static int kvm_get_fpu(CPUState *env) |
| 885 |
{
|
| 886 |
struct kvm_fpu fpu;
|
| 887 |
int i, ret;
|
| 888 |
|
| 889 |
ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); |
| 890 |
if (ret < 0) { |
| 891 |
return ret;
|
| 892 |
} |
| 893 |
|
| 894 |
env->fpstt = (fpu.fsw >> 11) & 7; |
| 895 |
env->fpus = fpu.fsw; |
| 896 |
env->fpuc = fpu.fcw; |
| 897 |
for (i = 0; i < 8; ++i) { |
| 898 |
env->fptags[i] = !((fpu.ftwx >> i) & 1);
|
| 899 |
} |
| 900 |
memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
|
| 901 |
memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
|
| 902 |
env->mxcsr = fpu.mxcsr; |
| 903 |
|
| 904 |
return 0; |
| 905 |
} |
| 906 |
|
| 907 |
static int kvm_get_xsave(CPUState *env) |
| 908 |
{
|
| 909 |
#ifdef KVM_CAP_XSAVE
|
| 910 |
struct kvm_xsave* xsave;
|
| 911 |
int ret, i;
|
| 912 |
uint16_t cwd, swd, twd, fop; |
| 913 |
|
| 914 |
if (!kvm_has_xsave()) {
|
| 915 |
return kvm_get_fpu(env);
|
| 916 |
} |
| 917 |
|
| 918 |
xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); |
| 919 |
ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); |
| 920 |
if (ret < 0) { |
| 921 |
qemu_free(xsave); |
| 922 |
return ret;
|
| 923 |
} |
| 924 |
|
| 925 |
cwd = (uint16_t)xsave->region[0];
|
| 926 |
swd = (uint16_t)(xsave->region[0] >> 16); |
| 927 |
twd = (uint16_t)xsave->region[1];
|
| 928 |
fop = (uint16_t)(xsave->region[1] >> 16); |
| 929 |
env->fpstt = (swd >> 11) & 7; |
| 930 |
env->fpus = swd; |
| 931 |
env->fpuc = cwd; |
| 932 |
for (i = 0; i < 8; ++i) { |
| 933 |
env->fptags[i] = !((twd >> i) & 1);
|
| 934 |
} |
| 935 |
env->mxcsr = xsave->region[XSAVE_MXCSR]; |
| 936 |
memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], |
| 937 |
sizeof env->fpregs);
|
| 938 |
memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], |
| 939 |
sizeof env->xmm_regs);
|
| 940 |
env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; |
| 941 |
memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], |
| 942 |
sizeof env->ymmh_regs);
|
| 943 |
qemu_free(xsave); |
| 944 |
return 0; |
| 945 |
#else
|
| 946 |
return kvm_get_fpu(env);
|
| 947 |
#endif
|
| 948 |
} |
| 949 |
|
| 950 |
static int kvm_get_xcrs(CPUState *env) |
| 951 |
{
|
| 952 |
#ifdef KVM_CAP_XCRS
|
| 953 |
int i, ret;
|
| 954 |
struct kvm_xcrs xcrs;
|
| 955 |
|
| 956 |
if (!kvm_has_xcrs()) {
|
| 957 |
return 0; |
| 958 |
} |
| 959 |
|
| 960 |
ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); |
| 961 |
if (ret < 0) { |
| 962 |
return ret;
|
| 963 |
} |
| 964 |
|
| 965 |
for (i = 0; i < xcrs.nr_xcrs; i++) { |
| 966 |
/* Only support xcr0 now */
|
| 967 |
if (xcrs.xcrs[0].xcr == 0) { |
| 968 |
env->xcr0 = xcrs.xcrs[0].value;
|
| 969 |
break;
|
| 970 |
} |
| 971 |
} |
| 972 |
return 0; |
| 973 |
#else
|
| 974 |
return 0; |
| 975 |
#endif
|
| 976 |
} |
| 977 |
|
| 978 |
static int kvm_get_sregs(CPUState *env) |
| 979 |
{
|
| 980 |
struct kvm_sregs sregs;
|
| 981 |
uint32_t hflags; |
| 982 |
int bit, i, ret;
|
| 983 |
|
| 984 |
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
| 985 |
if (ret < 0) { |
| 986 |
return ret;
|
| 987 |
} |
| 988 |
|
| 989 |
/* There can only be one pending IRQ set in the bitmap at a time, so try
|
| 990 |
to find it and save its number instead (-1 for none). */
|
| 991 |
env->interrupt_injected = -1;
|
| 992 |
for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { |
| 993 |
if (sregs.interrupt_bitmap[i]) {
|
| 994 |
bit = ctz64(sregs.interrupt_bitmap[i]); |
| 995 |
env->interrupt_injected = i * 64 + bit;
|
| 996 |
break;
|
| 997 |
} |
| 998 |
} |
| 999 |
|
| 1000 |
get_seg(&env->segs[R_CS], &sregs.cs); |
| 1001 |
get_seg(&env->segs[R_DS], &sregs.ds); |
| 1002 |
get_seg(&env->segs[R_ES], &sregs.es); |
| 1003 |
get_seg(&env->segs[R_FS], &sregs.fs); |
| 1004 |
get_seg(&env->segs[R_GS], &sregs.gs); |
| 1005 |
get_seg(&env->segs[R_SS], &sregs.ss); |
| 1006 |
|
| 1007 |
get_seg(&env->tr, &sregs.tr); |
| 1008 |
get_seg(&env->ldt, &sregs.ldt); |
| 1009 |
|
| 1010 |
env->idt.limit = sregs.idt.limit; |
| 1011 |
env->idt.base = sregs.idt.base; |
| 1012 |
env->gdt.limit = sregs.gdt.limit; |
| 1013 |
env->gdt.base = sregs.gdt.base; |
| 1014 |
|
| 1015 |
env->cr[0] = sregs.cr0;
|
| 1016 |
env->cr[2] = sregs.cr2;
|
| 1017 |
env->cr[3] = sregs.cr3;
|
| 1018 |
env->cr[4] = sregs.cr4;
|
| 1019 |
|
| 1020 |
cpu_set_apic_base(env->apic_state, sregs.apic_base); |
| 1021 |
|
| 1022 |
env->efer = sregs.efer; |
| 1023 |
//cpu_set_apic_tpr(env->apic_state, sregs.cr8);
|
| 1024 |
|
| 1025 |
#define HFLAG_COPY_MASK \
|
| 1026 |
~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ |
| 1027 |
HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ |
| 1028 |
HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ |
| 1029 |
HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) |
| 1030 |
|
| 1031 |
hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; |
| 1032 |
hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
|
| 1033 |
hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
|
| 1034 |
(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
| 1035 |
hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
| 1036 |
hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
|
| 1037 |
(HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
| 1038 |
|
| 1039 |
if (env->efer & MSR_EFER_LMA) {
|
| 1040 |
hflags |= HF_LMA_MASK; |
| 1041 |
} |
| 1042 |
|
| 1043 |
if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
|
| 1044 |
hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
| 1045 |
} else {
|
| 1046 |
hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> |
| 1047 |
(DESC_B_SHIFT - HF_CS32_SHIFT); |
| 1048 |
hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
| 1049 |
(DESC_B_SHIFT - HF_SS32_SHIFT); |
| 1050 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || |
| 1051 |
!(hflags & HF_CS32_MASK)) {
|
| 1052 |
hflags |= HF_ADDSEG_MASK; |
| 1053 |
} else {
|
| 1054 |
hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | |
| 1055 |
env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
|
| 1056 |
} |
| 1057 |
} |
| 1058 |
env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; |
| 1059 |
|
| 1060 |
return 0; |
| 1061 |
} |
| 1062 |
|
| 1063 |
static int kvm_get_msrs(CPUState *env) |
| 1064 |
{
|
| 1065 |
struct {
|
| 1066 |
struct kvm_msrs info;
|
| 1067 |
struct kvm_msr_entry entries[100]; |
| 1068 |
} msr_data; |
| 1069 |
struct kvm_msr_entry *msrs = msr_data.entries;
|
| 1070 |
int ret, i, n;
|
| 1071 |
|
| 1072 |
n = 0;
|
| 1073 |
msrs[n++].index = MSR_IA32_SYSENTER_CS; |
| 1074 |
msrs[n++].index = MSR_IA32_SYSENTER_ESP; |
| 1075 |
msrs[n++].index = MSR_IA32_SYSENTER_EIP; |
| 1076 |
if (has_msr_star) {
|
| 1077 |
msrs[n++].index = MSR_STAR; |
| 1078 |
} |
| 1079 |
if (has_msr_hsave_pa) {
|
| 1080 |
msrs[n++].index = MSR_VM_HSAVE_PA; |
| 1081 |
} |
| 1082 |
|
| 1083 |
if (!env->tsc_valid) {
|
| 1084 |
msrs[n++].index = MSR_IA32_TSC; |
| 1085 |
env->tsc_valid = !vm_running; |
| 1086 |
} |
| 1087 |
|
| 1088 |
#ifdef TARGET_X86_64
|
| 1089 |
if (lm_capable_kernel) {
|
| 1090 |
msrs[n++].index = MSR_CSTAR; |
| 1091 |
msrs[n++].index = MSR_KERNELGSBASE; |
| 1092 |
msrs[n++].index = MSR_FMASK; |
| 1093 |
msrs[n++].index = MSR_LSTAR; |
| 1094 |
} |
| 1095 |
#endif
|
| 1096 |
msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
| 1097 |
msrs[n++].index = MSR_KVM_WALL_CLOCK; |
| 1098 |
#if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
|
| 1099 |
if (has_msr_async_pf_en) {
|
| 1100 |
msrs[n++].index = MSR_KVM_ASYNC_PF_EN; |
| 1101 |
} |
| 1102 |
#endif
|
| 1103 |
|
| 1104 |
#ifdef KVM_CAP_MCE
|
| 1105 |
if (env->mcg_cap) {
|
| 1106 |
msrs[n++].index = MSR_MCG_STATUS; |
| 1107 |
msrs[n++].index = MSR_MCG_CTL; |
| 1108 |
for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
| 1109 |
msrs[n++].index = MSR_MC0_CTL + i; |
| 1110 |
} |
| 1111 |
} |
| 1112 |
#endif
|
| 1113 |
|
| 1114 |
msr_data.info.nmsrs = n; |
| 1115 |
ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); |
| 1116 |
if (ret < 0) { |
| 1117 |
return ret;
|
| 1118 |
} |
| 1119 |
|
| 1120 |
for (i = 0; i < ret; i++) { |
| 1121 |
switch (msrs[i].index) {
|
| 1122 |
case MSR_IA32_SYSENTER_CS:
|
| 1123 |
env->sysenter_cs = msrs[i].data; |
| 1124 |
break;
|
| 1125 |
case MSR_IA32_SYSENTER_ESP:
|
| 1126 |
env->sysenter_esp = msrs[i].data; |
| 1127 |
break;
|
| 1128 |
case MSR_IA32_SYSENTER_EIP:
|
| 1129 |
env->sysenter_eip = msrs[i].data; |
| 1130 |
break;
|
| 1131 |
case MSR_STAR:
|
| 1132 |
env->star = msrs[i].data; |
| 1133 |
break;
|
| 1134 |
#ifdef TARGET_X86_64
|
| 1135 |
case MSR_CSTAR:
|
| 1136 |
env->cstar = msrs[i].data; |
| 1137 |
break;
|
| 1138 |
case MSR_KERNELGSBASE:
|
| 1139 |
env->kernelgsbase = msrs[i].data; |
| 1140 |
break;
|
| 1141 |
case MSR_FMASK:
|
| 1142 |
env->fmask = msrs[i].data; |
| 1143 |
break;
|
| 1144 |
case MSR_LSTAR:
|
| 1145 |
env->lstar = msrs[i].data; |
| 1146 |
break;
|
| 1147 |
#endif
|
| 1148 |
case MSR_IA32_TSC:
|
| 1149 |
env->tsc = msrs[i].data; |
| 1150 |
break;
|
| 1151 |
case MSR_VM_HSAVE_PA:
|
| 1152 |
env->vm_hsave = msrs[i].data; |
| 1153 |
break;
|
| 1154 |
case MSR_KVM_SYSTEM_TIME:
|
| 1155 |
env->system_time_msr = msrs[i].data; |
| 1156 |
break;
|
| 1157 |
case MSR_KVM_WALL_CLOCK:
|
| 1158 |
env->wall_clock_msr = msrs[i].data; |
| 1159 |
break;
|
| 1160 |
#ifdef KVM_CAP_MCE
|
| 1161 |
case MSR_MCG_STATUS:
|
| 1162 |
env->mcg_status = msrs[i].data; |
| 1163 |
break;
|
| 1164 |
case MSR_MCG_CTL:
|
| 1165 |
env->mcg_ctl = msrs[i].data; |
| 1166 |
break;
|
| 1167 |
#endif
|
| 1168 |
default:
|
| 1169 |
#ifdef KVM_CAP_MCE
|
| 1170 |
if (msrs[i].index >= MSR_MC0_CTL &&
|
| 1171 |
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { |
| 1172 |
env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; |
| 1173 |
} |
| 1174 |
#endif
|
| 1175 |
break;
|
| 1176 |
#if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
|
| 1177 |
case MSR_KVM_ASYNC_PF_EN:
|
| 1178 |
env->async_pf_en_msr = msrs[i].data; |
| 1179 |
break;
|
| 1180 |
#endif
|
| 1181 |
} |
| 1182 |
} |
| 1183 |
|
| 1184 |
return 0; |
| 1185 |
} |
| 1186 |
|
| 1187 |
static int kvm_put_mp_state(CPUState *env) |
| 1188 |
{
|
| 1189 |
struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
|
| 1190 |
|
| 1191 |
return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
|
| 1192 |
} |
| 1193 |
|
| 1194 |
static int kvm_get_mp_state(CPUState *env) |
| 1195 |
{
|
| 1196 |
struct kvm_mp_state mp_state;
|
| 1197 |
int ret;
|
| 1198 |
|
| 1199 |
ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); |
| 1200 |
if (ret < 0) { |
| 1201 |
return ret;
|
| 1202 |
} |
| 1203 |
env->mp_state = mp_state.mp_state; |
| 1204 |
if (kvm_irqchip_in_kernel()) {
|
| 1205 |
env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
| 1206 |
} |
| 1207 |
return 0; |
| 1208 |
} |
| 1209 |
|
| 1210 |
static int kvm_put_vcpu_events(CPUState *env, int level) |
| 1211 |
{
|
| 1212 |
#ifdef KVM_CAP_VCPU_EVENTS
|
| 1213 |
struct kvm_vcpu_events events;
|
| 1214 |
|
| 1215 |
if (!kvm_has_vcpu_events()) {
|
| 1216 |
return 0; |
| 1217 |
} |
| 1218 |
|
| 1219 |
events.exception.injected = (env->exception_injected >= 0);
|
| 1220 |
events.exception.nr = env->exception_injected; |
| 1221 |
events.exception.has_error_code = env->has_error_code; |
| 1222 |
events.exception.error_code = env->error_code; |
| 1223 |
|
| 1224 |
events.interrupt.injected = (env->interrupt_injected >= 0);
|
| 1225 |
events.interrupt.nr = env->interrupt_injected; |
| 1226 |
events.interrupt.soft = env->soft_interrupt; |
| 1227 |
|
| 1228 |
events.nmi.injected = env->nmi_injected; |
| 1229 |
events.nmi.pending = env->nmi_pending; |
| 1230 |
events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); |
| 1231 |
|
| 1232 |
events.sipi_vector = env->sipi_vector; |
| 1233 |
|
| 1234 |
events.flags = 0;
|
| 1235 |
if (level >= KVM_PUT_RESET_STATE) {
|
| 1236 |
events.flags |= |
| 1237 |
KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; |
| 1238 |
} |
| 1239 |
|
| 1240 |
return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
|
| 1241 |
#else
|
| 1242 |
return 0; |
| 1243 |
#endif
|
| 1244 |
} |
| 1245 |
|
| 1246 |
static int kvm_get_vcpu_events(CPUState *env) |
| 1247 |
{
|
| 1248 |
#ifdef KVM_CAP_VCPU_EVENTS
|
| 1249 |
struct kvm_vcpu_events events;
|
| 1250 |
int ret;
|
| 1251 |
|
| 1252 |
if (!kvm_has_vcpu_events()) {
|
| 1253 |
return 0; |
| 1254 |
} |
| 1255 |
|
| 1256 |
ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); |
| 1257 |
if (ret < 0) { |
| 1258 |
return ret;
|
| 1259 |
} |
| 1260 |
env->exception_injected = |
| 1261 |
events.exception.injected ? events.exception.nr : -1;
|
| 1262 |
env->has_error_code = events.exception.has_error_code; |
| 1263 |
env->error_code = events.exception.error_code; |
| 1264 |
|
| 1265 |
env->interrupt_injected = |
| 1266 |
events.interrupt.injected ? events.interrupt.nr : -1;
|
| 1267 |
env->soft_interrupt = events.interrupt.soft; |
| 1268 |
|
| 1269 |
env->nmi_injected = events.nmi.injected; |
| 1270 |
env->nmi_pending = events.nmi.pending; |
| 1271 |
if (events.nmi.masked) {
|
| 1272 |
env->hflags2 |= HF2_NMI_MASK; |
| 1273 |
} else {
|
| 1274 |
env->hflags2 &= ~HF2_NMI_MASK; |
| 1275 |
} |
| 1276 |
|
| 1277 |
env->sipi_vector = events.sipi_vector; |
| 1278 |
#endif
|
| 1279 |
|
| 1280 |
return 0; |
| 1281 |
} |
| 1282 |
|
| 1283 |
static int kvm_guest_debug_workarounds(CPUState *env) |
| 1284 |
{
|
| 1285 |
int ret = 0; |
| 1286 |
#ifdef KVM_CAP_SET_GUEST_DEBUG
|
| 1287 |
unsigned long reinject_trap = 0; |
| 1288 |
|
| 1289 |
if (!kvm_has_vcpu_events()) {
|
| 1290 |
if (env->exception_injected == 1) { |
| 1291 |
reinject_trap = KVM_GUESTDBG_INJECT_DB; |
| 1292 |
} else if (env->exception_injected == 3) { |
| 1293 |
reinject_trap = KVM_GUESTDBG_INJECT_BP; |
| 1294 |
} |
| 1295 |
env->exception_injected = -1;
|
| 1296 |
} |
| 1297 |
|
| 1298 |
/*
|
| 1299 |
* Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
|
| 1300 |
* injected via SET_GUEST_DEBUG while updating GP regs. Work around this
|
| 1301 |
* by updating the debug state once again if single-stepping is on.
|
| 1302 |
* Another reason to call kvm_update_guest_debug here is a pending debug
|
| 1303 |
* trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
|
| 1304 |
* reinject them via SET_GUEST_DEBUG.
|
| 1305 |
*/
|
| 1306 |
if (reinject_trap ||
|
| 1307 |
(!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
|
| 1308 |
ret = kvm_update_guest_debug(env, reinject_trap); |
| 1309 |
} |
| 1310 |
#endif /* KVM_CAP_SET_GUEST_DEBUG */ |
| 1311 |
return ret;
|
| 1312 |
} |
| 1313 |
|
| 1314 |
static int kvm_put_debugregs(CPUState *env) |
| 1315 |
{
|
| 1316 |
#ifdef KVM_CAP_DEBUGREGS
|
| 1317 |
struct kvm_debugregs dbgregs;
|
| 1318 |
int i;
|
| 1319 |
|
| 1320 |
if (!kvm_has_debugregs()) {
|
| 1321 |
return 0; |
| 1322 |
} |
| 1323 |
|
| 1324 |
for (i = 0; i < 4; i++) { |
| 1325 |
dbgregs.db[i] = env->dr[i]; |
| 1326 |
} |
| 1327 |
dbgregs.dr6 = env->dr[6];
|
| 1328 |
dbgregs.dr7 = env->dr[7];
|
| 1329 |
dbgregs.flags = 0;
|
| 1330 |
|
| 1331 |
return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
|
| 1332 |
#else
|
| 1333 |
return 0; |
| 1334 |
#endif
|
| 1335 |
} |
| 1336 |
|
| 1337 |
static int kvm_get_debugregs(CPUState *env) |
| 1338 |
{
|
| 1339 |
#ifdef KVM_CAP_DEBUGREGS
|
| 1340 |
struct kvm_debugregs dbgregs;
|
| 1341 |
int i, ret;
|
| 1342 |
|
| 1343 |
if (!kvm_has_debugregs()) {
|
| 1344 |
return 0; |
| 1345 |
} |
| 1346 |
|
| 1347 |
ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); |
| 1348 |
if (ret < 0) { |
| 1349 |
return ret;
|
| 1350 |
} |
| 1351 |
for (i = 0; i < 4; i++) { |
| 1352 |
env->dr[i] = dbgregs.db[i]; |
| 1353 |
} |
| 1354 |
env->dr[4] = env->dr[6] = dbgregs.dr6; |
| 1355 |
env->dr[5] = env->dr[7] = dbgregs.dr7; |
| 1356 |
#endif
|
| 1357 |
|
| 1358 |
return 0; |
| 1359 |
} |
| 1360 |
|
| 1361 |
int kvm_arch_put_registers(CPUState *env, int level) |
| 1362 |
{
|
| 1363 |
int ret;
|
| 1364 |
|
| 1365 |
assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
| 1366 |
|
| 1367 |
ret = kvm_getput_regs(env, 1);
|
| 1368 |
if (ret < 0) { |
| 1369 |
return ret;
|
| 1370 |
} |
| 1371 |
ret = kvm_put_xsave(env); |
| 1372 |
if (ret < 0) { |
| 1373 |
return ret;
|
| 1374 |
} |
| 1375 |
ret = kvm_put_xcrs(env); |
| 1376 |
if (ret < 0) { |
| 1377 |
return ret;
|
| 1378 |
} |
| 1379 |
ret = kvm_put_sregs(env); |
| 1380 |
if (ret < 0) { |
| 1381 |
return ret;
|
| 1382 |
} |
| 1383 |
/* must be before kvm_put_msrs */
|
| 1384 |
ret = kvm_inject_mce_oldstyle(env); |
| 1385 |
if (ret < 0) { |
| 1386 |
return ret;
|
| 1387 |
} |
| 1388 |
ret = kvm_put_msrs(env, level); |
| 1389 |
if (ret < 0) { |
| 1390 |
return ret;
|
| 1391 |
} |
| 1392 |
if (level >= KVM_PUT_RESET_STATE) {
|
| 1393 |
ret = kvm_put_mp_state(env); |
| 1394 |
if (ret < 0) { |
| 1395 |
return ret;
|
| 1396 |
} |
| 1397 |
} |
| 1398 |
ret = kvm_put_vcpu_events(env, level); |
| 1399 |
if (ret < 0) { |
| 1400 |
return ret;
|
| 1401 |
} |
| 1402 |
ret = kvm_put_debugregs(env); |
| 1403 |
if (ret < 0) { |
| 1404 |
return ret;
|
| 1405 |
} |
| 1406 |
/* must be last */
|
| 1407 |
ret = kvm_guest_debug_workarounds(env); |
| 1408 |
if (ret < 0) { |
| 1409 |
return ret;
|
| 1410 |
} |
| 1411 |
return 0; |
| 1412 |
} |
| 1413 |
|
| 1414 |
int kvm_arch_get_registers(CPUState *env)
|
| 1415 |
{
|
| 1416 |
int ret;
|
| 1417 |
|
| 1418 |
assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
| 1419 |
|
| 1420 |
ret = kvm_getput_regs(env, 0);
|
| 1421 |
if (ret < 0) { |
| 1422 |
return ret;
|
| 1423 |
} |
| 1424 |
ret = kvm_get_xsave(env); |
| 1425 |
if (ret < 0) { |
| 1426 |
return ret;
|
| 1427 |
} |
| 1428 |
ret = kvm_get_xcrs(env); |
| 1429 |
if (ret < 0) { |
| 1430 |
return ret;
|
| 1431 |
} |
| 1432 |
ret = kvm_get_sregs(env); |
| 1433 |
if (ret < 0) { |
| 1434 |
return ret;
|
| 1435 |
} |
| 1436 |
ret = kvm_get_msrs(env); |
| 1437 |
if (ret < 0) { |
| 1438 |
return ret;
|
| 1439 |
} |
| 1440 |
ret = kvm_get_mp_state(env); |
| 1441 |
if (ret < 0) { |
| 1442 |
return ret;
|
| 1443 |
} |
| 1444 |
ret = kvm_get_vcpu_events(env); |
| 1445 |
if (ret < 0) { |
| 1446 |
return ret;
|
| 1447 |
} |
| 1448 |
ret = kvm_get_debugregs(env); |
| 1449 |
if (ret < 0) { |
| 1450 |
return ret;
|
| 1451 |
} |
| 1452 |
return 0; |
| 1453 |
} |
| 1454 |
|
| 1455 |
void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
| 1456 |
{
|
| 1457 |
int ret;
|
| 1458 |
|
| 1459 |
/* Inject NMI */
|
| 1460 |
if (env->interrupt_request & CPU_INTERRUPT_NMI) {
|
| 1461 |
env->interrupt_request &= ~CPU_INTERRUPT_NMI; |
| 1462 |
DPRINTF("injected NMI\n");
|
| 1463 |
ret = kvm_vcpu_ioctl(env, KVM_NMI); |
| 1464 |
if (ret < 0) { |
| 1465 |
fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
|
| 1466 |
strerror(-ret)); |
| 1467 |
} |
| 1468 |
} |
| 1469 |
|
| 1470 |
if (!kvm_irqchip_in_kernel()) {
|
| 1471 |
/* Force the VCPU out of its inner loop to process the INIT request */
|
| 1472 |
if (env->interrupt_request & CPU_INTERRUPT_INIT) {
|
| 1473 |
env->exit_request = 1;
|
| 1474 |
} |
| 1475 |
|
| 1476 |
/* Try to inject an interrupt if the guest can accept it */
|
| 1477 |
if (run->ready_for_interrupt_injection &&
|
| 1478 |
(env->interrupt_request & CPU_INTERRUPT_HARD) && |
| 1479 |
(env->eflags & IF_MASK)) {
|
| 1480 |
int irq;
|
| 1481 |
|
| 1482 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 1483 |
irq = cpu_get_pic_interrupt(env); |
| 1484 |
if (irq >= 0) { |
| 1485 |
struct kvm_interrupt intr;
|
| 1486 |
|
| 1487 |
intr.irq = irq; |
| 1488 |
DPRINTF("injected interrupt %d\n", irq);
|
| 1489 |
ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
| 1490 |
if (ret < 0) { |
| 1491 |
fprintf(stderr, |
| 1492 |
"KVM: injection failed, interrupt lost (%s)\n",
|
| 1493 |
strerror(-ret)); |
| 1494 |
} |
| 1495 |
} |
| 1496 |
} |
| 1497 |
|
| 1498 |
/* If we have an interrupt but the guest is not ready to receive an
|
| 1499 |
* interrupt, request an interrupt window exit. This will
|
| 1500 |
* cause a return to userspace as soon as the guest is ready to
|
| 1501 |
* receive interrupts. */
|
| 1502 |
if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
|
| 1503 |
run->request_interrupt_window = 1;
|
| 1504 |
} else {
|
| 1505 |
run->request_interrupt_window = 0;
|
| 1506 |
} |
| 1507 |
|
| 1508 |
DPRINTF("setting tpr\n");
|
| 1509 |
run->cr8 = cpu_get_apic_tpr(env->apic_state); |
| 1510 |
} |
| 1511 |
} |
| 1512 |
|
| 1513 |
void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
| 1514 |
{
|
| 1515 |
if (run->if_flag) {
|
| 1516 |
env->eflags |= IF_MASK; |
| 1517 |
} else {
|
| 1518 |
env->eflags &= ~IF_MASK; |
| 1519 |
} |
| 1520 |
cpu_set_apic_tpr(env->apic_state, run->cr8); |
| 1521 |
cpu_set_apic_base(env->apic_state, run->apic_base); |
| 1522 |
} |
| 1523 |
|
| 1524 |
int kvm_arch_process_async_events(CPUState *env)
|
| 1525 |
{
|
| 1526 |
if (env->interrupt_request & CPU_INTERRUPT_MCE) {
|
| 1527 |
/* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
|
| 1528 |
assert(env->mcg_cap); |
| 1529 |
|
| 1530 |
env->interrupt_request &= ~CPU_INTERRUPT_MCE; |
| 1531 |
|
| 1532 |
kvm_cpu_synchronize_state(env); |
| 1533 |
|
| 1534 |
if (env->exception_injected == EXCP08_DBLE) {
|
| 1535 |
/* this means triple fault */
|
| 1536 |
qemu_system_reset_request(); |
| 1537 |
env->exit_request = 1;
|
| 1538 |
return 0; |
| 1539 |
} |
| 1540 |
env->exception_injected = EXCP12_MCHK; |
| 1541 |
env->has_error_code = 0;
|
| 1542 |
|
| 1543 |
env->halted = 0;
|
| 1544 |
if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
|
| 1545 |
env->mp_state = KVM_MP_STATE_RUNNABLE; |
| 1546 |
} |
| 1547 |
} |
| 1548 |
|
| 1549 |
if (kvm_irqchip_in_kernel()) {
|
| 1550 |
return 0; |
| 1551 |
} |
| 1552 |
|
| 1553 |
if (env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI)) {
|
| 1554 |
env->halted = 0;
|
| 1555 |
} |
| 1556 |
if (env->interrupt_request & CPU_INTERRUPT_INIT) {
|
| 1557 |
kvm_cpu_synchronize_state(env); |
| 1558 |
do_cpu_init(env); |
| 1559 |
} |
| 1560 |
if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
|
| 1561 |
kvm_cpu_synchronize_state(env); |
| 1562 |
do_cpu_sipi(env); |
| 1563 |
} |
| 1564 |
|
| 1565 |
return env->halted;
|
| 1566 |
} |
| 1567 |
|
| 1568 |
static int kvm_handle_halt(CPUState *env) |
| 1569 |
{
|
| 1570 |
if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
| 1571 |
(env->eflags & IF_MASK)) && |
| 1572 |
!(env->interrupt_request & CPU_INTERRUPT_NMI)) {
|
| 1573 |
env->halted = 1;
|
| 1574 |
return 0; |
| 1575 |
} |
| 1576 |
|
| 1577 |
return 1; |
| 1578 |
} |
| 1579 |
|
| 1580 |
static bool host_supports_vmx(void) |
| 1581 |
{
|
| 1582 |
uint32_t ecx, unused; |
| 1583 |
|
| 1584 |
host_cpuid(1, 0, &unused, &unused, &ecx, &unused); |
| 1585 |
return ecx & CPUID_EXT_VMX;
|
| 1586 |
} |
| 1587 |
|
| 1588 |
#define VMX_INVALID_GUEST_STATE 0x80000021 |
| 1589 |
|
| 1590 |
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
| 1591 |
{
|
| 1592 |
uint64_t code; |
| 1593 |
int ret = 0; |
| 1594 |
|
| 1595 |
switch (run->exit_reason) {
|
| 1596 |
case KVM_EXIT_HLT:
|
| 1597 |
DPRINTF("handle_hlt\n");
|
| 1598 |
ret = kvm_handle_halt(env); |
| 1599 |
break;
|
| 1600 |
case KVM_EXIT_SET_TPR:
|
| 1601 |
ret = 1;
|
| 1602 |
break;
|
| 1603 |
case KVM_EXIT_FAIL_ENTRY:
|
| 1604 |
code = run->fail_entry.hardware_entry_failure_reason; |
| 1605 |
fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", |
| 1606 |
code); |
| 1607 |
if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
|
| 1608 |
fprintf(stderr, |
| 1609 |
"\nIf you're runnning a guest on an Intel machine without "
|
| 1610 |
"unrestricted mode\n"
|
| 1611 |
"support, the failure can be most likely due to the guest "
|
| 1612 |
"entering an invalid\n"
|
| 1613 |
"state for Intel VT. For example, the guest maybe running "
|
| 1614 |
"in big real mode\n"
|
| 1615 |
"which is not supported on less recent Intel processors."
|
| 1616 |
"\n\n");
|
| 1617 |
} |
| 1618 |
ret = -1;
|
| 1619 |
break;
|
| 1620 |
case KVM_EXIT_EXCEPTION:
|
| 1621 |
fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
|
| 1622 |
run->ex.exception, run->ex.error_code); |
| 1623 |
ret = -1;
|
| 1624 |
break;
|
| 1625 |
default:
|
| 1626 |
fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
|
| 1627 |
ret = -1;
|
| 1628 |
break;
|
| 1629 |
} |
| 1630 |
|
| 1631 |
return ret;
|
| 1632 |
} |
| 1633 |
|
| 1634 |
#ifdef KVM_CAP_SET_GUEST_DEBUG
|
| 1635 |
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
| 1636 |
{
|
| 1637 |
static const uint8_t int3 = 0xcc; |
| 1638 |
|
| 1639 |
if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
| 1640 |
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
| 1641 |
return -EINVAL;
|
| 1642 |
} |
| 1643 |
return 0; |
| 1644 |
} |
| 1645 |
|
| 1646 |
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
| 1647 |
{
|
| 1648 |
uint8_t int3; |
| 1649 |
|
| 1650 |
if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
| 1651 |
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
| 1652 |
return -EINVAL;
|
| 1653 |
} |
| 1654 |
return 0; |
| 1655 |
} |
| 1656 |
|
| 1657 |
static struct { |
| 1658 |
target_ulong addr; |
| 1659 |
int len;
|
| 1660 |
int type;
|
| 1661 |
} hw_breakpoint[4];
|
| 1662 |
|
| 1663 |
static int nb_hw_breakpoint; |
| 1664 |
|
| 1665 |
static int find_hw_breakpoint(target_ulong addr, int len, int type) |
| 1666 |
{
|
| 1667 |
int n;
|
| 1668 |
|
| 1669 |
for (n = 0; n < nb_hw_breakpoint; n++) { |
| 1670 |
if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
|
| 1671 |
(hw_breakpoint[n].len == len || len == -1)) {
|
| 1672 |
return n;
|
| 1673 |
} |
| 1674 |
} |
| 1675 |
return -1; |
| 1676 |
} |
| 1677 |
|
| 1678 |
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
|
| 1679 |
target_ulong len, int type)
|
| 1680 |
{
|
| 1681 |
switch (type) {
|
| 1682 |
case GDB_BREAKPOINT_HW:
|
| 1683 |
len = 1;
|
| 1684 |
break;
|
| 1685 |
case GDB_WATCHPOINT_WRITE:
|
| 1686 |
case GDB_WATCHPOINT_ACCESS:
|
| 1687 |
switch (len) {
|
| 1688 |
case 1: |
| 1689 |
break;
|
| 1690 |
case 2: |
| 1691 |
case 4: |
| 1692 |
case 8: |
| 1693 |
if (addr & (len - 1)) { |
| 1694 |
return -EINVAL;
|
| 1695 |
} |
| 1696 |
break;
|
| 1697 |
default:
|
| 1698 |
return -EINVAL;
|
| 1699 |
} |
| 1700 |
break;
|
| 1701 |
default:
|
| 1702 |
return -ENOSYS;
|
| 1703 |
} |
| 1704 |
|
| 1705 |
if (nb_hw_breakpoint == 4) { |
| 1706 |
return -ENOBUFS;
|
| 1707 |
} |
| 1708 |
if (find_hw_breakpoint(addr, len, type) >= 0) { |
| 1709 |
return -EEXIST;
|
| 1710 |
} |
| 1711 |
hw_breakpoint[nb_hw_breakpoint].addr = addr; |
| 1712 |
hw_breakpoint[nb_hw_breakpoint].len = len; |
| 1713 |
hw_breakpoint[nb_hw_breakpoint].type = type; |
| 1714 |
nb_hw_breakpoint++; |
| 1715 |
|
| 1716 |
return 0; |
| 1717 |
} |
| 1718 |
|
| 1719 |
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
|
| 1720 |
target_ulong len, int type)
|
| 1721 |
{
|
| 1722 |
int n;
|
| 1723 |
|
| 1724 |
n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
|
| 1725 |
if (n < 0) { |
| 1726 |
return -ENOENT;
|
| 1727 |
} |
| 1728 |
nb_hw_breakpoint--; |
| 1729 |
hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; |
| 1730 |
|
| 1731 |
return 0; |
| 1732 |
} |
| 1733 |
|
| 1734 |
void kvm_arch_remove_all_hw_breakpoints(void) |
| 1735 |
{
|
| 1736 |
nb_hw_breakpoint = 0;
|
| 1737 |
} |
| 1738 |
|
| 1739 |
static CPUWatchpoint hw_watchpoint;
|
| 1740 |
|
| 1741 |
int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) |
| 1742 |
{
|
| 1743 |
int handle = 0; |
| 1744 |
int n;
|
| 1745 |
|
| 1746 |
if (arch_info->exception == 1) { |
| 1747 |
if (arch_info->dr6 & (1 << 14)) { |
| 1748 |
if (cpu_single_env->singlestep_enabled) {
|
| 1749 |
handle = 1;
|
| 1750 |
} |
| 1751 |
} else {
|
| 1752 |
for (n = 0; n < 4; n++) { |
| 1753 |
if (arch_info->dr6 & (1 << n)) { |
| 1754 |
switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
| 1755 |
case 0x0: |
| 1756 |
handle = 1;
|
| 1757 |
break;
|
| 1758 |
case 0x1: |
| 1759 |
handle = 1;
|
| 1760 |
cpu_single_env->watchpoint_hit = &hw_watchpoint; |
| 1761 |
hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
| 1762 |
hw_watchpoint.flags = BP_MEM_WRITE; |
| 1763 |
break;
|
| 1764 |
case 0x3: |
| 1765 |
handle = 1;
|
| 1766 |
cpu_single_env->watchpoint_hit = &hw_watchpoint; |
| 1767 |
hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
| 1768 |
hw_watchpoint.flags = BP_MEM_ACCESS; |
| 1769 |
break;
|
| 1770 |
} |
| 1771 |
} |
| 1772 |
} |
| 1773 |
} |
| 1774 |
} else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
| 1775 |
handle = 1;
|
| 1776 |
} |
| 1777 |
if (!handle) {
|
| 1778 |
cpu_synchronize_state(cpu_single_env); |
| 1779 |
assert(cpu_single_env->exception_injected == -1);
|
| 1780 |
|
| 1781 |
cpu_single_env->exception_injected = arch_info->exception; |
| 1782 |
cpu_single_env->has_error_code = 0;
|
| 1783 |
} |
| 1784 |
|
| 1785 |
return handle;
|
| 1786 |
} |
| 1787 |
|
| 1788 |
void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) |
| 1789 |
{
|
| 1790 |
const uint8_t type_code[] = {
|
| 1791 |
[GDB_BREAKPOINT_HW] = 0x0,
|
| 1792 |
[GDB_WATCHPOINT_WRITE] = 0x1,
|
| 1793 |
[GDB_WATCHPOINT_ACCESS] = 0x3
|
| 1794 |
}; |
| 1795 |
const uint8_t len_code[] = {
|
| 1796 |
[1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 |
| 1797 |
}; |
| 1798 |
int n;
|
| 1799 |
|
| 1800 |
if (kvm_sw_breakpoints_active(env)) {
|
| 1801 |
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
| 1802 |
} |
| 1803 |
if (nb_hw_breakpoint > 0) { |
| 1804 |
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; |
| 1805 |
dbg->arch.debugreg[7] = 0x0600; |
| 1806 |
for (n = 0; n < nb_hw_breakpoint; n++) { |
| 1807 |
dbg->arch.debugreg[n] = hw_breakpoint[n].addr; |
| 1808 |
dbg->arch.debugreg[7] |= (2 << (n * 2)) | |
| 1809 |
(type_code[hw_breakpoint[n].type] << (16 + n*4)) | |
| 1810 |
((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
| 1811 |
} |
| 1812 |
} |
| 1813 |
} |
| 1814 |
#endif /* KVM_CAP_SET_GUEST_DEBUG */ |
| 1815 |
|
| 1816 |
bool kvm_arch_stop_on_emulation_error(CPUState *env)
|
| 1817 |
{
|
| 1818 |
return !(env->cr[0] & CR0_PE_MASK) || |
| 1819 |
((env->segs[R_CS].selector & 3) != 3); |
| 1820 |
} |