Revision 32b6c812
| b/target-sparc/translate.c | ||
|---|---|---|
| 2885 | 2885 |
rs2 = GET_FIELD(insn, 27, 31); |
| 2886 | 2886 |
gen_movl_reg_TN(rs2, cpu_T[1]); |
| 2887 | 2887 |
if (insn & (1 << 12)) {
|
| 2888 |
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
|
|
| 2889 |
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2888 |
tcg_gen_andi_i64(cpu_tmp0, cpu_T[1], 0x3f);
|
|
| 2889 |
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2890 | 2890 |
} else {
|
| 2891 |
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
|
|
| 2891 |
tcg_gen_andi_i64(cpu_tmp0, cpu_T[1], 0x1f);
|
|
| 2892 | 2892 |
tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
| 2893 |
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2893 |
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2894 | 2894 |
} |
| 2895 | 2895 |
} |
| 2896 | 2896 |
gen_movl_TN_reg(rd, cpu_T[0]); |
| ... | ... | |
| 2909 | 2909 |
rs2 = GET_FIELD(insn, 27, 31); |
| 2910 | 2910 |
gen_movl_reg_TN(rs2, cpu_T[1]); |
| 2911 | 2911 |
if (insn & (1 << 12)) {
|
| 2912 |
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
|
|
| 2913 |
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2912 |
tcg_gen_andi_i64(cpu_tmp0, cpu_T[1], 0x3f);
|
|
| 2913 |
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2914 | 2914 |
} else {
|
| 2915 |
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
|
|
| 2915 |
tcg_gen_andi_i64(cpu_tmp0, cpu_T[1], 0x1f);
|
|
| 2916 | 2916 |
tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
| 2917 |
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2917 |
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2918 | 2918 |
} |
| 2919 | 2919 |
} |
| 2920 | 2920 |
gen_movl_TN_reg(rd, cpu_T[0]); |
| ... | ... | |
| 2934 | 2934 |
rs2 = GET_FIELD(insn, 27, 31); |
| 2935 | 2935 |
gen_movl_reg_TN(rs2, cpu_T[1]); |
| 2936 | 2936 |
if (insn & (1 << 12)) {
|
| 2937 |
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
|
|
| 2938 |
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2937 |
tcg_gen_andi_i64(cpu_tmp0, cpu_T[1], 0x3f);
|
|
| 2938 |
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2939 | 2939 |
} else {
|
| 2940 |
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
|
|
| 2940 |
tcg_gen_andi_i64(cpu_tmp0, cpu_T[1], 0x1f);
|
|
| 2941 | 2941 |
tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
| 2942 |
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2942 |
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2943 | 2943 |
} |
| 2944 | 2944 |
} |
| 2945 | 2945 |
gen_movl_TN_reg(rd, cpu_T[0]); |
| ... | ... | |
| 2984 | 2984 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 2985 | 2985 |
break; |
| 2986 | 2986 |
case 0x5: |
| 2987 |
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
|
|
| 2988 |
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2987 |
tcg_gen_xori_tl(cpu_tmp0, cpu_T[1], -1);
|
|
| 2988 |
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2989 | 2989 |
if (xop & 0x10) |
| 2990 | 2990 |
gen_op_logic_cc(cpu_T[0]); |
| 2991 | 2991 |
break; |
| 2992 | 2992 |
case 0x6: |
| 2993 |
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
|
|
| 2994 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2993 |
tcg_gen_xori_tl(cpu_tmp0, cpu_T[1], -1);
|
|
| 2994 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 2995 | 2995 |
if (xop & 0x10) |
| 2996 | 2996 |
gen_op_logic_cc(cpu_T[0]); |
| 2997 | 2997 |
break; |
| 2998 | 2998 |
case 0x7: |
| 2999 |
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
|
|
| 3000 |
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 2999 |
tcg_gen_xori_tl(cpu_tmp0, cpu_T[1], -1);
|
|
| 3000 |
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 3001 | 3001 |
if (xop & 0x10) |
| 3002 | 3002 |
gen_op_logic_cc(cpu_T[0]); |
| 3003 | 3003 |
break; |
| ... | ... | |
| 3006 | 3006 |
gen_op_addx_cc(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 3007 | 3007 |
else {
|
| 3008 | 3008 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 3009 |
tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
|
|
| 3010 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 3009 |
tcg_gen_add_tl(cpu_tmp0, cpu_T[1], cpu_tmp0);
|
|
| 3010 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 3011 | 3011 |
} |
| 3012 | 3012 |
break; |
| 3013 | 3013 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 3030 | 3030 |
gen_op_subx_cc(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 3031 | 3031 |
else {
|
| 3032 | 3032 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 3033 |
tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
|
|
| 3034 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 3033 |
tcg_gen_add_tl(cpu_tmp0, cpu_T[1], cpu_tmp0);
|
|
| 3034 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 3035 | 3035 |
} |
| 3036 | 3036 |
break; |
| 3037 | 3037 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 3080 | 3080 |
break; |
| 3081 | 3081 |
#ifndef TARGET_SPARC64 |
| 3082 | 3082 |
case 0x25: /* sll */ |
| 3083 |
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
|
|
| 3084 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 3083 |
tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], 0x1f);
|
|
| 3084 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 3085 | 3085 |
gen_movl_TN_reg(rd, cpu_T[0]); |
| 3086 | 3086 |
break; |
| 3087 | 3087 |
case 0x26: /* srl */ |
| 3088 |
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
|
|
| 3089 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 3088 |
tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], 0x1f);
|
|
| 3089 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 3090 | 3090 |
gen_movl_TN_reg(rd, cpu_T[0]); |
| 3091 | 3091 |
break; |
| 3092 | 3092 |
case 0x27: /* sra */ |
| 3093 |
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
|
|
| 3094 |
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 3093 |
tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], 0x1f);
|
|
| 3094 |
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
|
|
| 3095 | 3095 |
gen_movl_TN_reg(rd, cpu_T[0]); |
| 3096 | 3096 |
break; |
| 3097 | 3097 |
#endif |
| ... | ... | |
| 3451 | 3451 |
tcg_const_tl(0), l1); |
| 3452 | 3452 |
if (IS_IMM) { /* immediate */
|
| 3453 | 3453 |
rs2 = GET_FIELD_SPs(insn, 0, 10); |
| 3454 |
tcg_gen_movi_tl(cpu_T[1], (int)rs2);
|
|
| 3454 |
tcg_gen_movi_tl(cpu_T[0], (int)rs2);
|
|
| 3455 | 3455 |
} else {
|
| 3456 | 3456 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
| 3457 |
gen_movl_reg_TN(rs2, cpu_T[1]);
|
|
| 3457 |
gen_movl_reg_TN(rs2, cpu_T[0]);
|
|
| 3458 | 3458 |
} |
| 3459 |
gen_movl_TN_reg(rd, cpu_T[1]);
|
|
| 3459 |
gen_movl_TN_reg(rd, cpu_T[0]);
|
|
| 3460 | 3460 |
gen_set_label(l1); |
| 3461 | 3461 |
tcg_gen_discard_tl(r_cond); |
| 3462 | 3462 |
break; |
| ... | ... | |
| 3494 | 3494 |
tcg_const_tl(0), l1); |
| 3495 | 3495 |
if (IS_IMM) { /* immediate */
|
| 3496 | 3496 |
rs2 = GET_FIELD_SPs(insn, 0, 9); |
| 3497 |
tcg_gen_movi_tl(cpu_T[1], (int)rs2);
|
|
| 3497 |
tcg_gen_movi_tl(cpu_T[0], (int)rs2);
|
|
| 3498 | 3498 |
} else {
|
| 3499 | 3499 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
| 3500 |
gen_movl_reg_TN(rs2, cpu_T[1]);
|
|
| 3500 |
gen_movl_reg_TN(rs2, cpu_T[0]);
|
|
| 3501 | 3501 |
} |
| 3502 |
gen_movl_TN_reg(rd, cpu_T[1]);
|
|
| 3502 |
gen_movl_TN_reg(rd, cpu_T[0]);
|
|
| 3503 | 3503 |
gen_set_label(l1); |
| 3504 | 3504 |
break; |
| 3505 | 3505 |
} |
| ... | ... | |
| 3965 | 3965 |
case 0x38: /* jmpl */ |
| 3966 | 3966 |
{
|
| 3967 | 3967 |
if (rd != 0) {
|
| 3968 |
tcg_gen_movi_tl(cpu_T[1], dc->pc);
|
|
| 3969 |
gen_movl_TN_reg(rd, cpu_T[1]);
|
|
| 3968 |
tcg_gen_movi_tl(cpu_tmp0, dc->pc);
|
|
| 3969 |
gen_movl_TN_reg(rd, cpu_tmp0);
|
|
| 3970 | 3970 |
} |
| 3971 | 3971 |
gen_mov_pc_npc(dc, cpu_T[2]); |
| 3972 | 3972 |
tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3)); |
| ... | ... | |
| 4081 | 4081 |
tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7)); |
| 4082 | 4082 |
ABI32_MASK(cpu_T[0]); |
| 4083 | 4083 |
tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx); |
| 4084 |
tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
|
|
| 4085 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL);
|
|
| 4086 |
gen_movl_TN_reg(rd + 1, cpu_T[0]);
|
|
| 4084 |
tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
|
|
| 4085 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
|
| 4086 |
gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
|
| 4087 | 4087 |
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
| 4088 | 4088 |
tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64); |
| 4089 | 4089 |
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL); |
| ... | ... | |
| 4151 | 4151 |
if (rd & 1) |
| 4152 | 4152 |
goto illegal_insn; |
| 4153 | 4153 |
tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7)); |
| 4154 |
gen_ldda_asi(cpu_T[0], cpu_T[1], cpu_T[0], insn);
|
|
| 4155 |
gen_movl_TN_reg(rd + 1, cpu_T[0]);
|
|
| 4154 |
gen_ldda_asi(cpu_tmp0, cpu_T[1], cpu_T[0], insn);
|
|
| 4155 |
gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
|
| 4156 | 4156 |
break; |
| 4157 | 4157 |
case 0x19: /* load signed byte alternate */ |
| 4158 | 4158 |
#ifndef TARGET_SPARC64 |
Also available in: Unified diff