root / hw / pci_host.h @ 331ad6f4
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU Common PCI Host bridge configuration data space access routines.
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 502a5395 | pbrook | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 502a5395 | pbrook | |
25 | 502a5395 | pbrook | /* Worker routines for a PCI host controller that uses an {address,data}
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26 | 502a5395 | pbrook | register pair to access PCI configuration space. */
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27 | 502a5395 | pbrook | |
28 | 502a5395 | pbrook | typedef struct { |
29 | 502a5395 | pbrook | uint32_t config_reg; |
30 | 502a5395 | pbrook | PCIBus *bus; |
31 | 502a5395 | pbrook | } PCIHostState; |
32 | 502a5395 | pbrook | |
33 | 502a5395 | pbrook | static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val) |
34 | 502a5395 | pbrook | { |
35 | 502a5395 | pbrook | PCIHostState *s = opaque; |
36 | 502a5395 | pbrook | if (s->config_reg & (1u << 31)) |
37 | 502a5395 | pbrook | pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1); |
38 | 502a5395 | pbrook | } |
39 | 502a5395 | pbrook | |
40 | 502a5395 | pbrook | static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val) |
41 | 502a5395 | pbrook | { |
42 | 502a5395 | pbrook | PCIHostState *s = opaque; |
43 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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44 | 502a5395 | pbrook | val = bswap16(val); |
45 | 502a5395 | pbrook | #endif
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46 | 502a5395 | pbrook | if (s->config_reg & (1u << 31)) |
47 | 502a5395 | pbrook | pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2); |
48 | 502a5395 | pbrook | } |
49 | 502a5395 | pbrook | |
50 | 502a5395 | pbrook | static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val) |
51 | 502a5395 | pbrook | { |
52 | 502a5395 | pbrook | PCIHostState *s = opaque; |
53 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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54 | 502a5395 | pbrook | val = bswap32(val); |
55 | 502a5395 | pbrook | #endif
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56 | 502a5395 | pbrook | if (s->config_reg & (1u << 31)) |
57 | 502a5395 | pbrook | pci_data_write(s->bus, s->config_reg, val, 4);
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58 | 502a5395 | pbrook | } |
59 | 502a5395 | pbrook | |
60 | 502a5395 | pbrook | static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr) |
61 | 502a5395 | pbrook | { |
62 | 502a5395 | pbrook | PCIHostState *s = opaque; |
63 | 502a5395 | pbrook | if (!(s->config_reg & (1 << 31))) |
64 | 502a5395 | pbrook | return 0xff; |
65 | 502a5395 | pbrook | return pci_data_read(s->bus, s->config_reg | (addr & 3), 1); |
66 | 502a5395 | pbrook | } |
67 | 502a5395 | pbrook | |
68 | 502a5395 | pbrook | static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr) |
69 | 502a5395 | pbrook | { |
70 | 502a5395 | pbrook | PCIHostState *s = opaque; |
71 | 502a5395 | pbrook | uint32_t val; |
72 | 502a5395 | pbrook | if (!(s->config_reg & (1 << 31))) |
73 | 502a5395 | pbrook | return 0xffff; |
74 | 502a5395 | pbrook | val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2); |
75 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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76 | 502a5395 | pbrook | val = bswap16(val); |
77 | 502a5395 | pbrook | #endif
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78 | 502a5395 | pbrook | return val;
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79 | 502a5395 | pbrook | } |
80 | 502a5395 | pbrook | |
81 | 502a5395 | pbrook | static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr) |
82 | 502a5395 | pbrook | { |
83 | 502a5395 | pbrook | PCIHostState *s = opaque; |
84 | 502a5395 | pbrook | uint32_t val; |
85 | 502a5395 | pbrook | if (!(s->config_reg & (1 << 31))) |
86 | 502a5395 | pbrook | return 0xffffffff; |
87 | 502a5395 | pbrook | val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4); |
88 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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89 | 502a5395 | pbrook | val = bswap32(val); |
90 | 502a5395 | pbrook | #endif
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91 | 502a5395 | pbrook | return val;
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92 | 502a5395 | pbrook | } |